2N6344A, 2N6348A, 2N6349A Triacs - didier villers on line

Designed primarily for full-wave ac control applications, such as .... 4.0. 0. 0. IT(RMS), RMS ON-STATE CURRENT (AMP). 8.0. 16. 12. 20. 2.0. 4.0. 6.0. 8.0. 10. 12.
60KB taille 3 téléchargements 223 vues
2N6344A, 2N6348A, 2N6349A Preferred Device

Triacs Silicon Bidirectional Thyristors Designed primarily for full-wave ac control applications, such as light dimmers, motor controls, heating controls and power supplies; or wherever full-wave silicon gate controlled solid-state devices are needed. Triac type thyristors switch from a blocking to a conducting state for either polarity of applied anode voltage with positive or negative gate triggering. • Blocking Voltage to 800 Volts • All Diffused and Glass Passivated Junctions for Greater Parameter Uniformity and Stability • Small, Rugged, Thermowatt Construction for Low Thermal Resistance, High Heat Dissipation and Durability • Gate Triggering Guaranteed in all Four Quadrants • For 400 Hz Operation, Consult Factory • 8 Ampere Devices Available as 2N6344 thru 2N6349 • Device Marking: Logo, Device Type, e.g., 2N6344A, Date Code

http://onsemi.com

TRIACS 12 AMPERES RMS 600 thru 800 VOLTS MT2

MT1 G

4

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating

Symbol

*Peak Repetitive Off−State Voltage(Note 1) (Gate Open, TJ = −40 to +110°C, Sine Wave 50 to 60 Hz, Gate Open) 2N6344A, 2N6348A 2N6349A

VDRM, VRRM

*On−State RMS Current (Full Cycle Sine Wave 50 to 60 Hz) (TC = +80°C) (TC = +95°C)

IT(RMS)

*Peak Non−repetitive Surge Current (One Full Cycle, 60 Hz, TC = +80°C) Preceded and followed by rated current

ITSM

Circuit Fusing Consideration (t = 8.3 ms)

I2t

*Peak Gate Power (TC = +80°C, Pulse Width = 2.0 µs) *Average Gate Power (TC = +80°C, t = 8.3 ms)

Value

Unit Volts 1

600 800 A

PGM

A

A2s

59 20

Watts

PG(AV)

0.5

Watt

*Peak Gate Current (Pulse Width = 2.0 µs; TC = +80°C)

IGM

2.0

A

*Peak Gate Voltage (Pulse Width = 2.0 µs; TC = +80°C)

VGM

10

Volts

*Operating Junction Temperature Range

TJ

−40 to +125

°C

*Storage Temperature Range

Tstg

−40 to +150

°C

February, 2004 − Rev. 2

PIN ASSIGNMENT 1

Main Terminal 1

2

Main Terminal 2

3

Gate

4

Main Terminal 2

ORDERING INFORMATION Device

*Indicates JEDEC Registered Data. 1. VDRM and VRRM for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant current source such that the voltage ratings of the devices are exceeded.

 Semiconductor Components Industries, LLC, 2004

3

TO−220AB CASE 221A STYLE 4

12 6.0 100

2

1

Package

Shipping

2N6344A

TO220AB

500/Box

2N6348A

TO220AB

500/Box

2N6349A

TO220AB

500/Box

Preferred devices are recommended choices for future use and best overall value.

Publication Order Number: 2N6344A/D

2N6344A, 2N6348A, 2N6349A THERMAL CHARACTERISTICS Characteristic

Symbol

*Thermal Resistance, Junction to Case Maximum Lead Temperature for Soldering Purposes 1/8″ from Case for 10 Seconds

Max

Unit

RθJC

2.0

°C/W

TL

260

°C

ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted; Electricals apply in either direction) Symbol

Characteristic

Min

Typ

Max

Unit

— —

— —

10 2.0

µA mA



1.3

1.75

Volts

OFF CHARACTERISTICS *Peak Repetitive Blocking Current (VD = Rated VDRM, VRRM; Gate Open)

TJ = 25°C TJ = 110°C

IDRM, IRRM

ON CHARACTERISTICS *Peak On-State Voltage (ITM = 17 A Peak; Pulse Width = 1 to 2 ms, Duty Cycle  2%)

VTM

Gate Trigger Current (Continuous dc) (VD = 12 Vdc, RL = 100 Ohms) Quadrant I: MT2(+), G(+) All Quadrant II: MT2(+), G(−) 2N6348A and 2N6349A only Quadrant III: MT2(−), G(−) All Quadrant IV: MT2(−), G(+) 2N6348A and 2N6349A only *MT2(+), G(+); MT2(−), G(−) TC = −40°C *MT2(+), G(−); MT2(−), G(+) TC = −40°C

IGT

Gate Trigger Voltage (Continuous dc) (VD = 12 Vdc, RL = 100 ohms) Quadrant I: MT2(+), G(+) All Quadrant II: MT2(+), G(−) 2N6348A and 2N6349A only Quadrant III: MT2(−), G(−) All Quadrant IV: MT2(−), G(+) 2N6348A and 2N6349A only *MT2(+), G(+); MT2(−), G(−) TC = −40°C *MT2(+), G(−); MT2(−), G(+) TC = −40°C

VGT

Gate Non−Trigger Voltage (VD = Rated VDRM, RL = 10 k ohms, TJ = 110°C) *MT2(+), G(+); MT2(−), G(−); MT2(+), G(−); MT2(−), G(+)

VGD

Holding Current (VD = 12 Vdc, Gate Open) Initiating Current = 200 mA

mA — — — — — —

6.0 6.0 10 25 — —

50 75 50 75 100 125 Volts

— — — — — —

0.9 0.9 1.1 1.4 — —

2.0 2.5 2.0 2.5 2.5 3.0 Volts

0.2





— —

6.0 —

40 75

tgt



1.5

2.0

µs

dv/dt(c)



5.0



V/µs

IH TC = 25°C *TC = −40°C

*Turn-On Time (VD = Rated VDRM, ITM = 17 A, IGT = 120 mA, Rise Time = 0.1 µs, Pulse Width = 2 µs)

mA

DYNAMIC CHARACTERISTICS Critical Rate of Rise of Commutation Voltage (VD = Rated VDRM, ITM = 17 A, Commutating di/dt = 6.1 A/ms, Gate Unenergized, TC = 80°C) *Indicates JEDEC Registered Data.

http://onsemi.com 2

2N6344A, 2N6348A, 2N6349A Voltage Current Characteristic of Triacs (Bidirectional Device) + Current

Symbol

Parameter

VTM

VDRM

Peak Repetitive Forward Off State Voltage

IDRM

Peak Forward Blocking Current

VRRM

Peak Repetitive Reverse Off State Voltage

IRRM

Peak Reverse Blocking Current

VTM

Maximum On State Voltage

IH

Holding Current

on state IH IRRM at VRRM off state IH Quadrant 3 MainTerminal 2 −

VTM

Quadrant Definitions for a Triac MT2 POSITIVE (Positive Half Cycle) +

(+) MT2

Quadrant II 2N6348A 2N6349A

(+) MT2

Quadrant I

(+) IGT GATE

(−) IGT GATE

All MT1

MT1

REF

REF IGT −

+ IGT (−) MT2

Quadrant III All

Quadrant 1 MainTerminal 2 +

(−) MT2

Quadrant IV

(+) IGT GATE

(−) IGT GATE

MT1

MT1

REF

REF − MT2 NEGATIVE (Negative Half Cycle)

All polarities are referenced to MT1. With in−phase signals (using standard AC lines) quadrants I and III are used.

http://onsemi.com 3

2N6348A 2N6349A

+ Voltage IDRM at VDRM

2N6344A, 2N6348A, 2N6349A 110

20

dc

PAV , AVERAGE POWER (WATTS)

TC , CASE TEMPERATURE ( °C)

30° 60° 100

90° 120° 180°

90 α α

80

α = CONDUCTION ANGLE

α

16 α 12

α = CONDUCTION ANGLE TJ = 110°C

8.0

90° 60 α = 30° °

4.0

dc

70 0

2.0

4.0 6.0 8.0 10 12 IT(RMS), RMS ON-STATE CURRENT, (AMP)

0

14

0

2.0

Figure 1. RMS Current Derating

I GT , GATE TRIGGER CURRENT (mA)

1.4 QUADRANT 4

1.2 1.0 1 QUADRANTS 2

0.6 0.4 −60

12

14

50 VD = 12 V

1.6

0.8

4.0 6.0 8.0 10 IT(RMS), RMS ON-STATE CURRENT (AMP)

Figure 2. On−State Power Dissipation

1.8 Vgt , GATE TRIGGER VOLTAGE (VOLTS)

180° 120°

3 −40

−20

0 20 40 60 80 100 TJ, JUNCTION TEMPERATURE (°C)

120 140

VD = 12 V 30 20

10

QUADRANT

7.0 5.0 −60

Figure 3. Typical Gate Trigger Voltage

−40

1 2 3 4

−20

0 20 40 60 80 100 TJ, JUNCTION TEMPERATURE (°C)

120 140

Figure 4. Typical Gate Trigger Current

http://onsemi.com 4

2N6344A, 2N6348A, 2N6349A 100

20 GATE OPEN I H , HOLDING CURRENT (mA)

70 50 30

TJ = 100°C

25°C

10 7.0 5.0 MAIN TERMINAL #2 POSITIVE

10

3.0

7.0

2.0 −60

5.0

60 0 20 40 80 100 TJ, JUNCTION TEMPERATURE (°C)

−20

120

140

Figure 6. Typical Holding Current

2.0 100 1.0 0.7 0.5 0.3 0.2

0.1 0.4

80

60 CYCLE

40

TJ = 100°C f = 60 Hz Surge is preceded and followed by rated current

20 0

0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 vTM, MAXIMUM INSTANTANEOUS ON-STATE VOLTAGE (VOLTS)

1.0

Figure 5. On−State Characteristics

r(t), TRANSIENT THERMAL RESISTANCE (NORMALIZED)

−40

3.0

I TSM , PEAK SURGE CURRENT (AMP)

i TM , INSTANTANEOUS ON-STATE CURRENT (AMP)

20

MAIN TERMINAL #1 POSITIVE

2.0

3.0 5.0 NUMBER OF CYCLES

7.0

10

Figure 7. Maximum Non−Repetitive Surge Current

1.0 0.5

0.2

ZθJC(t) = r(t) • RθJC

0.1 0.05

0.02 0.01 0.1

0.2

0.5

1.0

2.0

5.0

20 50 t,TIME (ms)

100

200

Figure 8. Typical Thermal Response

http://onsemi.com 5

500

1.0 k

2.0 k

5.0 k

10 k

2N6344A, 2N6348A, 2N6349A PACKAGE DIMENSIONS

TO−220AB CASE 221A−07 ISSUE AA

−T− B

F

T

SEATING PLANE

C S

NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. DIM A B C D F G H J K L N Q R S T U V Z

4

Q

A 1 2 3

U

H K Z R

L V

J

G D N

INCHES MIN MAX 0.570 0.620 0.380 0.405 0.160 0.190 0.025 0.035 0.142 0.147 0.095 0.105 0.110 0.155 0.014 0.022 0.500 0.562 0.045 0.060 0.190 0.210 0.100 0.120 0.080 0.110 0.045 0.055 0.235 0.255 0.000 0.050 0.045 −−− −−− 0.080

STYLE 4: PIN 1. 2. 3. 4.

MILLIMETERS MIN MAX 14.48 15.75 9.66 10.28 4.07 4.82 0.64 0.88 3.61 3.73 2.42 2.66 2.80 3.93 0.36 0.55 12.70 14.27 1.15 1.52 4.83 5.33 2.54 3.04 2.04 2.79 1.15 1.39 5.97 6.47 0.00 1.27 1.15 −−− −−− 2.04

MAIN TERMINAL 1 MAIN TERMINAL 2 GATE MAIN TERMINAL 2

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected]

N. American Technical Support: 800−282−9855 Toll Free USA/Canada

ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder

Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Phone: 81−3−5773−3850

http://onsemi.com 6

For additional information, please contact your local Sales Representative.

2N6344A/D