Xilinx PowerPC Development Workshop Featuring PowerPC and EDK 6.3
Embedded Processor Development Workshop
Agenda !
Lecture 1 • •
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Lab 1 • •
Lunch
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Lecture 2 •
10:00 – 12:00
Build a Simple PowerPC System Add Peripheral Cores to an Existing Design
!
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8:00 – 9:45
Processor, Bus Structures, Typical Systems Development Tools, Hardware and Software Design Flow
1:00 – 2:15
Build a Custom IP Core, PowerPC Debug with GNU and Xilinx Tools
Lab 2 • •
2:30 – 4:00
Build a Custom IP Core and Add it to an Existing Design Download and Debug System via JTAG
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Course Objectives !
Understand the PowerPC development flow and how to use the Xilinx embedded systems tools
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By the end of the day… • • •
Design a PowerPC system Develop a software application Debug the design in hardware
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Course Overview !
Present PowerPC Architecture • • •
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Explain PowerPC Development Flow • • •
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Processor Core Bus Structures Typical Systems
Embedded Development Kit (EDK) HW/SW Design Flow Debugging
Hands-on • • •
Implementing a PowerPC System Modifying an Existing Design Implementing a Custom IP Core
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Lab Station Description !
Laptop Configuration • • • •
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Embedded Processor Development Workshop
WindowsXP ISE v6.3.1 EDK v6.3 EDK BFM Package
Memec Design Virtex-II Pro LC Board
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Xilinx PowerPC Development Workshop Processor Architecture
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Virtex-II Pro Platform Architecture !
PowerPC Processor Core Features • • • • • • • • • • •
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PowerPC 405 Core 32-bit RISC Architecture 5-stage Data Path Pipeline 16KB Instruction and Data Caches 64-bit High-speed Processor Local Bus (PLB) Timers: PIT, FIT, Watchdog Dedicated On-Chip Memory (OCM) Interface for Instruction and Data JTAG Debug and Instruction Trace Support Built-in Memory Management Unit (MMU) 600 DMIPS at 400 MHz 0.9mW/MHz Typical Power
Supported FPGA Architectures •
Virtex-II Pro, Virtex-II Pro X and Virtex-4 FX
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PowerPC 405 Core PLB
IOCM
MMU I-Cache Array
I-Cache Controller
Instruction-Cache Unit
Data-Cache Unit
3-Element Fetch Queue
Timers
Timers and Debug Ports Execution Unit
Data Shadow-TLB (8-Entry)
D-Cache Controller
PLB
Fetch and Decode Logic
Unified TLB (64-Entry)
Cache Units
D-Cache Array
CPU
Instruction Shadow-TLB (4-Entry)
32x32 GPR
ALU
MAC
Debug Logic
JTAG
DOCM
I-Trace
PowerPC Reset Vector Resides at Address 0xFFFFFFFC
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Embedded On-Chip Memory Controller
PPC 405 Core
DSOCM BRAM Interface
ISOCM Controller
Instruction BRAM
ISOCM BRAM Interface
!
Provides direct, high-speed access to on-chip BRAM Dedicated controllers for I-side (ISOCM) and D-side (DSOCM) to provide highest performance User IP can communicate with the processor via on-chip dual-ported memory connected to the DSOCM
DSOCM Controller
! !
Data BRAM User Soft IP
A minimal processor based system
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CoreConnect Bus Architecture CoreConnect bus structure is used to connect I/O and memory devices to the PPC 405 core PLB
OPB
!
Processor Local Bus (PLB) " 32-bit address, 64-bit data " Separate read and write buses for overlapped transfers " High performance
!
On-Chip Peripheral Bus (OPB) " 32-bit address, 32-bit data " Single-cycle data transfers " Maximum peripherals / high load
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Device Control Register Bus (DCR) " 10-bit address, 32-bit data " Directly accessible by PPC " Interface to register-based I/O devices
PLB
PLB-OPB Bridge
CoreConnect consists of three distinct buses
PPC 405 Core
DCR
PLB Arbiter
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Soft IP_1
OPB Arbiter
. . .
Soft IP_n
DCR Bus
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CoreConnect System DCR
DCR Interface
Soft IP_1
. . .
Soft IP_n
PPC 405 Core
PLB Arbiter
High-speed Peripheral
Data
Instruction
PLB Interface
PLB
OPB
PLB-OPB Bridge
Memory Controller
I/O Device Interface
OPB Arbiter
Memory Controller FPGA
High-performance devices are connected to the PLB
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Memory and I/O devices with lower-performance requirements are connected to the OPB 11
Xilinx PowerPC Development Workshop Development Tools
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Development Tools Overview
! !
Synthesis Place & Route
Processor Development Front End Tool
! ! ! !
Third Party Tools: ! ModelSim HDL Simulator " ModelSim PE/SE ! WindRiver " Diab C/C++ Compiler " Single Step Debugger
Embedded Processor Development Workshop
! ! !
Xilinx Platform Studio (XPS) GUI Xilinx Microprocessor Debug (XMD) Board Support Package Generator Interface to Industry Standard Simulators Processor Peripheral IP GNU Compiler and Debugger Application Examples
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Embedded Development Kit (EDK) Embedded Development Kit (EDK) Toolkit
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Embedded Systems Tools • • • • • • • • •
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MicroBlazeTM Core & License • • • •
! ! !
Xilinx Platform Studio (XPS) Base System Builder (BSB) Tools for SW platform specification Custom IP creation wizard ChipScope Pro HW debug support Xilinx Microprocessor Debug (XMD) Board Support Package (BSP) generation for standalone, Xilinx MicroKernel, WindRiver VxWorks and Monta Vista Linux operating systems. Interface to industry standard simulation tools Bus Functional Model (BFM) simulation support 32-bit processor Instruction and data caches Hardware debug logic Fast Simplex Link (FSL) support
Processor Peripheral IP GNU Tools (Compiler and Debugger) Applications Examples
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Xilinx Platform Studio (XPS)
Custom IP creation wizard
HW generation using BSB wizard
Xilinx Platform Studio (XPS) Support for multiple software projects
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ChipScope HW debug support
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ChipScope Pro Support ! Enables co-debug of SW and HW with GNU Debugger and ChipScope Pro Analyzer ! The following ChipScope Pro cores are included in EDK • • • •
PLB IBA (Integrated Bus Analyzer) OPB IBA VIO (Virtual I/O) ICON (Integrated Controller)
! ChipScope Pro evaluation version is shipped on Embedded Development Kit CD • •
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90-day Analyzer evaluation license Core insertion/generation works indefinitely
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Xilinx PowerPC Development Workshop Design Flow
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Design Flow Embedded Development Kit (EDK)
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Generate a hardware platform using the BSB wizard
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Add additional cores to the design (optional)
3
Create user IP and add it to the design (optional)
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Specify hardware options
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Perform Bus Functional Model (BFM) simulation of the system (optional)
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Generate a bit file
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Generate software libraries
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Write application software
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Compile and link the software
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Combine the hardware bit file with the software (optional)
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Download the bit file to the board
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Use the GNU debugger and the ChipScope Pro to debug the system
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Xilinx PowerPC Development Workshop Building a Hardware Platform Using the Base System Builder (BSB) Wizard
Embedded Processor Development Workshop
Base System Builder Overview The XBD file is either located in the EDK install directory or in a user-created Repository folder.
BSB wizard is used to build a hardware platform for a user-defined system and should be the starting point for all designs.
Embedded Development Kit (EDK) Xilinx Board Description (XBD) File
EDK Hardware IP Library
EDK Software Driver Library
Base System Builder (BSB) Wizard
Platform Block Diagram (PBD)
Microprocessor Hardware Specification (MHS) File
download.cmd File
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Microprocessor Software Specification (MSS) File
User Constraints File (UCF)
System Test Program (TestApp.c)
System Linker Script (TestAppLinkScr)
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Base System Builder (BSB) Wizard 1
Start XPS and invoke the Base System Builder (BSB) wizard.
3 Create a new design in BSB or to open an existing BSB file saved from a previous session.
2a Specify the path to the project directory. The default name for the XPS project is system.xmp, but it can be modified.
2b
The Memec_Repository folder contains the Xilinx Board Description (XBD) files for the Memec boards. For instructions on creating this folder for Memec boards please refer to the following web site: http://legacy.memec.com/solutions/reference/xilinx/
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Base System Builder (BSB) Wizard 4a
Select a Board Vendor, Board Name and a Board Revision from the list of boards in the EDK install directory or the user board repository folder.
5a BSB shows the FPGA on the selected board (Memec Virtex-II Pro P4-FG456 board).
4b Alternately, the user can create a project for a custom board (custom boards do not require XBD files).
5b Select a processor for your system. BSB allows selection of MicroBlaze or PowerPC for development boards utilizing the Virtex-II Pro, Virtex-II Pro X and Virtex-4 FX FPGA family. For all other FPGA families, BSB allows only the selection of MicroBlaze.
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Base System Builder (BSB) Wizard 6a
Note: a 100 MHz oscillator is located on the Memec P4-FG456 development board.
Select the processor and bus clock. Please refer to xapp640 for more information on the processor and bus clock relationship.
6b Note: The Memec P4-FG456 board has an on-board push button that generates an active low reset signal.
FPGA JTAG - The PPC JTAG port can be connected to the FPGA JTAG port CPU Debug User Pins Only - The PPC JTAG port can be connected to a dedicated debug header using FPGA I/O pins CPU Debug and Trace Pins - PPC debugging can also be accomplished using the PPC trace port connected to a header on the board via FPGA I/O pins
6c PPC instruction and data memory can be implemented using internal FPGA Block RAMs connected to the high-speed OnChip Memory (OCM) buses.
6d PPC 16KB instruction and data caches can be enabled.
Embedded Processor Development Workshop
The size of the memory can be set to 8KB, 16KB or 32KB. The sizes of the instruction and data memories don’t have to be the same and they depend on the FPGA’s available Block RAMs.
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Base System Builder (BSB) Wizard 7
The Memec P4-FG456 development board utilizes an RS232 port, four user LEDs, three user push button switches (in addition to the reset push button switch), an eight-position DIP switch and 32MB of SDRAM. For this example, all of the devices are used and the RS232 interrupt is enabled. If a given device on the board is not needed in a design, the box next to the device can be un-checked.
User timing constraints are required to meet the design timing requirements.
Note: The datasheet for each IP, located in the EDK install directory can be viewed from the BSB wizard.
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Base System Builder (BSB) Wizard 8
The Memec P4-FG456 development board uses a header for connection to the Memec SystemACE Module (SAM). For this example, the SAM is used and the SystemACE controller interrupt is enabled.
9b
BSB allows inclusion of several IP cores that are connected to the PPC, but have no external connections to the devices on the board. These IP cores consist of: OPB BRAM controllers OPB timer OPB WDT PLB BRAM Controller
9a PPC instruction and data memory can be implemented using internal FPGA Block RAM connected to the PLB. Please refer to the Platform Generator chapter of the est_rm.pdf document located in the EDK install directory for more information on allowable memory sizes. If the PLB memory is not needed in a design, it can be removed using the “Remove” button.
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Base System Builder (BSB) Wizard 10
The BSB allows all PLB/OPB-based memories to be selected as cached or un-cached on an individual basis. For this example, the external SDRAM is set to be cached for instruction and data. The on-chip block RAM is not cached. Block RAM connected to the OCM is not cacheable by design, hence it is not included in the list of memory types to be cached.
11a If selected, BSB can generate a simple application program to test some of the devices/IP cores in the design. It can also generate a simple linker script for the design.
11b A device such as the RS232 port on the Memec P4-FG456 board can be used as the standard input/output device.
11c BSB allows the instruction, data, and stack area to be mapped to the BRAM connected to the PLB/OPB or any external memory in the system such as the SDRAM on the Memec P4-FG456 board.
Standard input/output devices are used by software to communicate with external devices using functions such as the printf().
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Base System Builder (BSB) Wizard 12
The BSB wizard shows the design settings after the system has been created. This system consists of OCM instruction/data memory, memory connected to the PLB and peripherals connected to the OPB. System hardware generation using the BSB wizard is complete. The rest of the design flow is outside of the BSB wizard.
13 The BSB wizard shows the files generated during the design creation. These files will be discussed in detail in the next few slides.
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Overview of the System Created by BSB The PowerPC processor, its driver version and also the OS type (standalone), used in this design.
The system is shown in the XPS GUI A list of files generated by the BSB wizard describing the system.
A list of soft IP cores used in the design.
system.mhs – Microprocessor Hardware Specification (MHS) is a text file describing the hardware platform. system.mss – Microprocessor Software Specification (MSS) is a text file showing default software drivers for IP cores listed in the system.mhs file. system.pbd – Platform Block Diagram (PBD) view of the system described in the system.mhs file. system.ucf – UCF for the top-level design. download.cmd – A command file describing the JTAG chain on the Memec P4-FG456 board. This file is used by iMPACT to download the bit file to the FPGA.
These files are copied from the EDK install directory to the project directory. fast_runtime.opt – A text file defining default synthesis and place & route options for the design. bitgen.ut – A text file describing bit file generation options for the design.
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Microprocessor Peripheral Description (MPD) File Each IP core in the EDK hardware library (or user library) has a Microprocessor Peripheral Description (MPD) file that contains port descriptions of the IP along with default settings for the PARAMETERs and PORTs used by the IP.
Right-click on the instance name of an IP core in the XPS GUI and then select “View MPD”
The default PARAMETERs and PORTs in the MPD file are overridden by the MHS file to tailor the IP for a specific application.
GPIO MPD file
MPD File
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System Block Diagram FPGA ISOCM BRAM (8KB)
External Devices
ISOCM Controller PLB SDRAM Controller JTAG Controller
PowerPC
Reset Reset Block
32MB SDRAM OPB
BRAM Controller
GPIO
PLB BRAM (16KB)
GPIO
PLB2OPB Bridge
Clock DCM
User LEDs
DIP Switches
GPIO
Push Switches
UART
RS232 Port
Interrupt Controller SystemACE Controller
DSOCM Controller DSOCM BRAM (8KB)
SAM Header
Denotes Soft IP Complete system connectivity is described in the MHS file.
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System Interrupt Controller Interrupts were enabled for the UART and the SystemACE controller during design creation, so the BSB wizard automatically adds the OPB interrupt controller to the design and connects the interrupt output of the UART and the SystemACE controller to the interrupt controller inputs.
UART
UART Interrupt
The interrupt output of the interrupt controller is connected to the interrupt input of the processor by the BSB wizard.
Intr1
OPB Interrupt Controller SystemACE Interrupt SystemACE Controller
PowerPC
Intr0
The BSB wizard assigns a higher priority interrupt to the UART than the SystemACE controller by default. The interrupt priority can be modified in the MHS file.
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System UCF and Download Command File Double-click on the system.ucf file in the XPS GUI to open the file. This file is generated by the BSB wizard for the Memec P4-FG456 development board.
A command file called download.cmd is generated by the BSB wizard that describes the JTAG chain on the Memec P4-FG456 development board. This file is used by iMPACT to download a bit file to the FPGA. The JTAG chain on the Memec P4-FG456 board contains two devices, an ISP PROM and the FPGA. The FPGA is the second device in the JTAG chain.
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Xilinx PowerPC Development Workshop Setting Up Hardware Options
Embedded Processor Development Workshop
Setting Up Project Options 1
Invoke the Project Options dialog box from the XPS GUI.
3 Setting up simulation options such as the language and the simulator of choice. XPS supports ModelSim and NCsim simulators.
Note: Device information set by the BSB wizard based on the selected development board.
Note: User repository folder containing description of Memec development boards.
2
XPS generates a Makefile that is used to generate various outputs for the design. Users can point to a different Makefile with different implementation settings, if they choose to.
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Setting Up Project Options The hierarchy and flow of the design can be set to a top-level design and implemented using the XPS Xflow implementation.
4a
In this case, the entire FPGA design is implemented using the XPS GUI. Although, the top-level design is implemented using the XST synthesis tool, user IP cores can be implemented using a third-party synthesis tool and integrated into the design.
Alternately, the hierarchy and flow of the design can be set to a sub-module design and implemented using the ISE Project Navigator implementation.
4b
The FPGA design can then be completed using ISE-FND and the XST synthesis tool, or using ISE-ALI with a third-party synthesis tool. In the latter case, the sub-module design is instantiated in the top-level as a black-box and implemented using a third-party synthesis tool.
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Xilinx PowerPC Development Workshop Generating a Bit File
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Generating a Bit File for the Hardware Platform Invoke Generate Bitstream from the XPS GUI to generate a bit file for the hardware platform.
When Generate Bitstream is invoked by the user, XPS copies the bitgen.ut file from the /data/xflow folder into the /etc folder of the project directory. The bitgen.ut file and the fast_runtime.opt file (copied from the /data/xflow folder into the /etc folder) are used by XPS to generate a bit file for the hardware platform.
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Bit File Generation Results
Upon successful completion of the bit file generation, open the system.par file located in the /implementation folder of the project directory to review the results.
A section of the system.par file showing the FPGA utilization for this design.
A section of the system.par file showing possible timing errors that must be corrected before proceeding.
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Xilinx PowerPC Development Workshop Setting Up Software Options and Generating Software Libraries
Embedded Processor Development Workshop
Setting Up Software Options 1
Invoke the Software Platform Settings dialog box from the XPS GUI.
2
Each IP core used in the design is assigned a default software driver by the BSB wizard. User can assign a different driver version to these IP cores via the drop-down dialog box.
4 Application specific libraries such as xilnet for networking or xilmfs for file systems can be added to the design. Please refer to the oslib_rm.pdf document located in the EDK install directory for more information.
Embedded Processor Development Workshop
3 An optional OS can be used in a design. XPS supports Xilinx MicroKernel, Monta Vista Linux and VxWorks. Standalone OS implies NO OS is used. 40
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Setting Up Software Options
5
Processor parameters such as the compiler (powerpc-eabigcc) and debug option (-g) are set by the BSB wizard. The processor operating frequency is set by the user. These parameters are usereditable and can be set based on the applications needs. For example, the WindRiver Diab compiler can be used instead of the GNU complier.
6
The UART and the SystemACE controller interrupts are enabled for this design. This dialog box allows the user to specify an interrupt handler routine for each of these interrupts.
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Setting Up Software Options
7 Default device assigned as the standard input/output by the user during BSB wizard design creation.
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System MSS File Double-click on the system.mss file in the XPS GUI to open the file.
Upon completion of the software option settings, the system.mss file is written and saved in the XPS project directory. This file shows the software driver and driver version for each IP core in the design, set by the BSB wizard or modified by the user after the BSB design creation.
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Generating Libraries 1
After setting the software options, generate libraries for the design from the XPS GUI.
Folders in blue are created by the library generator while the rest of the folders are generated by BSB.
Project Directory Structure After Library Generation
bsb_demo (project directory)
system.mss
etc
TestApp
download.cmd fast_runtime.opt bitgen.ut
data
system.mhs
ppc405_0
system.ucf
src TestAppLinkScrs
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pcores
code
include
lib
libsrc
TestApp.c
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Generating Libraries Processor Instance Directory Structure After Library Generation
ppc405_0
code
lib
include
libsrc
!
ppc405_0 – This folder is created upon activation of the library generator and has the same
!
code folder – The code folder can be used to store the output of the compiler (executable.elf
!
include folder – The include folder contains the system header files generated by the library
!
lib folder – The lib folder contains the standard C library.
!
libsrc folder – The libsrc folder contains a copy of the software driver for each core in the
name as the processor instance name given by the BSB wizard.
file). The user can store this executable file in any user defined folder as well as the code folder.
generator. The xparameters.h header file located in this folder defines memory space for each peripheral in the system that is connected to the processor bus. The xparameters.h file will be described in the next few slides.
system. The library generator copied each driver from the EDK install directory to the libsrc folder.
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System Include File (xparameters.h) Double-click on the xparameters.h file in the XPS GUI to open the file. This include file shows how the I/O and memory devices are mapped into the processor memory. The xparameters.h file shows the default parameters associated with the UART in the system.
These #define statements in the xparameters.h file show how the components are mapped in the processor memory. These #define statements will be used by the main program to access peripherals connected to the processor bus.
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System Include File (xparameters.h) SystemACE controller can be configured to operate in the 16 or 8-bit mode. The default is set to 16-bit mode of operation, but it can be modified in the MHS file. Shows the number of interrupts in the system (UART and SystemACE controller). Shows the interrupts as edge- or level-sensitive. A “1” in the bit position indicates that the interrupt is edge-sensitive. In this case, UART is edge-sensitive while the SystemACE controller is level-sensitive.
These #define statements show the priority of the interrupts in the system. In this system, RS232 has higher priority than the SystemACE controller. This #define statement is used by software timers.
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Xilinx PowerPC Development Workshop Writing Application Software
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High-Level View of the Software Development Flow Develop the application software in C/C++
Compile and link the application software
Simulate the software (optional) Bit File
Bit File Generate an object file
No (.elf file)
FPGA
Does the code need to be loaded into the FPGA BRAM along with the bit file?
Yes (.elf file)
External Memory
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DATA2MEM Utility
FPGA
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BSB Generated Software Files Click on the Applications tab in the XPS GUI to view the software files generated by the BSB wizard.
The system include file used by the compiler.
Output of the compiler, generated when the TestApp.c file is compiled.
Linker script generated by the BSB wizard. It can be replaced with a user created linker script.
Main program generated by the BSB wizard. This program is used to test the hardware platform generated by the BSB.
User header files are included in the project by right-clicking on the Headers and selecting Add File.
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A bootloop is a software application that keeps the processor in a defined state until the actual application can be downloaded and run.
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Linker Script Double-click on the TestAppLinkScr linker script file in the XPS GUI to open it.
A section of the BSB-generated linker script showing how the output of the compiler will be mapped to the physical memory when the TestApp.c program is compiled. As shown, the processor code and data will be stored in the BRAM connected to the PLB and the ISOCM bus.
The BSB wizard automatically maps the processor interrupt vector table for this design to the ISOCM memory, because the interrupt vector table needs to be on a 64K boundary. The BSB wizard maps the interrupt vector table to the OCM BRAM, because the PLB memory for this design: ! Needs to cover the processor reset vector at address 0xFFFFFFFC ! The size of the memory is 16KB (set by the user) Based on the above requirements the PLB memory must be mapped to the memory space 0xFFFFC000 – 0xFFFFFFFF, hence it cannot be placed on a 64K boundary.
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Linker Script 1
After creating the design using the BSB wizard, if the hardware platform is modified and more memory is added to the system, or if there is a need to change the memory map of the compiler output, a new linker script can be generated from the XPS GUI.
3
Set the Stack and Heap sizes
2 Make modifications to the sections and assign each section to the SDRAM, PLB or OCM BRAM (default SDRAM). The size of each section is shown as zero, because the TestApp.c program has not been compiled yet.
Embedded Processor Development Workshop
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Click on “Generate” to generate a new linker script. 52
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Main Program Double-click on the TestApp.c in the XPS GUI to open the file.
The TestApp.c header file #include statements. The xcache_I.h header file is included because cache was enabled during the design creation using the BSB wizard.
A section of the TestApp.c program showing the memory test routine. The BSB wizard includes the cache enable function calls in the main procedure of the TestApp.c program, if the cache is enabled. Each bit of the 32-bit value passed to these functions enables 128MB of the processor 4GB memory space. The MSB corresponds to memory space 0x000000000x01FFFFFF (SDRAM memory space).
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Compiler Options 1
Right-click on Compiler Options and then select Set Compiler Options… to invoke the Set Compiler Settings dialog box.
Note: Defaults to the “Environment” tab.
Note: For PPC applications, the processor mode is always Executable.
2 If a linker script is not used, the Program Start Address in the memory, the Stack Size and the Heap Size can be defined here.
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Compiler Options 3
5
Click on the “Optimization” tab.
Can be used to further optimize the code.
4 Set the optimization to “No Optimization” for debugging and also set the debug option to “Create symbols for debugging”. After debugging the code, the optimization can be set to levels 1-3 to optimize the memory usage and also speed up the execution time.
6 Click on the “Directories” tab.
7 Points to the location of the linker script generated by the BSB wizard. User can use this field to point to a different linker script file.
8
Points to the location of the compiler output file. User can set this to point to any folder in or outside of the project directory.
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User-Created Main Program
Write the application software in C/C++.
Write a linker script for the application or use the BSBgenerated linker script (optional).
Add a new software project to the XPS design and associate the new application software with this project.
Set compiler options for the new software project and compile/link the source files.
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Adding Software Projects to the Design 1
Note: A new software project called Applications will be added to the project. This new project can be used to load a different program into the processor memory (internal or external).
Click on the Applications tab and then right-click on the Software Projects and select Add SW Application Project…
2a
Note: The arrow next to the project name means the compiler output for this project will be loaded into the FPGA Block RAM along with the bit file.
Enter a software project name.
5 Set compiler options. Add a linker script and source and header files.
2b
This software project can be used to run a new program on the board.
Select a processor instance. This is only applicable in multiprocessor designs.
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Xilinx PowerPC Development Workshop Compiling/Linking the Application Software
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Compiling the Program 1
After setting the compiler options, compile the program sources from the XPS GUI. Compilation results are shown in the XPS GUI. Total required memory
Code size Stack size
Data size
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Xilinx PowerPC Development Workshop Initializing the FPGA BRAM with the Program
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Initializing the FPGA BRAM with the Program 1
The Update Bitstream command needs to be executed if user program or PPC bootloop needs to be loaded into the FPGA along with the bit file.
The hardware platform bit file (default system.bit) is stored in the /implementation folder of the project directory.
DATA2MEM
The Block RAM Memory Map file (default system_bd.bmm) is located in the /implementation folder of the project directory.
Block RAM Memory Map (project_name_bd.bmm)
Compiler Output File (output_name.elf)
The compiler output file (default executable.elf).
DATA2MEM Utility
The output of the DATA2MEM utility (download.bit file) contains the bit file for the hardware platform and the Block RAM initialization data (processor code/data).
Embedded Processor Development Workshop
Hardware Platform Bit File (project_name.bit)
DATA2MEM Output File (download.bit)
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Xilinx PowerPC Development Workshop Downloading the Bit File
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Downloading the Bit File Download the download.bit file to the target board using the XPS GUI. A program called iMPACT uses the download.cmd file located in the /etc folder to download the bit file.
Output of the TestApp.c program running on the Memec P4-FG456 development board. The Hyper Terminal is set to 9600 baud, 8-bits, one stop bit, no parity and no hardware flow control.
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Xilinx PowerPC Development Workshop Adding an IP Core to the Design
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Design Flow for Adding IP
1
Start XPS and invoke Add/Edit Cores dialog box
2
Add an IP core to the design
3
Connect the IP core to the processor bus
4
Specify address space for the IP
5
Connect the ports of the IP
6
Specify parameters for the IP
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Adding an IP Core to the Design 1
Open the project and select Add/Edit Cores… from the Project menu.
2a Select a bus to connect a core to.
2b Select a component type
2e The IP is added to the design with default instance name of opb_uartlite_0
2c Select an IP from the list.
2d Embedded Processor Development Workshop
Add the IP to the design.
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Connecting the IP Core to the OPB 3a Select the “Bus Connections” tab.
3b Under the “opb” column, click next to the “opb_uartlite_0 sopb” row, an “s” will appear indicating that the UART IP is a slave device to the OPB.
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Assigning Address Space to the IP Core 4a
Select the “Addresses” tab.
4b A default address space is assigned to the opb_uartlite_0 IP, however, this address space does not fall within the OPB address space (0xc27fe000 – 0xc27fefff) and it must be modified. Place a check mark next to the address space for all devices except the opb_uartlite_0.
4c Click on Generate Addresses.
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Assigning Address Space to the IP Core
4d A new address space is assigned to the opb_uartlite_0 IP core.
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Adding Ports of the IP Core to the Design 5d
Click on
