X5043, X5045
®
4K, 512 x 8 Bit Data Sheet
March 16, 2006
FN8126.2
CPU Supervisor with 4K SPI EEPROM
Features
These devices combine four popular functions, Power-on Reset Control, Watchdog Timer, Supply Voltage Supervision, and Block Lock Protect Serial EEPROM Memory in one package. This combination lowers system cost, reduces board space requirements, and increases reliability.
• Low VCC Detection and Reset Assertion - Four standard reset threshold voltages 4.63V, 4.38V, 2.93V, 2.63V - Re-program low VCC reset threshold voltage using special programming sequence. - Reset signal valid to VCC = 1V
Applying power to the device activates the power-on reset circuit which holds RESET/RESET active for a period of time. This allows the power supply and oscillator to stabilize before the processor executes code. The Watchdog Timer provides an independent protection mechanism for microcontrollers. When the microcontroller fails to restart a timer within a selectable time out interval, the device activates the RESET/RESET signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The device’s low VCC detection circuitry protects the user’s system from low voltage conditions, resetting the system when VCC falls below the minimum VCC trip point. RESET/RESET is asserted until VCC returns to proper operating level and stabilizes. Four industry standard VTRIP thresholds are available, however, Intersil’s unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the threshold for applications requiring higher precision. The memory portion of the device is a CMOS Serial EEPROM array with Intersil’s block lock protection. The array is internally organized as 512 x 8. The device features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple four-wire bus. The device utilizes Intersil’s proprietary Direct Write™ cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years.
• Selectable Time Out Watchdog Timer • Long Battery Life with Low Power Consumption - 3.3V, IOH = –1.0mA
VCC - 0.8
V
VOH2
Output HIGH Voltage (SO)
2V < VCC ≤ 3.3V, IOH = –0.4mA
VCC - 0.4
V
VOH3
Output HIGH Voltage (SO)
VCC ≤ 2V, IOH = –0.25mA
VCC - 0.2
V
VOLRS
Output LOW Voltage (RESET, RESET)
IOL = 1mA
VIL
VIH
Capacitance COUT CIN
(2)
V
TA = +25°C, f = 1MHz, VCC = 5V
SYMBOL (2)
0.4
TEST Output Capacitance (SO, RESET, RESET) Input Capacitance (SCK, SI, CS, WP)
CONDITIONS
MAX
UNIT
VOUT = 0V
8
pF
VIN = 0V
6
pF
NOTES: 1. VIL min. and VIH max. are for reference only and are not tested. 2. This parameter is periodically sampled and not 100% tested. 3. SCK frequency measured from VCC x 0.1/VCC x 0.9
13
FN8126.2 March 16, 2006
X5043, X5045 Equivalent A.C. Load Circuit at 5V VCC 5V
A.C. Test Conditions 5V 4.6kΩ
1.64kΩ Output
Input pulse levels
VCC x 0.1 to VCC x 0.9
Input rise and fall times
10ns
Input and output timing level
VCC x 0.5
RESET/RESET
1.64kΩ
30pF
30pF
AC Electrical Specifications
(Over recommended operating conditions, unless otherwise specified) 2.7V–5.5V
SYMBOL
PARAMETER
MIN
MAX
UNIT
0
3.3
MHz
DATA INPUT TIMING fSCK
Clock Frequency
tCYC
Cycle Time
300
ns
tLEAD
CS Lead Time
150
ns
tLAG
CS Lag Time
150
ns
tWH
Clock HIGH Time
130
ns
tWL
Clock LOW Time
130
ns
tSU
Data Setup Time
30
ns
tH
Data Hold Time
30
ns
tRI(4)
Input Rise Time
2
µs
tFI(4)
Input Fall Time
2
µs
tCS
CS Deselect Time
tWC(5)
Write Cycle Time
100
ns 10
ms
MIN
MAX
UNIT
0
3.3
MHz
Data Output Timing 2.7–5.5V SYMBOL
PARAMETER
fSCK
Clock Frequency
tDIS
Output Disable Time
150
ns
Output Valid from Clock Low
120
ns
tV tHO
0
ns
Output Rise Time
50
ns
(4)
Output Fall Time
50
ns
tRO tFO
Output Hold Time
(4)
NOTES: 4. This parameter is periodically sampled and not 100% tested. 5. tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle.
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FN8126.2 March 16, 2006
X5043, X5045 Serial Output Timing CS tCYC
tWH
tLAG
SCK tV MSB Out
SO
SI
tHO
tWL
tDIS
MSB–1 Out
LSB Out
ADDR LSB IN
Serial Input Timing tCS CS tLEAD
tLAG
SCK tSU
tH MSB In
SI
tRI
tFI
LSB In
High Impedance SO
Symbol Table WAVEFORM
INPUTS
OUTPUTS
Must be steady
Will be steady
May change from LOW to HIGH
Will change from LOW to HIGH
May change from HIGH to LOW
Will change from HIGH to LOW
Don’t Care: Changes Allowed
Changing: State Not Known
N/A
Center Line is High Impedance
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FN8126.2 March 16, 2006
X5043, X5045 Power-Up and Power-Down Timing VCC
VTRIP
VTRIP tPURST
0 Volts
tPURST
tF
tR
tRPD
RESET (X5043)
RESET (X5045)
RESET Output Timing SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
VTRIP
Reset Trip Point Voltage, (-4.5A) Reset Trip Point Voltage, (Blank) Reset Trip Point Voltage, (-2.7A) Reset Trip Point Voltage, (-2.7)
4.5 4.25 2.85 2.55
4.62 4.38 2.92 2.62
4.75 4.5 3.0 2.7
V
tPURST
Power-up Reset Time Out
100
200
400
ms
500
ns
tRPD tF
(6)
VCC Detect to Reset/Output
(6)
VCC Fall Time
10
µs
(6)
VCC Rise Time
0.1
ns
Reset Valid VCC
1
V
tR
VRVALID NOTE:
6. This parameter is periodically sampled and not 100% tested.
CS/WDI vs. RESET/RESET Timing CS/WDI tCST RESET (5043) tWDO
tRST
tWDO
tRST
RESET (5045)
RESET/RESET Output Timing SYMBOL
MIN
TYP
MAX
UNIT
Watchdog Time Out Period, WD1 = 1, WD0 = 1 (default) WD1 = 1, WD0 = 0 WD1 = 0, WD0 = 1 WD1 = 0, WD0 = 0
100 450 1
OFF 200 600 1.4
300 800 2
ms ms sec
tCST
CS Pulse Width to Reset the Watchdog
400
tRST
Reset Time Out
100
tWDO
PARAMETER
16
ns 200
400
ms
FN8126.2 March 16, 2006
X5043, X5045 VTRIP Programming Timing Diagram VCC (VTRIP)
VTRIP tTSU
tTHD
VP WP tVPS
tVPH
tPCS
CS
tVPO
tRP
SCK
SI 06h
02h
01h or 03h
VTRIP Programming Parameters PARAMETER
DESCRIPTION
MIN
MAX
UNIT
tVPS
VTRIP Program Enable Voltage Setup time
1
µs
tVPH
VTRIP Program Enable Voltage Hold time
1
µs
tPCS
VTRIP Programming CS inactive time
1
µs
tTSU
VTRIP Setup time
1
µs
tTHD
VTRIP Hold (stable) time
10
ms
tWC
VTRIP Write Cycle Time
tVPO
VTRIP Program Enable Voltage Off time (Between successive adjustments)
0
µs
tRP
VTRIP Program Recovery Period (Between successive adjustments)
10
ms
VP
Programming Voltage
15
18
V
VTRIP Programmed Voltage Range
1.7
4.75
V
VTRIP Program variation after programming (0-75°C). (Programmed at 25°C.)
-25
+25
mV
VTRAN Vtv
10
ms
VTRIP programming parameters are periodically sampled and are not 100% tested.
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FN8126.2 March 16, 2006
X5043, X5045 Packaging Information 8-Lead Miniature Small Outline Gull Wing Package Type M
0.118 ± 0.002 (3.00 ± 0.05) 0.012 + 0.006 / -0.002 (0.30 + 0.15 / -0.05)
0.0256 (0.65) Typ.
R 0.014 (0.36) 0.118 ± 0.002 (3.00 ± 0.05)
0.030 (0.76) 0.0216 (0.55)
0.036 (0.91) 0.032 (0.81)
0.040 ± 0.002 (1.02 ± 0.05)
7° Typ.
0.008 (0.20) 0.004 (0.10)
0.0256" Typical
0.150 (3.81) Ref. 0.193 (4.90) Ref.
0.007 (0.18) 0.005 (0.13)
0.025" Typical 0.220"
FOOTPRINT
0.020" Typical 8 Places
NOTE: 1. ALL DIMENSIONS IN INCHES AND (MILLIMETERS)
18
FN8126.2 March 16, 2006
X5043, X5045 Packaging Information 8-Lead Plastic Dual In-Line Package Type P
0.430 (10.92) 0.360 (9.14)
0.260 (6.60) 0.240 (6.10) Pin 1 Index Pin 1 0.300 (7.62) Ref.
Half Shoulder Width On All End Pins Optional
0.145 (3.68) 0.128 (3.25)
Seating Plane
0.025 (0.64) 0.015 (0.38) 0.065 (1.65) 0.045 (1.14)
0.150 (3.81) 0.125 (3.18)
0.110 (2.79) 0.090 (2.29)
.073 (1.84) Max.
Typ. 0.010 (0.25)
0.060 (1.52) 0.020 (0.51)
0.020 (0.51) 0.016 (0.41)
0.325 (8.25) 0.300 (7.62)
0° 15°
NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
19
FN8126.2 March 16, 2006
X5043, X5045 Packaging Information 8-Lead Plastic Small Outline Gull Wing Package Type S
0.150 (3.80) 0.228 (5.80) 0.158 (4.00) 0.244 (6.20) Pin 1 Index Pin 1
0.014 (0.35) 0.019 (0.49) 0.188 (4.78) 0.197 (5.00) (4X) 7°
0.053 (1.35) 0.069 (1.75) 0.004 (0.19) 0.010 (0.25)
0.050 (1.27)
0.010 (0.25) X 45° 0.020 (0.50)
0.050"Typical
0.050" Typical
0° - 8° 0.0075 (0.19) 0.010 (0.25)
0.250"
0.016 (0.410) 0.037 (0.937)
FOOTPRINT
0.030" Typical 8 Places
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
20
FN8126.2 March 16, 2006
X5043, X5045 Packaging Information 14-Lead Plastic, TSSOP, Package Type V .025 (.65) BSC
.169 (4.3) .252 (6.4) BSC .177 (4.5)
.193 (4.9) .200 (5.1)
.047 (1.20) .0075 (.19) .0118 (.30)
.002 (.05) .006 (.15)
.010 (.25) Gage Plane 0° - 8°
Seating Plane .019 (.50) .029 (.75) Detail A (20X)
.031 (.80) .041 (1.05) See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 21
FN8126.2 March 16, 2006
