7iJct ctroηά roηά COMMITTED TO E XCELLEN CE

WA R N I N G THE F O LL OWI N G S E RVICI N G I N STRU CTIO N S ARE FO R U S E B YQ U A LI F I E D P E R SO NNEL ONL Y. TO AVOID P E R SO N A L I NJUR Y , DO NOT PERFO RM ANY S ERVICI NG OT HER THAN THAT CO N TAI N E D IN O PER ATI N G I N STRU CTIO N S U N L E SS YO U AR E Q U A L I F I ED TO DO SO.

I

PL EAS E C HE C K FO R C HA NG E NF O RMATIO N AT THE R EA R O F THIS MA NU A L .

492/492 Ρ S PE CT RU M AN A L YZ ER

PORTABLE / R AC KM O UN TI BEN C H TO P

(S N β030000 & UP) S ERV IC E V O LUME 1

INSTRUCTION Tektronix, Inc . Ρ. Ο. Box 500 97077 Bea v erto n, Orego n 070-3783-01 Product Grou p 26

MANUAL

Serial Number .

F irst P rinting Revised F EB

FEB 1981 1982

Co p yrig h t ` 1979, 1980, 1981 Te k tronix, Inc . All rig h ts reserve d . Contents of t h is p ublicatio n may not be reproduce d in any form without t h e writte n permission of Te k tronix, I n c . I n c. and its subsi d iaries are covered by U .S. and foreign patents a n d /or p en d ing patents . P ro d ιιcts of Te k tronix,

are T EK T R O NIX, ΤΕΚ , SCO PE-M O B I LE, and registered tra d emar k s of Te k tro n ix, I n c. T ELE Q U I PΜΕΝΤ is α registere d trademar k of Te k tro n ix U .K . Li m ite d . P rinte d i n U .S .A . S p ecification privileges are reserve d .

a nd

p rice

c h ange

492/492Ρ Serv ice Vol . Ι (SN Β030000 & up)

TA BLE O F CO N TEN TS T his manual is divided into two volumes as follows:

VO LUME 1

Page

Page

LIST OF ILLUSTRATIONS LIST OF TABLES . . . . . . .

. . . . . . . . . . . ......... . . . . . . . . . . . ..... . . . . SERVICING SAFETY SUMMARY. . . . . . . . . . . . . . . Section 1

vi ix χ

GENERAL INFORMATION AND SPECIFICATION GENERAL INFORMATION . . . . . . . . . . Introduction . . . . . . . . . . . .... . . . . Product Service . . . . . . . . . . . . . . . . Instrument Construction . . . . . . . . . . Elapsed Time Meter . . . . . . . . . . . . . Changing P ower Input Range . . . . . R eplacing Fuses . . . . . . . . . . . . . . . . Selected Components . . . . . . . . . . . Component Circuit Numbering Scheme . . . . . . . . . . . . . . . . . . . . . . Firmware Version and Error Message Readout . . . . . . . . . . . . . . R ackmount/Benchtop Versions . . . . SPECIFICATION. . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . Frequency Related . . . . . . . . . Amplitude Related . . . . . . . . . . Input Signal Characteristics . . Output Signal Characteristics . General Characteristics . . . . . . Power Requirements. . . . . . . .

Envi ronmental

Characteristics . . . Physical Characteristics . . . . . . . .

ACCESSORIES. OPTIONS . . . . . Option 01 . . . Option 02 . . . Option 03 . . . Option 08 . . .

. . . . . .

. . . . . .

. . . . . .

. . . . . .

. . . . . .

. . . . . .

. . . . . .

. . . . . .

. . . . . .

. . . . . .

. . . . . .

. . . . . .

. . . . .. . . . . . . .

. . . . . .

. . . . . .

. . . . . .

. . . . . .

Optio n 20 . . . . . . . . . . . . . . . . . . . . . Optio n 21 . . . . . . . . . . . . . . . . . . . . . Optio n 22 . . . . . . . . . . . . . . . . . . . . .

1-1 1-1 1-1 1-1 1-2 1-2 1-2 1-2 1-3 1-3 1-3 1-4 1-4 1-4 1-7 1-10 1-10 1-11 1-11

1-12 1-13

1-14 1-14 1-14 1-17 1-17 1-18

1-18 1-19 1-19

Options 30, 31, 32 . . . . . . . . . . . . . . 1-19 Optio ns fo r power cord

configurations . . . . . . . . . . . . . . . . . . 1-20

REV AUG 1981

Section 2

Section 3

INSTALLATION AND REPACKAGING Introduction . . . . . . . . . . . . . . . . . . . Unpackaging and Initial Inspection . Preparation for U se . . . . . . . . . . . . Power Source and Power Requirements . . . . . . . . . . . . . . . . . Repackaging for Shipment . . . . . . .

. 2-1 . 2-1 . 2-1

CALIBRATION Introduction . . . . . . . . . . . . . . . . . . . History Information . . . . . . . . . . . . . Equipment Required . . . . . . . . . . . . PERFORMANCE C HECK PROCEDURE . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . Incoming Inspection Test . . . . . . . . Verification of Tolerance Values. . . . . . . . . . . . . . . Preliminary Preparation . . . . . . . . . 1 . Check Operation of Front P anel Push-buttons and Controls . . . . 2. Check Frequency R eadout Accuracy for 492/492Ρ and Tune Accuracy for 492P Only . . 2Α. 492Ρ O nly-TUNE Accuracy

. 2-1 . 2-2

. 3-1 . 3-1 . 3-1 . 3-4 . 3-4 . 3-4 . 3-4 . 3-4 . 3-4 . 3-7

Ch eck . . . . . . . . . . . . . . . . . . . . . . 3 . Ch eck Calibrato r . . . . . . . . . . . . .

4. Check RF Attenuator . . 5. Check IF Gain Accuracy 6. Check Display Accuracy Range . . . . . . . . . . . . . . 7. Amplitude Variation with in Resolution Bandwidth

. ...... . ...... and . ..... . Change . ... . . .

8 . C hec k Fre q ue ncy Respon se. . . . . 9 . C hec k Preselector U lti m ate Rejectio n . . . . . . . . . . . . . . . . . . .

3-8 3-10

3-11 3-12 3-14 3-14 3-15 3-20

10 . Check Frequency Span /Div Accuracy . . . . . . . . . . . . . . . . . . 3-20 11 . Check Time/Dίν Accuracy . . . . . 3-22 12. Check Pulse Stretcher. . . . . . . . 3-23

492/492Ρ Service Vol . 1 (SN Β030000 & up)

TA BLE OF CO N T EN TS (cont) Section 3

CAL IBRATIO N (cont)

Page

13 . Check Resol ution Bandwidth and Shape Factor . . . . . . . . . . . 14 . Chec k Sensitivity . . . . . . . . . . . . 15 . Frequency Drift . . . . . . . . . . . . . 16 . Chec k Residual FM . . . . . . . . . . 17 . Chec k Inte rmodulation Distortion . . . . . . . . . . . . . . . . . . 18 . Chec k Harmo nic Distortion . . . . 19 . Chec k Noise Sidebands . . . . . . 20 . C h ec k R esidual Res pon se . . . . 21 . C h ec k LO Emission Out the RF I NPUT . . . . . . . . . . . . . . . . . . . . 22 . C h ec k Digital Storage (Option 02) . . . . . . . . . . . . . . . . . 23 . C h eck Triggeri ng Operation and Se nsitivity . . . . . . . . . . . . . . 24 . Check Exte rn al Sweep Operation . . . . . . . . . . . . . . . . . . 25 . C h eck Vertical Output . . . . . . . . 26 . C h eck Horizontal Signal Output . . . . . . . . . . . . . . . . . . . . 27 . 492 Ρ GP IB Verification Prog ram . . . . . . . . . . . . . . . . . . . ADJU ST MENT PR OC EDURE . . . . . . . 1 . Check an d Adjust Low Voltage Power Supply . . . . . . . . . . . . . . . 2 . Crt Display (Z-Axis board) . . . . . . 3 . Deflection Am plifier (gain and frequency response) . . . . . . . 4 . Adj ust Sweep Timing . . . . . . . . . 5 . Cali brate 1st L O System and Center Frequency Co n t rol . . . . . . 6. Chec k 2nd L O Frequ ency and Ad just Tuning Range . . . . . . . . . . 7. Ad just 1st Converter Bias . . . . . . 8. Baseline Leveling (Video

3-28 3-29 3-30 3-30 3-31 3-31 3-31 3-32 3-34 3-34 3-34 3-42 3-43 3-44 3-45 3-47 3-50 3-53 3-57

. 3-61

. 3-63 . . . .

3-66 3-68 3-68 3-69

Level . . . . . . . . . . . . . . . . . . . . . 3-71

Page

CA LIBR ATION (cont) 16 . B and Leveling for Coaxial B an ds (Ba n ds 1-5) . . . . . . . . . . . . . . . 17 . B and Leveling for W avegui de B ands (Bands 6-11) . . . . . . . . 18 . Preselecto r Driver (Option 01) Calibration . . . . . . . . . . . . . . . . . 19 . Ph aseloc k Cali bration . . . . . . . .

3-23 3-24 3-26 3-27

Processor) . . . . . . . . . . . . . . . . . . 3-58

9. Log Am plifier Cali bration . . . . . . 10 . Calibrating Resolution B andwidt h an d Shape Facto r . . . . . 11 . Presetting Varia ble Resolutio n Gain a nd B an d Leveling . . . . . 12 . Calibrator Output Level . . . . . . 13 . IF Gain Cali bration . . . . . . . . . . 14 . Digital Storage Cali bration . . . 15 . Setting Β-SAVE Α Reference

Sectio n 3

Sectio n 4

MAI NTEN ANCE

Introduction . . . . . . . . . . . . . . . . . . . . Static-Sensitive Components . . . . . . PREVENTI VE MAI NTEN AN CE. . . . . . . Ela psed Time M eter . . . . . . . . . . . . . Cleaning . . . . . . . . . . . . . . . . . . . . . . Lubricatio n . . . . . . . . . . . . . . . . . . . . Service Fixtures and Tools for M ai ntenance . . . . . . . . . . . . . . . . . . . Visual Inspection . . . . . . . . . . . . . . . Transistor and Integrated Ci rcuit Chec ks . . . . . . . . . . . . . . . . . . . . . . . Perfo rmance Checks and Recalibration . . . . . . . . . . . . . . . . . . . TROUBLESHOOTI NG. . . . . . . . . . . . . . Troub leshooting Ai ds . . . . . . . . . . . . General Trou bles hooting Techn iques . . . . . . . . . . . . . . . . . . . . CO RRECTIVE MAI NTEN ANC E . . . . . . Obtaining Replacement P arts . . . . . . Parts Repair and Return P rogram . . Soldering Techn iq ues . . . . . . . . . . . . Replaci ng Square Pin fo r Mu lti-pin Connectors . . . . . . . . . . . . . . . . . . . . Selected Components . . . . . . . . . . . Installing M atched Crystals for the VR 100 Hz Filte rs . . . . . . . . . . . . . . . Replacing EPROM 's or ROM 's . . . . Firmware Version and Error M essage Readout . . . . . . . . . . . . . . Servicing the VR Mod ule . . . . . . . . . REPLACI NG ASSEMBL IE S AND SUB ASSEMBLIES . . . . . . . . . . . . . . . . Removing and Replacing Semi-rigid Coaxial Cables . . . . . . . . . . . . . . . . . Replacing the Dual Diode Assembly Replacing the Crt . . . . . . . . . . . . . . .

3-71 3-72 3-73 3-76

4-1 4-1 4-2 4-2 4-2 4-2 4-2 4-3 4-3 4-3 4-3 4-3 4-5 4-7 4-7 4-7 4-7 4-7 4-8 4-8 4-8 4-8 4-8 4-10 4-10 4-10 4-10

REV AUG 1981

492/492Ρ Service Vol. Ι (SN Β030000 & up)

TA BLE OF CO N T EN TS (cont) Sectio n 4

P age

MAINTENANCE (cont) Repai ring the Crt Trace Rotation Coil . . . . . . . . . . . . . . . . . . . . . . . . . . Fro nt P anel Assembly . . . . . . . . . . . Front P anel Board . . . . . . . . . . . . . . Replaci ng Front- Panel Push Butto n Switches . . . . . . . . . . . . . . . . . . . . . . Main P ower Supply M od ule . . . . . . . H ig h Voltage P ower Supply . . . . . . . Replaci ng the 1 st (YIG) L ocal Oscillator Interface B oa rd . . . . . . . . . Compliant M oun ted Fan . . . . . . . . . . M AI NTEN AN CE AD JU ST MENTS . . . . 110 MH z I F Assembly Return Loss Calibratio n. . . . . . . . . . . . . . . . . . . . . 2072 MH z 2nd Co nverter . . . . . . Fou r Cavity F ilter . . . . . . . . . . . . . M ixer . . . . . . . . . . . . . . . . . . . . . . 110 MH z Thr ee Cavity Filter . . . . 829 MHz Converter M ai nte nance . . . . . 1 . To gain acceses to the LO section . . . . . . . . . . . . . . . . . . . . . 2 . To gain access to the IF section . . . . . . . . . . . . . . . . . . . . . 3. 719 MHz Oscillator Range Ad justment . . . . . . . . . . . . . . . . . 4. 829 MHz Coaxial B an dpass F ilter Ad justment . . . . . . . . . . . . . . . . . Troubles hooting a n d Calibrating the 2182 MH z Phaselock ed 2nd LO . . . Oscillator Section . . . . . . . . . . . . . . . . . 1 . Prepa ration . . . . . . . . . . . . . . . . . 2. Adjust and C h ec k Oscillator Frequency . . . . . . . . . . 3. M easure Output Power . . . . . . . . 4. Chec k t he 2200 MH z Reference M ixer . . . . . . . . . . . . . 5. Chec k Tune Range . . . . . . . . . . . 6. Reassem bly . . . . . . . . . . . . . . . . . Troubles hooting and Cali brating th e 14-22 1 . 3. 4. 5. 6.

REV AUG 1981

LO

7. Check and Cali brate Tune Se nsitivity . . . . . . . . . . . . . . 8. Conclusion . . . . . . . . . . . . . . . . . . Troubleshooting Aids for the 2182 MHz Ph aseloc ked 2n d LO . . . . . . . . . . . . . . . M IC ROCOMPUTER SYST EM M AI NTEN ANCE . . . . . . . . . . . . . . . . . . M emory Board Option Switch . . . . . P ower-U p Self-Test M ode . . . . . . . . M icrocomputer Test Mode . . . . . . . . Instrument B us Check Mode . . . . . . F irmware Operati ng Notes . . . . . . . . Exceptions for Firmware Version 8.2 . . . . . . . . . . . . . . . . . . . . Exceptions fo r Firmware Versions 8 .2, 8.7 and 8.8 . . . . . . . . . Exceptio ns for Firmware Versio n 1 .1 (492 Ρ only) . . . . . . . . . . Exceptions for F irmware Versions 1 .1 and 1 .2 i n 492Ρ only . . Changes incorporated in Version 1 .2 F irmware . . . . . . . . . . . . TR OUBLE SHOOTI NG ON THE I NST RUMENT BU S . . . . . . . . . . . . . . . Instrument B us Data Transfers . . . . Instrument B us Registers . . . . . . . . .

4-14 4-14 4-14 4-15 4-15 4-16 4-16 4-16 4-18 4-18 4-18 4-19 4-19 4-19 4-20 4-20 4-20 4-20 4-21 4-24 4-26 4-26 4-26 4-27 4-28 4-28 4-28

Sectio n 5

THE ORY OF OPERATIO N Fu nctional and General Descri ption Detailed Description 1st Co nverter . . . . . . . . . . . . . . . RF I nterface Ci rcuits . . . . . . . RF Circuitry . . . . . . . . . . . . . . 2nd Converter. . . . . . . . . . . . . . . 2072 MHz 2nd Co nverter . . . 2182 MHz Ph aseloc k ed 2nd

Sectio n

Page

M AI NTEN ANCE (cont)

4-33 4-33 4-34 4-35 4-35 4-36 4-37 4-38 4-38 4-39 4-40 4-40 4-41 4-41 4-41 4-41 4-44

. . . 5-1 5-3 . . . 5-3 . . . 5-4 . . . 5-5 . . . 5-6 . . . 5-8

LO . . . . . . . . . . . . . . . . . . . . .

Assembly . . . . . . . . . . . .

4-29

General Descri ption . . . . . . . . .

Preliminary . . . . . . . . . . . . . . . . . . Chec k Voltages . . . . . . . . . . . . . . C hec k Tu n e Linearity . . . . . . . . . . Coarse Linearity Adj ustment . . . . Fine Li n ea rity Adj ustme nt . . . . . . Set th e Center Frequen cy of t h e 14-22 MHz Oscillator . . . .

4-30

2182

4-30

Oscillator . . . . . . . . . . . . . . . . .

4-30

2200

4-31

2200

4-32

14-22

of t h e 2nd 2.

MH z Phaselock

Sectio n 4

MHz

Refe re n ce Boar d . MHz R efere n ce M ixe r . MHz

829

5-10 5-10

.

5-11

.

5-11

MH z Ph aselock B oard .

5-11

Cavity 2nd 4-33

M ic r ostrip

5-10

LO Local

MHz 2 n d

Oscillator . .

5-12

Co n verter . . . . . . .

5-13

III

492/492P Service Vol. Ι (SN Β030000 & up)

TA BLE O F CONT EN TS (cont) Page

Page Section 5

110 MHz IF Amplifier and 3rd Co nverter . . . . . . . . . . . . . . . . . . . . 110 MHz IF Amplifier . . . . . . . . . . 110 MHz Bandpass Filter . . . . . . 3rd Converter . . . . . . . . . . . . . . . . . . IF Section . . . . . . . . . . . . . . . . . . . . . Variable Resol u tion Section. . . . . Logarithmic Am plifier and Detector . . . . . . . . . . . . . . . . . . . . Display Section . . . . . . . . . . . . . . . . . Functio nal Description . . . . . . . . . Amplifier ......... . . . . . . Video Video Processor . . . . . . . . . . . . . Digital Storage . . . . . . . . . . . . . . . Vertical Section . . . . . . . . . . . . Horizontal Section . . . . . . . . . . Deflection Amplifiers . . . . . . . . . . Ζ-Axis Circuits . . . . . . . . . . . . . . . H ig h Voltage Supply . . . . . . . . . . Crt R eadout . . . . . . . . . . . . . . . . Frequency Co ntrol Section. . . . . . . . Sweep . . . . . . . . . . . . . . . . . . . . . Span Attenuator . . . . . . . . . . . . . 1st Local Oscillator Driver . . . . . . Preselector Driver . . . . . . . . . . . . Sweep Shaper and B ias Ci rcuits. Ce nter Frequency Control . . . . . . Phaselock System (Option 03) . . . . . Functional Desc ription . . . . . . . . . Ph aselock Control . . . . . . . . . . . . Error Am plifier and Synthesizer. . Controlled Oscillator, Offset M ixer, and Strobe Driver . . . . . . . Digital Control . . . . . . . . . . . . . . . . . . Processor. . . . . . . . . . . . . . . . . . . Memory B oard . . . . . . . . . . . . . . . F ront P anel . . . . . . . . . . . . . . . . . Accessories Interface B oard . . . . M ain Power Supp ly and Fan Driver .

iv

Sectio n 5

THEORY OF OPER ATION (cont) 5-20 5-20 5-21 5-22 5-23 5-23 5-29 5-31 5-31 5-33 5-35

5-38 5-39 5-43 5-45 5-46 5-47 5-48 5-55 5-55 5-58 5-61 5-63 5-66 5-67 5-70 5-70 5-71 5-73 5-76 5-77 5-78 5-87 5-88 5-94 5-94

THEORY OF O PERATION (cont) Main Power Supply . . . . . . . . . . . 5-94 492Ρ G ENER AL PURPOS E INTERFACE BUS . . . . . . . . . . . . 5-98

Section β

RACKMOUNT/ ΒΕΝCΗΤΟΡ VERSIONS

Introduction . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . Standard Accessories . . . . . . . . . . . . . . Optional Accessories . . . . . . . . . . . . . . . R ackmo unting Installation Dime nsions . Slide-Out Tracks . . . . . . . . . . . . . . . . . . Mounti ng Procedure . . . . . . . . . . . . . Alternate R ear M ounting Met hods. . Slide-ou t Track Lubrication . . . . . . . . Removing or Installing the 492/492Ρ Spectru m Analyzer from or in the R ackmount Cabinet . . . . . . R emoving the Side, Top, and B ottom P anels . . . . . . . . . . . . . . . . . Installing Semi-rigid Coaxial Cables to Access the Cabinet Rear Panel Connectors to the Front Panel of the Instrument (O ption 31) . . . . . . . . . . . . . . . . . . . . PREPARING THE IN ST RUMENT F OR CALIBR ATION O R MAINTENANCE . . .

Appendix Α GLOSSA R Y General Terms . . . .. . . . . . . . . . . . . . . Terms R elated to Frequency . . . . . . . Terms R elated to Amplitud e . . . . . . . Terms Related to Digital Storage Spectrum Analyzers . . . . . . . . . . . . .

6-1 6-1 6-3 6-3 6-3 6-5 6-6 6-6 6-7

6-7 6-9

. . Α-1 . . Α-2 . . Α-2 for . . Α-3

CHANGE INFORM ATION

REV A UG 1981

492/492Ρ Servi ce Vol. Ι (SN Β030000 dι up)

TA BLE OF CO N TEN TS (cont) V O LUME 2 S ERVICING SA FE TY SUMMARY Section 7 REPLACEABLE ELECTRICAL PARTS Section 8 DIAGRAMS

REV A UG 1981

Section 9 REPLACEABLE MECHANICAL PARTS Digital Control System'Description Processor Memory Board Front Panel Accessories Interface B oa rd Main Power Supply and Fan Driver Main Power Supply F an Driver Boa rd

γ

492/492Ρ Service Vol. Ι (S N Β030000 ά up)

L IST

OF I L LUST R ATIO N S

F ig.

Page

No .

3-8

The 492/492Ρ Spectrum Analyzer Probe power conn ector pin out . . . . . . . . . Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . Internatio nal power cord and p lug configu ration fo r t he 492 . . . . . . . . . . . . . . . Test equipme nt setup for chec king frequency of the calibrator and the acc uracy of the frequency readout . . . . . . . Test equipme nt setu p s howing two methods that check cali br ator output level . . . . . . . . Test equipment setup for verifying atte nu ato r a nd gain accuracy . . . . . . . . . . . Test equi pment setup for c hecking the 10 kH z-10 MHz frequency respo n se . . . . Test equi pment setup for measuring the 0.01-2.0 GHz freq ue ncy response . . . . . . Typical display showing frequency response from α sweepi ng signal source . . . . . . . . . . Test equipment setup for measuring 2.018 .0 GHz frequency response . . ... . . . . . . . . Test equi pment setu p for checking span and

3-9

Display to illustrate how timi ng accuracy

3-10

M eas u ri ng

1-1 1-2 1-3 3-1 3-2 3-3 3-4 3-5 3-6 3-7

3-11

3-12

3-13 3-14 3-15 3-16 3-17 3-18 3-19

Vi

xii 1-12 1-14 1-20

3-8 3-10 3-12 3-16 3-17 3-17 3-19

timing accuracy . . . . . . . . . . . . . . . . . . . . . .

3-21

is ch ecked . . . . . . . . . . . . . . . . . . . . . . . . . .

3-22

sh ape factor

3-24

resol u tion

ba ndwidt h a nd

. . . . . . . . . . . . . . . . . . . . . . . .

Typical display of

drift

Displays that illustrate how to measure residual FM with PHAS ELOCK off. The same techn ique is used with PH AS ELOC K on (Option 03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test equipment setup for meas uring intermodulation distortion . . . . . . . . . . . . . . ntermod ulation products . . . . . . . . . . . . . . Test equi pment setup to check harmonic distortion . . . . . . . . . . . . . . . . . .- . . . . . . . . Typical disp lay of phaselock -wise . . . . . . . Multiple exposure to illust rate how-the differential between two signals ca n be measured . . . . . . . . . . . . . . . . . . . . . . . . . . . Test equ ipment setup for checking triggering requirements . . . . . . . . . . . . . . . . . . . . . . . . Test equi pment setu p to chec k external t riggering and horizontal input characteristics . . . . . . . . . . . . . . . . . . . . . . .

I

3-20

3-21 3-22 3-23 3-23 3-25 3-26 3-27 3-28 3-29 3-30 3-31

measureme nt witho ut

ph aselock showing width of marker stored with MAX HO L D and beginning d isp lay of marker saved i n Α . . . . . . . . . . . . . . . . . . . .

Fig . No.

3-27

3-27 3-28 3-28

Test oscilloscope display of α sinewave input signal to ΕΧΤ TRIG connector (i nput 1 .0 V peak at 2.0 V peak-to-peak) . . . . . . . Display of α full screen signal at the Vertical Output Connector. . . . . . . . . . . . . . Low voltage power s upply adjustments and test point locations . . . . . . . . . . . . . . . . Adj ustments and test points on the deflection am p lifier, H ig h Voltage module, and Ζ-Axis/ RF Interface board . . . . . . . . . . Locatio n of wi re stra p (W4036) on high voltage circuit b oard . . . . . . . . . . . . . . . . . . Test equipme nt setu p for calibrating the Deflection Amplifier . . . . . . . . . .... ... ..... Locatio n of ΤΡ 1101 on Crt Readout Test points and adjustments on t he Deflection Am plifier board for gain and frequency response cali bration . . . . . . . . . . Test equi pment setup for cali brating swee p timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Location of timi ng adjustme nt R5105 and ΤΡ 1061 on sweep board. . . . . . . . . . . . . . . Test equ ipment setup for calibrating sweep r amp for the 1 st LO Driver . . . . . . . 1st

LO

balan ce an d spa n

adj ustments

an d

3-33 3-34 3-44 3-45 3-45 3-46 3-47 3-47 3-48 3-49 3-50

test poi n ts . . . . . . . . . . . . . . . . . . . . . . . . . .

3-51

adj ustme nt of 1 st a nd 2nd

LO frequencies .

3-54

locations . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-55

mod u le . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-64

check and

3-32

Test equi pment setu p for

3-33

Cen ter

3-34

1 st LO Driver adjustments and test point locations . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-57 Test equipment setup fo r adj usting baseli ne leveli ng . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-58 Adjustments and test poi n ts on the Vi deo P rocessor board . . . . . . . . . . . . . . . . . . . . . 3-59 Ty pical response displays when adjusting baseline leveli ng . . . . . . . . . . . . . . . . . . . . . 3-60 Ty pical response dis plays when adjusting compensation of baseline leveli ng circuits . 3-60 Equipment setup for cali b rati ng log am plifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-61 Location of connectors and adjustments on the Log and Video Am plifier . . . . . . . . . . . . 3-62 Test equi pment setup for cali brati ng the . . . . . . . . . . . . . . . . . . . 3-64 VR section . . . . . on the VR #2 Cali bration adju stments ..

3-35 3-36 3-37

3-29 3-30

3-38

3-31

3-40

3-32

3-41

3-33

Page

3-39

3-42

Frequ ency

Control adjustment

REV AUG 1981

I

492/492 Ρ Service Vol . 1 (S N Β030000 & up)

L IST OF LLUSTRATIONS (cont) Fig .

Page

No.

3-43 3-44 3-45 3-46 3-47 3-48 3-49 3-50 3-51 3-52 3-53 3-54 4-1 4-2 4-3 4-4 4-5 4-6 4-6Α

4-7 4-8 4-9 4-10 4-11 4-12

Res ponse of th e 100 kH z filter . . . . . . . . . . Calibration adjustments on the VR #1 module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical response of 10 kH z, 100 kH z, an d 1 MH z b andwidth filters . . . . . . . . . . . . . . . Test equ ipme nt setup for ad justi ng I F gain and t h e location of the cali brator level ad j ustment . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Storage adjustment locations . . . . . Location of binary switch (S1014) for setting Β -SAVE Α refe rence level . . . . . . . Band leveling adjustments and gain diodes (w hen installe d) on VR #2 module . . . . . . . Test equ ipme nt setup for calibrating ba nd leveli ng of the external mixer ba nds . . . . . . Test equ ipme nt setup for calibrating Preselecto r Driver . . . . . . . . . . . . . . . . . . . . Preselector Driver adjustments and test poi n ts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test equ ipme nt setu po for cali brating Ph aseloc k assembly . . . . . . . . . . . . . . . . . . Adj ustments and test p oi nt locations in t he Ph aseloc k modu le . . . . . . . . . . . . . . . . . . . . Mu ltipin (harmo nica) connector co nfiguration . . . . . . . . . . . . . . . . . . . . . . . . Color code for some ta ntalum capacitors . . Diode pola rity markings . . . . . . . . . . . . . . . Electrode configuration fo r semiconductor components . . . . . . . . . . . . . . . . . . . . . . . . . Pre paring the VR module for service showing h ow it is supported when on an extender . . . . . . . . . . . . . . . . . . . . . . . . . . . RF deck of Β040000 an d up version sh owing major asemblies . . . . . . . . . . . . . . V iew of the 492/492Ρ RF dec k for Β 039999 and below s howing major assemblies and circ uit board s . . . . . . . . . . . . . . . . . . . . V iew of the 492/492 Ρ to p dec k s howing major assemblies . . . . . . . . . . . . . . . . . . . . . R emoving YIG oscillator interface ci rcuit boa rd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Exploded drawi ng of fa n assembly . . . . . . . Test equ ipment setup for adjusting return loss for the 110 MHz I F assembly . . . . . . . L ocation of the 110 MHz IF retu rn loss adjustments and IF Gain adju stme nt . . . . . L O section of 829 MHz converter showing test p oints αη &connectors . . . . . . . . . . . . .

REV AUG 1981

Fig . No .

3-65

4-13

3-65

4-14

3-67

4-15 4-16

3-68 3-70

4-17

3-71

4-18

3-72 3-73 3-74 3-74 3-76 3-77 4-4 4-4 4-5 4-6

4-19 4-20 4-21 4-22 4-23

4-24 4-25

4-9

4-26

4-11

4-27 4-28

4-12

4-29

4-13

4-30

4-16 4-17 4-19 4-19 4-21

4-31 5-1 5-2 5-3 5-4 5-5 5-6

Page

Locatio n of test jack and j umper on the 829 MHz am plifier b oard . . . . . . . . . . . . . . .

Test equi pment setup for alig ning the 829 MHz filter . . . . . . . . . . . . . . . . . . . . . . . Filter tune ta bs in the 829 MHz converter . Typical response when the first and second resonators of the 829 MH z filter are ad ju sted correctly . . . . . . . . . . . . . . . . . Typical response when the third and fo urt h resonators are tu ned correctly . . . . . . . . . . Test equ ipment setup fo r calibrating the oscillator section of the 2182 MHz Ph aseloc ked 2nd L O . . . . . . . . . Adjustments and test point locations within the oscillator section . . . . . . . . . . . . . Constr uction of α coaxial test p ro be for the 2182 MH z Ph aselock ed 2 n d LO . . . Test eq uipmen t setu p for calibrating th e ph aseloc k ed section of the 2182 MH z Ph aseloc ked 2nd L O . . . . . . . . . Location of test points and components associated with cali brating the 14-22 MH z Ph aseloc k circuit . . . . . . . . . . . Ju mper positions between Τ1077 and T1 075 vers us frequ ency compensation for t he 14-22 MHz Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . The M emory boa rd o ption switc h band S1033 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Α15 through Α12 i n microcompute r test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Α 15 and YO throug h Υ2 of address decoder U2044 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Enable and YO throug h Υ2 of address decoder U 1037 B . . . . . . . . . . . . . . . . . . . . . . . . . . Α15 and Memory board address d ecoder outp uts . . . . . . . . . . . . . . . . . . . . . . . . . . . . Α15 and YO thro ugh Υ2 of address decoder U 1021 on the GPIB board . . . . . . . . . . . . . One enable and outpu ts LORAM, H IRAM, and GPS of add ress decoder U 1028 on the GPI B board . . . . . . . . . . . . . . . . . . . . . . . . . Instrument bus ch ec k . . . . . . . . . . . . . . . . . Filter cross-section view . . . . . . . . . . . . . . . Filter eq uivalent ci r cuit. . . . . . . . . . . . . . . . . 2182 .0 MH z Cavity LO equivalent circuits . Diplexer simplified sc h ematic . . . . . . . . . . . Amplifier signal path . . . . . . . . . . . . . . . . . . Am plifier signal p at h . . . . . . . . . . . . . . . . . .

4-22 4-23 4-24 4-25 4-25 4-27 4-28 4-29 4-30 4-31

4-32 4-35 4-37 4-37 4-38 4-39 4-40 4-40 4-40 5-8 5-9 5-13 5-14 5-15 5-15

492/492 Ρ Service Vol . Ι (S N Β030000 & up)

L IST O F

I LLU

F ig . No .

ST R ATIO N S (cont) Page

F ig .

5-8 5-9 5-10

Simplified bloc k diagram of the ph aselock circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B ridged Τ attenuator equivalent schematic Three-stage log amplifier. . . . . . . . . . . . . . . Log amplifier gain curve showing

5-17 5-21 5-30 5-30

5-11

End s of loggi n g range . . . . . . . . . . . . . . . . .

5-34 5-35 5-36 R-37

5-30

5-38

5-32

5-39

5-7

5-12

5-13 5-14 5-15 5-16 5-17 5-18 5-19 5-20 5-21 5-22 5-23 5-24 5-25 5-26 5-27 5-28 5-29 5-30 5-31 5-32

Viii

brea kpoint . . . . . . . . . . . . . . . . .

Sim p lifie d detecto r circu it . . . . . . . . . . . . . .

Selection of d isplay position on log scale . . 5-33 5-37 Video filter simplified schematic . . . . . . . . . 5-40 Vertical control IC b lock diag ram . . . . . . . . H orizontal cont rol IC block diag ram . . . . . . 5-44 Simplified crt readout b lock diagram . . . . . 5-48 Character on/off timi ng . . . . . . . . . . . . . . . . 5-49 5-50 * * Character scan . . . . . . . . . . . . . . diagram . . ... . 5-51 C haracter generator (U1028) block Character scan timi ng . . . . . . . . . . . . . . . . . 5-52 Dot delay circ uit timi ng . . . . . . . . . . . . . . . . 5-53 Frequency d ot mar ker circ uit and timing . . 5-54 Sweep "i nterr u pt" circuits . . . . . . . . . . . . . . 5-59 Simplified digital-to-a nalog converter . . . . . 5-60 Simplified s pa n decade atte nuato r . . . . . . . 5-61 DAC variance graph . . . . . . . . . . . . . . . . . . 5-67 B asic tu ne voltage converter . . . . . . . . . . . 5-68 Timi ng diagr am fo r F ERRO R coun t. . . . . . 5-73 Simple Logic d iagram of processor cloc k . . 5-79 Block diag ram of 6800 microprocessor . . . 5-80 Read and write cycle timi ng on the microcomputer b us . . . . . . . . . . . . . . . . . . . 5-81

Page

No .

5-33

5-40

5-41

5-42 5-43 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8

Flow chart of th e 6800 main decision

paths . . . . . . . . . . . . . . . . . . . . . . . . .. 6821 Ρ1Α registers and control li nes Α 6800 write to the instrume nt b us . Instru ment bus poll sequence . . . . . . Scan by simplified keyboard encoder

. . . . . . . . . . . . . . .

5-82 5-84 5-87 5-88 5-89

encoder . . . . . . . . . . . . . . . . . . . .

5-90

Switc h matrix codes . . . . . . . . . . . . . . . . . .

5-92

Keyboard

.. .. .. .. ..

F re q uency con trol en code r timing . . . . . . . .

5-93

P rimary regulator inp ut and output wavefo rms (stylized) . . . . . . . . . . . . . . . . . . 5-96 Timing waveforms (stylize d) for soft-start ci rcuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-97 9914 GPIA b lock diagram . . . . . . . . . . . . . . 5-100 H ardware p rovided for slide track mou nting . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 Instrument installe d in α ca binet-type rack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 Complete slide-o ut track assemblies . . . . . 6-5 M et hod of mou nting the statio n ary sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 M easurements of front-rail mounti ng holes for the statio nary sections . . . . . . . . . 6-7 P rocedure for inserting or removing the instrume nt . . . . . . . . . . . . . . . . . . . . . . . 6-8 Alignment adju stment for correct operatio n . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 Alternative method of installi ng the in str u me nt using rear su p port brackets . . . 6-10

REV A UG 1981

492/492Ρ Service Vol . 1 (S N Β030000 & up)

L IST OF TA BLE S Table No . 1-1 1-2 1-3 1-4 1-5 2-1 3-1 3-2 3-3 3-4 3-5 3-6

3-7 3-8 3-9 3-10 3-11 3-12 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10

P age Electrical Characteristics . . . . . . . . . . . E nvironme ntal Characteristics . . . . . . . Ph ysical Characteristics . . . . . . . . . . . Option 01 E lectrical Characteristics . . Option 03 E lectrical Characteristics . . Shipping Carton St rengt h . . . . . . . . . . Equipment Requ ired for Cali br ation . . H armonic N umber (η) vs F requ ency Range . . . . . . . . . . . . . . . . . . . . . . . . . Correction Factor To Determine Tr ue

. . . . . . .

. . . . . . .

. . . . . . .

. . . . . . .

. . . .

1-4 1-12 1-13 1-15 1-17 2-2 3-1 3-7

Ta ble No . 4-11 4-12 4-13 4-14 4-15 4-16

4-49 4-49 5-5 5-7 5-16

5-5

Gain Ste p Combi n ations . . . . . . . . . . . . . . .

5-26

3-20

5-7

3-22

5-8

Sp a n/Div vs Time

M ark ers . . . . . . . . . . . . .

492/492 Ρ Sensitivity . . . . . . . . . . . . . . . . . . Sensitivity (O ption 01) . . . . . . . . . . . . . . . . . Adjustment Steps for Cali bration . . . . . . . . Power Sup ply Voltage Tolerances . . . . . . . Resolution and Sweep Rate as α Fu nction of Span in Auto Mode . . . . . . . . . . . . . . . . . Ext M ixer Band Leveling Adjustments . . . . Relative Susceptibility to Static Disch a rge Damage . . . . . . . . . . . . . . . . . . . . . . . . . . . . Equi pment Requ ired . . . . . . . . . . . . . . . . . . Equi pme nt Required for 2n d LO Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . Equipment R equi red for Calibrating 14-22 MHz Ph aseloc k Circuit . . . . . . . . . . . Variable Resolutio n Data Registe r . . . . . . . L og & V i deo Am p Registers . . . . . . . . . . . . V ideo Processor Control (7C) . . . . . . . . . . . Digital Storage Registe rs (7 Α, FA, and 7Β) Ζ-Axis and RF Deck Co ntrol (4 F) . . . . . . . . Crt Readout Registers (5 F and 2F). . . . . . .

REV A U G 1981

5-4 5-6

3-25 3-26 3-42 3-43 3-49 3-73 4-1 4-18 4-26 4-29 4-44 4-45 4-45 4-45 4-46 4-46

4-47 4-47 4-48 4-48 4-49

. . . . .

. . .

N arr ow and Wide Spans vs Freq uency B and . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . .

4-17 5-1 5-2 5-3

3-13 3-15

F ro nt- Panel Registers . . . . . . . . . . . . . . . . . Swee p Registers . . . . . . . . . . . . . . . . . . . . Span Attenu ator Registers (75 and 76) . . list L O Driver Registers (72 and 7Ε). . . . . Preselector Driver Control (77) . . . . . . . . . Center Frequency Control Registe rs (70, 71, and FO) . . . . . . . . . . . . . . . . . . . . . Ph aseloc k Control Registers (73 and F3) . RF Interface Lines . . . . . . . . . . . . . . . . . . . 2nd Co nverter I F Selectio n . . . . . . . . . . . . Switch and Am plifier Selection Summary .

Level . . . . . . . . . . . . . . . . . . . . . . . . . R ecommen ded Test Equip ment for M easur ing Freq ue ncy R espo n se . . . . . . . . .

Signal

P age

5-9 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 5-19 5-20 5-21 5-22 5-23 5-24 5-25 5-26 6-1 6-2

Bandwidth

Selection . . . . . . . . . . . . . . . . . .

Reductio n .

Progression of Gain F ilter Componen t Combination s . . . . . . . . . J 2039 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Cont rol P ort. . . . . . . . . . . . . . . . . . . . . . . . Address/Data Port . . . . . . . . . . . . . . . . . . Sweep Rate Selection Codes . . . . . . . . . . Calibratio n Control Selectio n Codes . . . . . Attenuation Selectio n Co des . . . . . . . . . . . U 4017 (U3027) Out p ut Lines . . . . . . . . . . U 5031 Output Lin es . . . . . . . . . . . . . . . . . Preselector Frequen cy B ands . . . . . . . . . . ADD RE SS 70 F ormats . . . . . . . . . . . . . . . DAC Tun ing Codes . . . . . . . . . . . . . . . . . . U 2025 Output Lines . . . . . . . . . . . . . . . . . Condition Codes . . . . . . . . . . . . . . . . . . . . Address Select Lines . . . . . . . . . . . . . . . . 492/492Ρ M icrocomputer Address Space ΡΙΑ Registe r an d Interface Select Codes . Inst rument Bu s Register Addresses . . . . . Parallel P OLL Byte . . . . . . . . . . . . . . . . . . GPIA Registers . . . . . . . . . . . . . . . . . . . . . En vironmental Characteristics . . . . . . . . . . Physical . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-24 5-27 5-37 5-46

. 5-53 . 5-53 . 5-58 . 5-60 . 5-61 . 5-62 . 5-64 . 5-65 . 5-69 . 5-69 . 5-75 . 5-78 . 5-83 . 5-83 . 5-85 . 5-86 . 5-87 . 5-101 . 6-1 . 6-2

492/492Ρ Service Vol . Ι (SN Β030000 & up)

S ERVICING SA FETY SUMMARY FO R QUA LIFIED S ERVICE PERSONNEL ONL Y Do

N ot Service Alone

U se the Proper Fuse

Do not perform internal service or adjustment of this product unless another person capable of rendering first aid and resuscitation is present .

To avoid fire h azard, use only the fuse specified in t he parts list for your product, and which is identical in type, voltage rating, and current rating .

U se Care When Servicing With Power On

R efer fuse replacement to qualified service personnel .

Dangerous voltages exist at several points in this product. To avoid personal injury, do not touch exposed connections and components while power is on . Disconnect power before removing protective panels, soldering, or replacing components .

Do

To avoid explosion, do not operate this product in an atmosphere of explosive gases unless it h as been specifically certified for such o peration .

SY MB O LS

P ower Source This product is intended to operate from α power source that will not apply more than 250 volts rms between t he supply conductors or between either supply conductor and ground . Α protective ground connection by way of the grounding conductor in the power cord is essential for safe operation.

N ot Operate in Explosive Atmospheres

In

This Manual T his symbol indicates where a p plicable cautionary or other information is to be found.

As

Marked on Equipment DANGER-High voltage.

TERMS In This Manual CAUTION statements identify conditions or p ractices that could result in damage to the equipment or other property . WARNING statements identify conditions or practices that

could result in personal injury or loss of life . As

Marked on Equipment

CAUTION indicates α p ersonal injury hazard not immediately accessible as one reads the marking, or α h azard to p roperty including the equipment itself . DANGER indicates α personal injury h azard immediately accessible as one reads the marking.

Protective ground (earth) terminal . ATTENTION-refer to manual .

P ower Source This p roduct is intended to operate from α power source that will not apply more than 250 volts rms between the supply conductors or between either supply conductor and ground . Α p rotective ground connection b y way of the grounding conductor in the power cord is essential for safe operation. Grounding the Product This product is grounded through t he grounding conductor of the power cord . To avoid electrical shock, p lug the power cord into α properly wired receptacle b efore connecting to the product input or o utput terminals. Α protective ground

REV A UG 1981

492/492Ρ Service Vol . Ι (S N Β030000 & up) conn ectio n by way of the grounding con ducto r in the p ower cord is esse ntial for safe operation. Da nger Arising From

L oss of

Groun d

Upo n loss of the protective-ground connection, all accessible co nductive parts (includi ng kn obs and controls that may appear to be insulating) ca n render an electric shock.

U se the Prope r Power Cord

U se only the power co rd and co nnector specified for your

produ ct .

REV AUG 1981

U se only α p ower cord t hat is in good conditio n. F or detailed information on power cords and conn ectors,

see the General Information and Specifications sectio n in

Volume 1 of the 492 Service manual .

Refer cord and conn ector changes to qualified service personnel .

492/492Ρ Service V ol . Ι (S N Β030000 & up)

T h e 492/492Ρ S p ectrum Analyzer.

ΧΙΙ

REV AU G 198 1

Sectio n 1-492/492Ρ Service Vol . Ι (S N 0030000 δ up)

G ENER A L I NF O RM ATIO N A N D S PE CI FICATIO N GENER A L I NF O RM ATIO N Introdu ction

Th e Service ma nual consists of two vol umes that contain

information n ecessary to test, adjust, and service the Portable R ackmount/Benchto p 492/492Ρ Spectru m Analyzer. The intent is to provide as complete info rmation as possible as an aid in servicing t h is instrument. The Table of Conten ts at the beginning of Volume 1 lists contents of each sectio n co ntained within Volume 1 . Change informatio n t hat involves manual corrections and/or add itio ns pending manual repri nt and bind, is located at the bac k of the Service manu al in the CHAN GE INFORMATION sectio n. History informatio n with the updated data is in teg rated into the text or d iagr ams when α page or diagram is up dated . Original p ages are identified by the symbol @, revised p ages by α revision d ate in t he lower insi de comer of the p age . The manu al may contain revisions that do not app ly to yo ur instrument ; h owever, h istory infor mation with updated data, is integrated into the text o r diagram when the page or diagram is revised . The pe rson using these instructio ns should be knowledgeable in d i gital and analog circuit theory . Circ uit analysis is primarily fu nction al . Th e inte nt is to provide sufficient information for the techn icia n to isolate the majority of malf unctio ns to α b lock of circuitry . Those users with an understand ing of logic and analog ci rcuitry should then be able to furt her isolate the malfun ction to α specific component or components .

M ost termi n ology is in accordance with th ose stan dards adapted by IEEE . Α glossary of terms is provided as an append ix . Abbreviations in the documentation are in accordance with ANSI Υ1 .1-1972, with exceptions and additions ex plained in parentheses after the abbreviatio n. Graphic symbols comply with ANSI Υ32 .2-1975. Logic symbology is based on ANSI Υ32 .14-1973 a nd the manufacturer 's d ata description. Α copy of ANSI standards may be obtained from the Institute of E lect rical and E lect ronic Engineers, 345 47th Street, N ew Yo rk, NY 10017. REV AUG 1981

Product Service To assure adequate prod uct service and maintenance fo r

our instruments, Tektronix has established Field Offices and

Service Centers at st rategic points throughout the U nited States and in countries where our products are sold . Several types of maintena nce or repai r agreements are available. For exam ple : for α fixe d fee, α maintenance agreement program provides maintena n ce and re-cali bration on α regular basis . Te ktronix will remin d you when α product is d ue for recalib r ation and perform the service within α specified time . Co ntact your local Service Center, representative, or sales engi neer for details regardi ng: Warranty, Calibration, Emergency Repai r, R epai r Parts, Scheduled Mainten ance, M ai nte nance Agreeme n ts, Pickup and Delivery, On-Site Service fo r fixed installation s, and other services availa ble through t hese centers. Te ktronix emerge n cy repai r service provides immediate attentio n to inst ru ment malfunctio ns if you are in an emergen cy situation such as α field t r ip. Again, co ntact any Tektronix Service Cente r for assistance to get you on your way within α mi n imum of time .

Inst ru ment Co nstruction

T he modular co n structio n of the 492/492Ρ in strume nt provides ready access to the major circuits. Circuit boa rds that contain sensitive ci rcuits are either mo unted on metal extr usions, each of whic h provides shielding between adjacent modules, or they are mounted within honeycom blike extrusions with α feedthrough connecto r through the wall of t he compartment. Interconnection between boards and assemblies is provided b y plugging these b oa rds onto α main moth e r board . M ost adjustmen ts and test points are accessi ble while the instrument is operational and the modules or assemblies secu red in their normal position. Extend ers are provided with α Service Kit ; see M ai ntenance section under Service Fixtu res and Tools for Mainten a nce. Any module can be removed without distu rbing the st ructu ral or fu nction al in tegrity of the other modules . The extenders allow most circuit boa rd assemblies to function in an extended position for service or a djustme nt. The ci rcuit

Specification-492/492P Service Vol . Ι (SN Β030000 & up)

b oard s mo u nted on the metal extr usion can be remove d b y

removing the secu rin g screws . All ot her ci rcuit board s - (w h ich should req ui re mi n imal service) are accessi ble b y removing α cover p late .

ΝΟΤΕ Disassembly of some modules may require special tools and procedures . These procedures will be found in the Maintenance section. In instru ments t h at h ave p hase lock; th e ph ase lock assembly contri butes to th e 492/492Ρ stability. Circuits a re com p letely rf isolated to en su re spuriou s free response, yet t h e close proximity minimizes losses o r interactions wit h ot h e r fu nctio ns. All com partments a re enclosed on bot h si d es b y metal plates a n d all interco nnectio n s b etween compartments are made by fee d through te rminals rat her th an ca bles. If t he compartments a re opened, b e su re th at t he s h ields and covers are properly reinstalled before ope rati ng.

E lapsed Time Meter Α 5000

hou r elap sed time indicato r , graduated i n 500

h our in crements, is installed on the Ζ Axis/ RF I nterface ci rcuit b oard . Th is provi d es α convenient way to chec k operati n g time . T h e meter on new instru ments may indicate f rom 200 to 300 h ours elapsed time . Most instruments go th rough α factory bu rn-in time to imp rove reliability . Th is is similar to usi n g aged components to im prove relia b ility an d operati n g sta b ility. Ch a ngi n g

Power

I np ut

R a nge

T he followin g p rocedures descr ibe how to set t h e i npu t

powe r range .

α. Disconnect t h e powe r plug a nd remove the cover .

b. R emove the access plate at t he uppe r left cor ner (viewed f rom the rear) of the power module . ε. S h ift plug Ρ1029 to t he app ro priate pi n s on J 1029 as indicated by t he sil k screen nome nclatu re. Replace t h e access plate .

1) Set the instrument on its face and remove the four screws that hold the power supply module to the side rails . Lift the module off the instrument. 2) Remove the top and bottom screws then the side screw that h olds the two sections of the power supply module together. Separate the two sections to expose the power supply circuit board. 3) Shift the plug Ρ1029 (upper left comer) to the appropriate pins on J 1029. Re-install the two sections and the power supply module.

d. Remove th e in pu t powe r specification p late over the inp u t f u se on the back panel. Turn t he p late over a nd reinstall so th e exposed information on power specifications is correct. e. Change the input fuse to t he new value specified on t he i n formation p late.

f. Replace the cove r an d the power cord ; then connect the i n strume nt to t he appropriate powe r source .

ΝΟΤΕ The power cord supplied with the instrument a nd instrument power voltage req uirements depend on the available power source (see the Specification part of this section for power cord options) . Re p laci n g

Fuses

Besi des t he i np ut ( back pa n el) fuse, t he 492/492Ρ powe r modu le h as five fuses for t he do su pp lies (+300 V, F3014 ; +100V, F 1034 ; +17V, F 1014 ; +9V, F1031 ; -7V, F 1011). Access to t h ese fu ses ca n be gained by removi ng t h e access plate at the up per rig h t corner of the power module, or by separating th e two sections as desc ribed for ch an ging t he i nput powe r range. F uses are i d e n tified with stam p ed circuit n umbe r s on th e circu it boa rd . Selected Compon e nts

ΝΟΤΕ

Some com po nents, suc h as microcircuits, are selected to meet Tek tronix specifications. These componen ts are indicated i n th e p arts list a nd carry α Te kt ro n ix P art Nu mber un der th e M fr . Part Number colum n .

The earlier version power supply module did n ot h ave this access plate . To access Ρ1029 proceed as follows:

Selected value componen ts th at compensate for par amete r differences between active compon e nts are i d e ntified

REV FEB 1982

Specification-492/492P Service Vol. Ι (S N Β030000 & up) on the circuit diagram and in th e p arts list as α "S EL " value. The component description lists either the nominal value or α range of value. If the p rocedure for selection is not obvious, such as setting t he gain or response of α stage, the criteria for selection is ex p lained in the Calibration or M aintenance section of t he manual . Wh ere the selection p rocedure is obvious, such as esta blishing the frequency of an oscillator, no proced ure is given.

initial power-up cycle, the firmware version flas hes on screen for approximately two seconds. The Replacea ble Electrical Parts list section, u nder Memory Board (Α54), lists the RO M 's and their Tektronix p art number fo r each firmware versio n. An a d ditional feature is error message readout . The following is α list of these messages and their meaning.

Component Ci rcuit Nu mbering Sc h eme In this instrument, circuit numbers were assigned according to the com ponents ph ysical location on the board. For exam p le, α component such as α resistor, located within row 2 column 08, is R2080 . The fourt h digit of the number is an ex pander u sed to designate two or more common components within α given gri d , such as R2080, R2082, etc. Chassis mounted components are assigned α three digit number to help identify their location . The Replaceable Electrical Parts list prefixes these circ uit numbers with an assembly number . R2080, on assembly Α20, becomes Α20132080 . Assembly and subassem bly numbers are assigne d in numerical order by location within the instrument .

F irmware Version and Error Message R ea d out Th is feature of the 492/492Ρ provides readout of the firmwa re versio n when the p ower on/off is cycled . During

REV A UG 1981

Error No .

Mea ning

57

Tune routine failed in ca rry from lower DAC.

58

F ailed to ph ase lock.

59

Lost lock.

60

Failed to recenter when ph ase loc k ca ncelled or when going to an unlocked span.

Rac k mo unt/ Benchtop Versions The rackmount ve rsion of the 492/492Ρ Spectru m Analyzer is the 492/492Ρ in α rackmo unt cabinet . Access to all front panel connectors is provided with O ption 31 of t h is ve rsion . Add itional cooling is provided and α front panel accessories drawer i n the cabinet p rovi des storage for most accessories. The b enchtop version is the same as t he rackmount with the exception of the si de r ails .

Specification-492/492P Service V ol. Ι (S N Β030000 & up)

S PE CI F ICATIO N The following list of i n strument characteristics and features apply to the basic 492/492Ρ Spectrum Analyzer after α 30-minute warm up, exce p t as note d. Changes to the b asic specifications due to the addition of options follow the b asic listings . Differences in the electrical and environmental c h aracteristics for the r ackmount/benc h versions of the 492/492Ρ are descri bed in the R ac kmount/Benc h to p section of this manual. R efer to section 6 for this i nformation. The Perfo rmance Req uirement column describes the limits of the characteristic, a n d the S upplemental column de-

scribes features and typical values or information that may be useful to the user . P rocedures to verify performance r equirements are p rovided in t he Cali bration section of the Service instructions . The Performance Check procedures require sop histicated equi pment as well as techn ical expertise to perform .

The Operators Manual contai n s α p rocedure that chec ks all functions of the 492/492Ρ. This chec k is recomme nded for incomi ng inspectio n s to verify that the inst rument is fu nctioning properly .

Ta ble 1-1 ELECTRICAL CHARACTER ISTICS Characteristic

Performa nce R equ irement

Suppleme ntal Information

FREQUENCY RELAT ED Center Frequency Range (I nternal M ixer)

100 kH z to 21 GHz

Acc uracy (after 2 hour warm up)

±(5 MHz + 20% of sp an/div) η or ±(0 .2% of the center frequency + 20% of t h e span/div) wh ichever is greater.

Readout Resolution TUNE command acc ur acy (492 Ρ only under remote control) after α 2 h our warmup . 1 st LO Tuni ng Freq Span/Div B and 1-3 4 5-11

±(7% of tune amount or ±150 kH z) η whic hever is g reater. (See listing of IF freq ue ncy, L O range, and h armonic numb er t hat follows, for value of η.)

U sable to 50 kH z with reduced performance .

W it hin 1 MHz.

> 50 kH z >100 kH z >200 kH z 2nd L O Tu ni ng

1-3 4 5-11

50 kH z Χ100 kH z _-200 kH z

Residual FM (s hort term) after 2 hour warm up

±(7% of tune amou nt)

_-(1 kH z p ea k-to- peak) η for α period of 20 ms, η is the 1st L O h armonic n umber used in the 1st mixer co nversion, and related to the selected frequency range (b and).

No video filter.

REV FEB 1982

Specification-492/492P Service V ol . Ι (SN Β030000 & up) Table 1-1 (co n t) Ch aracte ristic

Performance R eq uirement

Suppleme ntal Information

F requency Drift after 2 h our

_-200 kH z/hour, fundame ntal mixi ng.

Α re-sta bilizatio n time of 10 minutes per GHz of frequency change must be allowed if the center frequ ency is retu ned.

"Static" R esolution Bandwi dth (6 dB down)

1 kH z to 1 MHz in decade steps, plus an automatic (A UTO position) . Resol ution bandwidth (6 dB down) is within 20%ο of the bandwi dth selected .

In AUTO position the bandwidth is compu ted by an internal computer, b ased on the

S h ape F actor (60 d B/6 dB )

7.5 :1 or less .

Noise Sidebands

At least -75 dBc at 30 times the resolution offset for fund amental mixi ng .

warm up at α fixed frequency and stable am bient tempe rat ure

span/div, video filters, time/div, and vertical display selections . Wh en bot h t he ΤΙΜΕ/DIV and RE SO LU TION BANDWIDTH are in AUTO position, the resolution bandwi dth is α function of the FREQUENCY SPAN/DIV selection .

V ideo Filter

Narrow

Reduces video bandwi dth to approximately 1/300t h of the selected resolutio n bandwidth.

W ide

Reduces video bandwidth to approximately 1 /30th of the selected resolutio n bandwidth.

Fre que ncy Span/Div Range (in 1-2-5 sequence)

Band

Narrow Spa n

W i de

Spa n

1-3 (0-7 .1 GHz)

10 kH z/Div

200 MH z/Div

4-5 (5 .4-21 GHz)

50 kH z/Div

500 MH z/Div

6 (18-26 GHz)

50 kH z/Div

1 GHz/Div

7-8 (26-60 GHz)

100 kH z/Div

2 GHz/Div

9 (60-90 GHz)

200 kH z/Div

2 GHz/Div

10 (90-140 GH z)

500 kH z/Div

5 GHz/Div

11 (140-220 GHz) 500 kH z/Div

10 GHz/Div

Two ad ditio nal positio ns p rovi de full b and (MAX span) display or 0 H z (time domain) display. Accuracy

REV οcτ 198 1

W ithin 5%ο of the span/div selected over

the center eight divisions of α tendivision display.

1-5

Specification-492/492P Service Vol . Ι (SN Β030000 & up) Table 1-1 (con t)

Ch a r acte r istic

Perfor ma n ce

R equ ireme n t

Freq uency

Frequency R es p onse an d Display F latness Coaxial (direct) In p ut

B an d 1

100 kH z-4 .2 G H z 50 kH z-4 .2 G H z

Band

2 1 .7-5 .5 G H z

B and 3

3 .0-7 .1 G H z

B and 4

5 .4-18 .0 G H z

B and 5

15 .0-21 .0 G H z

A bout mean average

18 .0-26 G H z

B and 7

26-40 .0 G H z

B and 8

40-60 G H z

B and 9

60-90 G H z

B and 10

90-140 G H z

B and 11

140-220 G H z

R eferenced to 100 MHz

±1 .5 d B ±2 .5 d B ±1 .5 dB

±2 .5 d B

±1 .5 d B

±2 .5 d B

±2 .5 d B

±3 .5 d B

±3 .5 dB

±5 .0 d13

response is measure d wit h RF Atte nu ation ,10 d B an d PE A KI N G op timized for each center freq uency setting, w h en ap p lica b le . Res p o n se incl udes t he effects of i np ut vswr, mixing mode ( η ), gai n variatio n , pre-selector, and mixer . Dis p lay flatness is ty p ically 1 d B greater t han th e frequ e ncy res ponse

R efer to R ack mo u nt/ Benc h top section for variance of t h is performance .

T EK T R O N IX H ig h P erformance Waveg u ide M ixers

E xternal H ig h P erformance Waveguide M ixers B a nd 6

S upp lemental I n formatio n

±3 .0 d B ±3 .0 d B ±3 .0 d B De pen d ent on extern al mixer Depende nt on external mixer Depen dent on external mixer

REV AU G 198 1

Specification-492/492P Service V ol . Ι (S N Β030000 & up) Ta ble 1-1 (cont) Characteristic

Perfo rma nce Requ irement

Supplemental Info rmation

I F Frequency, LO

Range and Harmonic Nu mber (η)

LO Range (MHz) an d H armonic ( η)

B an d and Freq Range

1st IF (MHz)

1 (0 - 4.2 GHz)

2072 - 6272 (1-)

2072

2 (1 .7 - 5.5 GHz)

2529 - 6329 (1-)

829

3 (3 .0 - 7.1 GHz)

2171 - 6271 (1 +)

829

4 (5 .4 - 21 .0 GHz)

2072 - 6276 (3-)

829

5 (15 - 21 G Hz)

4309 - 6309 (3+)

2072

6 (18 - 26 G Hz)

2655 - 3988 (6+)

2072

7 (26 - 40 G Hz)

2443 - 3793 (10+)

2072

8 (40 - 60 G Hz)

3792 - 5790 (10+)

2072

9 (60 - 90 G Hz)

3861 - 5862 (15+)

2072

10 (90 - 140 G Hz)

3823 - 5997(23+)

2072

11 (140 - 220 G Hz)

3728 - 5890(37+)

2072

AMPLIT U DE RELAT E D Display M odes

10 dB/Div, 2 d B/Div, Delta Α.

L inear, and

Dis p lay R eference Level Range

-123 dBm to +40 d Bm (+40 dB m incl udes 10 dB of I F gain reduction, +30 dBm is the maximum safe input) for 10 dB/DIV and 2 dB/DIV log modes. 20 nV/Div to 2 V /Div (1 W maximum safe input) in li near mode .

Steps

10 dB, 1 d B, and 0.25 d B for relative (Δ) measurements in log mo de. 1-2-5 se q uence and 1 dB equivalent increments in L IN mode .

Accuracy

Accuracy is α function of t h e RF attenuation and reference level setti n gs, resolution switching, freque ncy response, frequ e n cy b a nd, and display mode . (See amp litude accuracies of th ese fu n ctions .) The attenuator is changed for reference levels above -30 dBm (-20 d Bm in minimum noise) u nless α MIN RF ΑΤΤΕΝ setting greater than the nominal attenuation is specified.

REV AUG 1981

Specification-492/49212 Service Vol . Ι (S N Β030000 & up) Table 1-1 (cont) Characteristic

Performance Requ irement

80 dB at 10 dB /Div and 16 d B at 2 dBV /Div for log mode p lus 8 divisions for linear mode.

Display Dynamic Range Accuracy

Suppleme ntal Info rmation

± 1 .0 dB/10 d B to α maximum cumulative error of ±2 .0 dB over the 80 d B window and ±0 .4 dB/2 dB to α maximum cumulative error of ± 1 .0 dB over t h e 16 dB window . L IN mode is ±5% of full screen .

RF Attenuator

0 to 60 dB i n 10 d B steps.

Range Accuracy Dc to 4 GHz

W it h in 0.3 dB /10 dB to α maximum of

4 GHz to 18 GHz

W it h in 0 .5 dB /10 dB to α maximum of

0.7 d B over the 60 dB range . 1 .4 d B over the 60 dB range.

I F Gain

83 dB of gain increase, 10 d B of gain decrease (MIN N OIS E activated) in 10 dB a nd 1 dB steps.

Ra n ge

Accuracy

Within 0.2 dB/1 dB except at the 10 d B

reference level transition from -29 to -30 dB m, -39 to -40 dBm, -49 to -50 dBm, -59 to -60 dB m, an d -69 to -70 d Bm, where the accuracy is 0.5 d B ; an d within 0.5 dB /10 dB to α maximum of ±2 d B over the 90 dB range .

Differential Am plitude Measureme nt (Delta Α mode) dB Difference 0.25 dB 2db 10 dB 50 dB

Ran ge

F rom 10 dB above to 40 dB below t he

Signal Amp litude V ariation With Resol ution Switching

Steps 1 8 40 200

Error 0.05 dB 0.4 dB 1 .0 dB 2.0 dB

Accuracy

reference level established whe n t he Delta Α mode was activated.

Provides differe ntial measurements in 0.25 dB increments Wit hin the reference level range of

-123 dBm to +30 d Bm

Do not u se Delta Α mode outside the -123 dBm to +30 dB m referen ce level range. Total range is at least 50 dB .

L ess than 0.5 dB

REV AUG 1981

Specification-492/492P Service Vol . Ι (SN Β030000 & up) Table 1-1 (co nt) Ch aracte ristic

Performa nce Req uirement

t

Suppleme n tal Info rmation

Sensitivity The following tabulation shows t he equ ivalent maximum in put noise for each resol ution bandwi dth, with the internal mixer for fre que n cy b ands 1-5 (100 kH z-18 GHz), and T EK TRON IX H ig h Perfo rmance W aveg uide M ixers fo r band s 6-10 (18 GHz-140 GHz) . The N ARR OW vi deo filter is activated, fo r narrow resolutio ns (1 kH z or less); WID E filter fo r wide resolution. SENSITI VITY (VER SUS B ANDWIDTH) Equivalent Input N oise for Resolution Bandwidths

Freq uency/Band

1 kH z

10 kHz

100 kH z

1 MHz

50 kH z-7.1 GHz (Ban d s 1-3)

-115 d Bm

-105 d Bm

-95 d Bm

-85 d Bm

5 .4-18 .0 GHz (Band 4)

-100 dBm

-90 dBm

-80 dBm

-70 dBm

15-21 .0 GHz (Band 5)

-95 dBm

-85 dBm

-75 dBm

-65 dB m

18 .0-26 GHz (Band 6)8

-100 dBm

-90 dBm

-80 dB m

-70 dBm

26-40.0 GHz (Band 7)8

-95 dBm

-85 dBm

-75 dBm

-65 dBm

40 .0-60.0 GHz (Band 8) 8

-95 dBm

-85 dBm

-75 dBm

-65 dBm

60 .0-90.0 GHz (Band 9)

Exte rn al M ixer De pe n de nt

90 .0-150 .0 GHz (Band 10)

External Mixer Dependent

140 .0-220 GHz (B and 11)

External M ixer Dependent

°TEK TRONIX H ig h Perfo rm ance Waveg uide Mixers. Spurious Res ponse R esidual (no input signal,

-100 d Bm or less

Thi rd o rder intermodulation products (MIN DISTORTION mode)

At least -70 d B c below any two onscreen signals within any frequ ency span

Harmonic Distortion (cw signal, MIN DISTO RTION mode)

At least -60 d Bc for full sc reen signal

LO Emissions (referenced to

-10 dBm or less

referenced to mixer inp ut, and fu ndamental mixing for ban d s 1, 2, and 3)

inp ut mixer)

REV AUG 1981

Specification-492/4. 92P Service Vol . Ι (S N Β030000 & up) Table 1-1 (cont) Characteristic

Su pp lemental Info rm atio n

Perfo rma nce R eq uirement

I NPUT SIGNAL CHARACTER ISTICS :IF I NPUT

Type Ν female co nnector, specified to 18 GHz, u sable to 21 GH z 50 ohm ; vswr 4.5 :1 maximum with 10 dB or more RF attenuation to 18 GHz and 3.5 :1 to 21 GHz

In p ut Impedance Input Level Optimum level for linear operation

-30 d Bm referenced to in put mixer

This is achieved by b eing in MIN DISTORΤΙΟΝ an d not exceeding full screen -18 d Bm, no RF attenuatio n

1 d B compression point Maximum input level

+13 d Bm (Input mixer limit)

RF Atte nuation at O dB

+30 dBm (1 W) continuo us, 75 W peak, pulse width 1 μs or less with α maximum d uty factor of 0 .001 (attenuator limit)

With 20 d B or more

RF Attenuation

Do N ot apply do voltage to the RF INPUT. External M ixer

Input for I F signal and the source of negative-goi ng b ias for exte rnal waveguide mixers . B ias ra nge +1 .0 to -2 .0 V

ΕΧΤ IN HOR IZ/T R IG

Dc coupled input for h orizontal drive a nd ac coupled for trigger sign al

In p ut V oltage R ange

O to +10V (dc + peak ac) for full screen deflection

Swee p Trigger

1 .0 V pea k (minimum). Freq uency 15 H z to 1 MH z

Maximum input: 50 V (dc + peak ac) Maxim u m ac in put : 30 V rms to 10 kH z

then de rate linearly to 3.5 V rms @ 100 kH z and above.

P ulse widt h 0.1

Ειs minimum

This co nnector is for future a pplications

ACCESSO RY (J104)

OUTPU T SIG NAL CHARACTER ISTICS Calibrator (CAL OUT) 1 st L O and 2 nd L O

1-10

-20 dB m, ±0 .3 d B at 100 MH z, ±1 .7 kH z

100 MHz comb markers are provided fo r frequ ency and span cali bration

P rovides access to the output of the respective local oscillators (1 st LO +7 .5 dBm mi nimum to α maximum of +15 d B m . 2n d LO -22 dBm minimum to α maximum of +15 d Bm) . These ports must be terminated in 50 Ω at all times

REV AUG 1981

Specification-492/492P Service Vol . Ι (SN Β030000 & up) Ta ble 1-1 (cont) Supple mental In fo rmation

Performance Requ ireme n t

Characte ristic VERTICA L

0.5 V, ±5°/ο of signal per d ivision of video above and below the ce nterline .

HOR IZ OU T

0.5 V/Div eit her si de of ce nter. F ull range -2 .5 V to +2 .5 V, ±10%

Source impedance ap proximately 1 k Ω

Source impedance approximately 1 kΩ TT L compatible, nominal +5 volts to lift pen

PEN LIFT I F O UT

Access to the 10 MH z IF. Output level is approximately -15 dB m fo r α full sc reen signal at -30 dB m reference level. N ominal impeda nce approximately 50 Ω

PROBE POWER

Provides operating power for active prove systems. Output voltages and p in-o ut are shown in Fig . 1-1 . GENERAL C HARACTER ISTICS Triggered, auto, manual, and external

Sweep Swee p Time

20 μs/Div to 5 s/Div in 1-2-5 sequence (10s/Div in Auto)

Accuracy

±5% --2 .0 division of signal for internal, and 1 .0 V peak minimum for external

Triggering

Internal, exte rnal, free run, and si ngle sweep. Internal is ac coupled (15 H z to 1 MHz) Displays : Reference level, frequency, vertical

Crt Rea dout

d isplay mode, frequency span/div, frequency ra nge, resolution attenuation

bandwidth,

and

POWER REQUI REMENTS Descriptio n

Characteristic In pu t V oltage

90 to 132 Vac or 180 to 250 Vac, 48 to 440 Hz

Power Power (O ptions 01, 02, 03)

At 115 V, 60 Hz ; 210 watts maximum, 3.2 amperes

Leakage Current

5 mA peak ΝΟΤΕ

If power to this instrument is interrupted, it may be necessary to re-initialize the microcomputer, when power is restored, turn the POWER switch Off for 5 seconds then back On .

REV AUG 1981

RF

Specification-492/492P Se rvice V ol . Ι (S N Β030000 & up)

PR OBE P OWER . T h e PRO BE P O WER co nn ector on t he rear p a nel of t h is i n strum e nt p rovid es o p e rati n g power for active p ro be syste m s . It is not recomme nd ed t h at t h ese co nn ectors b e used as α power so u rce fo r a pp licatio n s ot h er t h an t he co mpatible probes or ot h er accessories wh ic h a re s pecifically d esigned for use wit h t h is sour ce .

-15 V, 100mA max.

G ND.

+15V , 100 m A max.

+S V, 100m A max. 2726-21

F ig . 1-1 . Probe power co nnector pi n o ut.

Ta ble 1-2 ENVI RONMEN TAL CHARACTER ISTICS

M eets M I L Τ-28800 Β, type III, class 3, style C specifications, comprised of the following : Desc ription

Characteristic Tem p erature Operating an d humidity Non-operating

-15°C to +55°C/95% (+5%,-0%) relative humi d ity. -62°C to +75°C . ΝΟΤΕ

After storage at temperatures below the operating range, the microcomputer may not initialize on power-up . If so, allow the instrument to warm up for 15 minutes and re-initialize the microcomputer by turning the PO WER Off for 5 seconds then back On .

Altitude Operating Non-operating

15,000 feet . 40,000 feet .

Humidity (Non-operating)

Five cycles (120 hours) of M I L-St d -810 .

V ibration

M et hod 514 Pr ocedure Χ (modified ) M I L-Std-810C .

Op erating

i -i 2

Resonant searches along all three axes at 0.025 inch, freq uency varied from 10-55 H z, 15 mi n utes . All major resona nces must b e mi nimum per axis plus dwell at reasona n t freq uency of 55 Hz for 10 mi n utes minimum per axis . Instrume nt sec u red to vi b ration platform during test . Total vibratio n time about 75 minutes.

REV AUG 1981

Specification-492/492P Service Vol . Ι (S N Β030000 & up) Tab le 1-2 (cont) Descri ption

Cha racter istic Shoc k (Operati n g a nd Non-operating)

Three shock s of 30 g, one- h alf si n e, 11 ms duratio n , each directio n along each major axis . Guillotine-type sh ock s. Total of 18 s hock s.

Transit drop (free fall)

12 inch , o ne per each of six faces a nd eight corners .

E lect romag netic Interference (EMI)

Withi n limits describe d

in M I L-Std-461 .

Test Met h od Con ducted emissions

Conducted susce p tibility

Radiated emissions

R emark s

CE01

10 kHz to 20 kH z only .

CE 03 20 kH z to 50 MHz power lead s.

E xce pt 30 kH z to 35 kH z, relaxed by 15 dB.

CS01 30 H z to 50 kHz power lea d s.

Fu ll limits .

CS02 50 kH z to 400 kHz power leads.

Full limits .

CS06 s p ike power leads.

Full limit.

RE 01

Relaxe d by 10 dB for fu nd amen tal. 2 nd, and 3rd harmonic of power line .

30 Hz to 30 kHz m agnetic field

RE 02 14, ±3 kH z to 10 GH z. Radiated suscepti bility

RS01 30 Hz to 30 kHz mag netic field .

Full limit.

RS03 up to 10 GH z.

Full limit.

Ta ble 1-3 Physical Cha racteristics Descri ptio n

Characteri stics Weig h t (standard accessories and cover except manuals)

44 pound s (20.0 kg) maximum.

Dimensio ns (Fig . 1-2) Without front cover and han d le o r feet.

6.9 Χ 12 .87 Χ 19 .65 i nches (17.5 Χ 32 .69 Χ 49 .91 centimenters).

With fron t cover , feet and handle

9.15 Χ 15 .05 Χ 23 .1 i nches (h and le folded (handle fully extended).

REV AU G 1981

back over i nstrume nt), 28 .85 in ches

1-13

Specification-492/492P Service V ol . Ι (SN Β030000 & up)

c

.02 cm (13.0 i n ) -ή Ι

t 3 8.1 cm (15 in .)

57 .6 c m (23 i n.)

2726-10Β

Fig. 1-2. Dime nsions.

ACCESSORI E S See Accessories page following R eplaceable M echanical Parts list, Volume 2.

O PTIONS Options available for the 492/492 Ρ and thei r resultant changes to the specifications are listed below. Options are factory installed at the time of th e initial order . Contact your local Tektronix Field Office for additional informatio n. OPTION 01 This o p tion provides calibrated preselection to the first (1st) mixer for the 1 .7 to 18 GHz freque ncy ra nge and limiter protection below 1 .8 GHz. B and 1 b ecomes 100 kH z to 1 .8 GHz using an inp ut low-pass filter ; th e p reselector starts at B and 2 (1 .7 GHz) . The following changes and additions in elect r ical c haracteristics apply :

1-14

REV A UG 1981

Specification-492/492P Se rvice V ol. Ι (S N Β030000 & up) Ta ble 1-4 OPTION 01 ELECTRICAL CHARACTER ISTICS Characte ristic

Performance Requirement

Su pp lemental Info rmation

S purio us Res po n ses

I ntermodulation P roducts 1 .8-18 GHz

At least -70 dB c from any two on-screen signals within any frequency span.

1 .7-1 .8 GHz

At least -70 dBc from any two -40 dBm signals within any frequency span.

H armonic Distortion

(cw signal 1 .7-18 GHz)

-100 dB c or more for full screen signal (MIN DISTORTION mode).

LO emission, referen ced to

L ess than -70 dBm to 18 GHz.

in put mixe r and with zero RF attenuation

,-100 dBc when sig n als are separate d 100 MH z or more.

Input L evel

M aximum Safe Input with

1 watt or +30 dBm .

zero RF attenuation

1 dB Compression P oi nt (minimum) : 1 .7-2 .0 GHz

-28 dB m, no RF attenuatio n.

Ot herwise

-18 dBm, no RF attenu atio n.

F req uency Res pon se and

Display Flatness

Coaxial (direct) Input

B and 1

100 kH z-1 .8 GHz 50-1 .8 GH z

About mean average

Referenced to 100 MHz

±1 .5 dB ±2 .5 dB

B and 2 1 .7-5 .5 GHz

±2 .5 dB

±3 .5 dB

Band 3 3.0-7 .1 GHz

±2 .5 dB

±3 .5 d B

Band 4 5.4-18.0

±3 .5 d B

±4 .5 dB

Band 5 15 .0-21 .0 GHz

±5 .0 dB

REV AUG 1981

Freq uency response is measu red with RF attenu ation ,10 d B and PEAKI NG optimized for each center frequency setting, when applicable . Response includes the effects of inp ut vswr, mixi ng mode (η), gain variation, preselector, and mixer. Display flatness is typ ically 1 dB greater than the frequ ency response .

1- 1 5

Specification-492/492P Service Vol . Ι (SN Β030000 & up) Table 1-4 (cont)

C haracteristic

P erformance Requirement

Supplemental Information TEKTRONIX H igh Performance Waveguide Mixers.

E xternal H igh Performance Waveguide M ixers B and 6

18 .0-26 GHz

±3 .0 dB

±6 .0 dB

Band 7 26-40.0 GHz

±3 .0 dB

±6 .0 d13

±3 .0 dB

±6 .0 dB

B and 8

40-60 GHz

Band 9 60-90 GHz

Dependent on external mixer.

B and 10

Dependent on external mixer.

90-140 GHz

B and 11

Dependent on external mixer.

140-220 GHz

S ENSITIVITY T he following tabulation shows the equivalent maximum input noise for each resolution bandwidth, with t he internal mixer for frequency bands 1-5 (100 kHz-18 GHz), and TEKTRONIX H igh Performance Waveguide M ixers for bands 6-10 (18 GHz-140 GHz) . The N ARROW video filter is activated, for narrow resolutions (1 kHz or less) ; WIDE filter for wide resolution .

Equivalent Input N oise for Resolution Bandwidths

Frequency/Band 1 kHz

10 kHz

100 kHz

1 MHz

50 kHz-7.1 GHz (Bands 1-3)

-110 dBm

-100 dBm

-90 dBm

-80 dBm

5 .4-12.0 GHz (Band 4)

-95 dBm

-85 dBm

-75 dBm

-65 dBm

12 .0-18.0 GHz (Band 4)

-90 dBm

-80 dBm

-70 dBm

-60 dBm

15 .0-21 .0 GHz (Band 5)

-85 dBm

-

-

-

18 .0-26.5 GHz (Band 6)8

-100 dBm

-90 dBm

-80 dBm

-70 dBm

26 .5-40.0 GHz (Band 7)8

-95 dBm

-85 dBm

-75 dBm

-65 dBm

40 .0-60.0 GHz (Band 8)8

-95 dBm

-85 dBm

-75 dBm

-65 dBm

50 .0-90.0 GHz (Band 9) 90 .0-140 GHz (Band 10) 140-220 GHz (Band 11)

E xternal M ixer Dependent

E xternal Mixer Dependent E xternal Mixer Dependent

*TEKTRONIX High Performance Waveguide M ixers.

1- 1 6

REV AUG 1981

Specification-492/49213 Service Vol. Ι (S N Β030000 & up)

OPTION 02 This option p rovides digital storage. Th e following are the changes an d add itions to the inst rument. Mu ltiple memory (Α & Β) d is play storge is provided with: Save Α, Max H old, Β memory mi nus Save Α memory, d igital display averaging, and storage bypass for non-store d isplay . When d igital storage is used, an add itio nal qu antization error of 0.5% of full sc reen must be added to the measured amplitude characteristics (i .e ., fr eq uency response, sensitivity, etc.) .

OPTION 03 This option provides fi rst (1 st) local oscillator stabilization by phase locking to an inte rn al reference to reduce resi du al FM w hen narrow b ands are selected. The microcom puter automatically selects ph ase lock for α s pan/divisio n of 50 kH z or less in bands 1 throug h 3, 100 kH z or less in band 4, and 200 kH z or less in bands 5 and above. This option also add s α 100 H z r esolution filter. The following electrical characteristics h ave been changed :

OPTION

C haracte ristic

03

Tab le 1-5 ELECTRICAL C HARACTER ISTICS

Performance Requ irement

Suppleme ntal Informatio n

Frequen cy Span/Div Range

B and

Narrow S pan

Wide S pan

1-3 (0-7 .1 GHz)

500 Ητ/Div

200 ΜΗτ/Div

4-5 (5 .4-21 GHz)

500 Ητ /Div

500 ΜΗτ/Div

6 (18-26 GHz)

500 Ητ/Div

1 GHz/Div

(26-60 GHz)

500 Ητ/Div

2 GHz/Div

9 (60-90 GHz)

500 H z/Div

2 GHz/Div

10 (90-140 GHz)

500 Ητ/Div

5 GHz/Div

11 (140-220 GHz) 500 Ητ /Div

10 GHz/Div

7-8

Two add itional positions provide full b and display (Max span) or 0 Hz (time domai n display. Accuracy

Resol ution

REV A UG 1981

Within 5% of the span/div selected over t he center eight divisions of α ten division display. Additional resolution bandwidth of 100 Hz with 7.5 :1 shape factor.

1- 1 7

Specification-492/492P Service V ol . Ι (S N Β030000 & up) Ta ble 1-5 (co n t)

P erfo rma nce Req uirement

Characteristic Noise Sidebands

At least -75 dBc at 30 times the resolution bandwi dth offset (-70 dBc fo r 100 Hz resolution bandwidth) for fundamental mixi ng.

Resid ual FM (s hort te rm) after 2 hour warm up

--(50 Hz pea k-to-peak)η, for α period of 20 ms . η is the 1 st LO h armo nic number u sed in the 1 st mixer co nversion, and related to the selected f requency r ange (b and) .

Supplemental Information

No video filter.

Frequency Drift, at α fixe d frequency : Β039999 and below and after α 2 hour warmup.

_-25 kH z/hou r, fundamental mixing.

Β040000 and up and after α 30 mi nute wa rmup;

_-15 kH z/10 mixing .

after α 1

hour wa rmup .

fundamental

_-5 kH z/10 mi nutes, ty pical .

_-3 kH z/10 mi nutes, fundamental mixing.

~1 kH z/10 mi nutes, typical .

mi nutes,

8 dB bette r t han 1 kHz sensitivity.

Sensitivity (100 Hz)

OPTION 08

Deletes External M ixer ca pability. Standard accessories do not incl ude the Diplexer. F requency range of the instrument is 50 kH z to 21 GHz.

I ncludes : Ge neral

Purpose

OPTION 20

Waveg uide

M ixers; 12 .5 to 40 GHz as listed below. Te kt ronix P art No. 016-0640-00.

Freq u e ncy Range

P art Nu mber

Se nsitivity : Equivalent Input Noise Q 1 kHz Band widt h (Typical)

12 .4-18 GHz 18 .0-26.5 GHz 25 .6-40 GHz

119-0097-01 119-0098-01 119-0099-01

-75 dBm -70 d Bm -60 d Bm

Cable : TNC-to-S MA male connecto rs, 012-0748-00

1- 18

REV A UG 1981

Specification-492/492 Ρ Service Vol . Ι (S N Β030000 & up)

OPTION 21 (WM 490-2)

Incl udes: H ig h Performance Waveguide M ixers; 18 to 40 GHz mixers and cable as listed. Frequ ency Res ponse

N omenclature

Sensitivity: Eq uivalent Input Noise @ 1 kH z B and wi dth (Maximum)

Mean Average

R efe renced to 100 MHz

18 .0-26.5 GHz

WM 490 K

-100 dB m

±3 .0 dB

±6 dB

26 .5-40 GHz

WM 490A

-95 dB m

±3 .0 dB

Frequ e n cy R a n ge

Ι

±6 dB

Ca ble : SMA-to-S MA co nnector, 012-0649-00

OPTION 22 (WM 490-3)

Includ es : H ig h Performance Wavegui de M ixers: 18 to 60 GHz mixe rs and ca ble as listed.

Freq ue n cy R esponse

Nome n clat u re

Se n sitivity : E quivale nt Input N oise @ 1 kHz Ba ndwidth (M axim um)

18 .0-26.5 GHz

WM 490K

-100 dB m

±3 .0 d B

±6 d B

26 .5-40 GHz

WM 490A

-95 d Bm

±3 .0 d B

±6 dB

40-60 GHz

WM 490U

-95 d Bm

±3 .0 dB

±6 d B

Frequ e n cy Range

Mea n

Refe re n ce d

Ave rage

to 100 MH z

Ca ble : S MA-to-S MA male conn ector, 012-0649-00 ΝΟΤΕ These characteristics assume that the waveguίde mixer is connected to α cw signal source an d that the PEAKING control is adjusted for maximum signal amplitude. The signal must be stable (not fre quency modulated more than the resolution bandwidth); otherwise, freque ncy response specifications ca nnot be met.

OPTION 30 Rack mo unt ve rsion of 492/492Ρ Spectru m Analyzer . (See Rackmount/Benc h to p Versions, Sectio n 6.)

OPTION 31 Rackmo unt ve rsion of 492/492Ρ with cables from front panel to

back of the cabinet . (See Section 6.)

OPTION 32 B enchtop versio n of 492/492Ρ Spectrum Analyzer. (See Sectio n 6.)

REV AUG 1981

1- 19

Specification-492/492P Service Vol . Ι (SN Β030000 & up)

OPTIONS F OR

POWER CO RD CO NF IG URATIO N

Tektronix h as im pleme nted options that provide internationally approved power cord and plug config urations. These are s h own and illustrated in Fig . 1-3.

Power Co rd Option Numbe r

N orth American

_ 120V/1 5A

181-0118-00

A3 Australian

_ 240V/1 OA

161-0135-00

_ _

Α2 _

Un iversal

E uro

UK

240V/1 3A

220V/1 3A

~ 161-0132-00

161-0133-00 -

[A4]

Nort h American

_ _ _ _ _ _ 240V/1 5A

161-0134-00

Α5 Swiss

/6 Α _ _ _250V/6

161-0167-00

3784-171

F ig . 1-3 . Inte rn atio nal power cord and plug co nfiguration fo r t he 492/492Ρ.

1- 20

REV FEB 1982

Section 2-492/492Ρ Service Vol . Ι (S N Β030000'& up)

I N STA LL ATIO N

A N D REP AC KAGI N G

I ntrod uctio n

This sectio n describes unpac king, installation, power requi reme n ts, and repackaging information for the 492/492Ρ Spectrum Analyzer. Refer to Rackmo unt Benchtop section for informatio n on th ese versions of th e in strume nt.

The h andle of the 492/492Ρ can be positioned at seve ral angles to serve as α tilt stan d, or it can b e positioned at th e top rear of the in st ru ment between the feet a nd the rea r panel so that 492/492Ρ i nstruments can be stacked. To position the handle, press in at b oth pivot points and r otate the h andle to the d esired position .

Unpackaging and I nitial Inspection

Before unpacking the 492/492Ρ from its shipping container or carton, inspect for signs of external d amage. If the carton is d amaged, notify the ca rrier as well as Tektronix, I nc. The shipp ing carton contai ns the b asic instrument an d its stan dard accessories. Optional accessories are shipped in separate containers . Refer to the Accessories page followi ng the Replaca ble M ec hanical Parts list in the 492/492Ρ Service Volume 2 manual for α complete listing. If the contents of the shipp ing co ntainer are incomplete, if there is mechanical damage or defect, or if the instru ment does n ot meet operatio nal chec k requ irements, contact your local Tektronix Field Office or repr esentative . Th e instrument was inspected both mechanically and electrically before s hipment. If should be free of mech a n ical damage and meet or exceed all elect r ical specification s. Procedures to chec k functional or operational performa nce are in the Cali bration section. The functional chec k procedu re ve rifies proper instrument operation a nd should satisfy the re qui rements fo r most receiving or i ncomi ng inspections. The electrical performance check follows the fu nctional chec k. Pr eparation for

U se

The 492/492Ρ can be installe d i n any position t hat allows air flow in the bottom a n d out the rear of t he in st ru ment . Feet on the four corn ers allow am ple clea rance even if the instrument is stac ked with other inst ruments . Α fan draws air in thro ugh the bottom and expels ai r out the back. Avoid locating the 492/492Ρ where paper, p lastic, or like material might b lock the ai r i ntake. The front panel cover for the 492/492Ρ provides α dusttight seal . U se the cover to protect the front p anel when storing or transporting the instrument. The cove r is also used to store accessories and external waveguide mixers. The cover is removed by first pulli ng up and in on the two release latches then pulling up on the cove r. T he accessories door is u nlatc hed by pressing th e latch to the side and lifting the cove r.

REV AUG 1981

Removing or replacing th e cabinet on th e in strumen t can be haza rdous . The cabinet sh ould only be removed by qualified service personnel . See Removing th e Cabinet at the beginning of the Calibration Procedure section .

Power So urce an d Power R eq uirements The 492/492Ρ is designed to operate from α si ngle-phase

power source that h as one of its current-carrying conduc-

tors (neu tral) at ground (earth) potential . Operating from power sources where bot h current-carrying conductors are isolated o r above ground potential (such as ph ase-to-phase on α multi-ph ase system or across the legs of α 110-220 V single-ph ase, three-wire system) is not recommended, si nce only the line cond uctor h as over-current (f use) protection within the unit . R efer to the Safety Summary at the front of this manual . The ac p ower conn ector is α three-wire pola rized plug with the ground (earth) lead conn ected directly to the instrume nt frame to p rovide electrical shock protection. If the unit is conn ectd to any ot her power so urce, the u nit frame must be con n ected to an eart h grou nd . Power and voltage requ irements are p rinted on α back p anel plate mounted below the power i nput j ack. Th e 492/492Ρ can be operated from either 115 Vac o r 230 Vac n ominal li ne voltage with α range of 90 to 132 on 180 to 250 V ac, at 48 to 440 Hz . Α multipin (harmonica) type connector on the power supply etched ci rcuit board can b e positioned to accommodate either voltage range . When the power supply circuitry is changed to accommodate α different power source, the information p late on the bac k panel must also be changed to reflect the n ew power requ irements . Refer to Changing Power In p ut R ange in Section 1 .

Installation and Repackaging-492/492P Service Vol . Ι (S N Β030000 & up)

R epac kaging for Shipment When the 492/492Ρ is to be shipped to α Tektronix Service Center for service or repair, attach α tag showing: owner and address, name of individual at your fi rm that can be co ntacted, complete se rial n umbe r, and α descri ption of the service required. If the original pac kaging is unfit for use of n ot available, repac kage the equi pment as follows: 1 . Obtain α carton of cor r ugated cardboard h aving inside dimensions t hat are at least six inches more than the eq uipment dimensions, to allow for cushio ning. Table 2-1 lists instrume nt weig hts and carton strength requi rements .

2. Install the front cover on the 492/492Ρ and su rround the equipment with polyethylene sheeting to p rotect the finish.

Ta ble 2-1 SHIPPING CA RTON TEST STRENGT H Gross W eight

Carton Test Strength

Pound s

K ilograms

P ounds

Kilog rams

0-10

0-3.73

200

74 .6

10-30

3.73-11 .19

275

102 .5

30-120 8

11 .19-44 .76

375

140.0

120-140

44 .76-52 .22

500

186.5

140-160

52 .22-59 .68

600

223.8

eApp licable to the 492/492Ρ.

3. Cushion t h e eq u ipment on all si des with pack i ng material or uret h ane foam b etween t h e carton and the sides of the equi pment. 4. Seal with shipping tape or industrial stapler.

2-2

If you h ave any questions, contact your local Te ktronix Field Office or representative .

REV AUG 1981

Section 3-492/492Ρ Service Vol . 1

CA L I BR ATIO N H ISTO RY INFORMATIO N

I NTRODU CTION

Cali bration co nsists of α Performance Chec k and an Adjustment P rocedure. The descriptive detail for these procedures assume the user is kn owle dgeable in t he use of sophisticated test equi pment and test procedures. The Performance Chec k describes proced ures to verify that the inst ru ment is performi ng properl y and meets specifications listed in Section 1 . All tests can be performed without access to the inte rior of the inst ru ment. The Adjustment Proced ure provides instructional steps required to recali brate the instrume nt ci rcuits. After adjustment, the performa nce should be checked b y the p rocedu re described under the Performance Check part. We recomme nd adjusting only t hose circuits that do not meet performance criteria .

T he instrument and man u al are pe riodically eval uated

and updated . If mod ifications require changes in the calibra-

tion procedure, h istory information applicable to ea rl ier inst ruments is incl uded as α deviation within α step o r as α sub-part to α step .

Si nce most in struments will h ave one or more options, procedures fo r t hese options are α sub-part of the step and integrated into this sectio n. The limits, tolerances, and waveform illustrations are aids to calibrate the instrument and are not intended as pe rforma nce specifications.

E QUIPMENT REQUIRE D Ta ble 3-1 lists th e test equ ipme nt and calibration fixtures for the Performance Check and Adjustment Procedure . The characteristics specified are the minimum require d for the checks. Substitute equ ipment must meet or exceed these characte ri stics. Special cali bratio n fixt ures that are listed facilitate the procedure. These are available from Te ktronix, Inc., and may be ord e re d through your local Te ktro nix F ield Office or represe ntative .

recommended

Sophisticated test equ ipment and/or procedures are reir qu ed to accurately measure some h igh tolerance characteristics. In t hese cases, α compromise may b e made in the p rocedure . Any compromise is ind icated by α footnote . Procedures to check t hese h ig h tole rance specifications, when α compromise has been made, can be supplied by Tektronix Service Centers.

Ta ble 3-1

E QUIPMENT RE QUIRED Equipment o r Test

Fixture

Ch a racteristics

Recomme ndation a nd Use

PERFORM ANCE C HECK Test Oscilloscope

Vertical sensitivity, 50 mV/Div to 5 V/Div

Any T EKTRONIX 7000-Series oscilloscope with plug-in units for real-time display such as : 7Α11 /7 Β50Α, and Ρ6108 1 Χ Probe (used to mo nitor signal a n d voltage levels)

Two Time Mark Generators

M arker output, 1 s to 1 μs; accu racy, 0.001

M icrowave Frequency Co unter 10 Hz to 10 GHz, -20 dB m se nsitivity

REV AUG 1981

TEKTRONIX TG 501 an d TM 500-Series Power Modu le (used to check time/div and s pan accuracy)

Hewlett P ackard Microwave

Freque ncy Counter 5342 Α (used to measure the Calibrator o r 2n d LO frequency)

Calibration-492/492P Service Vol. 1 (SN 13030000 & up)

Equipment o r Test

Fixture

Table 3-1 (cont) Characteristic

Funct ion or Sine-Wave

1 Hz to 1 MHz; 0 to 20 V ρ-ρ

Signal Generator(s)

10 Hz to 10 MHz constant outpu t. 250 kHz-110 MH z, leveled output

Generator

Sweep Oscillator

Recommendatio n and Use TEKTRONIX FG 503 Function Generator (used to check external trigge r and horizontal input requi rements)

H ewlett-Pac kard Model 654 (used to

check freq ue ncy response)

Two 500 kH z to 2 .0 GHz generators calibrated and leveled. Output, +10 dBm to -100 dBm; spectral purity, ,60 d B below fu ndamental

TEKT RONIX SG 503 Signal Ge nerator H ewlett-Packard Model 8640Α/Β Option 02 and two 8614Α (used to check freque ncy response ; also used as α signal source for IM and d isplay accuracy check s)

100 kH z to 18 GHz; frequency response, ± 1 .0 dB

Hewlett-Packard Model 8620C with

Power Divide r

Model 86290Α Option 8 and 86222Β Sweep Oscillators (used to chec k frequency response and flatness) H ewlett-Pac kard Model 11667Α

Power M eter with Power Sensors

-60 dBm to -20 dB m full scale; 100 kH z to 18 GHz

H ewlett-Packard Model 435Α with 8482Α and Power Sensors

Vector Voltmeter

Frequency to 100 MH z

Hewlett-P ackard Model 8405A (used to check CALibrato r O UTput)

Power Meter with Lowρass Filter

Measure -20 dB m within ±0.1 dB . The filter must h ave rolloff of 40 dB or more at 200 MHz

H ewlett-Packard Model 435Α with

Comb Ge nerator UHF

Provide comb line to 18 GHz; accuracy, 0.01%

TEKTRONIX Cali bration Fixture 067-0885-00 with TM 500 Power

Spectrum An alyzer

Frequency range, 2.0-3.0 GHz

TEKTRONIX 71-18,71-13 MOD 139U, or 492/492Ρ (used to adjust 1 st and 2nd LO frequency offset)

Attenuator (S MA connectors)

3 dB, 50 Ω; do to 20 GHz

Wei nch el Model 4M . Tektronix Part No. 015-1053-00

Attenuators (bnc connectors ; two required)

20 dB, 50 Ω; do to 2.0 GHz

Tek t ron ix P art No. 011-0059-02

or

8481 Α Sensor (used to check CALibrator O UTput) . Filter : Texscan or Lark

Module (used to check frequency readout accuracy)

Coaxial Cable (50 Ω, 5 ns SMA connectors)

Tektronix Part No . 015-1006-00

Adapter (Ν male-to-SMA male)

Tektronix P art No. 015-0369-00

Adapter (Ν male-to-bnc female)

Te ktronix Part No. 103-0045-00

Τ Connector (bnc)

Tektronix Part No . 103-0030-00

3-2

REV A UG 1981

Calibration-492/492P Service Vol. 1 (SN Β030000 & up) Ta ble 3-1 (cont) Equipme nt or Test

F ixture

Characteristic R an ge, 0-110 dB in 10 dB and 1 dB steps; accu racy, ±0 .1 dB ; freq uency ra nge, do to 18 GHz

Step Attenuators

Recomme ndatio n a nd Use

Ι

Step attenu atoι such as H ewlettPackard 849Β and 8496 Β, calibr ated by precision stand ard attenuators ; such as Weinc hel M odel AS-6 attenuator Te ktronix Part No. 012-0482-00

Coaxial Cables (50Ω; 2 requ ired) ADJU ST MENTS

All the items listed a bove plus the following are requ ired for the Adjustment Procedure.

M odel 62 BF50

R et u rn Loss Bridge

10 MHz to 1 GHz, 50 Ω

Wiltron VSWR Bridge

Attenuator (3 dB miniature)

Frequency, to 5 GHz; connectors, 5 mm

N ARDA M odel 4479 with male-tamale connecto rs

Autotransforme r

Capable of varyi ng line voltage from 90 to 130 Vac

General Radio Variac Type W10MT3

Digital Multimeter

~10ΕιV to -_350 Vdc

TEKTRONIX DM

501A or DM 502Α.

Dc Block

Tektronix Part No . 015-0221-00

Adapter (Sealectro male-to-male)

Tektronix P art No . 103-0098-00; Sealectro P art No . 51-072-0000

Adapter (bnc female-toSealectro male)

Tektronix P art No . 103-0180-00

Three Extensio n Cables (Sealectro female-toSealectro male)8

Tektronix P art No . 175-2902-00

Adapter (bn c-to-Sealect ro)

Tektronix P art No . 175-2412-00

Adapter (bnc female-to-S MA male)

Tektronix P art No . 015-1018-00

Ca ble (20"), Tip plugs to bnc

Tektronix P art No . 175-1178-00

Coaxial cable (8")

Tektronix P art No . 012-0208-00

Screwdriver, tun ing

Tektronix P art No . 003-0675-00

Alig nment tool

Squ are pi n adjustment tool for VR cali bιation

Tek tronix P art No . 003-0968-00

Screwdriver, flat, 6" with 1/8" tip. Screw driver, Ph illips type

No . 1

Allen wrenches (3), 3/32", 5/64", 7/64" Service Kit (Extend e r boards)8

Tektronix P art No . 672-0865-00

°These fixtures a re part of t he Service Kit 006-3286-00, listed in the Mai nte nance Section.

REV AU G 1981

3-3

Calibration-492/492P Service Vol . 1 (SN Β030000 & up) P erformance Check

PERFO RM A N C E C HE C K PR OC ED URE I NTR OD UCTIO N

b. Set the front-panel controls as follows:

As stated in the section introduction, the following procedure is α functional as well as performance check. All performance requirements listed under electrical characteristics in the Specification section are verified . The tests do not include any internal adjustments or c hecks. The checks should be performed in t he sequence given because some tests rely on the satisfactory performance of related circuits . They are also arranged to minimize test equipment setup. If α performance measurement is marginal or below specificat ion, an adjustment procedure to optimize the circuit performance will Adjustment

be found under α similar heading in the P rocedure of this section . If adj ustme nt fails to

return t he circuit to specified performance, refer to the M aintenance section for troubleshooting and repair procedures.

After adjustment, return to the Performance Check to continue with t he calibration process.

I

N CO M I N G I N SPE CTION

TE

ST

The Operators manual contains α functional check that checks all functions of the 492/492 Ρ. T his check is recommended for incoming inspections because it provides α reliable indication t hat the instrument is performing properly . This Performance Check procedure checks all instrument specifications and requires sophisticated equipment as well as technical expertise to perform.

VERI FICATIO N O F TO LERANC E VA LUE S Compliance tests of specified limits, listed in the Performance Requirement column of the instrument specifications, shall be performed after sufficient warm-up time and preliminary preparation (such as front-panel adjustments). M easurements shall be performed by instruments that do n ot affect the values measured .

Measurement tolerance of test equipment should be negligible in comparison to the specified tolerance; and, when not negligible, the error of the measuring apparatus shall be added to the tolerance specified.

BASELINE C LIP T RIGGERING

ΤΙΜΕ/DIV FREQUENCY RANGE FREQUENCY Vertical Display FREQ SPAN/DIV

A U TO

RE SO LUTIO N RF LEVEL

MIN RF ΑΤΤΕΝ dB MIN NOISE (push button) F INE (push button) Digital Storage (Option 02)

Off FREE RUN

AUTO Band 1 (0-4 .2 GHz, 0-1 .8 GHz Option 01) 100 MHz 10 dB/DIV 100 kHz On -20 d Bm 0

Off (MIN DISTORTION) Coarse (not illuminated)

V I EW V I EW

On On

SAVE Α Β -SAVE Α PEAI VAVERAGE

Off F ully εω

Α Β MAX H O LD

Off Off

ε. Allow the instrument to warm up for at least two hours before proceeding with t his check. 1 . Check O peration of Front and Controls

Panel Push Buttons

The following procedure checks functions activated by front-panel push buttons and that the buttons illuminate when the function is active . Operation of the front-panel controls is also checked.

I

W ith the CAL OUT signal applied to the RF NPUT, tune the 100 MHz, -20 dBm signal to center screen . Reduce the FREQ SPAN/DIV to 100 kHz k eeping the signal centered on screen with the FREQUENCY control. Press or c hange the following p ush buttons and controls and note their effect.

INTENSITY. Rotate the control through its range and

n ote crt beam brightness change. PREL I MI NA RY PREPARATIO N α. Perform the initial calibration described under Turn On Procedure in the Operator's manual . For rackmount/ b enchtop versions, refer to Rackmount/Benchtop section of this manual .

3- 4

READOUT. Inactive state, no crt readout . Active state, crt readout of REF LEVEL, FREQUENCY, FREQ SPAN/DIV, VERT DISPLAY, RF ΑΤΤΕΝ , FREQ RANGE, and RESOLUTION BANDWIDTH . The INTENSITY control c hanges brightness.

REV AUG 1981

Calibration-492/492P Service Vol . 1 (SN Β030000 & up) Performance Ch ec k

DRAT ILLUM . I nactive state, no graticule lights . Active

state, graticule lights .

BAS EL INE CLIP. I nactive, no clipping of the display baseline. Active, d isplay intensity at the b aseline is clipped (subdued).

T RIGGER ING. Trigge ring mo de is activated by pressing one of four push butto n s. Pressing any one of the b utto ns cancels or deactivates the other mo de. FREE RUN. Active, t r ace free runs. INT. Active, trace dis played when signal or noise level at left edge is --2.0 divisions and risetime is faster than 24 ms (15 Hz).

LI NE . Active, trace triggered at power line frequency . EXT. Active, trace runs when an external sign al --1 .0 V peak or less is applied to the b ack panel ΕΧΤ IN con nector. SINGLE SWEEP . Pressing this button to activate si ngle swee p aborts the rec urrent sweep; pressi ng the button agai n arms the sweep generator and lights READY, which remains lighte d un til the sweep completes. The analyzer makes α single swee p of the selected spectru m when the conditio ns determi ned b y TRIGGER ING are met. Single swee p mode is cancelled when any TRIGGER ING button is presse d. The effect of SI NGLE S WEEP may be more appare nt if VIEW Α, V I EW Β, and Β -SAVE Α are off.

LIN. Active, display is linear b etween t he reference level (top of graticule) and zero volt (bottom of graticule); the crt VERT DISPL AY reads out in volts/division.

PULSE ST RE TC HER. Active, increases the fall time of video signals to make narrow pulses on t he d isplay easier to see. W it h FREQ SPAN/DIV at MAX, ΤΙΜΕ/DIV at 5 ms and Digital Storage off, the markers should increase in brightness when PULSE ST RETCHER is active. VID E O F ILTER. Two filters, indepe nd ently selected to provide W ID E (1/30t h) or NARROW (1/300th) of the resolution band widt h for noise reduction. DIGITA L STORAGE (O ption 02). Either or both sectio ns of memory can be selected to provi de digital storage. When either or bot h a re activated, sig n al amplit ud e should remain constant. Vary the PEAK/AVERAGE control and note that n oise level below the PEAK/AVERAGE cursor is averaged . VIEW Α/VIEW Β. When SAVE Α is off, either VIEW Α or VI EW Β will d isplay all d ata (1024 bits) in memory . Bot h sectio ns of memory are updated each sweep. When SAVE Α is activated, VIEW Α d isplays data saved in the Α sectio n of memory (512 bits) and VIEW Β displays data (512 bits) in t he Β section of memory. Β sectio n is updated each sweep. SAVE Α. Active, contents in Α memory are saved nd not updated. Verify operation by changi ng REF LEVa EL a nd observe that the V IEW Α display does not change when VIEW Β is inactive .

TIME/DIV . Selects swee p rate an d ma nu al scan operation. In MNL position, M ANU AL SCAN co ntrol should vary the crt beam across the full h orizontal axis of the crt graticule .

MAX H OLD. Active, stores maximum signal am plitud e at each memory location . Verify operation by changing FREQUENCY or REF LEVEL and note that the maximum level at each location is retai ned .

VERTICA L DISPLAY. Display modes are activated by three push buttons . P ressing any of these bu tton s cancels t he other mo de. 10 dB/DIV. Active, d isplay is α cali brated is 10 dB/division, 80 dB dynamic range. Cali bration checked later in this procedure .

Β-SAVE Α. Active, the difference between u pdated data in Β section of memory and that saved in Α is displaye d. Verify by savi ng d ata in Α, then changi ng the refrence level and pressing Β -SAVE Α; only t he d iffe rence ca n be observed by ca ncelling VIEW Α a nd VIEW Β. T he referen ce (zero d ifference) level is normally set at graticule ce nter, b ut can be internally adjusted. See Adjustment Procedure, step 15 .

is cali brated 2 dB /DIV. Active, d isplay 2 dB/division , 16 dB dynamic range . Cali bration is check ed later in this procedure.

PEAK/AVERAGE . When digital storage is activated with VIEW Α or VIEW Β, t his control position s α ho rizontal line or cursor on the display. Signals above the cursor

REV AUG 1981

3-5

Calibration-492/49213 Service Vol. 1 (S N Β030000 & up) Performance Chec k

a re peak detected; signals below th e cursor are ave raged . The cu rso r should position a nywhere within the gratic ule wi ndow.

IDENTI FY 500 kHz/ONLY. Wh en active, the vertical position of the d is play alternately shifts about one d ivisio n. Spurious signals shift horizontally on the alte rn ate sweep, t rue signals do not shift. Reduce FREQ S PAN/DIV to 500 kHz with α signal tuned to cente r screen, reduce ΤΙΜΕ/DIV to α slow sweep rate, and press the ID ENTI FY b utto n. N ote the d isplay of th e cali brator signal . PHAS ELOCK (O ption 03). Activated to reduce residual FM when narrow spans are selected. The butto n lights when active ; p ressing the button turns phasel αk off. When active, the microcomputer automatically selects phaselαk for α span/division of 50 kH z or below in band s 1 t hroug h 3, 100 kHz or below in band 4, and 200 kHz or below in bands 5 and above. AUTO RESO LUTION. Wh en activated, RE SO LUTION BANDWIDTH c hanges so b andwidth is com patible with FREQ SPAN/DIV selection . Chec k by changi ng FREQ SPAN/DIV and n oting that RE SO LUTION BANDWIDTH ch an ges. UN CA L indicator should not light over the FREQ S PAN/DIV range if ΤΙΜΕ /DIV selector is in AUTO position . FRE QUENCY SPAN/DIV. As this control is rotated clockwise, FREQ SPAN/DIV s hould change from 0 to MAX in 1-2-5 se que nce . Display should indicate this change . Range of the Span/Div depends on Options (see Specification sectio n).

FREQUENCY RANGE. Two pus h buttons that shift the 492/492Ρ frequency band s. P ress the Δ b utto n and note the up s hift of bands ; then press the σ butto n and n ote that the bands shift down to the 0 to 4 .2 GHz ra nge (0 to 1 .8 GHz Option 01). CAL. C hec ked when performing Tu rn On Procedure. REFEREN CE LEVEL. Continuous control that requests the microcomputer to change the r eference level one step for each detent. In the 10 dB/DIV Vertical Display mode, the steps are 10 dB. When FINE is activated, the steps are 1 dB . In the 2 dB /DIV mode, the steps are 1 dB or 0.25 dB for th e FINE mode. Wh en F I NE is activated in the 2 dB/DIV mode, the AA mo de is operational . The REFERENCE LEVEL goes to 0 .00 dB then steps in 0.25 dB increments from an initial 0.00 dB reference level. Set the MIN RF ΑΤΤΕΝ to 0 dB . Set the vertical d is play to 10 dB/DIV, and rotate the REFERENCE LEVEL control counterclockwise to +30 dB m then clockwise to -120 dBm. N ote the change in the d is play. Return t he REF LEVEL to -20 dB m and note that 10 dB of RF ΑΤΤΕΝ is switched in at -20 dB m .

MIN RF ΑΤΤΕΝ. Sets the mi nim um amount of RF attenuation . Changing RF LEVEL will not dec rease RF atte nuation below that set by the MIN RF ΑΤΤΕΝ selector.

RE SOLUTION BANDWIDT H. As th is control is rotated, resol ution band width s hould change in decade steps from

F INE. When activated , REF LEVEL switches in 1 dB increments fo r 10 dB/DIV display mode, and 0.25 dB for 2 dB/DIV dis play mode . In the 2 dB/DIV dis play mode, F INE actuates AA mode.

AF . When activated, ce nter frequency readout initializes to 0 MHz. The freq uency d ifference, to α d esired signal or point on the display, can now be determi ned by tun ing that point to ce nter sc reen and noting the readout. Check by measur ing the difference between cali brator markers. If the frequency is tuned below "0", the readout will ind icate minus (-).

MIN NOISE/MIN DISTORTION. O ne of two algorith ms is selected to control attenuator and F gain. MIN N OISE (button illuminated) reduces the noise level by reduci ng attenuation 10 dB a nd decreasing IF gain 10 dB . MIN DISTORTION redu ces IM distortion due to inp ut mixer overload. To observe any change, the RF ΑΤΤΕΝ, dis played b y the εrt readout, must be 10 dB hig her t han t hat set by the MIN RF ΑΤΤΕΝ selector.

1 MHz to 1 kH z (100 Hz O ption 03).

D E GA USS . Wh en pressed, residual magnetism build-up in t he local oscillator system is reduced. Switch FREQ SPAN/DIV to 1 MH z and tune the cali brator ma rker to center screen . Note the signal position, t he n press the DEGA USS button . The signal should shift horizontally and t hen ret urn to α new location . Press again and the signal should return to the same new location. R et ur n FREQ SPAN/DIV to 100 MH z.

3-6

I

UNCA L. T h is light comes on when the d isplay is

uncalibιated. Set the ΤΙΜΕ/DIV to 50 ms, deactivate the

AUTO RE SO LU TION , and set the RESOLU TION BAN DWIDTH to 10 kH z. UN CA L should light and remain lit until t he FRE Q SPAN/DIV is reduced to 200 kH z or t he RE SO LUTION BANDWIDTH is increased to 1 MHz. Return the ΤΙΜΕ/DIV to AUTO and activate the AUTO RESOLUTION . Set the FREQ SPAN/DIV to 100 MHz.

REV AUG 1981

Calibration-492/492P Service V ol. 1 (SN Β030000 & up) Performa nce Chec k

E XTERNAL MIX ER /PE AKI NG. In active mode, b ias for external waveguide mixers is p rovided at the ΕΧΤ M IX ER connection. Activate t he Extern al Mixer mode b y changi ng

the FREQUENCY RAN GE to 18-26 GHz and then measure the b ias with α VOM betwee n the ce nter conducto r and ground of the ΕΧΤ M IX ER port. Bias should r a nge from about -2 .0 to +1 .0 V as the PEAKING control is va rie d. If your mixer requires positive-goi ng bias, the 492 b ias pola rity can be reversed. Co ntact your local Te ktronix F ield Represe n tative. If the instrume nt h as α p reselector (Option 01), the control also varies the preselector tu ning to augment trac king fo r t he coaxial b and s (0-21 GHz). This completes the functional check of the front-pa nel controls and push buttons.

ΝΟΤΕ

Due to residual magnetism buildup in the 1st (Υ/G) oscillator tuning coils, accuracy of the frequency readout should be checked after the tuning coil has been degaussed by pressing the DEGAUSS button. Degauss when the FREQ SPAN/DIV is either 2 MHz or 1 MHz before reducing the FREQ SPAN/DIV to 500 kHz.

α. Test equ ipment setup is sh own in Fig . 3-1 . Set the front-pa nel co ntrols as follows, t hen apply the comb ge nerator o utput to the RF INPUT. FREQUENCY R ANGE FREQUENCY FREQ SPAN/DI V

R eado ut

2. C hec k Frequ ency

492/492Ρ

AUTO

Accuracy for

a nd Tu ne Accuracy of 492Ρ O nly

Readout accuracy ±(5 MHz + 20%ο Span/Div) Χ η o r ±(0.2%ο of center frequ ency + 20% of the span/division) whichever is greater. Tu ne accur acy (492P only) is ± (7% of frequ ency or 150 kH z) Χη or whichever is g reate r, in bands 1 and 2. "η" is the h armo nic n um ber of the 1st LO that is used in the first conversion. Table 3-2 lists " η" and bands .

Ta ble 3-2

H ARMONIC NUMBER (η) vs FREQUENCY RANGE

Band

Frequ ency Range

η

1

0.0-4 .2 GHz (0 .0-1 .8 GHz, Option 01)

1

2

1 .7-5 .5 GHz

1

3

3.0-7 .1 GHz

1

4

5.4-18 GHz

3

5

15-21 GHz

3

6'

18 .0-26.5 GHz

6

7Θ

26-40 GHz

10

8Θ

40-60 GHz

10

9'

60-90 GHz

15

10Θ

90-140 GHz

23

11'

140-220 GHz

37

'External Mixer requ ired.

REV AUG 1981

RE SO LU TIO N

MIN RF ΑΤΤΕΝ Vertical Display Video Filte r ΤΙΜΕ /DIV Digital Storage (O ption 02)

0-4 .2 GHz (0-1 .8 GHz Option 01) 1 .0 GHz 200 MH z On 20 dB

10 dB/DIV WID E AUTO V IEW Α/VIEW Β

b. Tu ne the 1 .0 GHz comb line to center sc reen . Decrease the FREQ SPAN/DIV to 2 MHz o r 1 MHz, keeping the 1 .0 GHz signal ce ntered. Press th e DEGA USS b utton, d ecrease the FREQ S PAN/DI V to 500 kH z, and center the signal und er the frequency dot . ε. Press the ID EN TI FY 500 kH z/ONLY button to ve rify

t h at the signal is α true respo nse . Deactivate the iden tify

feature. If the signal is true, activate the frequency CAL push butto n.

d. Cali brate the frequency readout by adju sting the frequency control for α readout of 1 .000 GHz. Deactivate the CAL pushb utto n. e. Return the FRE Q SPAN/DIV control to 200 MH z and tune the FREQUENCY to the next comb line (1 .5 GHz). Decrease the FRE Q SPAN/DIV to 2 MHz, d egauss the tuning coils, then decrease the span to 500 kH z/div and center t he com b line und er t he frequency d ot. The n press the ID ENTIFY 500 kH z/ONLY pu sh button to verify that the signal is α t rue r esponse . If tr ue, chec k the frequ ency readout accuracy . If α s purious response, tun e to the n ext marker and check. Reado ut must equ al 1 .500 GHz ±(5 MHz + 20% Span/Div) χ η or ; ±(0.2 οό of Center frequency + 20%ο Span/Div) whichever is greate r.

3-7

Calibration-492/492P Service Vol . 1 (S N Β030000 & up) Perfo rmance Chec k

TM 503 Mai n Frame

2727-1 Α

Fig . 3-1 . Test equ ipme nt setup fo r checking frequ ency of the calibrator and the accuracy of the frequ ency rea dout. f. Repeat this process checking frequency readout accuracy in 1 GHz or 2 GHz increments for band s 1 throug h 3 (0 to 7.1 GH z) app lying the limit ±(0.2% of ce n ter fre qu ency +20% of span/div) above 2.5 GHz. Tune α comb line (mark er frequ ency) to ce nte r screen with the FREQ SPAN/DIV at 1 MH z. Press DE GA U SS and recente r t he marker if necessary with th e FRE QUENCY control . Activate the CA L p ushbutton and ad just the FREQUENCY control so the frequency readout e q uals the requi red accuracy at that p oint . (i .e . If the ma rker is above the reado ut frequency the n ad just the readout for α h ig her reading; fo r exam ple, t he rea dout for α 2.000 GHz marker would b e moved to read 2.005 GHz with t he ma rker centere d .) Now r ec heck t he frequency readout accuracy to ensure that the readout is within specificatio ns over the range of the oscillator tuning .

the preselector (Option 01). Wh en c hecking in st ruments with the preselecto r, adjust the PE AKIN G co ntrol for maximum signal r espo nse, when operating above ba nd 1 (0 to 1 .8 GHz), as each signal is tuned to ce nter sc reen. g. Leave the comb gen erator co nnected for 492Ρ; disconnect the comb generator fo r t h e 492. 2Α. 492Ρ only-TUNE Accuracy Check ± (7% of freque ncy or 150 kH z)η, whichever is greater, after α 2-hour warm-up α. Enter the following program on α 4050-Series controlle r:

Since the ot her ban ds operate on harmonics of the osci!Iator fundamental, accuracy o r error will be the same as that meas ured fo r the fun damental b ands multiplied by the h armo nic nu mber (η) of the band .

100 REMARK TUNE CHECK 110 PR INT @1 :"SAVEA OFF ;TRIG FRERUN" 120 WB YT E @33,1 : 130 INPUT Τ$ 140 PR INT @1 :"SIGS WP ;SAVEA ON;T UNE";Τ$;" ;SIGSWP " 150 INPUT W$ 160 GO TO 110

If you choose to check the h ig h er b ands, it may be necessary to increase the REF LEVEL to -10 dBm to locate t rue response of the 500 MHz comb. MIN RF ΑΤΤΕΝ should not be decreased below 10 dB u nless the inst ru ment h as

b. Con n ect the 4050-Series controller to th e 492 Ρ with α GPIB ca ble (bot h should al rea dy be turned on). Set the 492Ρ GPIB ADDRE SS switches for address 1 (switch 1 up, all ot hers in t he switch bank down).

3- 8

REV OCT 1981

Calibration-492/492P Service Vol . 1 (S N Β030000 & up) P erfo rma n ce Chec k ε. Ch ange the front-panel controls for: 1 .7-5 .5 GHz FREQUENCY R ANG E 200 MHz FREQ SPAN/DIV 2 .0 GHz FREQUENCY Off VID EO F ILTER F ully εω PEAK/AVERAGE

d. Type RUN and press RETURN on t he co ntroller. Lin e 110 of the prog ram immediately sets the sweep and the digital storage so you can change FREQUENCY a nd ot her local controls as r equi red for t he TUNE check. Lin e 120 restores local co ntrol with the GT L message.

k. Discon nect the microwave comb generator and connect t he outpu t of the time ma rk generator to the RF NPUT. Set the time mark generator for 1 gs output .

I

Ι. Change the FREQUENCY (and REF LEVEL if n ecessary) while decreasing the FREQ SPAN/DIV to 100 kH z to maintain α centered mark er a bove the 0 H z spurious response . m. Type 1 Μ and press RETURN on the co ntroller. Note the d ifference in t he dis played signals, then press RETURN again .

e. Center the ma rker while decreasing the FREQ SPAN/DIV to 10 MH z. Adju st PEAKING as necessary and set REFERENCE LEVEL to display the comb marker. For non-Option 01 inst ruments, set the SPAN/DIV to 500 kH z and use ID EN TI FY to ma ke sure the analyzer is ce ntered on α real signal, then return to 10 MH z/div.

η. Repeat part m seven times. Reset FREQUEN CY after noti ng the error if the accu mulated TUNE erro r is great enough to move the signal off sc reen . (T he FREQUENCY control is active at the point where you note the TUNE error.) The largest erro r should not exceed 1 .5 d ivisio ns (150 kHz) .

f. Enter 500Μ (type 500Μ an d press RETURN) . If you ma ke an error in this procedure, press BREAK twice and run the program again. If the 492Ρ asserts SRQ (evident by message on controller sc reen an d S in 492 Ρ lower readout), enter WB YT E @20: to clea r t h e SRO.

This completes the chec k of TUNE command performa nce r elated to the 1 st LO. The following steps chec k the upper DAC of the pair that control the 2nd LO center freque ncy .

g. The analyzer t unes 500 MH z, takes α single swee p, and sets up α display of the marker signal you centered and the signal ac qu ired after the TUNE command execute d. Note the error betwee n the two signals.

h. P ress RE TURN to co nti nue. Change FREQ SPAN/DIV to 200 MH z and FREQUENCY to 3.0 GHz. Repeat parts e through g, then repeat the procedure for α frequency of 4.5 GHz. i. Tun e error for t he above chec ks shoul d not exceed 3 .5 d ivision s (7% of 500 MHz tu ne step is 35 MHz) .

T he foregoing procedure chec ks performa nce related to

th e up per DAC of the 1 st LO center frequ ency control . The remaining procedure ch eck s t he lower DAC for the 1 st LO. j . Press RETURN a nd change the controls as follows: FREQUENCY RANGE

0-4.2 GHz (0-1 .8 GHz, Option 01) 200 FREQ SPAN/DIV MH z FREQUENCY 1 MH z REF LEVEL +30 dB m

REV AUG 1981

ο. Increase FREQ SPAN/DIV to 1 MHz and change FRE QUENCY to center α marker at least three d ivisions away from the 0 H z marker: ρ. Decrease the span to 10 kH z/div keeping the marker ce ntered and c hange the time mark er o utput to 10 Ειs . C hange the REFERENCE LEVEL as necessary to k eep the ma rk e r above the noise.

q. Type 100Κ and press RETURN on the co ntrolle r. Note the difference in t he displayed signals, then press RE-

TURN again.

ι. Increase span to 50 kH z/div, c h a nge th e time ma rker

output to 1 μs, and tune FREQUENCY two ma rkers to the left (-2 MHz) . Repeat parts ρ and q. s. Increase the span to 50 kH z/div, change t he time marker output to 1 μs, an d t une FREQUENCY four markers to the r ig ht (+4 MHz) . Repeat parts ρ a nd q.

t. The largest error noted should not exceed 0.7 division (7% of 100 kH z tune or 7 kHz) .

3- 9

Calibration-492/492P Service Vol . 1 (SN Β030000 & up) Perfo rma nce Chec k

T his com p letes α c heck of the 2nd LO upper DAC. Α check of the 2nd LO lower DAC follows. Perform the rest of

1 . Vecto r Voltmeter Method α. Terminate the voltmeter probe with α 50 Ω feedthroug h termi nation and then conn ect t he te rminated probe to the 492/492Ρ CA L OUT co nnecto r (Fig . 3-2) .

this step for Option 03 inst ruments only.

υ. Apply 0.2 ms markers, then cente r one of the markers with the FREQUENCY while reduci ng FREQ SPAN/DIV to 1 kH z (c hange REFERENCE LEVEL as necessary).

b. Set t he vector voltmeter freque ncy to 100 MH z.

ν. En te r 5Κ at the controller and note the difference in the dis played signals. Since mo re than two time marks may be displayed, note the differen ce between th e centered timemarker and the nearest time-marker. The difference should n ot exceed 0.35 division (7% of 5 kH z tune or 350 Hz) .

ε. Chec k-for an rms reading between 21 .11 mV a nd 22 .69 mV (-20 dBm is 22 .36 mV rms across 50 Ω). 2. Powe r Meter Measurement α. Test equ ipment setu p is shown in Fig . 3-2.

3. Check Calibrator (frequ en cy 100 MH z ± 1 .7 kH z, output level -20 dB rn ±0 .3 d B)

b. Connect the power meter sensor t hroug h α

α. Chec k the calibr ator frequency by conn ecti ng α frequency counter (e.g ., TEKTRONIX DC 508 or HewlettPac kard Model 5342 Α Digital Counter) to the 492/492 Ρ CA L O UT co nnector and measure t he frequency . F u ndamental frequency is 100 MHz ± 1 .7 kH z.

lowpass filter (--40 d B at 200 MH z to remove harmo nics of the fundamental) to the CAL OUT co nnector. ΝΟΤΕ

Insertion loss of the filter with pads, measured at

100 MHz, must be determined to within ±0.05 dB. To ensure α 50 Ω match, use approximately 3 dB minimum-loss matching pads (attenuator) on both sides of the filter.

b. Three procedures for measuring output level are giv-

en ; vector voltmeter, power meter, an d comparison method using an accurate -20 dBm so urce.

492 Spectrum A nalyzer

M et hod #1

Vecto r

Voltmeter

150 MHz Low Pass Filter 2727-2Α

Fig . 3-2. Test equ i pmen t setup s howing two met hods that chec k calibrator outpu t level.

3- 1 0

REV AUG 1981

Calibration-492/492P Service Vol. 1 (S N Β030000 & up) Perform an ce Chec k ε. N ote the power reading. Reading, plus the loss through the filter a nd pads, must equal -20 dBm, ±0 .3 dB . 3. Signal Sub stitution Met hod ΝΟΤΕ Α power meter is used to venfy the output level of the reference signal. Harmonics of the signal source must be greater than 40 dB down. α. Apply α 100 MHz signal from α signal source (sig n al ge nerator) through α 3 dB attenuator to t he power meter. Adj ust the outpu t level for -20.0 dBm reading on t he power meter.

b. Set the front- panel controls as follows: FREQUENCY 100 MH z 500 FREQ SPAN/DIV kH z RE SO LU TION 1 MHz REF LEVEL -10 dBm ΤΙΜΕ/DIV AUTO Off Video F ilter Digital Storage VI EW Α/Β (Optio n 02) PEAK/AVERAGE Fu lly εω c. Disconnect the meter an d (using the same inst ru ment ca ble and atte nuator) app ly the calibrated reference signal to t he 492/492Ρ RF NPUT.

I

ΝΟΤΕ

If greater accuracy is desired, the vertical signal can be amplified through an external amplifier, such as the TEKTRONIX 7Α15, to increase the vertical sensitivity. This is done by applying the vertical signal at the rear panel VERT connector of the 4921492Ρ to the external amplifier input and selecting the vertical amplification and Τlme/Di v values that provide the degree of accuracy desired. 4. Check RF Attenu ator (wit hin 0.3 dB/10 dB to α maximum of 0.7 dB over the 60 dB range to 4 GHz; within 0.5 dB/10 dB to α maximum of 1 .4 d B over t he 60 dB range to 18 GHz)

ΝΟΤΕ

The attenuator is factory checked to ensure accuracy. Any change in characteristics should be large enough to be readily noticed in operation. The Functional Check in the Operators manual provides α good indication of attenuator performa nce and would detect component failure. External 10 dB, 20 dB, or α 30 dB step attenuator (calibrated by the user or manufacturer to within 0.05 dB) must be used as α standard to check the RF attenuator in this procedure. α. Test equipme nt is show n in Fig . 3-3. Apply α 0 dBm, 4 GHz signal, from α signal generator through 30 dB of calibrated attenuation to the RF INPU T of the 492/492Ρ. Set the front p anel controls as follows:

FREQUENCY RANGE Band 3 (3 .0-7 .1 GHz) 200 FREQ SPAN/DIV MH z AUTO RE SO LU TION On d . Switch to the 2 dB /DIV dis play mode and tune REF LEVEL -30 dBm the refere nce signal to cente r screen. Select α REF LEVEL t h at positions the top of the signal Vertical Display 10 dB/DIV to α g raticule line (2nd or 3r d from the to p of t he ΤΙΜΕ/DIV AUTO scree n). Select α s pan/d iv and resolution band wi dth to obtain α broad display for mo re accu rate meas urement. If the 492/492Ρ has Opb. Tune the signal to center screen as the FRED tion 02, store the reference d isplay by activating SPAN/DIV is reduced to 20 kH z and change the RESOLUSAVE Α. TION BAN DWIDTH to 100 kH z. Activate the 2 dB/DIV Vertical Dis play mode a nd t h e N ARROW Vid eo Filte r. Adjust t he signal gene rator outpu t so the signal pea k is at some e. Remove the reference signal and apply the CA L g raticule refere n ce level, such as seven d ivision s. If th e inO UT signal to the RF INPUT. str ume nt has Digital Storage, activate SAVE Α. f. Note the displacement of the CAL signal from the reference. If the 492/492Ρ h as Option 02, activate Β -SAVE Α and note the dis placement between t he CA L signal and the reference . Displacement must not exceed 0.3 dB (0 .75 mi nor d ivisio n with α 2 dB/DIV display mode).

REV AUG 1981

ε. Change the REFERENCE LEVEL 10 dB by switching to -20 dB m (this will add 10 dB of RF ATTENuation).

d. Remove 10 dB of external atte nuatio n and compare the difference between the reference level and the new level. 3- 1 1

Calibration-492/492P Service Vol. 1 (SN Β030000 & up) Perfo rma nce Chec k V a riation plus the cali br ated 10 dB external attenuator cor-

rection factor must not exceed 0.3 dB. (If Digital Sto rage is provi ded, activate B- SAVE Α to obtain the differen tial . Deactivate SAVE A and 13- SAVE A.) e. Readjust the signal gene rator o utp ut to esta blish α new reference level . R epeat the process to chec k t he 20 dB atte nuato r by switching the REF LEVEL from -30 dBm to -10 d Bm for 20 dB ΑΤΤΕΝ, then remove 20 d B of exte rnal atte nu ation. E rror must not exceed 0.6 d B. f. R ei nstall the 30 dB of exte rnal atte nuatio n an d set the REF LEVEL to -30 dBm. Re-establish α sig n al reference level as described above. g . Chec k t he 30 dB attenuato r against the exte rn al standard, b y switching the REF LEVEL to 0 dBm, for 30 dB RF ΑΤΤΕΝ, then remove 30 dB of external attenuation. Error must not exceed 0.7 dB . (I nclude the calibr ated atte nu ator correction factor.)

h. Si nce the remaining 60 dB range of the RF ATTEN uator is obtained by the combination of these three attenuators, this completes the check of the RF attenuator. Error of any combination must not exceed 0.7 dB .

5. Check IF Gain Accuracy (±0.2 dB /d B an d ±0 .5 d B/10 d B to α maximum of ±2 dB over the full 90 d B range, 70 d B for α non-Option 03 inst r ume nt) ΝΟΤΕ This check requires calibrated attenuators as the standa rd to check the 10 dB and 1 dB steps. Wh en making signal meas urements within 10 dB of the noise floor, α correction factor should be used to correct for the logarithmic addition of noise in the system and analyzer, as shown in Table 3-3.

492 Spectrum Analyzer

Signal Sour ce +30 d B m to -80 dBm 100 kHz to 10 GHz

Ι Ι t Ι Ι

Calibrated Atte nuators 10 dB &20 dB d

Α

Ι 1 t

1 Ι 1 1 1 1 1

Calibrated 10 dB an d 1 dB step attenuators or se parate 10 d B an d 1 dB atte nuators. 2727-3 Α

Fig . 3-3. Test eq uipment setup for verifyi ng attenuator and gain accuracy.

3- 1 2

REV AUG 1981

Calibration-4921492P Service Vol . 1 (SN Β030000 & up) Performance Check α. Test equipment setup is shown in Fig . 3-3 . Apply α -20 dBm, 10O MHz signal, from the signal generator through 10 dB and 1 dB step attenuators (set at 0 dB), to the RF NPUT ; or directly to the RF NPUT of the 492/492Ρ if individual fixed attenuators are to be used as the standard . Set the front-panel controls as follows:

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I

FRED SPAN/DIV AUTO RESOLUTION Vertical Display Video F ilter REF LEVEL MIN RF ΑΤΤΕΝ

g. Deactivate MIN N OISE . R eturn t he 1 dB step attenuator to 0 dB, decrease the signal generator output to 10 dB or add 10 dB of external attenuation with the 10 dB step attenuator . R eadjust the generator output so the signal level is again at the reference line (6 division amplitude) .

h . Change the REF LEVEL in 1 dB increments from -20 dBm to -30 dBm adding 1 dB increments of external attenuation with the 1 dB step attenuator and note incremental and 10 dB step accuracies .

20 MHz On 10 dB/DIV WIDE -10 dBm 10 dB

b. Tune the signal to center screen, then decrease the FRED SPAN/DIV to 10 kHz. Now c hange the RESOLUTION B ANDWIDTH to 10 kHz and again center the signal on screen . ε. C hange the Vertical Display to 2 dB/DIV . Adjust the signal generator output so the signal amplitude is six divisions with t he top of the signal positioned on the 6th g raticule line . d. Activate MIN N OISE a nd note signal level shift. Shift must n ot exceed ±0 .8 dB, or 2 minor divisions (attenuator plus gain accuracies) . e. Re-position t he signal level to the graticule reference line by adjusting the output of the signal generator. f. Switch t he REF LEVEL from -10 dBm to -20 dBm in 1 dB steps, adding 1 dB of external attenuation at each step and note incremental accuracy and the 10 dB gain accuracy . Incremental accuracy must be within 0.2 dB/dB (0 .5 minor division). M aximum cumulative error must not exceed 0.5 dB (1 .5 minor divisions) except when stepping from the 9 dB to 10 dB increment, where the error could be an additional 0.5 dB .

Ι . Return t he 1 dB step attenuator to 0 dB, decrease signal level 10 dB by adding 10 dB more of external attenuation or decreasing the signal generator output level then reestablish the signal reference amplitude.

j . C heck t he -30 dBm to -40 dBm gain accuracies as previously described .

k. Repeat the procedure checking gain accuracies to -70 dBm. Ι. Establish α signal reference at -70 dBm, activate NARROW VIDEO F ILTER, then check gain accuracy to -80 dBm.

m . Limitation to gain variation measurements over the remaining range is imposed by noise and residual FM'ing . Without Option 03 (phaselock stabilization) oscillator FM'ing

limits practical gain variation measurements to the 10 kHz resolution bandwidth position which further compounds the measurement problem with α 10 dB higher noise floor t han t he 1 kHz resolution b andwidth . The gain variation accuracy of the -80 dBm to -100 dBm REF LEVEL positions are closely related to the accuracy of the previous checks ; t herefore, they are not validated in an instrument without O ption 03 .

Table 3-3 CORRECTION FACTOR TO DETERMINE T RUE SIGNAL LEVEL Ratio in dB n oise-noise

of

signal

p lus

Subtract this correction factor for true signal level

REV AUG 1981

3.01

4.0

5.0

6.0

7.0

8.0

9.0

3.01

2.20

1 .65

1 .26

0.97

0.75

0 .58

~

10 .0

12 .0

14 .0

0.46

0.28

0.18

3- 1 3

Calibration-492/492P Service Vol. 1 (SN Β030000 & up) Perform ance Chec k If the inst rument has Option 03 (phaselock) the 1 kH z resol ution ban dwi dth is utilized. P roceed with t he following:

1) dec rease t h e RESO LU TION BANDWIDTH a nd FREQ S PAN/DIV to 1 kH z and re-esta blish α signal reference level as described previously ; 2) chec k t he -80 to -90 dBm gain accuracies by repeating the process p reviously d escribed; 3) the remaining 10 dB of gain range can not b e c hec ked accurately because of baseline noise. It is, h owever, d irectly related to the -70 dBm to -80 dB m check.

β. C heck Display Accuracy an d Range (80 dB in 10 dB/DIV mode with an accu racy of ±0 .5 dB/10 d B to α maximum cumulative error of ±2 .0 dB over the 80 dB wi ndow; 16 d B in 2 dB/DIV mode with an accuracy of ±0 .2 d B/dB to α maximum cumulative e rror of ± 1 .0 dB over the 16 dB window ; L in mode is ± 5°/ο of full scale) α. Test equipme n t setup is shown in Fig . 3-3. Apply +10 dBm sign al through external attenu ators set to 0 dB to the RF INPU T. Set the front-panel controls as follows:

f. Ret urn t he external attenuation to 0 dB . Change the Vertical Display to LI N. Adjust the signal generator output for α full sc reen display. g. Add 6 dB of external atte nuation . N ote that the signal amplit ude dec reases half screen to 4, ± 0.4 d ivisions.

h. Add an additional 6 dB of attenuatio n. Note signal am plitude decreases to 2, ± 0.4 d ivision s or half am plitude . Ι. Add anot her 6 dB of attenu ation. Signal am plitude s hould decrease to 1 .0, ± 0.4 divisions.

j . Return the Vertical Dis play to 10 dB/DIV and d isco nnect the signal to the RF In pu t.

7. Am plitude Variation with Ba ndwidth (2 divisions, external trigger >1 .0 V, 15 H z to 1 MHz)

α. Apply t he output of α sign al generato r, modulate d by α si ne-wave generator, to the RF NPUT of the 492/492Ρ. M onitor t he output of the si ne-wave generator with α test oscilloscope (see Fig . 3-18).

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REV AUG 1981

Fig . 3-17. Mu ltiple ex pos ure to illustrate how the d ifferential betwee n two signals can be measured.

3- 3 1

Calibration-492/492P Service V ol. 1 (SN Β030000 & up) Perfo rma nce Chec k ΝΟΤΕ

Because of deflection amplifier response, the display amplitude will decrease at the high frequency end. The triggering signal can also be applied through α bnc-tojack cable, to pins 1, 2 and 3 (see Fig . 3-25) of the rear-panel ACCESSOR IES connector (pin 2 is Video in ; pin 1 Ext Video select an d pin 3 is ground) . Connect α jumper between pins 1 and 3.

h. Disconnect t he test equ ipment . Apply, thr ough α bnc

"Τ" connector and coaxial cable, the sine-wave ge nerator output to the ΕΧΤ IN H ORIZ/TRIG connector on the back panel of the 492/492Ρ (see F ig . 3-19). M o nitor the input signal amplit ude with α test oscilloscope . Ι. Set t he sine-wave generator frequ ency to 1 kH z. Adjust its output level fo r 2 V peak-to-peak (1 .0 V peak) as ind icated on the test oscilloscope (see Fig . 3-20). i . Change the 492/492Ρ ΤΙΜΕ/DIV to .2 s. Activate t he ΕΧΤ Triggering .

k. Chec k that sweep runs as the ge nerator freq uency is varied from 15 Hz to 1 MH z. Ι. Ret ur n the TR IGGER ING to FREE RUN and the input signal level to 0 V .

24 . Check External Sweep Operatio n (0 to 10 V ± 1 V s hould provide α f ull sweep across the 10 division graticule span) α. W it h t he test equi pment connected as di rected for th e previous step, change t he ΤΙΜΕ/DIV to ΕΧΤ and deactivate V I EW Α/VI EW Β. b. Change the Vertical Dis play to 2 dB/DIV a nd position

the crt beam on t he left graticule edge with the POSITIO N co ntrol . This esta b lishes the 0 V reference.

7000 Se ries Test Oscillosco pe

Signal Source

2727-22 Α

Fig. 3-1 β. Test equipme nt setup fo r checking t rigge ring requ irements .

3-32

REV A UG 1981

Calibration-492/492P Service Vol . 1 (S N Β030000 & up) Perfo rmance Ch eck 7000

Series

Test Oscilloscope

492 Spectrum Analyzer 2727-23 Β

Fig . 3-19 . Test equ ipme nt setup to chec k extern al triggering and horizontal input characteristics.

ε. Connect the outpu t of the sine-wave ge nerator, with α frequ ency of 1 kHz, to the b ack panel EXT IN connector . Increase the output for α full 10-divisio n sweep.

IVAN

~`i~Ailli

d . Chec k t he outpu t pea k-to-pea k voltage level of t he ge nerator. Output should equal 20 V, ±2 V peak-to-peak (10 V ± 1 V peak).

Aldif Ο

ΝΟΤΕ Α variable voltage source can be used in lieu of the sine-wave generator to check external sweep operation. 3783-21

Fig . 3-20 . Test oscillosco pe d is play of α si newave input signal to ΕΧΤ TR IG connector (input 1 .0 V pea k at 2.0 V pea k-topeak).

REV AUG 1981

e. Discon nect and remove the test eq uipment. Return ΤΙΜΕ/DIV to AUTO .

3- 33

Calibration-492/492P Service Vol . 1 (S N Β030000 & up) P erformance Chec k 25. Chec k Vertical Output (provides 0.5 V + 5% of signal pe r division of display from the centerline) α. Connect the VERT OUTPU T to the inp ut of α decoupled test oscilloscope with α sensitivity of 1 V/DIV an d sweep rate of 10 ms .

b. Set the 492/492Ρ controls as follows: FREQUENCY 100 MHz FREE RUN Triggering ΤΙΜΕ/DIV AUTO 2 d B/DIV Vertical Display RE SO LU TION BANDWIDTH 100 kH z 100 kH z FREQ SPAN/DIV -20 dB m REF LEVEL Digital Storage (Option 02) Off

I

ε. Apply the CA L OU T signal to the RF NPUT a n d tune t he 100 MH z signal to center screen.

d. Activate the FINE step REF LEVEL f unction and adjust the REF LEVEL for an eight d ivisio n display. e. Check the vertical signal output level on the test oscilloscope. Output level should equal plus an d minus 2 V for α total of 4 V ± 0.2 V (see F ig . 3-21). 26. Chec k Horizontal Signal Outp ut (0 .5 V ±5°/ο eit he r side of center sc ree n with α full ra nge of -2 .5 V to +2.5 V ± 10%)

α. Connect α dc-coupled test oscilloscope to the H ORIZ OU TPU T conn ector. Set the 492/492Ρ ΤΙΜΕ/DIV to MNL position .

b. Ad just the crt beam five d ivisio ns either side of cen ter screen with the M ANU AL SCAN control . The outpu t range should equal -2 .5 V to +2 .5 V, ± 10°/ο.

3-34

Fig . 3-21 . Display of α fu ll sc reen signal at the Vertical Output connector.

ε. Ret urn the ΤΙΜΕ/DIV to AUTO ; disconnect and remove the test equi pment. 27 . 492Ρ G PIB Verificatio n Program This verificatio n prog ram fo r T EKTR ON IX 4050-Series Compu te r Te rminal checks functional ope r atio n of the GPIB interface in α 492Ρ Spectrum Analyzer . All interface li nes are verified as well as all interface messages, except those fo r parallel poll . In add itio n, th e inst ru ments' interface is chec ked for operation on other primary addresses, as well as the talk-o nly and listen-o nly modes. The program is written in TEK TRONIX 4050 B ASIC, and is divided into individual tests, each for α specific interface li ne, message, or fu nction. The tests start on even 1000 li ne numbers to allow easy modification of the program .

REV AUG 1981

Calibration-492/492P Service Vol . 1 (SN Β030000 & up) Perfo rma n ce Chec k

The following describes t h e fun ctio n of each test in t he prog ram . Interfaces to user definable keys for recovery from α failed test. Lines 1-5000 : Lines 5000-6000:

Lines 6000-7000: Lines 7000-8000:

Inputs the primary address of the 492Ρ under test (1 should be u sed). ID query respo nse test . The instru ment must b e a ble to talk and listen, to send out its ID? response and manipulate all eight of the DIO li nes for the test to be successful.

Local lock-o ut test. Tests correct operatio n of the interface message that should disable all programma ble front p anel controls.

Lines 8000-9000 :

Go to LOCAL test . Tests correct oper atio n of the interface message that should enable all fro nt pa nel cont rols.

L ines 9000-10000 :

Group Execute Trigger test . Checks that α GET message does cause the 492Ρ to abort the present sweep and re-arm the trigger, ca using α sweep to start and en d, sending out an E nd-ofSweep SRO. Thus, the SRO line, as well as the GET message, is verified.

Lines 10000-11000:

Selected Device Clear Test. T h is test verifies that an SDC message does indeed reset t he 492Ρ's GPI B outpu t bu ffer clea ring out it's ID? response .

Lin es 11000-12000:

Device clear test . This test is identical to the selected device clear test, except the universal command DC L is used instead.

Lines 12000-13000:

Addressed as listener, tal ker test . This test checks to see that the 492Ρ microprocessor correctly recog nized that the GPIA chip has been addressed to listen or talk, and se nds the appropriate character to the crt readout (L or Τ).

L ines 13000-14000:

Se rial Poll test. This chec ks co rrect operation of the serial poll enable (S PE) and serial poll d isable (S PD) interface messages . The status byte is read, and if a nything other than ordinary operatio n is in dicated, the instrument fails the test .

Lines 14000-15000:

GPIB rea r panel switch test. All five primary address switches are c heck ed for correct operatio n. Three subrou ti nes are called in the process of testing one address switch. The fi rst two se nd α formatted messge to the 4050 display, and the third performs the address switch test .

Lines 15000-16000 :

Line feed or ΕΟΙ switch test . Check s for correct selection of line feed as α termination whe n

Lines 16000-17000 :

Talk-only mo de test . When selected, this mode should cause the instrument to send α SET? response and (o ptionally) α C URVE? response whenever th e RESET-TO-LOCAL butto n is p ressed . The stri ng received from the instrument is thus examined for existence of α portion of the correct SET? response after t he RESET-TO-LOCAL b utton is pressed.

Li nes 17000-18000:

selected by this switch by send ing an ID? termi nated only by α li ne feed.

Listen-only mode test . Wh e n selected, this mode will cause the instrument to respond to any message on the bus, since it is always addressed to listen . The command "REF 0" is sent to the bu s without addressi ng the instru ment, then the listen-only mo de is deselected a nd t he instrument interrogated to see if it did respond to the REF command while in the listen-only mode.

Lines 18000-19000:

REV AUG 1981

Interface clea n (and Remote E nable) test . This IFC li ne on the GPIB will un add ress the instrume nt's interface. Th is fact is verified by noti ng that the "L" is not present in t he crt readout, indicating that th e IFC li ne worked ; also the REN line will be unasserted wh e n the end statement is execute d (except for some early 4052 and 4054's). Thus, α front p a n el in the local mode is evidence that the REN line was successfu lly un asserted. (Evi dence it was asserted is that the inst ru ment was able to execute comma nds se nt to it b y previo us tests.)

3-35

Calibration-492/492P Service Vol. 1 (S N Β030000 & up) P erfo rma nce C h eck Lin es 19000-end :

Utility routines. " Rear panel i n terface switch test text routine" pu ts head e rs on the interface switch test d isp lay. T he " rear panel test text routi ne" tells th e operator w h at to do after ch a nging th e address switches. "Test address switch " acq uires an ID? respon se from th e i n strument on its new add ress du ri n g t h e address switc h test. T he "S R Q h a nd ler" will h a n dle any 49Χ S RO's t h at occur , alth ough no ne, except t he power-up S R Q, wou ld be expected . (Th e e nd of sweep SRO dur ing the G ET test is h and led by an oth e r SRO handler.) "Delay Ge n erato r" gene rates delays fo r oth er tests. T he " Failu re Decision Ha nd ler" allows the prog ram to be restarted with the u ser defi nable keys if any test fails .

1 GO TO 5000 4 132=1 5 RE T URN 20 Β2=5 21 RETURN 5000 REM " " 49ΧΡ G P I B VER I F ICATIO N PR OG RA M 5030 ΙΝΙΤ 5040 ON SR Q THEN 19280 5050 DI M V $(400), W$(400) 5060 Ι7=0 5070 P AG E 5080 PR I N T "JJJEN TER 49ΧΡ'S PR I MA RY ADD RE SS (D EF A UL T = 1) " ; 5090 INPUT Τ$ 5100 I F Τ$"" THEN 5130 5110 Α 1=1 5120 GO ΤΟ 5180 5130 Α 1= V A L (Τ$) 5140 I F Α 1>0 A N D Α 1 128 A ND Τ 6< 128 THEN 7000 6160 PR I N T "JJJ" "' D108 T E ST F AI L ' " "G" 6170 GO TO 19530 6180 REM 6190 REM 6200 REM 6210 REM 6220 REM 7000 REM "' LOCA L LOCK-OUT . . . . . .. . . ... . . LL O 7010 PR I N T " "' " LOCA L LOCK-OUT. . . ... . ... LL O

I

I

3-36

REV A U G 1981

Calibration-492/492P Service Vol. 1 (SN Β030000 & up) Performance Chec k 7020 7030 7040 7050 7060 7070 7080 7090 7 100 7110 7120 7130 7140 7150 7160 7170 7180 7190 8000 8010 8020 8030 8040 8050 8060 8070 8080 8090 8100 8110

WB YT E @32+ Α 1,17 : PR INT @Α 1 :"SET?" INPUT @A1 :V$ PR I NT " ΙΙ 49 ΧΡ IN L OCAL LOC K-O UT M OD E (LLO)" PR I NT "ΙΙΑΤΤΕΜΡΤ TO U SE 49 ΧΡ CO NTROLS" PR I NT " II PRESS RE TURN WHEN DO NE " ; INPUT Τ$ PR I NT @Α 1 :"SET?" NPUT @A 1 :W$ I F W$ V$ THEN 7130 GO TO 8000 PR INT "J"` L OCAL LOCK-OUT ... . . .. . . ... .LL O ''' F AI L . . . G GO TO 19530

I

REM REM REM REM REM REM GO TO LOCAL. . . .. . . . . . . . .GT L . . . PR I N T @Α 1 :" ΙΝΙ ;ΤΙΜ?"

I NPUT @A1 : R

PR INT @Α 1 :" ΤΙΜ IN C" PR INT "' "' GO TO LOCAL. . .. . . ... . . ..GT L WB YT E @32+ Α 1,1 : PR INT @Α 1 :" ΤΙΜ?" INPUT @Α 1 :Τ6 I F R Τ6 THEN 8100 GO TO 9000 PR I NT "J ` "' " GO TO LOCAL. . . ... . . .. . GT L "' GO TO 19530

F AI L ***G"

8130 REM 8140 REM 8150 REM 8160 REM 9000 REM "" GROUP EXECUTE TRIGGER. . . ... . .GET 9010 PR INT """' GROUP EXE C UTE TRIGGER . . .GET 9020 ON S RQ THEN 9120 9030 Ι7=0 9040 PR INT @Α 1 :" ΙΝΙΤ ;ΤΙΜ 100M;SIG ;EOS ON" 9050 WB YT E @32+ Α 1,8: 9060 T6 = 3 9070 GOSUB 19390 9080 PR I NT @Α 1 :" EOS OFF" 9090 IF 1 7 < > 1 THEN 9150 9100 ON SR Q THEN 19280 9110 GO TO 10000 9120 WB YT E @20: 9130 Ι7= 1 9140 RE T URN 9150 PR INT "G ROUP E XECUTE TRIGGER . . . GET "' F AI L . .'G" 9160 GO TO 19530 9170 REM 9180 REM 9190 REM 9200 REM 9210 REM 10000 REM " " " S ELECT ED DEV IC E CLE AR . ..SDC ' " " 10010 PR I NT """ SELE CT ED DEV IC E CLE AR .. .SDC 10020 PR INT @Α 1 :"ID?" 10030 WB YT E @32+ Α 1,4: 10040 WB YT E @64+ Α 1 : 10050 RB YT E R 10060 IF A BS( R)255 THEN 10080

REV AUG 1981

3- 37

Calibration-492/492P Service Vol . 1 (S N Β030000 & up) Perfo rma nce Chec k 10070 GO TO 11000 "' G" 10080 PR INT ""' S ELECT ED DEV IC E CLEAR . ... . ... SDC "" FAI L 10090 GO TO 19530 10100 REM 10110 REM 10120 REM 10130 REM 10140 REM 11000 REM "" DEV IC E CLEAR. . .... . ... . DC L "" 11010 PR INT """' D EV IC E CLEAR . . .. . . .. . . . .DC L 11020 PR INT @Α 1 :"ID?" 11030 WB YT E @20: 11040 WB YT E @64+ Α 1 : 11050 RB YT E R 11060 IF A BS( R)255 THEN 11080 11070 GO TO 12000 11080 PR I NT """' D EV IC E CLEAR .... . ... . . .DC L "' F AI L "'G" 11090 GO TO 19530 11100 REM 11110 REM 11120 REM 11130 REM 11140 REM 12000 REM " ADDRE SS ED AS L ISTENER, TA LKER 12010 PR I NT " " " 49 ΧΡ ADD RE SS ED AS L ISTENER ..' 12020 WB YT E (8132+ Α 1 :76,79,82,68,79,-63 12030 Τ6=1 12040 GOSUB 19390 12050 INPUT @A 1 :V$ 12060 Τ$=SEG( V$,16,1) 12070 IF Τ$=" L" THEN 12100 FAI L " .G" 12080 PR I NT "J'"' 49 ΧΡ ADD RE SS ED AS L ISTENER 12090 GO TO 19530 12 100 PR I NT "' "' 49 ΧΡ ADD RE SS ED AS TA LKER . . .." "' 12110 PR I NT @Α 1 :" ΙΝΙ ;ΤΙΜ 50M ;SIG ;SIG ;WAI ; LORDO?" 12120 I NPUT @A1 :V$ 12130 Τ$=SEG( V$,16,1) 12140 I F Τ$=" Τ" THEN 13000 12150 PR INT "' " " 49 ΧΡ ADDRE SS ED AS TA LKER "' F AI L 12160 GO TO 19530 12170 REM 12180 REM 12190 REM 12200 REM 12210 REM 13000 REM "' SER IA L P OLL "' 13010 PR INT " " " SER IA L POLL . . . .. . . .. SP D / SPE 13020 WB YT E @95,63,24,64+ Α1 : 13030 RB YT E R 13040 WB YT E @95,25 : 13050 I F R =0 OR R = 16 THEN 13080 13060 PR INT "J"' SER IA L P OLL "" F AI L ""G" 13070 GO TO 19530 13080 Τ 6=3 13090 GOSUB 19390 13100 REM 13110 REM 13120 REM 13130 REM 13140 REM 14000 REM GPIB NTERF AC E RE AR PANEL SWITCH TE ST "' 14010 P AG E 14020 Α 1 = 2 14030 GOSUB 19000

I

Calibration-492/492P Service Vol . 1 (SN Β030000 & up) P erfo rma nce Check 14040 PR INT " 0 _1 0 _1 0 _1 0 0 0 1 0" 14050 GOSUB 19070 14060 GOSUB 19190 14070 P AG E 14080 Α 1 = 4 14090 GOS UB 19000 14100 PRINT "010_10_100100" 141 10 GOS UB 19070 14120 GOS UB 19190 14130 P AG E 14140 Α 1=8 14150 GOS UB 19000 14160 PR INT "01010101000" 14170 GOS UB 19070 14180 GOS UB 19190 14190 P AG E 14200 Α 1= 16 14210 GOS UB 19000 14220 PR INT " 0 _1 0 _1 0 _1 1 0 0 0 0" 14230 GOS UB 1907 0 14240 GOS UB 19190 14250 REM 14260 REM 14270 REM 14280 REM 14290 REM "L"' OR " ΕΟΙ" SWITCH . . . 15000 REM 15010 P AG E 15020 Al =1 15030 GOSUB 19000 15040 PRINT "0_10_11_100001" 15050 GOSUB 19070 15060 PR I NT " JJ TESTING "LF" OR " ΕΟΙ " SWITCH" 15070 GOSUB 19190 15080 WB YT E @32+ Α 1 :73,68,63,10 15090 INPUT @Α 1 :Τ$ 15 100 Τ$=SEG(Τ$,1,9) 15110 IF Τ$="ID ΤΕΚ/49" THEN 15140 15120 PR I NT "J"LF" OR " ΕΟΙ" SWITCH "" F AI L "'_ G" 15130 GO TO 19530 15140 Τ6=2 15150 GOSUB 19390 15160 REM 15170 REM 15180 REM 15190 REM 15200 REM 16000 REM " ` TA LK O NL Y M OD E "' 16010 P AG E 16020 GOSUB 19000 16030 PRINT "0 Ι 1_10_100001" 16040 GOSUB 19070 16050 PR INT " JJJTESTIN G TA LK O NL Y" 16060 INPUT @A1 :V$ 16070 17= POS(V$," FINE OFF", 1) 16080 IF 170 THEN 17000 16090 PR INT "JJJTA LK O NL Y M OD E "' F AI L "' G" 16100 GO TO 19530 16110 REM 16120 REM 16130 REM 16140 REM 16150 REM 17000 REM " " L ISTEN O NL Y MOD E

REV AUG 1981

3-39

Calibration-492/492P Service Vol . 1 (SN Β030000 & up) P erfo rm a n ce Ch eck 17010 P AG E 17020 GOSUB 19000 17030 PR INT " 1 _1 0 1 0 _1 0 0 0 0 1" 17040 GOSUB 19070 17050 PR I N T " JJJTESTING L ISTEN O NL Y" 17060 PR INT @ υΑ 1:" ΙΝΙ" 17070 Τ6=0.5 17080 GOSUB 19390 17090 WB YT E 82,69,70,32,-48 17 100 PAG E 17110 GOSUB 19000 17120 PRINT "0_10_10_100001" 17130 GOSUB 19070 17140 PR INT @Α 1 :" REF?" 17150 INPUT @A1 :V$ 17160 F V$" REFLVL +0 .0" THEN 17180 17170 GO TO 18000 17180 PR INT "JJJLISTEN O NL Y M OD E FAI L '""_ G" 17190 GO TO 19530 17200 REM 17210 REM 17220 REM 17230 REM 17240 REM NTERFAC E CLE AR A ND REMOT E EN ABLE TEST . . . .. . I FC & REN 18000 REM 18010 P AG E 18020 PR I NT " JJJTESTING IFC(INTERFAC E CLE AR), AND REN(REMOT E EN ABLE)" 18030 WB YT E @32+ Α 1 : 18040 Τ6 = 3 18050 GOSUB 19390 18060 PR I NT "JJCHE CK THE 49 ΧΡ CRT, F OR AN "L" BE TWEEN THE VERTICA L" 18070 PR I NT "DIS PL AY AND THE MIN RF ΑΤΤΕΝ RE ADOUTS ." 18080 PR I NT "JPRE SS RE TURN TO CO NTI NUE ." ; 18090 INPUT Ρ$ 18100 ΙΝΙΤ 18110 PR INT "J IF AN "L" IS STILL PRESEN T, THE IF C L INE IS F AUL TY," 18120 PR INT "I F THE "L" V AN IS HE D, I F C TEST ED OK ." 18130 PR INT "JJCHE CK A LSO THE 49 ΧΡ FR ONT P ANEL FOR PR OPER LOCAL CO NTROL" 18140 PR I "I F THE FR ONT P ANEL IS L OC KE D OUT, THE REN LINE IS F AULTY, IF" 18150 PR INT "NOT, REN TEST ED OK" 18160 PR I NT "JJJ GP I B VERI F ICATIO N CO MPLETEG_" 18170 EN D 18180 REM 18190 REM 18200 REM 19000 REM "' RE AR PA NEL NTERFAC E SWITCH TEST TEXT ROU TI NE "' 19010 PR INT "S ET GPI B ADDRE SS SWITCHE S TO :" 19020 PR INT "J JL ISTEN ITALK ILF O RI ADDRE SS" 19030 PR INT " 6NL YIONL YI E 61116 8 4 2 1" 19040 PR INT "------_Ι----_Ι -----_Ι =----_--" 19050 RE TURN 19060 REM 19070 REM " " RE AR PANEL TEST TEXT ROUTI NE 19080 PR INT "JJA FTER C HANGI N G THE SWITCHE S, " ; JJ" 19090 PR INT "PRE SS THE REMOT E / LOCAL BU TTON O NCE_ 19100 PR I NT "_YΝΟΤΕ : IF YO U GET Α GPI B NTERFAC E ERROR MESSAGE, IT ME ANS THAT THE SWITCH(ES) WERE 'ΝΤ " 19110 PR INT " Ι 19120 PR INT "_ Ί RE AD CO RRECTLY. TO RE -T EST, TYPE" 19130 PR INT " Ι "RUN" F O LL OWE D BY THE L INE NUMBER IN THE" 19140 PR INT '_ Ί ERROR ME SSAG E) " 19150 PR INT "JJ IPRE SS RE TURN WHEN DO NE " ; 19160 INPUT Τ$ 19170 RE TURN 19180 REM

I

I

I

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3-40

REV AUG 1981

Calibration-492/492P Service Vol. 1 (S N Β030000 & up) Perfo rmance C h eck 19190 19200 19210 19220 19230 19240 19250 19260 19270 19280 19290 19300 19310 19320 19330 19340 19350 19360 19370 19380 19390 19410 19420 19430 19440 19450 19460 19470 19480 19490 19500 19510 19520 19530 19540 19550 19560 19570 19580 19590 19600 19610 19620 19630

REM "' T E ST ADD RE SS SWITC H "' PR I N T @Α 1 :"ID?" I NPU T @A 1 :T$ Τ$=S E G(Τ$,1,9) I F Τ$="ID ΤΕΚ/49" THEN 19260 PRI N T "ADD RE SS SWITC H TE ST F AI L "

GO TO 19530 RE T URN

REM REM "' S R Q HA N D LER "'

Τ6=3 GOS UB 19390 P O LL Ζ 1,Ζ 1 ;Α 1 PRI N T @Α 1 :" ERR ?" I NPU T @A1 :S$ PR I N T "GGA N N T ERRUPT OCC URE D ON THE BU S, THE 49 ΧΡ RETURN S " ;S$ PR I N T "JPRE SS RET URN TO CO NTI NUE " ; I NPU T Τ$ RE T URN

I

REM REM "" D EL AY G ENER ATO R "" REM "' Τ6 GI VEN IN SE C (G L O B A L ) "' 19 SC RATCH "' I F Τ60 .5 THEN 19490 REM """ 4051 "'

Τ6= Τ6'220 FO R 19=1 TO Τ6 NEXT 19 GO TO 19510 REM "' 4052 CA LL " WAIT",Τ6 Τ6=0 RETURN REM "" FAI LURE DE CISIO N H AND LER PR I NT "JJ ISELE CT Α UD K :" PR I NT -Ub RE -START" PR I NT " Ι (5) EN D" S ET KEY Β2=0 I F Β21 AN D Β25 THEN 19590 I F Β2=5 THEN 19630 PAG E GO TO 6000 EN D

Th is con cludes the Performance Check p art of t he Cali bratio n Procedure.

REV A UG 1981

3-41

Calibration-492/492P Service Vol. 1 (SN 6030000 & up) Adjustment Procedure

AD JU ST MENT PR OC ED URE If the 492/492Ρ ope ratio n is out of tolerance for α particula r specification, determi ne the cause, repair if necessary, then use t he appropriate adjustment procedu re to return the instrument operation to specification. After any adjustment, repeat that part of the Performance Check to ve rify operation. Allow instrument to warm up fo r at least two hours in am bie nt air of +20°C to +30°C before performi ng an adjustment.

4. Hold the IC devices by their body rather than the terminals. 5. Use containers made of conductive material or filled with conductive material for storage and transportation. Αvoid using οrdίηαη ρΙαstίc containers. Any static sensitive part or assembly (afrcuit board) that is to be returned to Tektronix, Inc., should be packaged in its onίginal container or one with anti-static packaging material.

Waveform illustrations used in t h ese in structions may be idealized. They are not in te nded to be representative of speci fication tole ran ces. Page

Adjustment steps that interact are noted, and reference is made within t he procedu re to the affected circuit or steps.

Ta ble 3-9 ADJU ST MENT ST EPS FOR CALIBRATING THE 492/492Ρ

Adju stme nt Step 1 . Check and adjust low voltage powe r supply . . .

3-43

2. Crt dis play . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44 3. Deflection amplifier, gain and frequency response 3-45 4. Adjust sweep timing . . . . . . . . . . . . . . . . . . . . . . 3-47 STATIC DISCHARGE CAN DA MAGE MANY SEMICONDUCTOR COMPONENTS USED /Ν THIS INSTRUMENT. Many semiconductor components, especially MOS types, can be damaged by static discharge. Damage may not be catastrophic, therefore, not immediately apparent. It usually appears as α Weakening' of the semiconductor characteristics Devices that are particularly susceptible are: MOs, CMOS, JFETs, and hίgh impedance operational amplifiers. Damage can be significantly reduced by observing the following precautions. 1. Handle static-sensitive components or circuit assemblies at or on α static-free surface. Work station areas should contain α static-free bench cover or work plane such as conductive polyethylene sheeting and α grounding wrist strap. The work plane should be connected to earth ground. 2. Α1/ test equipment, accessories, and soldering tools should be connected to earth ground. 3. Minimize handling by keeping the components in their οrίginal containers υηtί/ ready for use. Minimize the remove/ and installation of semkonductors from their circuit boards.

3- 42

5. Cali brate the 1 st LO system and center frequ ency control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-50

6. Check 2nd LO freque ncy and adjust tuni ng range 3-53 7. Adjust 1 st converte r bias . . . . . . . . . . . . . . . . . . 3-57 8. B aseline leveli ng (Video P rocessor) . . . . . . . . . . 3-58 9. Log amplifier cali bration . . . . . . . . . . . . . . . . . . . 3-61 10 . Cali brating the resol ution ba ndwidth and shape facto r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11 . Presetting the varia b le resolution gain and leveling . . . . . . . . . . . . . . . . . . .

band

. . . . . . . . . . . .

3-63

3-66

12 . Cali brator output level . . . . . . . . . . . . . . . . . . . . . 3-68 13 . IF gain calibration . . . . . . . . . . . . . . . . . . . . . . . . 3-68 14 . Digital storage calibratio n . . . . . . . . . . . . . . . . . . 3-69 15 . Setting B- SAVE Α reference level . . . . . . . . . . 3-71 16 .

B an d leveling for coaxial bands (1-5). . . . . . . . 3-71

17 .

B and leveling for waveguide b and s (6-11) . . . . 3-72

18 . Preselector driver (Option 01) calibration . . . . . . 3-73 19 . Phaselοck calibratio n . . . . . . . . . . . . . . . . . . . . . 3-76

REV A UG 1981

Preparation To p repa re the rackmount or benchto p version for adju stment, refer to the Rackmount/ B e nchtop Versions section of this manual (Section 6) . Remove the ca binet of the 492/492Ρ as follows: 1) set the 492/492Ρ on its face or front panel ; 2) loosen the four screws throug h the b ack rubber feet ; 3) pull the cove r up and off of the 492/492Ρ; 4) place the inst ru ment on the bench and recon nect the power cord.

a nd Adjust L ow Voltage Power Supply This high efficiency power supply uses an inte rn al oscilla-

1 . Check

to r. The frequency of the oscillator is adjusted for 66 kH z. This adjustme n t is no rmally required only after replaci ng oscillator components ; therefore, Part 1 of t h is step s hould only be perfo rmed afte r repair. Part 2 is the normal adjustment an d c heck procedure. 1 . Check

a nd Adjust Low Voltage P ower S upply

This h ig h efficiency power su pply u ses an inte rn al oscillator. Th e freque n cy of the oscillator is adjusted for 66 kH z. This adju stme n t is normally required only after replaci ng oscillator components ; therefore, Part 1 of this step should only be performed afte r repair. P art 2 is the normal adjustment an d c heck procedu re. WA RN I NG The 4921492Ρ uses α high efficiency power supply. The potential of the primary ground for this supply is different than chassis or earth ground. An isolation transformer, with α tums ratio of 1 :1 and α 500 VA minimum rating, should be used between the power source and the 4921492Ρ power input receptacle . The transformer must have α three-wire input and output connector with ground through the Input and output. Stancor No. 6298 is α suitable transformer. Α jumper shouldalso be connectedbetween the primary ground side to chassis ground (emitter of 02061 and the ground terminal of the input filter FL301). If the power supply is separated from the instrument and operated on the bench, hazardous potentials will exist within the supply for several seconds after power is disconnected. This is due to the slow discharge of capacitors C6101 and C6111. Α relaxation oscillator ligh ts DS5112 (next to C6111) when the potential exceeds 80 volts. Part 1 Adj usting the Power Supply Oscillator Frequency

α. Remove the Power Su pply module as desc ribed in the M aintenance section. Remove the Power Supply modu le cove r a nd discon nect Ρ3045 . REV FEB 1982

Calibration-492/492P Service Vol. 1 (SN 6030000 & up) Adjustment Procedure b. Apply power to the module b y pluggi ng the power cord into the power input p lug and connect it to α suitable power source (115 V ac or 230 V ac, depending on the position of P1091 on J1091). ε. U se α plastic or insulated t un ing tool or equivalent, to insert between the two power switches to engage these switches .

d. Connect α test oscilloscope probe with α deflection se nsitivity of 5 V/div and sweep rate of 10 As/div to ΤΡ6053 (Fig . 3-22). Note the output waveform of the oscillator U6059 . Am plitude should be approximately 10 V. e. Adjust R6061 (Oscillator Freq Adj) for α waveform period of 15,us (66 kHz) . f. Rei nstall the power supply module cover, then in stall the module on the 492/492P.

Part 2 Chec k and Adjust Low Voltages

α. Connect α Vari αε (line voltage regulator) in line with the 492/492Ρ power input and set the Variaε fo r 117 Vac.

b. Connect α digital voltmete r (DVM) to +15 V test point ( Fig . 3-22Β) on the Ζ-Axis board to monitor th e +15 V supply . ε. Remove t he power supply cover screw located below (see Fig . 322Α). Th is will provide access to the +15 V adjustment, R6028.

t he 10 MHz IF O UTPUT jack on the rear panel

d. Insert α narrow bit screwdriver through the sc rew hole a nd en gage ad justmen t R 6028. Adjust for +15 V on t he DVM . e. Vary the input voltage r ange from 90 to 132 Vac and note that the +15 V s upply remains regulated.

f. Chec k the ot her supply voltages at test points indicated in Fig . 3-22Β against tole rances listed in Table 3-10.

Ta ble 3-10

POWER SUPPLY VOLTAGE TOLERANCES Supply

Tolerance

+9V

+8 .92 V to +10.1 V

-5 V

-4 .95 V to-5 .05 V

-15 V

- 14 .84 V to - 15 .13 V

+5 V

+4 .73 V to+5 .23 V

+17V

+16.8V to +18.6V

+100 V

+95 V to +105 V

+300 V

+280 V to +310 V 3-43

Calibration-492/492P Service V ol . 1 (SN Β030000 & up) Adj ustmen t Procedure

ΝΟΤΕ

α. Switch POWER off and p reset th e INTE N SITY control fully countercloc kwise, MAN U AL SCAN to midrange, and ΤΙΜΕ/DIV to MNL. Set the Intensity Limit R1027 on the ΖAxis b oard ( F ig . 3-23) fully counterclock wise an d Crt B ias R2040 on the H ig h Voltage board (Fig . 3-24) fully clockwise .

Instruments prior to serial number Β042200 do not have Crt Bias adjustmen t 82040. If your instrument does not h ave 82040, proceed to part b of this step. Auto Focus Tracking R1067 and Auto Focus Gain 81063 no longer affect th e display. They are set mid range and not described in this procedure.

b. Switch POW ER on and after the power-up state h as stabilized ch ange the Vertical Display mode to 2 d B /DIV, deactivate READO U T, an d if the instrument h as Option 02 turn Digital Storage off .

g . Remove the li n e voltage regulator (Variac) and

recon nect the 492/492Ρ d irectly to the power sou rce. 2. CRT Display (Z-Axis board)

R. L ocatio n of ϊΡ 6053 and 86061 .

ς. Voltage test paints; on Ί -Ax +s c ίrcurt boai' Fig . 3-22 . Low voltage power supply adj ustm e nts a nd test poi n t location s. 3-44

REV F E B 1982

Calibration-492/492P Service Vol . 1 (S N Β030000 & up) Adju stm e nt P rocedu r e

Fig . 3-23 . Adju st m ents and test points on t he d eflectio n amplifier, High Voltage mod u le, and Ζ Axis/RF nterface b oa rd.

I

c. Adjust Crt Bias as follows: 1) U si ng α voltmeter on the 20 volt range, meas u re an d record the collector voltage of Q4058 or Q4059 (Fig . 3-22) on the Ζ-Axis board. 2) Tu rn INTENSITY cloc kwise u ntil α crt bea m dot app ears on the screen . 3) F oc u s th e dot b y adjusting R 3033 on th e H ig h Voltage boar d ( Fig . 3-23). 4) Set the INT E NSITY control for α collector voltage whic h is about 5 .5 volts h ig her than t he voltage noted in part 1 . 5) Use the non-metallic screwdriver to ad just Crt B ias R2040 co untercloc kw ise u ntil th e crt beam is visi ble, th e n t urn th e adj u stment clockwise u ntil the dot j ust exti n guishes, with t he screen s h a d ed. (If no dot appears with t he ad j u stment full y countercloc kwise, this will b e the b ias setti ng.) 6) Tur n the I NT ENSITY control clockwise u n til α dot is visi ble . Defocus th e dot wit h t he focus ad justment, then ad just Astigmatis m R1058 ( F ig . 3-23) for α round dot . Re-focus the crt beam dot. 7) Turn the I NTEN SITY control co u ntercloc kwise un til the dot ju st d isapp ears and agai n m eas u re the collector voltage of Q4058 or Q4059. Voltage should equal or exceed t he voltage measured in part 4. If the voltage is less, re peat t he proced ure for setting Crt B ias. REV F E B 1982

Β . E arly versio n, of H ig h Voltage assembly . Fig . 3-24 . Location of wi re st r ap ( W4036) on hig h voltage ci rc u it b oard.

d . Adj ust the Crt cathode curre n t as follows : 1) Switch POWER off th en remove Ρ4036 (Fig . 3-24) on t h e H ig h Voltage board. Tur n t he INTE N SIT Y control fully cloc k wise, the M ANU AL SCAN fully counterclock wise an d ensure that the ΤΙΜΕ/DI V is in MNL position. Set the Inte n sity Limit R 1027 on the ΖAxis board ( Fig . 3-23) fully cloc kwise . 2) Connect the voltmeter between ΤΡ 4028 (Fig . 3-24) and t he q rou nd lu q on the crt shield . 3) Tu rn POW E R on . After the instrument in itializes, activate the 2 dB/DIV d isplay mode and switch RE ADOUT and Digital Storage off. 4) Adj ust Intensity Limit 81027 (Fig . 3-23) for α voltage readi n g of 0.9 volt at ΤΡ 4028 . 3-45

Calibration-492/492P Service Vol . 1 (S N Β030000 & up) Adjustment Proce du re Pa rtial of 492 Bac k Panel showing J 104 Accessory Connector

Test Oscillosco pe

Digital Multimeter

D

Function Ge nerator

492 Spectrum An alyzer

2727-16C

F ig . 3-25 . Test equipme nt setup fo r calibrati ng th e Deflection A mp lifier. If th e instrument h as Digital Storage, turn the storage on 5) Switc h POWER off and re-i nstall the jum per and use the PEAK/AVERAGE cursor, positioned at the top Ρ4036, on the H ig h Voltage board. Tu rn POWER on . and b ottom of the sc reen, as α reference line to set geometry . e. Apply t he CA L OU T signal to the RF NPUT and set the front p anel controls as follows : h. Change the REF LEVEL to position t he trace wit hin FREQUENCY 100 MH z t he graticule area with the Vertical Disp lay mode in FREQ 10 SPAN/DI V MHz 2 dB/DIV. Activate Digital Storage if the instr ume n t has Op-

I

RESO LU TION BANDWIDTH MAX ΤΙΜΕ/DIV AU TO REF LEVEL -20 dB m V ID EO FI LTER NARR OW MIN RF0 ΑΤΤΕΝ d B Vertical Display 10 dB Digital Storage off

f. Red uce the FREQ SPAN/DIV toward 0 Hz while k ee pi ng the cali br ato r signal centered on screen wit h t he FREQUENCY control. Adjust the REF LEVEL so the trace is approximately mid-screen ; then adjust the Trace R otation R1021 (Fig . 3-23) so the trace is aligned with t he graticule lines . g. Change th e REF LEVEL so the trace is a pproximately 15 to 20 dB below the top of the screen . Now, while alternately switching between 2 dB/DIV and 10 dB/DIV, adjust Geometry R1051 (Fig . 3-23) for the st raightest trace at the top and bottom of the screen . 3-46

tion 02 .

i . A djust I NTEN SITY so t he trace is just visi ble . j . Ad just Δ Intensity R1030 (Fig . 3-23) so t he brightness of the readout characters is the same (just discernible) as the trace.

k. R otate the INTEN SITY co n trol a nd note th at the b rightness of the trace and readout characters trac k .

3. Deflection Am plifier (gai n respon se)

a nd freq uency

α. Test equi pme nt setup is shown in Fig . 3-25 . Set the ΤΙΜΕ/DIV to 5 ms, Vertical Display to 2 dB/DIV, and switch Digital Storage off. Position t he trace on the bottom graticule li n e. REV FEB 1982

Calibration-492/492P Se rvice V ol . 1 (SN Β030000 & up) Adju stment Procedure d. Set ΤΙΜΕ/DIV to MNL, an d Vertical Display to 2 dB /DIV. e. Connect α digital voltmeter (D VM ) to ΤΡ 1061 (Fig . 3-23) and adjust M ANU AL SCAN for 0.0 V at ΤΡ 1061 . Adjust horizontal Position control to center M ANU AL SCAN dot. f. Ad j ust MAN U AL SCAN for α read ing of +5 V at ΤΡ 1061 . Now ad just H oriz Gain, R1055 (Fig . 3-23), to position t h e crt b eam to the righ t graticule edge (10th graticu le li ne) . g. Adjust M AN UAL SCA N so crt beam moves to th e left edge of the graticule and ch ec k th at the voltage at ΤΡ 1061 is now approximately -5 .0 V .

h. Turn t he P OW ER off an d disconnect the DVM . Remove an d install the Deflection Amplifier board on an exte nd er .

b. Apply α 5 kH z, 0 to +4 V signal, from th e sine-wave generator, throug h α b nc-to-pi n -j ac k ad apter, to the Ext V ideo inp u t (pin 2) an d V ideo Select (pin 1) of the ACCESSORI ES j ack (see Fig . 3-25).

i. Ch ange the test oscilloscope to Ext Trigger. Apply the Readout Off signal at ΤΡ 1011 (Fig . 3-26), in t he upper left co rner of t h e crt rea dout b oard, to the test oscillosco p e E xt Trigger in p ut . Adjust the controls fo r α triggered sweep. Turn th e 492/492Ρ sweep off by acti vating SI NGLE SWEEP, d eactivate Digital Storage and ensure RE ADOUT is on .

c. Adj ust Vert Gain, R1066 (Fig . 3-23), for α fu ll screen display (0 to +4 V) . Remove the 5 kH z signal from pi n 2 of t he ACCESSORIES j ac k .

j. Connect the test oscilloscope probe to the collectors of Q1031 and Q1024. Adj ust C5021 (Fig . 3-27) fo r t he best frequency response (no overshoot or rolloff) .

Fig . 3-26 . Locatio n of ΤΡ 1 101 on Crt Rea d out.

Fig . 3-27 . Test poi nts an d ad j u st m en ts on th e Deflectio n Am p lifier boa rd fo r gain and freq uency respo nse cali bration. RE V FEB 1982

3- 47

Calibration-492/492P Service Vol . 1 (SN Β030000 & up) Adjustment Procedure k. Connect the probe to the collectors of Q1043 and Q1049. Adjust C4057 (Fig . 3-27) for the best response .

q. Adjust C5021 and C4057 for best REF LEVEL readout (straightest letters and numerals).

Ι. Connect the probe to the collectors of Q1072, Q2078 (Fig . 3-27), and adjust C4061 for the b est response.

4. Adjust Sweep Timing

m. Connect the probe to the collectors of Q1095, 02096 (Fig . 3-27), and adjust C5104 for best response. η. Remove the probe and Ext Trigger connection to ΤΡ 1011 . ρ. Set the Vertical Display to L IN and adjust REF LEVEL for 100 μV/ . Set ΤΙΜΕ/DIV to MNL a nd adjust M ANUAL SCAN fully clockwise. ο. Check t he appearance of "Ζ" in GHz of the frequency readout. If n ecessary, adjust C5104 and C4061 (vertical output) for the straightest top on t he Ζ.

α. Test equipment setup is shown in F ig . 3-28 . Select ΕΧΤ Triggering, ΤΙΜΕ /DIV of 10 ms, and α FREQ SPAN/DIV of 10 MHz or less .

b. Apply 10 ms time marks from the time-mark generator to the ΕΧΤ Video In (pins 2 and 1 of the ACCESSORIES j ack, see Fig . 3-28) and the Trigger Output of the timemark generator to the ΕΧΤ TRIG input on t he back panel of the 492/492Ρ. This should provide α display of 10 ms markers. c. Adjust Sweep Timing, R5105 (see Fig . 3-29), for 1 marker/division. (Use POSITION adjustments to align markers.)

492 Back Panel showing J 104 Accessory Connector

71

2727-17Α

F ig .

3- 4 8

3-28 . Test equ i p me nt setup fo r calibrati ng swee p timi ng .

REV FEB 1982

d . Chec k t he re maining TIMΕ/DIV selectio n s fo r ±5% or

less error over th e center eight divisio ns.

e. Set the ΤΙΜΕ/DIV to AUTO, F R E D SPAN/DI V to MAX, and activate A U TO RE SO LU TIO N .

Table 3-11 RE SOLUTION AN D SWE E P RAT E AS Α FUN CTION OF SPAN IN τΗΙ= AU ι ν Μνυε FR E D SPAN/DIV

R E SO L UTION

Calibration-492/492P Service Vol . 1 (S N Β030000 & up) Adjustment Proced u r e f. Check t he Time/Div ve rsus Resol ution Band wi dth as per Table 3-11 for the different FREQ SPAN/DIV settings . g. Return Triggering to FRE E RUN and remove the timem ark generator markers to the 492/492Ρ. Repositio n the trace if moved in part c.

Table 3-11 (cont)

ΤΙΜΕ /DI V

FRED SPAN /DI V

RE SOL UTION

ΤΙ ΜΕ /DIV

MAX

1 MH z

20 ms

200 kH z

10 kH z

10 ms

200 MHz

1 MH z

10 ms

100 kH z

10 kH z

10 ms

100 MHz

1 MHz

10 m s

50 k Hz

10 kH z

10 ms

50 MHz

1 M Hz

10 m s

20 kH z

10 kH z

10 ms

20 MHz

1 MH z

10 ms

10 kH z

1 kH z

50 ms

10 MHz

1 MHz

10 ms

5 MHz

100 k H z

10 m s

5 kH z

1 kH z

20 ms

2 MHz

100 kH z

10 ms

2 kH z

1 kH z

10 m s

1 MHz

100 kH z

10 ms

1 kH z

100 Hz

.5s

500 kH z

100 kH z

10 ms

500 H z

100 Hz

1 s

OPTION 03 ONLY

Fig . 3-29 . Locatio n of timi ng adjustm ent R 5105 a nd ΤΡ 1061 on Sweep board .

REV FEB 1982

3-49

Calibration-492/49213 Service Vol. 1 (SN 8030000 & up) Adjustment Procedure 5. Calibrate the 1 at Frequency Control

L O System

and Center

An alternate procedure for the 492Ρ is provided using program control Before proceeding with this step, check sweep timing and amplitude accuracy. α. Adjust Coarse Tuning R ange 1) Test equipment setup is shown in Fig. 3-30 . Set the front-panel controls as follows: FREQUENCY R ANGE

0-4.2 GHz (0-1 .8 GHz O ption 01 and activate EXTERNAL M IXER). If the 492/492Ρ has Option 01 and Option 08 (External Mixer deleted), switch POWER off, remove Preselector D river board, switch POWER on and select band 1 .

FREQ SPAN/DIV ΤΙΜΕ/DIV Triggering MANUAL SCAN

200 MHz MNL FREE RUN Midrange

2) Connect the digital voltmeter (DVM), set to the 20 V range, between ΤΡ 1058 of the list LO Driver a nd chassis ground (Fig . 3-31), so the voltage at the test point can be monitored . Adjust FREQUENCY for α readout of 0 MHz as the FREQ SPAN/DIV is reduced to 5 MHz. Note the DVM reading. 3) Tune the FREQUENCY for α readout of 4.278 GHz (switch FREQ SPAN/DIV to 200 MHz to facilitate tuning, then reduce to 5 MHz). 4) N ote the DVM setting . 5) If the differential between 0 MHz and 4.278 GHz is not 20 .00 V, adjust Coarse Tuning Range R 1032 on t he Center Frequency Control b oard (Fig . 3-31) until the voltage d ifference between t he two frequency points is 20 .00 V.

Fig. 3-30. Test equipment setup for calibrating sweep ramp for the 1st LO Driver.

3-50

REV AUG 1981

Calibration-492/492P Service Vol . 1 (S N Β030000 & up) Adjustme nt Procedure

b. Cali brate 10 V Su pply 1) Connect the DVM to ΤΡ 1059, on the 1st LO Driver (Fig . 3-31 Α). 2) Adj ust 81034 (Fig . 3-31 A) for -10.00 V). ε. Adjust Sweep Offset 1) Connect α s horti ng strap from ΤΡ 1035, on the Span Attenu ator b oard , to chassis grou nd (Fig. 3-31). M onitor t he voltage on ΤΡ1073 (Fig . 3-31) with t he DVM . 2) Ad j u st Sweep Offset R1063 for 0.00 V. 3) R emove s h orti ng strap an d switch EXTERNAL MIXER off. If th e Preselector Driver board was removed t urn POWER off and replace th e board. Turn POWER on . d. Calibrate Frequency Span to Cen ter Frequ ency Rea dout. (This is followed b y an alternate procedure for 492Ρ only instruments.)

Tune Coil Sweep

I

1) Apply t he Calibrator output to the RF NPUT. Set the FREQ SPAN/DIV to 100 MHz, activate FREQUENCY CA L, then set the readout cali bration at the cente r of the CA L ra nge (range is about ±15 MHz) . Deactivate the FREQUENCY CA L function. 2) Initialize the front panel co ntrol settings by switching POWER off, t hen on . Set t h e FREQ SPAN/DIV to 200 MHz, ΤΙΜΕ /DIV to AUTO, and REFERENCE LEVEL to -30 dBm (MIN RF ΑΤΤΕΝ at 0 dB). 3) Adjust th e FREQUEN CY to tune t he 18th mark er of the Calibrator signal to th e cen te r of the screen , t he n reduce the FREQ SPAN/DIV to 2 MHz, activate DEGA USS, and set the FREQUENCY readout to 1 .800 GHz. 4) Adjust the 1st LO Offset R1032 (Fig . 3-31) on the 1st LO Driver board to ce nter the 1 .8 GHz marker . 5) Tu ne the FREQUENCY fo r α readout of 100 M Hz (s witch the SPAN/DIV to α higher setting to facilitate tu n ing, t hen bac k to 2 MHz) . Degauss by pressi ng DE GA U SS .

R 1065

Fig . 3-31 . 1st LO b alance and span adjustme nts and test poi nts .

RE V AU G 1981

3- 5 1

Calibration-492/492P Service Vol . 1 (S N Β030000 & up) Adju st ment Procedure 6) Adj ust 1 st LO Sensitivity R 1031 (Fig . 3-31) on t he 1 st LO Driver board to center the 100 MH z marker. 7) Repeat these steps to correct fo r any interaction . 8)

9)

(Press U SER key 3 to start the sequence and press th e BREAK key to stop.)

Tu ne the FREQUENCY for readout of 4.200 GHz (for Option 01 instruments, select ba nd 2 an d tu ne for α readout of 5.500 GHz) . Switch t h e SPAN/DIV to α h ig her setting to facilitate tu ni ng th e n back to 2 MH z. Press the DEGA USS bu tton. Chec k t hat the 4.2 GHz (5 .5 GHz, Option 01) marker is within 8.4 MHz (11 .0 MHz, Option 01) of screen center. (If the error is large it may be necessary to change the SPAN/DIV to 5 MHz.) If th e error is greate r than 8.4 MHz (11 .0 MH z, Option 01) procee d with t he next step, if not proceed to pa ragra ph 11 .

10) Center t he 4.2 GHz (5 .5 GHz, Option 01) marker on screen with the FRE QUENCY control . α) If the readout is equal to or greate r t han 4.216 GHz (5 .522 GHz Op tion 01) ad just the 1st L O Offset R1032, on t he 1st LO Driver b oard , (Fig. 3-31) to move the marker 4 MHz (5 .5 MHz, Option 01) lowe r.

b) If the readout is between 4.208 and 4.216 (5 .511

and 5.522, Option 01) adjust R1032 to move the a ma rk er one h lf the difference between the error and 4.208 GHz (5 .511 GHz, Option 01); for exam ple, α readout of 4.212 wo uld require α 4.210 (4.212 - 4.208) correction.

11) Tu ne the FREQUENCY readout to 4.207 GHz (5 .510 GHz, Option 01) an d ad just the 1st LO Sensitivity R1031, on the 1 st LO Driver board , ( Fig . 3-31) so the marker is at center screen. 12) Rech eck readout accu racy as described in t he Perfo rmance Check part (step 2) of this sectio n, across band 1 (band 1 and 2 of Option 01 inst ruments) to ensure that the accuracy is within performance requ irement.

QUENCY SPAN TO CEN TER FREQUENCY READOUT, FOR 492Ρ INSTRUMENTS. for

the

4050

prog ram

are give n

in

1 . Send

"I NIT ; REF -20;S PAN 2 M;SIG" "FRE Q 100 M;D EG;SIG ;WAIT;FREQ SIG;WAIT; REP 1200"

3-52

2. If the adjustments are fairly close, two signals will appear on sc reen on alternate sweeps; α large and α small signal . The small signal is 1 .8 GHz, the la rge at 100 MHz. Procee d with t he following adjustments : α) Ad ju st the 1st LO Offset R 1032 on t he 1st LO Driver board, to bring t he two signals to the same h orizontal position . If o ne or no signals appear on screen, adjust R1031 u ntil α signal comes on screen. Then adju st R1032 (1st LO Offset) until the second signal app ea rs while alternately adju sting the 1 st LO Sense R1031 to k eep the first signal on screen.

b) Adjust 1st L O Se nse R 1031, on t he 1st LO Driver board, to alig n t he two signals with the vertical ce nterline of the graticu le .

ε) Se nd "FRE Q 4.2 G;DEG" (For Option 01, send; "FREQ 5.5 G; Deg")

d) If the marker is greate r t han 8.6 MHz (11 .0 MHz, Op tion 01) perform steps d(10) and d(11)

e) Rec hec k across band 1 b y re-sendi ng th e 4050 pr ogram of paragra ph 1 above and repeat pa ragrap h 2 procedu re. e. Adjust 1st LO Swee p (App licable to 492Ρ instruments)

both 492 and

1) Wit h t he Cali brator outpu t applied to the RF INPUT, set the FREQ SPAN/DIV to 100 MHz and tune the FRE QUENCY to about 500 MH z. 2) Adjust Tu ne Coil Swp R1065 (Fig . 3-31) on the Span Attenuator b oard so the 100 MHz harmo nics of the Cali brator are spaced at one division intervals over the ce nter eight divisions of the gratic ule . Adjust the FREQUENCY as necessary to align the mar kers. 3) R emove the Cali brator sign al .

A LTERNATE PROCEDURE TO CA LIBRATE FRE-

Instructions parentheses.

This will give an adjustment sequence for a bout two minutes. If necessary, re-send the command to complete the adjustme nt.

1 .8G;D EG;-

4) Set th e FREQ SPAN/DIV to 2 MHz, REF LEVEL to +10 dBm, FREQUENCY about 15 MHz, then apply 0.5 As markers from α time-mark gene rator to the RF INPU T. 5) Adju st t he 1st LO FM Coil Swp R 1071 (Fig . 3-31) for 1 ma rker/division over the center eig h t divisions of the d isplay. f. Adjust 2nd LO Swee p

REV OCT 1981

1) Set the front panel controls as follows : FREQUENCY RANGE FREQUENCY FREQ SPAN/DIV AU TO RESO LU TION Vertical Display REF LEVEL MIN RF ΑΤΤΕΝ

5.4-18 G Hz (Band 4) 6.0 G Hz 20 MHz Activated 10 dB/DIV -10 dBm 20 dB

2) Conn ect th e comb generator to the RF INPU T and apply 10 lιs markers from the time-mark generator to the FM Input of th e comb generator. Adjust PEAKING (Option 1 instrume nts) to maximize the am plitude of the comb markers. ΝΟΤΕ

ifα signal cannot be located at 6.0 GHz with Option 1 instruments, check preselector tracking, step 18. 3) Adjust REF LEVEL and FREQUENCY to display and center the 6.0 GHz comb line, then reduce FREQ SPAN/DI V progressively to 100 kH z while keeping the 6.0 GHz signal centered on the display. 4) Adjust the 2nd LO Sw p, R 1067, (Fig . 3-31) on the Span Attenuator circuit board, so the two comb lines n ea r the graticule edges are 8 divisions (800 kH z) apart. 5) Disconnect and remove the comb ge nerator and time-mark ge nerator from the RF INPU T. R eturn the FREQUENCY RANGE to b and 1 . β. Check 2nd LO Freq uency and Adjust Tun e Range

The procedure applies to both ve rsions of the 2nd LO. An alternate procedure is also described for use with the programma ble 492Ρ over the GPIB bus. α. Chec k the 2nd LO frequen cy as follows: 1) Set the FREQUENCY R ANGE to SPAN/DIV to MAX.

ban d 1 and FREQ

2) Connect α microwave frequ ency coun te r, such as H ewlett P ack ard 5342Α, with α sensitivity of -20 d Bm or better, to the 2nd LO Outp ut connector. 3) M easure the 2nd LO freq uency . Frequ ency should be 2182 MHz ± 1 .0 MHz. If the freque ncy is not within this limit, proceed as follows : Instruments that have the 2182 MHz Phaselock ed 2nd LO (13040000 and up)

REV OCT 1981

Calibration--492/492P Service Vol . 1 (S N Β030000 & up) Adjustment Proce dure

refer to the M ai nte nance section for repai r. If your instrume nt h as the Cavity 2nd LO (Β039999 and below) proceed with t he following adjustment.

α) U si ng α 5/16 inch open-end wrench and α 5/64 inch Allen wrench, loosen the lock nut an d adjust the Fine Tune slug in the cavity (Fig . 3-32B) for a counter readi ng of 2182 .0 MHz.

Do not adjust the two slotted slugs . These are Varactor diode mounts.

b) Tighten the lock nu t and recheck t he oscillator frequency . If correct, d isconnect the counte r and proceed with part b. b. Adjust tun ing range of the 2nd LO as follows : 1) On the Center Frequency Control ci rcuit board, center the Fine Tune R ange, R4040, and the Fine Tun e Se nsitivity, R 3040, adjustments (see Fig . 3-33). 2) Set th e FRE QUENCY TO 5 MHz, FREQ SPAN/DIV to 100 kH z, REF LEVEL to +10 dB m and MIN RF ΑΤΤΕΝ to 10 dB . Apply 21ιs markers from α timemark ge nerator to the RF INPUT. 3) Adjust the FREQUENCY to position α freque ncy marker 2 .5 major divisions right of center then reduce the FREQ SPAN/DIV to 50 kH z. Mar kers should now appear at the graticule edge . 4) Turn the FREQUENCY control countercloc kwise until the 2 nd LO reaches the end of its tuning range (markers stop moving). 5) Note the position of the marker signal . If the instrume nt has digital storage, activate SAVE Α to save the marker reference position. β) Turn the FREQUENCY control clockwise and count th e markers as they cross the reference signal location u ntil t h e end of the tu ning range is reached. The 9t h marker s hould now be on screen close to the reference point. N ote its position with respect to the reference esta blished in part 5. 7) If the 9t h ma rker is more than o ne majo r division from the reference, adj ust Fine Tune Range R4040 so as to reduce this dista nce by one half.

3-53

Calibration-492/492P Service Vol . 1 (S N Β030000 & up) Adjustment Procedure

8) The 492Ρ, if u sed with an external controller, r equires adjustment of the F ine Tune Sensitivity 83040. Α controller is re qu ired to ma ke this adjustment. See Alternate Procedu re for 492 Ρ; ot herwise, R3040 should remain centered . c. Adj ust Identify Offset as follows: 1) Apply 1 μs markers to the RF I NPUT and set the FREQ S PAN/DIV to 500 kH z;

2) Tu ne the FREQUEN CY to 5 MHz th en center o ne of t he 1 jus ma rkers on screen . 3) Acti v ate the ID EN TI FY 500 kH z/ONLY mode; 4) Adju st Coarse Tun e Se nsitivity 81042 (Fig . 3-33) on t h e Center Frequency Co ntrol b oa rd so that, on alternate swee ps, the signals alig n horizontally wit h each other .

492 Spectr um Analyzer

Α. Test e q uipme n t set up fo r ch ec k a n d a djustme nt of 1 st an d 2 nd LO frequency.

Β. T uni ng adjustme nt on th e 2nd LO.

3783-15

Fig . 3-32 . Test equipme nt setup fo r ch eck a nd adju stm e n t of 1 st and 2 nd LO freq u encies .

3- 54

REV OCT 1981

ALTERNATE PROCEDURE FOR 492Ρ ΝΟΤΕ

lnstructίons In parentheses refer to the 4040-Senίes program as listed at the end of step 7 (Adjust 1st Converter Bias) . At the end of any programmed procedure press the RETURN TO LOCAL button. α. Adj u st the 1 st

LO Tune Sensitivity as follows:

1) Set the MIN RF ΑΤΤΕΝ to 30 dB and apply 1 Ει s markers to the RF NPUT from t he time mark ge nerator . Set the FREQ SPAN/DIV to 500 kH z and adjust FREQUENCY to center o ne of the markers on screen.

I

2) Se nd : "I NIT ;FREQ 10 M ;S PAN 100k " to the 492Ρ over the G P IB bu s. 3) Ad ju st the FREQUENCY control to center the marker on screen, then sen d : "TUNE 5Μ ; SIG; WAIT;TUNE -5 M ;SIG ;WAIT; RP T 1200" . This will repeat the adj ustment sequence for about two minutes . Send the instruction again if necessary to complete the adju stment .

Calibration-492/492P Service Vol . 1 (S N Β030000 & up) Adju stme nt Proce dure (Pr ess U SER D E FI NABLE KEY #4 to start the sequence and press BREAK to stop the sequence .) b. Adjust the Coarse Tune Sensitivity R1042 until the

h armo nics of alte rnate swee p are at the same horizontal position in the d isplay as the regular sweep. It is not important where they are i n t he d is play, just so they a re at the same horizontal location . c. Adjust the 2nd L O ra nge as follows:

1) Tu ne the FREQ UENCY to ab out 10 MHz and center one of the 1 Ειs mar kers on screen. 2) Decrease the FREQ S PAN/DIV to 50 kH z k ee ping the marker centered on scree n with the FREQUENCY control . 3) Se nd : "TUNE 2 M ;SIG ;WAIT ;T UN E -2 M ;SIG ; WAIT; REP 1200" . T h is will re peat th e adju stment se quence fo r about two minutes. Repeat the command if necessary.

R 1032 Coat se Tune Sε~ n s,it+νί tγ

Fig . 3-33 . Center Fr equ ency Co ntrol adjust men t location s.

REV OCT 1981

3- 5 5

Calibration-492/492P Service Vol. 1 (S N Β030000 & up) Adjustment Procedure Pr S ER D EF INABLE KEY #5 to start the sequence and BREAK to stop t he seque nce .)

d. Adjust Fine Tu ne Range, R 4040, until the dis played signals for alte rnate sweeps align horizontally with those on t he initial swee p. e. Adjust the 2nd LO Tune Sensitivity as follows: 1) Apply 0.5 ms markers to th e RF INPU T, change the FREE S PAN/DIV to 1 MHz, a nd tune FREQUENCY to about 0 MHz. Decrease the FREQ S PAN/DIV to 5 kH z and tu ne the zero spur to the left side of the display. Decrease the FREQ SPAN/DIV to 500 Hz .

2) Send: "T UNE 2 K;SIG ;WAIT;T UNE -2 K;SIG ; WAIT ; REP 150" . This will repeat the adjustment sequence for five minutes . Repeat the command if n ecessary.

(Press U SER D EF INABLE KEY #6 to start the sequence a nd press BR EA K to stop t he sequence .) 3) Adjust F ine Tune Sensitivity R3040 un til the h armonics dis played in altern ate sweep h ave the same horizontal location as the even sweep. N ote: This may ta ke some time because of the long swee p time and drift.

PROGRAM TO FACILITATE CALI BRATING THE 1 st LO DRIVER AND THE CENTER FREQUENCY CONTROL BOA RDS OF THE 492Ρ, U SING TEKTRONIX 4050-S ERIES CO MPUTER T ERMI NAL

1 2 4 5 8 9 12 13 16 17 20 21 24 25

100

110 120 130 140 150 200 210 220 230

240 300 310 320 330 400

3-56

ON SRO THEN 700 GO TO 700 ON SRO THEN 100 GO TO 210 ON SRQ THEN 100 GO TO 230 ON SRO THEN 100 GO TO 300 ON SRO THEN 100 GO TO 400 ON SRQ THEN 100 GO TO 500 ON SRO THEN 100 GO TO 600 λλλ REM λλλ ERROR HANDLING ROUTI NE POLL Ζ8,Ζ9;Α9 PR INT @Α9:" ERR?" INPU T @Α9: Ζ$ PRINT @Z$ R ET URN REM λλλ ADJU ST COARSE TUNE RANGE R1032 CΕΝ FRE CO NTROL BR D PRINT @A9:'FRE 0" R ETURN PRINT @A9:"FRE 4278M" R ETURN REM "' ADJU ST 1 ST LO SEN SE (GAI N) AND OFFSET PRINT @Α9:" FRE 100M ;D EG;SIG ; WAI" PRINT @Α9:" FRE 1 .8G;DEG;SIG ; WAI" GO TO 310 REM λλλ ADJU ST COARSE T UNE S EN SITIVITY R 1042 CEN FRE CON BR D

REV A UG 1981

Calibration-492/492P Service Vol . 1 (S N Β030000 & up) Ad justment Procedur e 410 420 430 500 510 520 530 600 610 620 630 700 710 720 730 740 750

PR I N T @A9 :"TUN 5M ;SIG ; WAI" PRINT @A9:"TUN -5 M ;SIG ;WAI" GO TO 410 RE M *** AD JU ST FIN E T UNE RANGE R4040 CEN FR E CO N BR D *** PRINT @A9:"TUN 2 M ;SIG ;WAI" PRINT @A9:"TUN -2 M ;SIG ; WAI" GO TO 510 REM *** AD JU ST FI N E 'T UNE S E N SITI VITY R 3040 CEN FRE CO N BIRD PRINT @A9:"TUN 2 K;SIG ;WAI" PRINT @A9:"TUN -2 K;SIG ;WAI" GO TO 610 REM *** START UP PROC EDURE *** PAG E PR INT "ENTER THE 492Ρ'S GPIB PR I M ARY ADDRE SS"; I NPUT Α9 P OLL Ζ8,Ζ9;Α9 R E TURN

7. Adju st 1 st Co nverte r Bias NOTE

This adjustment should only be n ecessaη if frequency response problems are encountered.

α. Switch the FREQUENCY RANGE co ntrol to the 3.0-7 .1 GH z band . Adjust B ias 1 (131043) on the 1st LO Driver (Fig . 3-34) for 0.25 V at ΤΡ 1011 .

b. Switch t he FRE QU ENCY RANGE to th e 5 .4-18 GHz b and. Adjust Bias 2 (R1022) for 0.25 V at ΤΡ 1011 .

Fig . 3-34. 1 at LO Driver adjust ments and test point locations.

REV AUG 1981

3-57

Calibration-492/492P Service Vol. 1 (SN Β030000 & up) Adjustment P roce dur e ε. C hange the FREQUENCY RA NGE co ntrol to the 15-21 GHz band. Adjust B ias 3 (111026) fo r -0 .25 V at ΤΡ 1011 .

8.

Baseli ne L eveling (Video P rocessor)

b. Switch POWER off, pull t he Vi deo Processor board and install it on an extender board. ε. On the Video Processor board pull the Leveler Disa ble plug Ρ3035 (see Fig . 3-36).

This procedure adj usts the b aseline so band 4 respon se perturbations are offset to level the d is play.

d. Switc h POWER on and set the controls as follows: FRE QUENCY RANGE FREQ SPAN/DIV MIN RF ΑΤΤΕΝ REF LEVEL FRE QUENCY Vertical Display RESO LU TION ΤΙΜΕ/DIV

5 α. Test equ ipment setup is s hown in Fig . 3-35 .The output of the swee p gen erator is applied thr ough α 3 dB atte nuato r and h ig h performance coaxial ca ble to α power divider. Connect one outpu t of the power d ivider directly to t he RF NPUT of the 492/492Ρ a nd the ot her to the se nsor fo r the powe r meter. Set th e RF pl ug-in ALC switch to M TR position and 10 co nnect α coaxial cable between R ecorder Output of the power meter and the Ext ALC Input of the 2-15 GHz plug-in unit on the sweeper. Set the Power Level to approximately -10 dBm then adjust the Gain on t he unit for stable operation (output stops oscillating) .

I

V i d eo Processor

Board

.4-18.0 GHz (band 4) MAX 10 dB -10 dB m 10 GHz 10 dB/DIV AUTO ms

e. On th e sweep generator, select α 5.5 GHz εω marker and adjust t he output fo r -10 dBm reading on t he power meter.

on Exten sion

P ower

M eter

To Record er

Out co nn ector ( Bac k P a n el)

R G/58

: ~::.

To Ext. ALC I nput co nnector ( Back Panel)

::. : .::;;:? .::::. ::::; :.::. . . .. ...:.::::~:. ...... . ..; ::;:::: ... ::::: ::::::. 0- ι η r_ υ . οε ι ι ..σι

492 Spectru m Analyzer

Ι /1

Ι%Ι Ι %1 IIII

L ow L oss

Coax Ca b le wit h

SMA

co nnecto r s

2727-150

Fig.

3-58

3-35 . Test equi pme n t set up for

a dju sti ng baselin e

leveli n g .

REV

AU G

1981

Calibration-492/492P Service Vol . 1 (S N Β030000 & up) Adjustment Procedure f. Switch t he Vertical Displa y to 2 dB/DIV and adjust th e REF LEVEL so th e signal amplitude is h alf screen . If the 492/492Ρ h as Option 01, adjust PEAK ING for maximum res pon se .

k. Switch t he Vertical Display mo de to 10 dB/DIV and note the b aseline. Activate N ARR OW Video Filte r and adjust the REF LEVEL so the b aseline moves to the top of the scree n.

g. On the swee p generator, change to the automatic internal sweep (Mar ker Sweep) and set the sw ee p tim e for 100 s/sweep (its slowest sweep).

Ι. Switch the Vertical Display mo de to 2 dB/DI V. Activate V I EW Α and adju st the REF LEVE L so SAVE Α display a n d

h . Activate V I EW Α and VIEW Β t hen select α s w eep time on the 492/492Ρ so the stored display is solid (no breaks in the d igitized dis pla y , see Fig . 3-37 Α).

m . Unplug Ρ2060 (Fig . 3-36) and move it from Normal to Invert m ode (o ne p in to the left). Replace Leveler Disable p lug Ρ3035 .

i . Activate MAX H OLD and SAVE Α. Trace and record

η. Start with R 1061 an d adju st the leveli ng potentiometers sequentially, from R1061 thro ugh R1013, so the contour of the b aseline is an average of the SAVE Α d isplay. In the pr ocess use Horiz adjust R 1069 (Fig . 3-36) to shift the b aseline to the right or left so the baseline aligns with t he average contour of SAVE Α display.

th e respo n se of b and 4.

j . Deactivate V IEW Α V I EW Β still active).

and MAX H OLD (SAVE Α and

the baseli ne are at cen ter scree n.

Fig . 3-3β. Adjustm e n ts and test p oi nts on th e V ideo Processo r board .

REV AUG 1981

3- 59

Calibration-492/492P Service Vol. 1 (SN Β 030000 & up) Adjustment Procedure ο. Replace Ρ2060 to the Normal mode position (one p in to the right) . The b aseline will now be 180° or the inverse of its previous position . ρ. Deactivate and then activate VI EW Α, V IEW Β , SAV E Α, and MAX H OLD. Retrace and c heck new r esponse. Response should appear flat (see F ig . 3-37 Β).

q. Switch POW ER off, and reinstall the Video Processor

I

board. Disconnect and remove the signal to the RF NPUT from the test equipment .

j

208 /

10 .024Ι;Ν2

3000

5

4 -18

2) adjust the REF LEVEL so the b aseline is near full screen the n switch to the 2 dB/DIV mode and adjust so the d isplay is mid-screen (see Fig . 3-38 Α);

NAX

$5 .4i-t ::

1 ΝΚ

Β. Typical display whe n display breaks up .

Β. Typical response after baseline lev eling. 2727-152 ~rr

Fig. 3-37 . Typical response d isplays wh e n adj usti ng baseline leveli ng.

3- 60

1) with t he front-panel controls set as d irected in p art d, activate N ARROW Video F ilter and change ΤΙΜΕ/DIV to 50 ms . Alternately turn the 19 level adjustm e nts clockwise and counterclockwise so every other potentiometer is fully clockwise and the adjacent potentiometer is fully co u ntercloc kwise . Display s h ould now appear as α periodic triangular waveform ;

Α. Series of wavefor m s. Am plitude ap proximately t5 dB a bove and below baseline reference .

Α. Typical response before baseli n e leveling.

? -14ΩΒΜ

ι. Compensation adjustment R1065 is set at the factory and usually does not require adjustment. Pull Leveler Disable plug Ρ3035 t h en replace it . If the baselin e remains straight or breaks up after t he p lug is r eplaced, co m pensation is req u ired . Adjustment procedure is as follows:

2727-153

Fig. 3-38 . Typical respon se display s w hen a djusting compensation of baseline leveli n g circ u its.

REV AUG 1981

Calibration-492/492P Service Vol . 1 (S N Β030000 & up) Ad ju stme n t Procedure 3) t urn Compensation a djustment R 1065 co untercloc kwise until the display b reaks up (see Fig. 3-38 Β); 4) now turn R 1065 clockwise 1 .5-2 turns past the point the d isplay again becomes α periodic triangular waveform ; 5) turn Horiz adjust R1069 to ce nte r t he d isplay;

9. Log Am plifier Calibration

Use only an insulated screwdriver or tuning tool, such as Tektronix Part No . 003-0675-00, to make these adjustments.

α. Test equipment setup is shown in Fig . 3-39 . Set the 6) return the b aseline levele r adju stments to th eir front-panel controls as follows: midrange position for α straight line display and proceed REF LEVEL -70 dB m with the b aseline leveling alignment as p reviously deMIN RF ΑΤΤΕΝ O dB h q). scribed (parts α t hroug 200 FRED SPAN/DIV MHz 200 MH z FREQUENCY AU TO ΤΙΜΕ/DI V 10 dB/DIV Vertical Display Ce nte red CA L (LOG and AMPL)

BN C to Sealectr o A d apter

on

10

MHz Leveled Signal

Ge n er ator, 0-10

dam

Το

J 621

Log Amp l.

Bd .

ΓJ

492 Spectrum A nalyzer

27

2 7-2s

Fig. 3-39. Equ ipment setup for cali brating log amplifier.

REV AUG 1981

3-61

Calibration-492/492P Service Vol . 1 (S N Β030000 & up) Adjustment Pr ocedure

b. Remove Ρ621 an d apply α 10 MHz signal of 0 dBm from the signal gen e rator, thr ough 10 d B and 1 dB step attenuators, to the input of the Log Am plifier at J 621 ( Fig . 3-40). Set the step attenuators for 50 dB of attenuation .

g. Alternately switch t he Vertical Display b etween 10 d B/DIV and 2 dB/DIV wh ile adjusti ng Input Ref Lvl, R 4071 (Fig . 3-40), fo r mi n i mu m amplitude change b etween t he two displa ys .

c. Position the display at α g raticule refere nce line with t he variable output of the signal generator; then switch t he REF LEVEL from -70 dBm to -120 dB m, and adjust the front p anel LOG CA L so each 10 dB step eq uals one division .

h. Switch Vert Display to 2 dB/DIV. Switch in 10 dB of atte nu ation and note how close th e 10 dB step is to five d ivisio ns of display change. If the 10 dB step is short (trace falls short of t he correct line), ad just gain with R4020 slig htly in t he same direction ; then switch o ut the 10 dB of attenuation and a djust 81071 for α full screen dis play. Repeat th is chec k until t he 10 dB step is within 0.2 dB. Switc h to 10 dB/DIV display mo de and recheck 10 dB logging.

d . Set th e REF LEVEL to -20 dBm and the attenuators for 0 dB . e. Increase the step atten uators in 10 dB steps. Adjust Log Gain, R4020 ( Fig . 3-40), so each 10 dB of change produces α division of change on the d is play. f. R eturn the step attenuato r to 0 dB . Display should be full scr een (0 d Bm) ; if not, readjust the signal generator output for 0 d Bm.

i . S witch to the 2 dB/DIV mode ; then mome nta rily remove the input signal to the Log Am plifier a n d positio n t he display on the bottom graticule line . R e-apply the signal to the Log Amplifier . j . Adjust Output Ref Lvl, R4081 (Fig . 3-40), for α full screen (eig ht divisions) display.

Fig . 3-40 . Location of co nn ecto rs and adjustments on th e L og an d V ideo Amplifier.

3-62

REV AUG 1981

Calibration-492/492P Service Vol . 1 (SN 13030000 & up) Adjustment Procedure

k. Switch to the 10 dB/DIV mode and set the step attenuators for 40 dB. Adjust Log L inearity, R 1085 (Fig . 3-40), so the display is mid-screen. Ι. If α large change in t he setting of R 1085 was required in part k of this step, repeat the adjustments of R 4071 and R4081 because of interaction. m. Check t he accuracy of 10 dB/DIV and 2 dB/DIV display modes by switching the attenuation in 10 dB steps for 10 dB/DIV mode and 1 dB steps for the 2 dB/DIV mode . N ote that the display steps one division ±0 .25 minor division for each 10 dB step, and ± 1 .0 minor division for the 2 dB mode . Once the individual steps h ave been verified, reset the signal level for full screen ; then switch in the appropriate step attenuation to step the d isplay down screen to measure the worst case error over the dynamic range . M aximum error m ust not exceed ± 1 .5 dB over t he first 80 dB of range, or ± 1 .0 dB over t he 16 dB range. η. If the 10 dB log step in the 2 dB/DIV mode is long, adjust gain with R4020 for less gain and rebalance R4071 . ο. Set the step attenuators for 10 dB of attenuation ; then adjust the signal output level for α full screen display (+10 dBm) in the 2 dB/DIV mode. ρ. Activate MIN NOISE and switch out the 10d13 of attenuation .

q. Check that the display level returns to within ± 1 .0 dB

of reference.

r.

Set the Ref level to -15 dBm and adjust the signal generator output for α full screen display in t he 2 dB/DIV mode . s. Switch t he Vertical Display to L IN and adjust Lin ΒαΙ, R 4052 (Fig . 3-40), for α full screen display. Display ampli-

tude of L IN, 2 dB/DIV, and 10 dB/DIV display should now be the same . t. Check LIN mode lineari ty b y adding 6 dB, 12 dB, and 18 dB of attenuation and noting that the display level is down from top of screen four (±0.4), six (±0.4), and seven (t 0.4) divisions . υ. Remove the signal generator signal connection to the

Log Amplifier input Jack and replace Ρ621 .

REV A UG 1981

10 . Calibrating the Resolution Bandwidth and

Shape F actor

ΝΟΤΕ

The filters are aligned separately and then combined with α signal applied through both the VR #1 and VR #2 modules. The final touch-up adjustments can be made for filter shape and bandwidth. Because of interaction, it is easy to offset one filter with misa djustment of the other, therefore, only slight adjustments should be made. Adjust the bandwidth of each filter section at the 3 dB down level. This point should be as wide or slightly ωίder than the 6 dB down point of the combined two filter sections.

For gain levels and alignment theory, refer to the VR

part in the Theory of Operation section.

α. Equipment setup is shown in Fig. 3-41 .

1) place the VR module on an extender and connect the output 10 MHz signal, from the 3rd Converter, to the input of the VR#2 section . U se α Sealectro male-to-male adapter and coaxial cable to connect between P693 and Jβ83 ; 2) connect t he output of VR#2 to the input of the Log Amplifier assembly by connecting α cable from J682 to Jβ21 (see Fig . 3-40); 3) connect the CAL O UT signal through α coaxial cable to the RF INPUT; 4) set the front-panel controls as follows : FREQUENCY FREQ SPAN/DIV RESOLUTION BANDWIDTH REF LEVEL

100 MHz 50 kHz 100 kHz -20 dBm

b. Tune the signal to center screen and c hange the Vertical Display to 2 dB/DIV . Adjust the REF LEVEL for α seven division signal . Tune the d isplay to center screen.

ΝΟΤΕ 10 kHz filteris used as the reference for centering the response of α// filters. The

3-63

Calibration-492/492P Serv ice Vol . 1 (S N Β0300Α0 & up) Adjustment P rocedur e J 693

2727-26 Β

Fig . 3-41 . Test equipme n t setup for calibrating the VR section . ε . I ncrease the FREQ SPAN/DIV to 50 kHz and the RESOLUTION BANDWIDTH to 100 kH z .

d . Adjust C2050 and C5055 (Fig . 3-42) for t he best 100 kHz filter s hape a nd wavefor m centering (100 kHz, 3 dB down, and centered with respect to th e 10 k Hz reference) . Refer to Fig . 3-43 .

Fig . 3-42 . Cali bratio n ad ju stments on the VR #2 m odule .

3-64

REV A UG 1981

Calibration-492/492P Service Vol . 1 (SN Β030000 & up) Adjustment Procedure g. If the instru ment h as Option 03 (100 Hz filter) switch RESOLUTIO N B ANDWIDTH to 100 H z and FREQ SPAN/DI V to 500 Hz .

th e

h . Adjust the 100 H z filter shape and response ampli-

tu de with C6011 and C7011 . Adjust for maximum amplitude an d α bandwidth, at th e 3 dB down point, of 100 Hz . i. Now discon n ect the 10 MHz third converter signal (Ρ693) from the VR#2 input and connect it to the input of V R#1 (J693), through t he Sealectro male-to-male adapter and coaxial cable. Connect the output of VR#1 (Ρ683) th rough another Sealectro male-to-male adapter and coaxial cable to the input of the Log Amplifier at J 621 (Fig .

j . Change the FREQ SPAN/DIV to 500 kHz and RESO-

Fig . 3-43 . R esponse of the 100 kHz filter . e. Return t h e RESOLUTION BA NDWIDT H to 10 kHz and recheck for centering. Switch t he FR EQ SPAN/DIV to 500 k Hz and the RESOLUTION BA N DWIDTH to 1 MHz. f. Adjust C2026 and C1022 (Fig . 3-42) for t he best 1 MHz filter shape and waveform centering.

it

βtδΠί

3 ΐ ι"

LUTION BANDWIDTH to 100 kHz. Readjust the REFERENCE LEVEL for α seven d ivision signal in t he 2 dB/DIV display mode .

k. Switch t h e FREQ SPA N/DIV to 10 kHz and the RESOLUTION BANDWIDTH to 10 kHz . Center the response on screen . Ι. Now, switch the FREQ SPAN/DIV to 50 kHz, the RESOLUTION BANDWIDTH to 100 kHz, and adjust the 100 kHz filter with C3023 and C3035 (Fig . 3-44) for filter s h ape and frequency centering.

L..C." 8 . ήet'. eS"

42 10 dl'i Gain No t

U Se d

R20δ0

R 2025

R 3035 0

εiε? :. υ Ε

}0 d~ sαχί r R σ023

.'00 ί,1ίλ1

.0 ί

Fig . 3-44. Calibration a dj ustments on t he VR #1 module.

REV AUG

1981

3-65

Calibration-492/492P Service Vol . 1 (SN Β030000 & up) Adjustment Procedure m. Switch back to 10 kHz RESOLUTION BANDWIDTH

and recheck centering.

η. Switch the RESOLUTION BANDWIDTH to 1 MHz a nd FRED SPAN/DIV to 500 kHz; then adjust the 1 MHz filter response and centering with C1033 and C1026 (Fig . 3-44). ο. Return the FRED SPAN/DIV to 5 kHz and RESOLUTION BANDWIDTH to 10 kHz and center the signal on screen .

ρ. Adjust the 10 kHz filter with C2037 (Fig . 3-44) for best filter s hape .

q. If the instrument has Option 03, switch the RESOLUTION BANDWIDTH to 100 Hz and the FRED SPAN/DIV to 500 Hz. Adjust the 100 Hz filter with C1030 and C1035 (Fig . 3-44) for amplitude and waveshape. r. Disconnect the cable b etween Ρ683 and the Log Amplifier input (.1621) . Reconnect Ρ683 to J 683 and connect the output from the VR#2 to the Log Amplifier input (J621) . The signal should now pass through both VR#1 and VR#2 to the input of the Log Amplifier.

s. Check the waveshape, bandwidth, and centering of all filters. Center the 100 kHz and 1 MHz filter response around the 10 kHz filter . If necessary, make only fine or minor adjustments. Figure 3-45 shows typical response shapes . t. Check filter leveling using the 100 kHz filter as the reference amplitude. Adjust all filters to the 100 kHz level as follows:

Filter 1 MHz 10 kHz 1 kHz 100 Hz (Option 03)

Adjust

Locat i on

R 1065 R 3035 R 3025 R3015

VR#2 VR#2 VR#2 VR #2

Locations of the adjustments are shown in Figs. 3-42 and 3-44 .

3-66

11 . Presetting the Variable Resolution Gain Band Leveling

a nd

ΝΟΤΕ

The Log Amplifier must be calibrated before adjusting any VR gain settings. Log Amplifier calibration can be

verified by applying α 0 dBm, 10 MHz signal to the input (J621) of the Log Amplifier and checking for full screen display with α -20 dBm REF LEVEL. The Post VR Gain, R2038 (Fig. 3-42), is normally

preset by removing the VR#2 module cover and applying α -16 dBm, 10 MHz signal to pin JJ. Adjust for

α full screen display with α REF LEVEL of -30 dBm. Replace the cover before proceeding with the other gain a djustments. Bandgain adjustments, other than band 1, must be done after tracking has been calibrated and flatness checked. if the range of any band gain adjustments is insufficient, add α diode between the output from U3023 and the base of Q2049, as shown on the schematic diagram for Variable Resolution No . 2. α. Test equipment is shown in Fig. 3-41 . Install VR#2 module on an extender board as shown in Fig. 3-42 . Set the front panel-controls as follows: REF LEVEL MIN RF ΑΤΤΕΝ FREE S PAN/DIV RESOLUTION BANDWIDTH VERT DISPLAY

-30 dBm O dB 1 MHz 100 kHz 2 dB/DIV

b. As described in the preceding note, the gain of the P ost VR Amplifier s hould be 16 dB for best signal-to-n oi se

ratio through the VR stages . If any maintenance h as been performed on this stage, perform the following steps. 1 . Remove the cover for the VR#2 module. Disconnect the jumper connector to the input of the Post VR Amplifier (pin JJ). 2. Apply α 10 MHz, -16 dBm signal from α 50 Ω signal generator source to pin JJ of the amplifier. 3. Adjust Gain R2038 for α full screen display.

4. R emove the signal from the input to the Post VR Amplifier and replace the j umper between pins JJ of the 2nd Filter Select output and the input to the Post VR Amplifier. R eplace the cover for the VR#2 module.

REV AUG 1981

Calibration-492/492P Service Vol . 1 (SN Β030000 & up) Adjustment Procedure c. Set band 1 Gain R2031 (Fig . 3-42) on VR#2 fully counterclockwise for minimum gain .

d. Disconnect Ρ693 from the VR#1 module (Fig . 3-44). Apply α 10 MHz, -35 dBm signal from the signal generator through α bnc-to-Sealectro adapter to J 693 (input to VR Input circuit) . Note the amplitude of the display . e. If the amplitude of the signal is above the top graticule line (full screen), reduce the Post VR gain by adjusting R2038 (Fig . 3-42). If the signal is below the top of the screen, adjust band 1 gain with R2031 (Fig . 3-42) for α full screen (eight division) display . Α.

R esponse

of 10 kHz filter

Β.

R esponse

of 100 kHz filter

f. Change the input signal level to -40 dBm. Turn the front-panel AMPL CAL fully clockwise and note the display amplitude. g. Decrease the input signal level 6 dB and adjust AMPL CAL so the d isplay returns to the reference n oted in part e. This provides 6 dB of r ange .

h. Change the generator output for -47 dBm signal level into the VR and change the REF LEVEL to -40 dBm. Adjust the signal generator output for α seven division display. i. Change the REF LEVEL to -30 dBm and the signal level to -37 dBm. Adjust 10 dB Gain, R3035 (Fig . 3-44), of VR#1, so the display is at the seven division reference level. J. Set the REF LEVEL to -50 dBm and the signal generator for -57 dBm. Adjust the signal generator output for α

,

Βω =

ι

>800 kHz -~

Ι. C hange the generator to -77 dBm and the REF LEVEL to -70 dBm. Adjust the signal generator output for α seven division reference level.

10 kH z F I LT ER

t~s=

m . R eturn the REF LEVEL to -30 dBm and the generator output to -37 dBm. Adjust the second 10 dB Gain, R2060 (Fig . 3-44), so the display is at the seven division reference level.

τ ιιι4τ

ο~ C. R esponse of 1 MHz filter

2727-42Α

Fig.

3-45 . Typical res pon se of 10 kHz,

bandwi dth filters. A UG 1981

i

1 MHz FI LTER

k. Change the REF LEVEL to -30 dBm and the generator to -37 dBm. Adjust 20 dB Gain, R2023 (Fig . 3-44), so the display is at the seven division reference.

REV

21F3kNC

,9 δ 111 ΉΖ

-2 ι .2 i ιοπ

seve n division display (2 dB/DIV mode).

100 kHz and

1

MHz

3- 67

Calibration-492/492P Service V ol . 1 (S N Β030000 & up) Adju stment Proce dur e η. Increase RE F LEVE L to -40 d Bm and ge nerator output to -47 dBm. Chec k for seven division dis play level. Repeat for REF LEVEL(S) of -50, -60, and -70 dBm and c hec k that seven d ivisio n reference level is maintained . Readjust ap p roximate gain adj ustments if necessary. ο. Remove the 10 MH z signal to J 680 and reconnect Ρ683. T he fi nal b and gain level adjustments are described after Calibrating the Preselector Trac k ing an d Ch ec king Flatness. The mean level for each band is set to the level of ba nd 1 . 12 . Calibrator O u tput

L evel

T he calibrator output level is cali brated to α known reference . The procedure for c heck ing the level is d escribe d in

step 3 of the Performance Chec k part . Outpu t level is adju sted with Cal Level, R 1045 (Fig . 3-46). An adjustable capacitor, C3031 within th e cover, is only adjusted if t he oscillator fails to start. It is ad j u sted for maxi mum outp ut. If the Cal L evel ad justment (131045) should run out of ra nge, change t h e value of select resistor Α34 Α1 R1018 .

13 . IF Gain Cali bration α. Set the RE SO LU TION BANDWIDT H to 100 kH z, REF LEVEL to -20 dB m, and apply -20 dB m, 110 MHz sig n al, t h ro ugh t he step attenuators, to the input (J365) of the 110 MHz filter, FL36 ( F ig . 3-46).

110 MHz Filte r Inp u t

IF Gain

R 1015

TM 503 M ai n Frame 110 M Hz IF Input

I

To 110 MHz F input

10 dB a nd 1 dB Step Atte n uato rs 2727-63 Α

Fig . 3-4β. Test equi p me nt setup fo r adjusting IF gain and t h e location of th e calibrator level ad ju stme nt.

3-68

REV FEB 1982

Calibration-492/492P Service Vol . 1 (S N Β030000 & up) Adju stme n t Procedure

b. Set the step atte n uators for 0 dB attenuation ; then

adjust the signal source output for α d isplay reference of seven (7) divisions.

20

ε. Remove the 110 MHz signal to the 110 MHz filter and

reconnect Ρ365.

d. Set the step attenuators for 21 dB ; then apply the 110 MHz signal to the input (.1321) of the 110 MH z IF amplifier (Fig . 3-46). e. Adjust the gain of the IF am plifier wit h R 1015 for α display amplitud e that equals the seven division reference set in part b. f. Remove th e 110 MHz signal and reconnect Ρ321 . g. Apply the CA L O UT signal to the RF INPU T. Set the REF LEVEL to -20 dB m. Ce nter the 100 MHz cali brator signal on sc reen then decrease th e FREQ SPAN/DIV to 100 kHz with α RE SO LUTION BANDWIDTH of 100 kH z. Keep the calibrator signal centered on screen with the FREQUENCY control .

h. Adjust IF Gain R 1015 for f ull screen (eight d ivisions) signal amplitude. En sure that the front-panel AMPL CA L still has 7 dB of range increase .

ΝΟΤΕ Two variable capacitors, C325 and C2047, do not require adjustment during calibration. Procedure requires return loss measurement which is α maintenance and repair function.

14. Digital Storage Cali bration ΝΟΤΕ

This is α two-partprocedure, the first can be used to calibrate the 492/492Ρ, the second is a program to be used with TEKTRONIX 4050-Series Compu ter terminal with the programmable 492Ρ only.

REV A UG 1981

α. Apply th e CA L O UT sign al to the RF INPU T an d set the fron t- pa nel controls as follows: FREQUEN CY FREQ SPAN/DIV REF LEVEL Vertical Display AU TO RE SO LUTION ΤΙΜΕ/DIV Digital Storage (Option 02)

200 MHz MHz -10 dBm 10 dB/DIV On AU TO VIEW Α

b. Adjust the PEAK/AVERAGE cursor so it is about one division above the bottom of the screen. ε. On t he H orizontal Digital Storage board:

1) adjust Horizontal Offset, R 3041 (Fig . 3-47), so t he left edge of the cursor is at the left edge of the crt (about 0.25 divisio n over-s pa n from the left graticule line); 2) adjust Output Gain, R 1040 ( Fig . 3-47), so the right edge of the cursor is at t h e right edge of the crt;

3) alternately switch the VIEW Α (Digital Storage) on and off while adjusting Input Gain, R 1045 (Fig . 3-47), so the storage signal at the right edge tracks with the non-store signal .

d. On the Vertical Digital Storage board : 1) output Gain R1024 and O utput Offset R 1036 (Fig . 3-47) are adjusted at the factory in the 492Ρ only (the alternate procedure follows) . These adjustme nts should not be changed ; however, if they are disturbed, center these adjustme nts and center Input Gain R1034 before proceeding ; 2) switch to 2 dB/DIV display mode ;

3) u sing α signal near the bottom of the d isplay, adju st Vertical Offset R 1030 (Fig. 3-47), so the stored display is the same amplit ude as the non-store signal ;

4) change the REF LEVEL to raise the am plitude of the signal to full screen; 5) adjust Input Gain R1034 (Fig . 3-47), so the stored display of the high amplitude signal is the same as the nonstore d isplay; 6) repeat the low level and hig h level adjustments to compensate for interactio n.

3-69

Calibration-492/492P Se r v ice Vol . 1 (SN Β030000 & up) Ad ju stme nt Proced ure ALTERNATE PROCEDURE FOR 492Ρ INSTRUMENTS α. Set the front-panel controls as follows: FREQU EN CY FREQ SPAN/DIV REF LEVEL AUTO RSO LU TION RESO LU TION BANDWIDTH Vertical Dis play V ideo Filter ΤΙΜΕ/DIV Digital Storage (Optio n 02) PEAK/AVERAGE

100 MH z 10 MHz -10 d Bm Off 1 MHz 2 dB/DIV NARR OW AUTO V I EW Α and VIEW Β Fully ccw

d. Enter and run the following prog ram : 100 DI M C(1000) 110 Κ=125 120 Ι1=0 130 FOR 1 =1 ΤΟ 10 140 FOR J =1 ΤΟ 100 150 C( ΙΙ + J)= Κ 160 NEXT J 170 Κ= Κ-25 180 1 1= 1 1+100 190 IF K>=25 THEN 210 200 Κ =225 210 NEXT Ι 220 PR I NT @1 : "SIGSWP " 230 WBYT E @33:64,C,-255

I

b. Co nn ect CA L OUT to the RF NPUT. c. Connect the 492Ρ and 4050-Series Co ntroller with α G PIB cable (bot h s hould al ready be turned on). Set the 492Ρ GPI B ADDRESS switches on the rear p anel for address 1 (switc h 1 up, all others down).

e. A dju st th e POSITIO N controls to cente r the FREQUEN CY dot and place th e baseline on the bottom graticule li n e.

Fig. 3-47. Digital Storage adj ust men t locations.

3-7 0

REV AUG 1981

Calibration-492/492P Service Vol . 1 (SN Β030000 & up) Adjustme nt Procedure f. Adju st the following ( Fig . 3-47) to matc h t he step waveform to the graticule: Ad ju stme nt

Assembly

H orizontal Digital Storage Horizontal Digital Storage Vertical Digital Storage Vertical Digital Storage

Horizontal Offset, R 3041 Output Gain, R1040 Output Offset, R1036 Outp ut Gain, R1024

Be sure that the left and r ig ht edges of the step waveform coi ncide with the left an d right edges of t he gratic ule. (T his matc hes the horizontal d isplay width of α 1000-point waveform to the graticule.) g . Pr ess FREE RUN and redu ce the span to 200 kH z/div. Keep the signal centered with the FREQUENCY control .

h. Increase REF LEVEL for α signal peak about one divi-

sion a bove the bottom of the graticule.

i. Cancel V I EW Α, wh ile pressing V IEW Β repeate d ly, and adju st Vertical Offset 81030, on the Vertical Digital Storage board to minimize the am plitude d ifference b etwee n t he stored a nd real-time wavefo rms. j. Reduce R EF LEVEL to b ri ng the signal pea k close to the top of t he graticule.

15 . Setting Β-SAVE Α Reference

Level

When Β -SAVE Α is selected, the ex pression im plemented is (Β-SAVE Α)-k wh ere k is α consta nt set by the input data for an 8-to-4 line encoder, U1015 . Eac h bit will move the reference level about 0.2 mi nor division . Normally, the refe rence level is set at the center graticule line ; h owever, it can be set anywh e re within the graticule area by the setting of an 8-bit b in ary switch, S1014 (Fig . 3-48). The M SB (switch #8) s hifts the d is play about five d ivisions, switch #7 h alf this amount, etc. The following procedure sets the reference level. α. Estimate the amount and direction th e reference level is to be shifted.

b. Switch t he POWER on and close or open the switches on S1014 (Fig . 3-48) to obtain the desire d Β -SAVE Α referen ce level.

16 .

B a nd Leveling for Coaxial Bands (Bands 1-5) ΝΟΤΕ

The mean value of the flatness response for each band is set to α -20 dBm reference at 100 MHz. α. Perform b an d 1 gain ad ju stment as d escribed un de r Baseline Leveling (step 8) .

k. Again, wh ile pressing V I EW Β re peatedly, adjust Input Gain 81034 on the Vertical Digital Storge boa r d to mi nimize the amplitud e difference betwee n t he stored a nd real-time waveforms. Ι. B ecause the offset and gain adju st ments interact, repeat parts h t hro ugh k as n ecessary . m. Ca ncel the N ARR OW V ideo Filte r.

I

η. ncrease FREQ SPAN/DIV to 10 M Hz and tu n e the signal to wit hin one division o f t he right edge of the g ratic ule . ο. Wh ile pressing V I EW Β repeatedly, adjust In put Gain 81045 on the H orizontal Digital Storage b oard , so the h orizontal position of the stored signal matches that of the nonstored signal .

REV

AUG

1981

Fig . 3-48 . Location of b inary switch (S1014) fo r setting Β -SAVE Α refe re n ce level.

3- 7 1

Calibration-492/492P Service Vol . 1 (S N Β030000 & up) Adju stme nt Pr ocedure

b. Perfo rm flat ness check of bands 1 t h ro ugh 5 as desc ri bed under F requency Response Check of the Perfo rma nce Chec k and n ote t h e frequency at the mean level for each b and . c. Set t h e fro n t- panel con trols as follows:

17 . B a n d Leveling for Waveg u ide β -11)

Band s (B and s

α. Test eq u ipme nt setup is show n in Fig . 3-50 . Apply 2072 MHz at -58 d B m , thro u g h α dc-blocking ca pacitor to the ΕΧΤ M I XE R nput. Monitor t he inp u t wit h α power meter to set the inpu t level. Set the fron t-panel cont rols as follows:

i

Vertical 2 Displa y d B/DIV 18-26 FREQ U EN CY RANG E GHz (band 6) RE F L EVEL -20 dBm 200 FREQ S PAN/DIV MHz FR 10 E Q SPAN/DIV MH z On AU TO RE SO LUTIO N

RESO LU TION BANDWIDTH 1 MH z ΤΙΜΕ/DIV AU TO Digital Storage (O ption 02) V I EW Α/ V ΦEW Β

d. Switch th e frequency range to ba nd 2 (1 .7-5 .5 GHz) and apply α calibrated -20 dBm sig n al whose freque ncy is the same as that n oted fo r th e mean level in p art b.

ΝΟΤΕ If α power m eter is used to mon itor signal le vel, connect the power meter sen sor at th e RF INPU T.

e. Tu n e th e signal to cente r screen and reduce t h e FREQ SPAN/DIV to either 1 MHz or 500 k H z. f. Adjust band 2 Gain R 3034 (Fig . 3-49), fo r α full screen (-20 dB m) display.

RE F LEVEL

-30 dBm

ΝΟΤΕ Th e baseline of the display will rise when 2072 MHz signal is applied to the EXT MIXER Input port conn ector.

b. W it h -58 d B m i n put level applied, adjust ba nd 6 Gai n Leveli n g R3032 (Fig . 3-49), for full screen dis play. c. Chan ge the F REQUE N CY RANG E an d inp ut signal level as listed in Ta ble 3-12 . Adj u st the appro priate B and Gain adj ust men ts (Fig . 3-49) for full scree n d is pla y . Input levels and gain adj ustment for th e waveg uide b a nd s n eed to be adj usted only if t h ese ba n ds will be u sed.

d. Tu rn power off; r eplace

V R mod ule .

g. Increase the FREQ SPAN/DIV to about 200 MH z an d change the FR EQUENCY RANGE to band 3 (3 .0-7 .1 GHz) . Apply α calibrated -20 dB m signal at the frequency n oted for the mea n level in part b.

h. Tu ne the signal to center screen an d again decrease the span to about 500 kH z/Div with α RE SO LUTION B ANDWIDTH of 1 MHz. i. Adjust band 3 Gain 83030 (Fig . 3-49), for α fu ll screen

d is play.

J. Repeat the above p rocedure for each coaxial b and (1-5) and set th e gai n of each with t he appro p riate adjustme nt (see F ig . 3-49). If th e ran ge of any ad justment is in sufficien t, add or remove the appropriate diode (see schematics a nd Fig . 3-49) to obtain the required ra n ge . Adding the d iode increases gain.

3-72

Fig . 3-49 . Band leveli ng a djustments and gain diodes (when installe d) on VR #2 modu le .

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1981

Calibration-492/492P Service V ol. 1 (SN Β030000 & up) Adjustment Proce dure Table 3-12 ΕΧΤ M IXER BAND LEVELING ADJU ST MENTS

B and 6 (18-26 7 (26-40

GH z) GH z)

8 (40-60 GHz) 9 (60-90 GHz) 10 (90-140 GHz) 11 (140-220 GHz)

18 .

Input Level

Gain Adjustme nt

dB m dB m -60 d Bm -60 dB m -60 dB m -60 d Bm

R3024 R3026

-60 -60

d. Apply the CA L OUT signal to the RF INPU T. Set the REF LEVEL to -30 d Bm, FREQ SPAN/DIV to 20 MHz an d activate AUTO RE SO LU TION. Select the 1 .7-5 .5 GHz FREQUENCY RANGE a nd adjust the FREQUENCY to cente r t he 2.1 GHz marker. Center In put Offset adjustment R1031 (Fig . 3-52), press DEGA USS button, and th e n center the 2.1 GHz marker on screen with the FREQUENCY cont rol .

R3032 R3029 R3028 R3028

P reselector D river (O ption 01) Calibratio n

α. Turn P OWER off, pull Preselector Driver and install on extender boa rd (Fig . 3-51), then switch POWER on . b. Set the offset for dr iver U2054 as follows: (Offset hould s only requ ire adj usti ng if U 2054 is changed .) 1) set the FREQUEN CY (0-1 .8 GHz) ;

R ANGE

to

band

ε. Conn ect digital multimeter betwee n center tap of PEAKING pote ntiometer an d gro und. Adjust the co ntrol fo r 0 V ind icatio n. If index on th e knob is n ot aligned with th e ma rk on the front pa nel, loosen knob a nd position t he ma rk so it is alig ned .

1

2) pull Ρ3055 and co nnect α voltmeter betwee n ΤΡ4054 a nd analog ground ( Fig . 3-52). Set the voltmeter r a n ge to 30 μV or less ;

e. Groun d ΤΡ 1069 (Fig . 3-52), with α j umper st rap an d adjust the Preselector Offset (131064) fo r maximum response of the 2.1 GHz signal . Remove the grounding strap a nd press DEGAUSS button. f. Pea k t he 2.1 GHz signal with t he -829 MH z I F Offset, R1049 (Fig . 3-52).

I

g. Remove the Cali brator signal to t he RF NPUT and connect the output of the microwave comb generator to the RF NPUT (see Fig . 3-51) . C h an ge the REF LEVEL to 4) disco nnect mete r and re place Ρ3055 ; 0 dBm. Now tu ne the CENoTER FREQUEN CY to 5 .5 GHz and r rd center the 5.5 GHz c mb marker on sc ree n. Press 5) turn POWER off, reinstall Preselector Drive boa DEGAUSS, then rece nter the 5.5 GHz signal . switch POWER on . and 3) adjust Drive r Offset R2066 (Fig . 3-52) for 0 V;

I

492 Spectru m Analyzer

2072 MHz Signal Ge nerator -50 dam to -80 dam P ower Meter

2727-18 Α

Fig .

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1981

3-50. Test equipme nt setup fo r calibratin g

ba nd

leveli ng of th e external

m ixer ba nds.

3- 7 3

Calibration-492/492P Service V ol. 1 (SN Β030000 & up) Adjustment Proced ur e

Preselecβ or Driver Boar d on E xte nd ers

2727 -6α

Fig. 3-51 . Test equ i p me n t set up fo r calib r ati n g Preselectoι Driver.

Fig. 3-52 . Preselector Dri v e r adjustme nts a nd test poi n ts .

3- 74

REV AU G 1981

Calibration-492/492P Service Vol. 1 (SN Β030000 & UP) Adjustment P rocedure

h. Peak t he 5.5 GHz signal with t he Preselector Sense, R 1065 adjustment . ί. Repeat p arts f through h to ensure that the 2.1 and 5.5 GHz frequency points track t he input tuning. ). Change the FREQUENCY RANGE to band 4 (5 .4-18 .0 GHz) . Center t he 6 GHz marker on screen with the FREQUENCY control, then press the DEGAUSS button . Peak the 6 GHz signal with the front-panel P EAKING control.

k. Adjust FREQUENCY to center the 9 GHz marker on screen . Peak this response with the Χ3 Gain, R1052 adjustment.

Ι. Repeat

range.

parts

j

a nd k to ensure tracking over this

m. Increase FREQUENCY to the 12 GHz marker, press DEGAUSS, then peak the 12 GHz point with S haper #1, R 1054 adjustment (Fig . 3-52). π. Adjust FREQUENCY to center the 17 GHz marker, press DEGAUSS, then peak the signal with S haper #2, R 1056 adjustment . ο. Recheck the 6, 9, 12, and 17 GHz points to verify that they all peak at the same position of the front-panel PEAKING control. If they do n ot, repeat parts g through η. ρ. C hange the FREQUENCY RANGE to the 1 .7-5 .5 GHz band. Center α comb marker between 5.4 and 5.5 GHz, press DEGAUSS, then peak the signal with the front-panel P EAKING control.

t. Adjust -829 MHz IF Offset R1049 (Fig . 3-52) to peak

the 3.5 GHz response .

υ. C hange FREQUENCY RANGE to 3.0-7 .1 GHz and center 5.0 GHz marker signal on screen with the FREQUENCY control after the DEGAUSS button has been pressed. ν. Peak the 5.0 GHz signal with the +829 MHz IF Offset R1045 adjustment . ω. C hange FREQUENCY R ANGE to 15-21 GHz and adjust FREQUENCY to center the 15 GHz marker on screen . Press the DEGAUSS button as signal is tuned to center screen . χ. Peak the PEAKING control.

15 GHz signal with

the front-panel

γ. Tune the 19 GHz marker to center screen and press DEGAUSS. τ. Peak the 19 GHz signal with Shaper #3, R1061, adjustment (Fig . 3-48). αα . Tune to the 21 GHz marker, d egauss, then peak the signal with Shaper #4, R 1063, adjustment . ab. R echeck the 15, 19, and 21 GHz points to verify that they all peak at the same position of the PEAKI NG control. ac . Change the FREQUENCY R ANGE to 5.4-18 GHz, then center the 15 GHz marker on screen . Degauss as the signal is centered .

q. Change FREQUENCY R ANGE to the 5.4-18.0 GHz band and center the same signal u sed in part ρ with the

ad . Peak the signal with the PEAKING control, then switch FREQUENCY R ANGE to 15-21 GHz and center the same 15 GHz marker on screen . Press the DEGAUSS button .

r. Repeat parts ρ through q until the signal amplitude peaks, on both bands, occur at the same position of the PEAKING control.

ae. Peak t he 15 GHz signal with Preselector Offset, R 1064, if n ecessary .

FREQUENCY control . Press DEGAUSS, then adjust Input Offset R 1031, to peak t he signal .

s. Set PEAKING control so the index mark aligns with the front-panel mark . Change FREQUENCY R ANGE to 1 .7-5.5 GHz, adjust FREQUENCY to center the 3.5 GHz comb marker, then press DEGAUSS. REV AUG 1981

af. Change FREQUENCY RANGE to 3.0-7 .1 GHz and center α 5.0 GHz signal on screen. Press DEGAUSS as the signal is centered .

3- 75

Calibration-492/492P Service Vol . 1 (S N Β030000 & up) Adjustment Procedure ag . P ea k the signal with adjustment.

the

+829 MH z IF, R1045

ah. Change to the 1 .7-5 .5 GHz band a nd center α 3.5 GHz marker on screen after d egaussi ng. ai . Pea k the 3.5 GHz signal with the -829 MH z IF, R1049, adjustment. aj . All bands should now t rack. The signal peak with t he front- panel PEAKI NG control should occur with the kn ob index ma rker near the front-panel mark.

bly on extender boards and into the instrume nt. U se extender ca bles and adapters to reconn ect signal ca bles to their respective connector (cable with yellow band to J501, cable with black band to J 502, and ca ble between J 500 and J 511 on Ph aselock Control board). b. Switch the 492/492Ρ POWER on, set the ΤΙΜΕ/DIV to MNL, FRED SPAN/DI V to 50 kHz, and Phaselock on . ε. Check Offset M ixe r-Th is part of the procedure is only required after repai r or replaceme nt of the M ixer boa rd . 1 . Co nnect the Direct Input of α freq uency coun te r to

p in Ν (Fig . 3-54 Α) a nd adjust the counter controls for α count . N ote the frequency .

19 . Ph aselock Calib ratio n

The phaselock assembly normally re quires cali bration only after some p art of the assembly h as been repaired or replaced. Ph ase noise, produced by the phaselock loop, is specified for -70 dBc or better 3 kH z out from the response . This should be chec ked before calibrating the assembly . α. Test equ ipment setup is s how n in Fig . 3-53. Remove

the Ph aseloc k module and the two cover plates so all ci rcuit test points and adjustme nts are accessible . Plug the assem-

2. Connect the counter to pin Κ and note the frequency . 3. Connect the counte r to the collecto r of 01040 an d note the frequency. Frequency should equal th e difference between pins Ν a nd R (e.g ., 25 .080 -25 .00 = 80 kHz) . Disconnect the counter probe from t he collector of 01040.

Fr C L Probe

Probe

2727-66

F ig .

3- 76

3-53 . Test equ i pm en t setup for cali brati n g

Ph aseloc k

asse mb ly.

REV

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1981

Calibration-492/492P Service Vol . 1 (SN B030000 & up) Adjustment Procedure

A

n Clint Wer and tDoMroWl

ESbMeMnandWMAMMMM. Fig . 3-54 . Adjustments and test point locations in the Phaselock module .

REV AUG 1981

177

Calibration-492/492P Service Vol. 1 (SN 8030000 & up) Adjustment Proce dure 4. Connect the probe of α test oscilloscope to the collecto r of 01040 and check for α 50% duty cycle.

d. Check Controlled Oscillator freque ncy-T his part of the check is only requ ired afte r repai r o r replacement of the Controlled Oscillator board. 1 . Connect the Di rect Input of th e frequency counter to ΤΡ2011 (Fig. 3-54Α). G roun d p in L on the Offset Mixer board. 2. Conn ect an 80 k resistor in series with α 2 k variable potenti ometer f rom pin Η to ground ; then adjust the variable resistor for α voltage reading of 12.0 ±0 .1 V at pin Η. 3. Adjust C1013 (Fig. 3-54Α) for α frequency of 25 .10 MHz. 4. Now replace the 80 k resistor with α 4 k resistor

a nd adjust the variable resistor for α reading of 5 .75 ±0 .1 V at pin H.

5. Adjust C2011 (Fig . 3-54Α) for α frequency of 25 .032 MHz. 6. Repeat sub-parts 3 throug h 5 until the oscillator range is 25 .100 to 25 .032 MHz. e. Error Amplifier Adjustme nt-This part of the procedu re sets loop gain and error co unt break point. This p art is requ ired when either the Ph asekκk assembly, 1st LO, Ph ase Detector, or Error Amplifier is replaced. 1 . Set the ΤΙΜΕ/DIV to 1 s, FREQUEN CY R ANGE to

band 2 (1 .7-5 .5 GHz), PH AS ELOC K on, FRE QUENCY SPAN/DIV to 50 kHz, and AU TO RE SO LUTIO N on .

2. Pull Ρ3057 (Fig . 3-54 Β); this tu rns the st robe to the Ph ase Gate on . Tu rn Loop Gain R3082 fully counterclockwise . Pull a nd install Ρ2035 between pins 2 and 3. 3. Conn ect the test oscilloscope probe to ΤΡ3081 (Fig . 3-50Β) and trigger t he test oscilloscope on t he signal at ΤΡ 2037 ( U 2048-6) shown in Fig. 3-54 Β. Set the Time/Div to 5 ms a nd Volts/Div to 0.5 V. Note the beat notes. Beat n otes are produced by the d iffe rence between strobes from the ph aselock (one every 5 MHz) and the particula r frequency the 1 st LO is tuned to .

3- 78

4. Turn Loop Gain R3082 clockwise slowly and note the ampli tude of the b eat notes prior to lock. This usually occurs between 0.5 V and 1 .5 V peak to peak. The b eat notes will disappear when lock occurs . 5. Tu rn Loo p Gain R3082 fully clockwise, increase FREQ SPAN/DIV to MAX, set RESOLU TION BANDWIDTH to 100 H z, and ΤΙΜΕ/DIV to AUTO . 6. As the sweep scans ac ross the span note the positi on of the smallest beat note. Tune the cen ter FREQUENCY to position th e frequency dot at this location. 7. Redu ce the FREQ S PAN/DIV to 100 MHz. Set ΤΙΜΕ/DIV to 1 s and activate VIEW A if the instrument h as Digital Storage. 8. Adjust Loop Gain until the beat note amplitude is 1 .5 times the amplit ude noted in part 4 of this step. If this d oes n ot occur, it is an ind ication t he Phase Gate is defective. 9. Ch ange the ΤΙΜΕ/DIV to MNL, deactivate VI EW AN I EW Β, reduce the FREQUENCY SPAN/DIV to 50 kHz, t he n increase to 100 kHz an d center the crt beam on scree n with t h e M ANU AL SCA N control . Now adjust FREQUEN CY for α null (zero frequency) of the d isplay on t he test oscilloscope. 10 . Adjust MANUAL SCAN to position the crt beam four divisions from t he ce nter screen reference (four divisions represents 400 kHz) . 11 . M onitor a nd trigger the test oscilloscope on ΤΡ1031 at the top of R1038 (Fig. 3-54Β) and adjust the Error Co unt Breakpoint potentiometer R1061, from its mid- range position, clockwise until the display ju st starts to break up . 12 . Move the crt b eam four divisions to the other side of cente r with the M ANU AL SCAN control and note that the squ are wave respo nse again starts to brea k up 400 kH z from cente r. As the beam crosses center, the dis play on the test oscilloscope should go through α null . If α null is not found, readjust cen te r frequen cy. Adjust R 1061, if n ecessary, so break points are 400 kHz either side of the null at ce nter screen. 13. Reconnect Ρ2035 between pins 1 and 2 and install Ρ3057 . Disconnect the test oscilloscope trigger and

@ AUG 1981

Calibration-492/492P Service Vol. 1 (SN Β030000 & up) Adjustment Proce dur e probe connections. Insure that Ρ2035 and Ρ3057 are installed correctly; thei r a bsence will produce spurious responses on t he display . 14 . Reduce FREQ SPAN/DI V to 50 kH z an d ensu re ph aselock occur s.

16 . P erfo rm the ph aselock noise check as d escribed in th e Perfo rmance Check part. This co ncl ud es the Ad ju stmen t Procedure . Repeat the appropriate Perfo rmance Check to ve rify specificatio n.

15 . Replace the covers on the assembly and rei nstall

t he module in the 492/492P .

@ AUG 1981

3- 79

Section 4-492/492Ρ Service Vol. 1

M AINTEN AN C E Introduction

This section describes the procedure for red uci ng or pre-

ve nting instrume nt malfunctio n, pl us trou bleshooti ng, and corrective maintenance. Preventive maintena nce improves instrument reliability . S hould the instrument fail to function properly, corrective measures should be ta ken immediately ; otherwise, additional pro blems may develop within the instrument.

6)

p ick up components b y the body, never by the leads;

7) do not slide th e components over any surface;

8) avoid handling components in a reas that h ave α floor or wor k-surface covering capable of generating α static c h a rge ; 9) use α soldering iron t hat is co nnected to eart h grou nd;

10) use only special anti-static suction type or wick type

desolde ring tools. Static-Sensitive Components

Static discharge can damage any semiconductor component in this instrument.

This instru ment co ntains electrical components that are

susceptible to damage from static d isc h a rge . See Table 4-1

for relative suscepti bility of various classes of semiconductors . Static voltages of 1 kV to 30 kV are common in unprotecte d environme nts .

O bserve the followi ng precautions to avoid damage:

Ta ble 4-1 RE LATI VE SUSCEP TI BILITY TO STATIC DISC HARGE DA MAG E

Semico nductor Classes

Relative u S scepti bility L evels°

M OS or C MOS microcircuits

or discretes, or linear microcircuits with MOS inp uts. (Most Se n sitive)

ECL Sc hott k y sig n al

1 2

diodes

3

1) mi nimize handling of static-sensitive components ;

Sc hottky TT L

4

2) transport and store static-sensitive components or assemblies in thei r origi nal containers, on α metal rail, or on conductive foam . Label any p ackage th at contai ns staticsensitive assemblies or components ;

H igh-frequency bipolar transistors

5

JFETs

6

Linear microci rcuits

7

Low-power Schottky TTL

8

TT L

9

3) d ischarge the static voltage from your bo dy by wearing α g rounded wrist st rap while h and li ng these compon e n ts . Servici ng static-sensitive assemblies or components should be performed only at α static-f ree work station by q ualified service personnel ; 4) not hing capable of ge nerating or h ol ding α static charge s hou ld be allowed on the work statio n surface;

5) keep the component leads shorted together whenever possible ;

REV AU G 1981

°Voltage equivalent fo r 1 = 100 to 500 V 4 = 2 = 200 to 500 V 5 = 6= 3 = 250 V

(Least Sensitive) levels :

500 V 7 = 400 to 1000 V (ext) 400 to 600 V 8 = 900 V 600 to 800 V 9 = 1200 V

(Voltage discharged from α 100 pF capacito r thro ugh α resista nce of 100 Ω.)

Maintenance-492/492P Service Vol . 1 (SN Β030000 ά up)

PREVENTIVE MAINTENANCE P reventive mainte nance co nsists of clea ning, visual inspection, perfo rma nce check, and if needed, α recalibration . The preventive maintenance sc hedule that is established for t he instrument should be based on the envi ronment in wh ich t he instrument is operated and the amount of use. Under average conditons (laboratory situation) α preventive maintenance check should be p erformed every 1000 hours of instrument operation.

E lapse d Time Meter

Α 5000 hour elapsed time indicator, graduated in 500 hour increments is installed on the Ζ-Axis/RF I nterface ci rcuit board . This provides α conve n ient way to ch eck ope rating time . The meter on new in strume nts may indicate from 200 to 300 hours elapsed time. M ost instruments go through α factory burn-in time to improve reliability. This is similar to usi ng aged components to im prove reliability and operating stab ility.

Do not allow water to get inside any enclosed assembly orcomponents such as the hybrid assemblies, RF Attenuator assembly, potentiometers, etc. Instructions for removing these assemblies are provided in the Corrective Maintenance section. Do not clean any plastic materials with organic cleaning solvents such as benzene, toluene, xylene, acetone or similar compounds because they may damage the plastic. Lubrication Components in this instrument do not re qu ire lubrication. Service

F ixtures

and Tools for Mai nte nance

The following k its and fixtures are availa ble to aid in servicing the 492/492Ρ:

Nomenclat ure Clea ning

Clean t he instrume nt ofte n en ough to prevent du st or dirt from accumulating in or on it . Dirt acts as α thermal insulating blanket and prevents efficient heat d issi pation. It also provides high resistance electrical leakage pat hs between co nd uctors or components in α hu mid environment.

E xterior. Clea n the d ust from the outside of the instrument by wiping or b rushing the surface with α soft cloth or small brush. The brush will remove dust from around the front-panel selector buttons. Hardened dirt may be removed with α clot h dampened in water that contains α mild detergent . Abrasive cleaners should not be used . Interior. Clean t he interior by loosening accumulated dust with α dry soft brush, then remove the loosened dirt with low pressure air to blow the dust clea r. (Hig h velocity air can damage some components .) Hardened dirt or g rease may be removed with α cotton ti pped applicato r dampened with α solution of mild detergen t in water. Do n ot leave detergent on critical memory components. Abrasive clea ners should not be used . If the ci rcuit b oa rd assemblies need clea ning, remove the ci rcuit b oa rd by referring to the instructions un der Corrective M ainten an ce in this section. After cleaning, allow t he interior to thoroughly dry before

applyi ng power to the instrume nt.

4- 2

Service Kit ; consisting of : 1 Front panel extender 1 Power module extender 1 Accessories Interface extender 1 Ribbon ca ble 3 Coaxial cables, Sealectro male-to-Sealectro female 1 VR modu le ha ndle 1 Circ uit board extender assembly k it : consisting of: 1 Left exte nder boa rd 2 R ig ht extender boards 1 F rame (extrusion for ci rcuit board extender) 6 Screws, panhead with flat an d lockwashers

Te ktronix Part No . 006-3286-00 067-0973-00 067-0971-00 067-0972-00 175-2901-00 175-2902-00 367-0285-00 672-0865-00 670-5562-00 670-5563-00 426-1527-00 211-0116-00

In addition to the above, the following tools are recommended: Screwdriver, flat, with 1/4 to 3/8-inc h bit . Screw driver, Posidrive® 440-2. Wrench, 5/16-i nch open end (used to remove or replace semi-rigid coaxial ca ble conn ectors) . H ex drive wren ches, 3/32, 5/64, 7/64-inch (used to remove hex screws that h old mo dule assemblies and t heir covers in place) .

REV A UG 1981

Maintenance-492/492P Service Vol. 1 (S N Β030000 & up)

Visual Ins p ection

Afte r cleaning, ca refully c hec k th e i n st ru ment for suc h defects as defective con nections, damaged parts, and improperly seated transistor s and integrated circu its. Th e remedy for most visi b le defects is o bvious. If h eat-damaged parts are discovered, try to d ete r mine t h e cause of ove rh eati ng befo re t he damaged part is replace d ; oth erwise, th e damage may b e repeated.

Tr a nsistor a n d I n teg rated Circ u it Ch ec ks Periodic ch ecks of t he tran sistors a n d integ r ated ci rcuits are not recommended . T h e best measure of perfo rmance is the actual operation of t he component in th e ci rc u it . Performa n ce of these components is th oroughly checked du ring t he performance c heck or recali bratio n ; an y sub-stan da rd

transistors or i n teg rate d circuits will usually be detected at th at time.

i

Wh en h a ndling M OS F ET's, keep th e shorting st rap n place until the transistor is i n its socket.

P erfo rma nce Chec k s a nd

Recalib ratio n

Th e i n str ume nt perfo rma nce s ho uld be ch ec ked after eac h 1000 ho u rs of ope ration or every six month s if th e instrument is used i ntermitte ntly to en sure maximum performance a nd assist in locating d efects t hat may not be apparent duri n g regula r operatio n . Instruction s for con ducti n g α perfo r mance c h eck a re provide d i n t h e P erfor mance Ch eck p art of t he Calibr atio n sectio n .

T RO UBLES HOOTI NG The followin g are α few aid s a n d su ggestio ns t h at may assist i n locati n g α problem. Afte r the d efective assem b ly or component h as been locate d , refer to t he Corrective M ain te n a nce part of th is section for removal and re placemen t i n structio n s.

W ir i ng Colo r Cod e. Color coded wires are u sed to aid circuit traci ng. P ower su pply do voltage lead s h ave eit her α red b ack g rou nd for p ositive voltage or α violet bac kgro u nd for n egative voltage. Signal wires a nd coaxial ca b les use an iden tifyi n g on e-ban d or two-band color code .

Troub les h ooting Aids

Mu lti p le Ter mi n al ( Harm onica) Co nn ecto rs. Some i n te rci rc u it co n nections are made th rough p i n connectors th at may be mo u nted i n α h a r monica type holder . T he te r min als in t he holder are identified b y nu mbe rs t h at appear on th e h ol d e r an d t he circ uit d iag rams. Connecto r orientation to th e circuit board is keyed by tria ngles on t he h olde r a nd the circuit boar d (see F ig . 4-1) . In some cases, th e triangle or a rrow is scree n ed on t he c hassis adj acen t to th e connector . Some co nnecto rs co n tai n mo re th an o ne section . Conn ectors are ide n tified on t he sch ematic a nd board with α "Ρ" or

Diagrams. B loc k a nd circu it d iagrams, on foldout p ages in the Diag rams section , co n tain any sig n ificant waveform, voltage, and logic d ata i n formatio n . Any necessary i n fo rmation as to how t he data was acquired, s u ch as o p e r ational state of t h e instrumen t, is provide d on th e diag ram or adjacent to it. Refer to the Rep lacea b le Electr ical P arts list section for α descriptio n of all assem b lies and compo nents .

"J" .

ΝΟΤΕ Corrections and modifications to the ma n ual and instrumen t are described on inserts bound in to the rear of the manual. Check this section for changes a nd corrections to the manual or the instrument. Ci rcu it Boa rd Illu str atio n s. E lectrical compone nts, co n necto rs, and test p oi n ts are identified on circuit board illustrations located on t h e inside fold of t he correspo nd ing ci rcuit diag ram or th e b ack of the precedi n g d iagram . Α gri d on t he ci r cuit board illust ratio n s and the ci rcuit schematic p l us α look-up ta b le, provides t he means to quic kly locate compone nts on eit he r d iag r am .

REV A UG 1981

Resisto r Values. Many types of resistor s (suc h as composition, metal film, tapped, thic k film resistor network p ackage, plate, etc.) are used in th e 492/492Ρ. Th e val u e is either colo r cod e d in accordance wit h the ΕΙΑ color code, or pri n ted on t he body of th e componen t. Ca pacitor M ark ing. T he capacita nce val ue of ceramic

d isc plate an d slug ca p acitors or small elect rolytics are ma rked in microfarad s on t he side of t he component body . T he ce ramic tub u lar cap acito rs an d feedthrough ca pacitor s a re color coded i n picofarads . Tantal u m capacito rs are color coded as s how n in F ig . 4-2.

4-3

Maintenance-492/492P Service Vol. 1 (SN Β030000 & up)

1st Figure 2nd Fig ure Mu ltiplier

DI PPED TANTA LUM CA PACITOR MARK ING Α A ND Β CASE CA PACITANCE AND VOLTAGE CO LOR CODE

Fig. 4-1. Multipin (harmo nica) connector config uration. Diode Color Code. T he cathode of each glass encased

diode is in dicated by α stripe, α series of stripes, or α dot . Some diodes have α d iode symbol printed on one side . F igure 4-3 illust rates d iode types and polarity markings that are u sed in this instrument.

Tra nsistor a nd Integrated Ci rcuit E lect rode Configuration. Lead identification for the transistor s and M OS FET's is shown in Fig . 4-4. IC pi n outs are show n either by ta ble or box on the schematic diagram . Semiconductor failures acco unt for the majority of electronic equi pment fail ures. M ost semiconductors are soldered to the boa rds . The following guidelines should be observed when substituti ng these components .

ΝΟΤΕ

Rated

Voltage

V DC 250C

3-4 3δ 3-10 3-15 3-20 3-25 335 3-50 3

Color

CODE FOR CAPACITANCE IN P ICOFARADS 1st Figure

Black Brown R ed Orange

Yellow G reen Blue Violet G ray White

0 1 2 3 4 5 6 7 8 9

2nd Figure Mu ltiplier

None

0 1 2 3 4 5 6 7 8 9

Χ10

Χ102 Χ10 3 Χ104 Χ101 Χ106 Χ10"

(1733) 1735-9

Fig. 4-2. Colo r co de fo r some tantalum capacitors.

Before using any test equipment to make measure-

ments on static-sensitive components or assemblies, be certain that any voltage or current supplied by the test equipment does not exceed the limits of the components to be tested. α. Try to isolate the p ro blem to α component throug h sign al analysis . Dete rmine that circuit voltages will not damage the replacement .

b. Tu rn the power off before removi ng α compone nt.

4-4

ε. U se α de-soldering tool and 25 watt or less soldering iron to remove the components .

d. U se only good components for su bstitution and be sure, the new component is inserted into the socket properly before soldering. Refer to the manufacturer's d ata s h eet o r Fig . 4-3 for lead co nfigu ration. e. Turn power on and chec k performance.

REV AUG 1981

Maintenance-492/492P Service Vol . 1 (SN Β030000 & up)

resistance ratios can usually be taken by referring to the schematic and pulling appropriate transistors and pin connectors to remove low resistance loops around the d iode .

Do not use an ohmmeter scale with α high external curren t to check the diodejunction. Do not check the forward-to-back resistance ratios of mixer diodes. See Replacing the Dual Diode Assembly instructions under Replacing Assemblies .

Troubleshooting and C hecking the Power Supply W ARNING The 4921492Ρ uses α high efficiency power s upply. The potential of the primaηground for this supply is different than chassis or earth ground. An isolation transformer, with α turns ratio of 1:1 and α 500 VA minimum rating, should be used between the power source and the 4921492Ρ power input receptacle. The transformer must have α three-wire input and output connector with ground through the input and ou tput. Stancor No. 6298 is α suitable tra n sformer. Α jumper should also be connected between the primaryground side to chassis ground (emitter of 02061 and the ground terminal of the input filter FL301).

F ig . 4-3. Diode polarity markings. ΝΟΤΕ If α substitute is not available, check the transistor or MOS FET with α dynamic tester such as the TEK TRONIX Type 576 Curve Tracer. Static type testers, such as an ohmmeter, can be used to check the resistance ratio across some semiconductorjunctions if no othermethod is available. (Do not measure resistance across MOS FE T's because they are very susceptible to static charges.) Use the high resistance ranges (R Χ 1k or higher) so the external test current is limited to less than 6 mA . If uncertain, measure the external test current with an ammeter. Resistance rahos across base-to-emitter or base-to-collector junctions usually run 100.1 or higher. The ratio is measured by connecting the meter leads across the terminals, noting the reading, then reversing the leads and noting the second reading. Diode Checks. M ost d iodes can be checked in the circuit by taking measurements across the d iode and comparing these with voltages listed on the diagram . F orward-to-back

REV FEB 1982

If the power supply is separated from the instrument and operated on the bench, hazardous potentials will exist within the supply for several seconds after power is disconnected. This is due to the slow discharge of capacitors C6101 and C6111. Α relaxation oscillator lights DS5112 (next to C6111) when the potential exceeds 80 volts. General Troubleshooting Techniques The following procedure is recommended to isolate α

problem and expedite repairs.

1 . Ensure that the malfunction exists in the instrument . Check the operation of associated equipment and the operating procedure of the 492/492Ρ (see Operating Instructions). 2 . Determine and evaluate all trouble symptoms . Try to isolate the problem to α circuit or assembly . For example: Absence of the frequency marker dot could indicate α malfunction in the video summing stage, the marker generator, or the switching circuitry. Α test oscilloscope will check the

4-5

Maintenance-492/492P Service Vol . 1 (SN Β030000 & up)

Β

D

P lastic-Cased

Transistors

Metal-Cased T r ansistors

FE T's

Voltage Regulator

I

nput

Gnd

Outpu t

Ta b Key Integrated Circ uits

F ig . i

4-4.

E lect rode co nfigur atio n for se miconductor components .

nput to the video summing stage and isolate t he

problem to

o ne or the ot her of the two circuits . The block diagrams i n t he Diag rams section can aid in signal tracing an d ci rcuit isolatio n. It also s hows th e required signal level at d ifferen t points to produce full screen deflection. B lock diagrams are provided in t h ree levels . The first level shows all major ci rcuit systems for t he 492/492Ρ, t he second level shows d etail block diag rams of each system, such as the phaseloc k system, and the third level s h ows α block diagram of α give n circuit or ci rcuit boa rd within t he system. Levels two and three b lock diag rams usually contain signal and voltage levels for each stage.

When measuring voltages and waveforms, use extreme care in placing meter leads or probes. Because of high component density and limited access within the instrument, an inadvertent movement of the leads or probe could cause α short circuit. This may produce transient voltages which can destroy many components.

4- 6

2184-36

3. M ake an educated guess as to the nature of the pro blem such as component failure or cali bration, and t he fun ctional area most li kely at fa ult . 4. V is ually inspect the area or assembly for such defects as broken or loose connections, improperly seated components, overheated or b urned components, chafed insulation, etc. Repair or re place all obvious d efects . In the case of overheated components, try to d etermi ne the ca use of the overheated condition and correct b efore applying power. 5. By s uccessive electrical c hec k s, locate t he problem . At this time an oscilloscope or signature analyzer is α valuable test item for eval uating circuit performance. If applicable, chec k t he calibration adjustments . Before changing an adj ustment, note its position so it can be returned to its original setting. This will facilitate recali bration after th e trouble h as been located and repai red . 6. Determine the extent of the repair needed ; if complex, we recommen d contacting your local Te ktronix Field Office or rep resentative . If mino r, such as α component replacement, see the R eplaceable Parts list fo r replacement info rmation. R emoval and replacement proce dure of t h e assemblies and su b-assem blies is d escribed under Corrective M aintenance .

REV FEB 1982

Maintenance-492/492P Service Vol . 1 (S N Β030000 & up)

CORRECTIVE MAI N TENAN C E Corrective mainten an ce consists of componen t rep lacement a nd instru me n t repai r . Special tech ni q ues a nd procedures req uired to re p lace compon e nts in this i n st ru ment a r e described h e re.

Ob tai ni n g R eplacement P arts

All elect rical an d mechanical parts are available t h roug h your local Te ktro n ix Field Office or represe n tative. The Rep lacea b le P arts list section co n tai n s information on h ow to order t hese re p lacemen t parts .

ΝΟΤΕ Some components that are heat sinked to the circuit board extrusion or module wag are soldered to the board after the board is mounted In place. This is η eιessaηto avoid cracking the IC case when the mounting screw is tightened. These components are identified by α note on the schematic drawing. Their part number appears with chassis mounted components in the Replaceable Electrical Parts list.

P arts o rie ntation an d lead d ress s h o u ld be du p licated becau se some com p on ents are orie nted to reduce interaction or control circuit ch aracter istics . If α part you h ave o rd ered h as been replaced with α new or improved part, yo u r local Fiel d Office o r re p resen tative will co n tact you concern i n g any ch a nge i n the part nu mber . Afte r repair, th e circuits may nee d recali bration .

Parts R e p air and R eturn Program

Assem b lies con taining hy bri d circuits o r subst rates in α semi-sealed module, com plex assem b lies suc h as t he YIG oscillator, 829 MHz converter assem b ly, or ph ase gate detector can be ret ur ned to Tektron ix for re p air u nder the repai r and return p rog ram . Co ntact your local Field Office for exch ange rates . Tektronix re p air ce n te rs provi d e replacement or repair service on maj or assem b lies as well as th e un it . Return t he instr u me n t or assem bly to your local F ield Office for t h is service.

REV A U G 1981

Sold e ri ng Tec hn iq u es

Disconnect the instrument from its power source before replacing or soldering components. Some of t h e circuit boar d s i n t h is in strumen t are multilayer ; th e refo re, extreme ca ution must be use d when α soldered com ponent is removed or rep laced . E xcess h eat from th e soldering iro n and bent com p o n ent leads may pull t he p lati ng out of th e hole. We suggest clipp ing th e old comp on e n t free . Leave e no ugh lead length so t he new component leads can be soldered i n p lace . If you desi r e to remove t he com po nen t leads, u se α 15 watt or less pen cil type i ron . St raig h te n t he leads on t h e back si d e of t he boa rd ; th en when t h e solder melts, gently pull t h e soldered lea d t h ro u g h t he h ole. Α d esolder ing tool sh ould be u sed to remove th e old solder .

Rep lacing t h e Sq u a re P i n fo r t h e Mu lti- p i n Co nnector s

It is important not to damage or distu rb the ferrule when removing th e old stub of α bro ken pin. Th e ferrule is presse d i n to t h e circuit board an d provides α base for solderin g th e pi n connector. If th e broken st ub is lon g enou g h , g r asp it with α pair of need le n ose pliers, apply h eat with α small soldering iron to th e pi n base of th e ferrule, and pull t h e old pin out. (T he pi n is p ressed into t he ferrule so α firm pull is req uired to pull it ou t.) If th e bro k en st ub is too short to gr as p wit h p liers, use α small d owel (0 .028 inch i n diamete r) clamped in α vise to pus h t h e pi n out of t he ferrule after th e sol d e r h as been h eated . T h e old ferrule can be cleaned by re heati n g th e solder an d p lacing α sharp obj ect such as α toot hpic k o r small dowel i n to t h e hole. Α 0.031 i nc h d rill mou n te d in α p in vise may also be used to ream th e solder out of th e old ferrule.

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Maintenance-492/492P Service Vol . 1 (S N Β030000 & up)

U se α pai r of diagonal cutters to remove the fe rrule from the n ew pin ; then insert the pin into the old ferru le an d solder the pin to both sides of t h e ferr ule . If it is n ecessary to bend t h e new p in, grasp the b ase of the p in with needle nose pliers a nd bend against the pressu re of t he p liers to avoid breaking the board a round the ferrule. Selected Components Some components, such as microcircuits, are selected to meet Tektronix specifications . These components carry only Tektronix p art numbers unde r the Mfr Part number column, in t he Replaceable Parts list . Some circuits re qui re α selected component value to compensate fo r pa rameter differences between active components . These are identified on th e ci rcuit diagram and the Replaceable P arts list . The R eplaceble P arts list descri ption fo r t he component gives either α n ominal value or range of value. If the procedure for selectio n is not obvious or complex, such as setting the gai n or resp onse of α stage, the criteria fo r selection is ex plain ed in the Calibr atio n o r t his sectio n of t he ma n ual . Wh ere the selectio n procedu re is obvious, suc h as esta blishing the freq uency of an oscillator, no procedure is given. Installi ng F ilters

Matched Crystals fo r the VR 100 H z

The crystals for t he 100 Hz filter ci rcuit of the VR assem-

bly are matc hed . The fo ur crystals come with rubber tiedown st raps. Plug the matched crystals into the two boards, insert the rubber tie-down into the two h oles provided on either side of the crystal on the board an d pull t hroug h u ntil the crystal is hel d in place by the tension of the rubber tiedown.

4-8

R eplacing EPROM's or ROM's Firmware for t he microcomputer is co ntained in ROM's on the M emory and GPI B board s. Refer to the Replaceable E lectrical P arts list (Vol . 2) under these assemblies (Α54 M emory, and Α56 G PI B) for the versions and IC part n umbers.

Firmware Version a nd

Error Message R eadout

T his feature of the 492/492Ρ provides readout of the fi rmware version when the powe r on/off is cycled . During the initial power-up cycle, the fi rmware version flas hes on screen for approximately two seco nds . The Replaceable E lectrical P arts list sectio n, u nder M emory board (Α54), lists the ROM's and their Te ktronix part n umber for each fi rmware version . An additional feature is error message readout. The followi ng is α list of these messages and thei r meaning.

Error #

M eaning

57 58 59 60

Tun e routi ne failed to carry from lower DAC. F ailed to ph aselock. Lost lock. F ailed to recenter when phaselock cancelled or when going to an unlocked s pan.

Servicing t h e VR Modu le

The VR module requires mechanical support when it is installed on board extend ers. M echanical support is provided b y moving the mounti ng p late at the upper side of the module ( Fig . 4-5Α) to the bottom si de. This allows installation of α mounti ng screw through α s upport brac ket into the mounting plate screw hole as shown in F ig . 4-5Β.

REV AUG 1981

Maintenance-492/492P Service Vol . 1 (S N Β030000 & up)

Β. VR m o dule on extend er boards a nd secu re d f o r servici n g.

F ig . 4-5.

Pre p arin g th e VR module for service showi n g supp orted wh e n on an exte nd e r .

h ow

it is

Maintenance-492/492P Service Vol. 1 (SN Β030000 & up)

REPLACING ASS EMBLIES AND SUB ASSEMBLIES Most assemblies or sub-assemblies in th is inst rument are easily removed and replaced. Th e following describes

Α t un ing sc rew, moun ted through t he top of the diode asem bly, adjace nt to the 8-32 sc rew hole is adjusted to null α start spur on b and 1 to -10 d l3m. Although pre-cali brated, care should be ta ke n not to fo rce the tun ing sc rew after it b ottoms out on t he surface of the quartz suspended substrate. (T he null usually occurs about one tu rn f rom the bottom .)

Removi ng or Replaci ng Se mi-rigid Coaxial Cables

The d iode assem bly is p ackaged in α static-free p ackage. Keep t he diode su b-assem bly in this package until ready to install. The following procedure should be used when replacing t his sub -assem bly .

procedures for replacing those assemblies that re qui re special attention. Top and bottom views of the 492/492Ρ with Options 01, 02, and 03, are show n in Figs. 4-6 and 4-7. These figures identify most assem blies by n ame and assembly number .

Performance of t he instrume nt is easily degraded if these conn ectors are loose, dirty, or damaged. The following procedure will h el p ensu re good performance. 1 . U se α 5/16 inch open-end w rench to loosen o r tighten the connecto rs. It is good practice to u se α second wrench to h ol d t he rigid (receptacle) portion of the conn ector to preve nt bending or twisti ng the cable . 2. En sure that the plug and receptacle are clean and free of any foreign matter. 3. Insert the plug connector fully into t he receptacle before screwing the nut on . Tig hten the connection to 8 to 10 inch pounds . Do not overtighten (15 to 20 inch pounds) because this can damage the co nnector.

Replaci ng the Dual Diode Assembly

Th e d iode sub-assembly h ousing the Sc hott ky mixe r diodes permits easy fiel d replaceme nt of the diodes .

The diodes are beam-lead devices mounted on α quartz suspended substrate, these diodes are extremely static sensitive. Refer to the Caution note on static that precedes this section. Do not expose the diode assembly to any RF field. The diode sub-assem bly is secured in place with four 080 sc rews. An 8-32 threaded hole is provided to facilitate insertion and removal of the sub-assembly. There are three co ntact points located on t he subst rate side of the subassembly. U se care when mounting and orienti ng these contacts with t he mating co ntacts in the mixer assembly to ensure proper fit and function. I nsertion and removal of the sub-assembly more than twice is not recommended due to the gold ri bbo n attach technique used in fabricatio n.

4- 1 0

1 . Remove the two mo unting sc rews and remove the assembly from the 492/492Ρ; then loosen and disconn ect the three coaxial ca ble conn ections to the mixe r assembly . 2. Remove the four 0-80 screws and insert α 8-32 screw into the threaded hole p rovi ded in t he center of the diode assembly . 3. Lift the d iode assembly out of the mixer assembly by means of the 8-32 screw ; then remove the sc rew . 4. Open the diode p ackage, gras p t he d iode assemb ly by its side with tweezers and place it on α static-free surface. Grasp the side of the assembly with the fingers to avoid contact with the d iodes and insert the 8-32 screw .

5. Orient the d io de assembly so t he three contact tips are aligned with t heir respective contacts in the mixer; then u sing the ind ex fi ngers of both hand s so equ al pressure is applied, press the sub -assembly into p lace. 6. Insert the four mo un ti ng screws, tighten, then replace an d tighte n t he three coaxial connectors so they are ju st snug. Install the two mounting screws that hold the assembly in the 492/492 Ρ.

Replacing the Crt Removal 1 . Remove the snap-i n printed bezel a nd crt light filter . 2. U se α 8/ β4 in ch Alle n wrench to remove the four bezel sc rews, unplug and remove the in ne r bezel .

REV A UG 1981

Maintenance-492/492P Service Vol . 1 (S N Β030000 & up)

2182 MHz P H AS E L OC KE D 2nd L O ( Α 22)

100 MHz OSC & 3rd CO NVERT ER (Α34)

DI RECTIONA L F I LT E R ( FL 16)

S WITC HE D E NUATOR (ΑΤ 10)

ATT

3783-31

Fig . 4-6 . RF d eck of t he Β 040000 a nd up v e r sio n sh owi ng th e m aj o r assemblies .

REV A U G 1981

4- 1 1

Maintenance-492/492P Service Vol . 1 (S N Β030000 & up)

2727-69A

Fig. 4-6Α. Vie w of t he 492/492Ρ R F dec k for Φ3039999 a n d b elow ve rsio n s s howin g m aj o r assemblies a n d circ u it boa r ds .

4- 1 2

R EV AU G

1981

Maintenance-492/492P Service Vol . 1 (SN Β030000 & up)

Fig . 4-7. View of the 492/492Ρ to p deck sho wing major asse mb lies .

REV AU G 1981

4- 1 3

Maintenance-492/492P Service Vol. 1 (SN Β030000 & up) 3. Unsolder the grou nd wire from the front-panel casting and unplug the crt cables at thei r respective board connections (high voltage mo du le, deflection am plifier, and Ζ-Axis b oard). 4. Slide the crt, with its shield, out th roug h t he front

panel .

5. R emove the crt shield as follows: α) remove the tube base cap and unplug the socket ;

b) remove the two side sc rews that hold the upper shield in place ; then remove the shield ;

If t he "start" ( black) lead is broken and the lead is too short to res p lice, attempt to fish out the broken end so one or two turns can be unwo und. Resplice and solder to the lead; then rewind and retape . Front-Panel Assembly

The front-panel assembly does not have to be removed to replace any of the pu sh butto ns. Refer to Replaci ng Front-Panel Pu sh Buttons procedure that follows . The crt is removed with th e fro nt-panel assembly . Removal

c) loosen t he screws that clam p the plastic br acket around t he εrt ; then remove the bracket .

1 . U nscrew and remove the mounting nu ts and washers for t he RF INPU T, ΕΧΤ M IX ER, plus the two 1 st and 2nd LO OU T PU T connecto rs.

Replacement

2. R emove the two screws that t he RF deck (center and left side).

1 . Install the plastic bracket so the back on t h e clam p is 5.07 inches from the back of the crt socket guide. 2. Replace the crt shield plus the socket and base shield by reversi ng the removal procedure. The finis hed crt assembly length, with cap installed, must equal 11 .05 inches . If it is longer, the assembly may s hort circuit the Log Am plifier circuit board wh e n it is installed. 3. Install crt with s hield assemb ly into the front panel . Install bezel an d tigh te n the four mo un ting sc rews.

h old the front panel to

3 . U nplug the CA L O UT coaxial cable from the 3rd Converter ; then disco nn ect the five crt ca bles from the ΖAxis/RF nterface, High Voltage mo du le, and Deflection Amplifier.

I

4. Loo king at the to p of the instrument, remove th e one sc rew that holds the front panel to the si de extrusio n, between the crt and the rig ht side of the instrument . 5. Now set the inst ru ment on its side and remove the fo ur screws that h ol d t he front panel to the si de rails .

Do not reposition the front-panel blue plastic crt holders. They have been factory aligned so the crt assembly seats properly. Visually inspect to ensure that the εrt assembly clears the circuit board components. 4. Reconnect cables to thei r respective board connectors and resolder t he g roun d lead to its terminal . Replace crt light filter and snap-i n bezel.

Repairi ng the Crt Trace Rotation Coil The trace rotation coil is part of the crt assembly . If the coil is d amaged beyo nd repair, the crt with t he coil must b e replaced. If th e "finis h" (red) lead is broken, remove the tape and unwi nd o ne or two turns so it can be res pliced and soldered to the lead wi re. Rewind and retape.

4- 1 4

6. Pull t h e front p anel up and off the M other board . Replaceme nt

Replace the front panel procedure.

by reve rsi ng the removal

Fro nt-Panel B oard ΝΟΤΕ Α replacement Front-Panel board comes with switches and controls for α// Options (01, 02, 03, etc.). Before rep/acing an existing board, remove the switches and controls on the new board that are not used on the existing instrument.

REV AUG 1981

Maintenance-492/492P Service Vol . 1 (S N Β030000 & up) Removal

Main Power S upply Modu le

1 . Remove the fro nt- panel assembly as descri bed

previously.

2. U se an Allen wrenc h to loosen the k nob locking screw and remove all knobs. 3. Lay the front-panel on its face ; then remove the eleven ci rcuit boa rd screws and the screw that h eat sinks and hol ds IC U 6090 on the b oard. Note that the screw n ext to the connecto r plug h as α fi ber washer . 4. To prevent losi ng the grounding ri ngs or b ushi ngs b etween the front-panel controls and t he front- panel casting, hold the ci rcuit board agai nst the front-panel casting while turning the complete assembly so it rests on the base of the crt assembly . 5. Ge ntly lift the casting from the ci rcuit board. Ensure that the grou nding rings remai n on th e s haft of all controls as the casting is removed. Replaceme nt Reverse t h e removal procedure, ensuring that the fi ber washer is on the board screw next to the connecto r plug. This was her prevents the screw from shorti ng α circuit b oard run to th e front- panel casting.

R eplaci ng Front- Panel Pu sh Button Switches

To avoid damage to the Mother board connector J5041 and Interface connector J1034 during removal or installation of the Power Supply Module, use the following procedure. Removal 1 . Disconnect the p ower cord, set t he 492/492Ρ on its face or front p anel and remove the instrume nt cover . 2. U nplug the coaxial ca ble connecto r Ρ620 from th e

Log Am plifier assembly and pull th e cable throug h so it is

clea r.

3. Remove the three sc rews that h ol d the power modu le to the RF deck flange (bottom rig ht si de) . 4. Remove the four screws that h old the p ower supply modu le to the si d e- rails . 5. With t h e instrument on its face and the RF dec k on th e near si de, pull the left si de of the power modu le from its side- rail (no more than one and one-half inch). Now grasp both si des of the module an d lift to separate the module from the M ot her boa rd.

The front-panel assembly does not h ave to b e removed to re place any push button switch. The p rocedu re follows : 1 . Remove front- panel kn obs. Loosen an d remove nuts an d washers for the RF I NPUT, E XT ERN AL MIX ER, p lus the 1st an d 2nd LO co nnectors.

W A RN I N G

Because C6011 and C6101 discharge νeη slowly, hazardouspotentials exist within the power supply for

2. Remove th e screw that was under t he FREQUENCY tuni ng knob wh ich holds the panel to the front- panel casting.

severalminutes after the power switch is turned off. Α relaxation oscillator, formed by C5113, R5111, and DS5112, indicate the presence of voltages in the circuit until the potential across the filter capacitors is below 80 V.

3. L oosen the b lack screws through the crt bezel so the panel can be moved enough to lift it off the casting .

Replaceme n t

4. U nplug a nd replace the d esired switches .

REV A UG 1981

1 . Set the instrume nt face dow n with t he RF dec k on the

n ea r side.

4- 1 5

Maintenance-492/492P Service Vol . 1 (SN Β030000 & up) 2. H old the power supply module over th e instrument so th e right side is touching t h e si de-rail an d the left si de is about one and one- half inch above its side-rail.

U n sol e r

7

a nd

lift

3. Alig n connectors Ρ5041 and P1 034 wit h th eir respective M ot her board and Interface board co nnectors and p ress the module into place between the si de-rails. 4. Replace the four module holding screws and the three flange screws . Unsol d er and " Ν

5. Th rea d the coaxial cable u n der the semi-rigid cables on the RF deck and through t h e dec k o pening to the Log Am plifier assembly connector J 620 so the cable will not catch wh e n t he instrume nt cover is re p laced. Α.

6. Replace the instru ment cover.

Oscillator assem bly .

H ig h Voltage Power Supply

B efore the Hig h Voltage P ower Suppl y circuit board ca n be unplugged and removed, α screw thro ugh t he si de-rail into α nylon standoff bushing, at the bottom corner of the board, must be removed.

Replaci ng the 1 st (YIG) Local Oscillator I nterface

Board

The YIG oscillator assem bly incl udes an interface circuit board that can be or dered separatel y. 7ο re place the b oard refer to Fig . 4-8 an d the following procedure. Use α d esol dering tool to remove the solder as these leads are un soldered . 1 . Unsolder and lift one end of C1014 (820 μF) ca pacitor at the to p of t he board.

Unsolder ci rcled connectio n s .

Β.

I n te r face

2. U nsol der and lift one end of VR 1010 . 3 . Unsolder and lift the wire to the grou n d lug on P1 66 . 4. Unsolder the eight leads to t he Y IG and lift the board off the assembly . Co mpliant

Mounted Fa n

Instru ments SN Β010322 and up may h ave α compliant F ig . 4-9) . It is important t h at th e mou nting screws for th ese fa n s are not ove r-tig h tened . mo u nted fan (see

4- 1 6

board

s howing termi n als

to u nsolder for r emov al . 2727-6 α

Fig . 4-8 . R emoving Υθ G Oscillator i nterface circuit board. Removal 1 . R e move p ower supply as described in th is sectio n . 2. R emove six scre ws that hold the po wer supply cover in place. Ta ke the coaxial cable out of th e plastic retainer clip and lift the power sup ply cove r with fa n up, so harmonica connector Ρ 3045 can be d isconnected a n d t h e cover remove d .

REV AU G

1981

Maintenance-492/492P Service Vol. 1 (SN Β030000 & up)

F A N PL AT E

386-4595-

00

FA N

F A N S P AC E R

3(o1-1099 -00

ιι»)ηητη»»»]γ ιΑυτιοΝ

SEE MAINTENANCE N ST R U CTIO N S FO R I

INSTALLATION

PR OCE E D UR E .

ιΗηη) I%

4-40 Χ .312 M AC H IN E SC RE W (9 ΕΑ )

4- φ 0 SELF- 1 DC Kf N G NY L O N N U T (2 ΕΑ) 220-0665-00 4-40 N U T~ WASHER (-t ΕΑ )

Ζ11-0097-00

)

)J

M ~ ~ ~ / ν

GgO MME T ~(2 ΕΑ.) 3φ 8-0093-00

Y E LET (z ΕΑ ) 210- 0774-01 E

FLAT WAS HER ' (2ea .) 210- 0851-00

5/8 °

4-40 MAC H .SC R E W

211-001(-00

2727 154

Fig. 4-9. Exploded drawing of fan assembly .

3. Unsolder the leads to the fan . 4. Using α 1/4 inch o pen-end wre nch or n eedle- n ose pliers, retain th e nylon nut while u nscrewing t he fa n mo unting scre ws with α Ph illips screwdriver .

ΝΟΤΕ After the fa n is remo ved, be sure to retain th e rubber and steel washers on the screws. These are essential for proper operation of the compliant moun t. Do not remove the self-locking nylon nuts. 5. Remove the lead gask et from t he old fa n and install it on the replacement fan assem bly . Do n ot over-tig hten th e screws retaining t h e gas ket . The lead is soft enough to b e deformed by over-tig htening . Re placement 1 . Refer to Fig . 4-9 and replace as follows: α) place the foam gasket between the fan h ousing and the power su pply module cover ;

REV A UG 1981

b) insert the two 5/8 inch machine screws, with washers

mounted as shown in Fig . 4-9, th roug h the two eyelets . Place the fan in position; t he n , while h oldi ng the nylon n ut with n eedle-nose pliers, screw the mounting screws into the nu t until t he end of the screws is just fl ush with th e nut . Do not re-use these nuts because they ca n loosen with v i bration . The nylon nuts are self-locking. 2. Re-solder the fan p ower leads, brown to pi n 1, red to pi n 2, orange to p in 3, and yellow to pin 0. 3. Reconnect th e pl ug Ρ3045, ma king sure the index markers are aligned, then replace the cover with t he fan onto t he power supply module . 4. After installi ng the six screws that h old the cover in place, en su re that the fa n assembly moves freely. Replace the coaxial ca ble in the plastic retaining clip. 5. R ei nstall the power su pp ly assembl y as directed under Power Supply Re placement. Apply power an d chec k for n ormal fa n operation . If fan d oes n ot run, ch ec k t he co nn ection of h armonica connector p lug Ρ3045 .

4- 1 7

Maintenance-492/492P Service Vol. 1 (SN Β030000 & up)

M AINTENANCE ADJUST M ENTS The following procedures are not part of the reg ula r cali bratio n. They are applica ble when an assembly is replace d o r after majo r repair. 110 MHz IF Assembly Retum

Loss Cali bration ΝΟΤΕ

The IF assembly must be removed to gain access to the adjustmen ts. Ta ble 4-2

E QUIPMENT REQUIRED Recomm end e d Type

Characte ristics

Test Equipment Spectrum Analyzer

Freque ncy range >110 MHz

TEKTR ON IX 492/492Ρ o r 71-18 Spectrum

Signal Ge nerator

Frequency 110 MHz at +10 dBm

TEKTRONIX SG 503 for the TM 500 Series

Analyzer

Wiltron VSWR Bridge,

VSWR Bridge

M odel 62BF50

10 dB and 1 dB Step Attenuators

50 Ω, 0 dB to 40 dB

TEKTRONIX. 2701 Atteηuator

Termin ation

500

Tektronix P art No. 011-0049-01

Ad apte r

Βηιαto -Sealectro

Tektronix P art No. 175-0419-00

1 . Test equi pment setup is shown in Fig . 4-10 . Apply 110 MHz at 2 V peak to peak (+10 dBm) through 35 dB attenu ation to the RF Inp ut of the VS WR bridge. Connect the RF Out of the VSWR bridge to the RF Input of the spectrum analyzer. (Do not connect t he 110 MHz IF to the VS WR bridge .) 2. Set the spectrum analyzer center frequency to 11O MHz, SPAN/DIV to 5 MHz, RESOLU TION BANDWIDTH to 3 MHz, VERTICA L DIS PLAY to 10 dB/DIV, and REFERENCE LEVEL to -20 d Bm. 3. Adjust the step atte n uato r for full screen (-20 dB m) display. 4. Co nn ect th e 110 MHz IF input to the VS WR bridge and connect α 50 Ω termination to the output of the IF am plifier. Now p lug th e power ca ble Ρ3045 into the + and -15 V source a nd g rou nd the case of the assembly. 5. Adjust C2047 and C325 (Fig . 4-11) simultaneously for minimum signal amplitude on the spectrum analyzer d isplay.

4- 1 8

M inimum amplitude must be at least 35 dB down from the full screen reference of -20 dBm.

6. Disconnect test equ ipmen t setu p a nd replace the 110 MH z IF assembly.

Do not open the assembly. Adjust the tuning slug only after checking the filter characteristics . 2072 MHz 2 ND CO NVERTER

The 2nd Co nverter assembly consists of α four cavity 2072 MHz bandpass filter, mixer, and α 110 MHz lowpass filter . The assembly is calibrated at the factory, prior to installation, and re quires no cali bration after it is installed. We recommend replacing the assembly if it should malfun ction. The following procedure describes adjustments th at can be made if the b iasi ng should malfun ction or th e seal on any of the filter tuning slugs is broken. The mixer d iodes a re n ot to be replaced in the field. Return the assembly to Tektronix, Inc., fo r repai r.

REV AUG 1981

Maintenance-492/492P Service Vol . 1 (S N Β030000 & up) TM 503 M ain F ra me

2η7-7 τη

Fig . 4-10 . Test equ ipm ent setup fo r adj ustin g retu rn loss fo r t he 110 MHz I F assem bly.

M IX ER To gain access to the B ias adjustments, remove th e assembly from its mounting ; then remove the mou nti ng plate on t he b ottom of the assembly . Reco n nect th e M ixer to the in put/output lines, u sing the same cables (cable length of semi-rigid ca bles is critical). Apply the CA L OU T signal to the RF NPUT and tune α marker to center screen . Sim ultaneously adju st bot h bias potentiometers for maximum signal am p litude .

I

110 MHz THREE CAV ITY F I LTER

I

Fig . 4-11 . Locatio n of the 110 MHz F ret urn loss adjustments and F Gain adju stment.

I

FOUR CAV ITY FI LTER T he characteristics of the filter are checked with α network analyzer . Fre q uency of the filter is 2072 M Hz, b andpass is 15 MHz down 1 dB , retu rn loss is 20 dB or greater, and insertion loss is 1 dB . If the seal is broken on any tuning slug, ad j ust for maximum ret u rn loss .

RE V AUG

1981

Alig n me nt is not α normal cali bration adjustment . Th e t un ing slugs are adj uste d for ce n ter fre que ncy and r es ponse shape so the resol utio n ban d wi dt h is within specificatio ns. The adjustment p rocedu re follows. 1 . With t he CA L OU T signal applied to the RF I NPUT, tune the signal to center screen and reduce the RESOLUTION B ANDWIDTH to 1 kH z. 2. Tune the sig n al to cen ter scree n to esta b lish center freq u e ncy refere nce ; th e n in crease the RE SO LU TION BAN DWIDTH to 1 MHz.

4- 1 9

Maintenance-492/492P Service Vol . 1 (S N 13030000 & up) 3. Adjust the tun ing sl ugs fo r best respo nse shape, ce ntered around t he reference. Ensure bandwidth (6 dB down) is 1 MHz. 4. Chec k resolution bandwidth accuracy over the range of the RE SO LUTION BANDWIDTH selector to ensure that band wi dth is within specification. 829 MH z Co nverter

Maintenance

Some circuit boards in this assemb ly contain critical le ngt h printed elements . When damaged, these elements are usually not repaira ble ; t h erefore, th e circuit board must be replaced. E ven though replacement boards are precalibrated and repair can b e accomplished by replacing the b oard, we recommend send ing the inst ru men t or asse mbly to your Tektro nix Service Ce nter for repair. The 829 MHz ba nd pass filter in t he IF sectio n, and the 719 MHz LO in t he LO section, requi re adjustment only if t he board h as bee n damaged o r active components (t ransistor or varactor) have been replaced. The following describes prepa ration for service and replaceme nt procedu res . The first two steps d escribe how to gain access to either t he LO or the IF section ; the remai ning steps descri be adju stment p rocedure fo r each section. 1 . To gain access to the LO section

α. Switch POWER off; u se α 5/64 Allen wrench to loosen and remove the cove r screws.

b. Remove the cover. ε. Refer to step 3 fo r adjustment procedure. 2. To gai n access to t h e IF section α. Switch POWER off; use α 5/16 inch wrench to d isco nnect and remove all coaxial connecto rs to the 829 MHz converter.

b. U nscrew and remove the six mounting screws, unplug the input power co nnecto r Ρ4050, then remove the 829 MH z converter assembly .

reco nnected to the M other board. Be sure to observe plug orientation (pin 1 to pin 1) . e. Refer to step 4 for adju stme nt procedure. 3. 719 MHz Oscillator Ra n ge Adjustment

α. Adjustme nt requires th e following test equipme nt:

Α frequency coun te r with α frequency range to 1 GHz (nine digit readout), se nsitivity of 20 mV rms prescale, 15 mV rms direct (such as TEKTRONIX DC 508Α); α digital voltmete r with α 3.5 digit readout (suc h as TEKTRONIX DM 502Α); test leads for the DVM, α 50 Ω coaxial cable with bn c conn ectors (Tektronix part n umber 012-0482-00) and α sma male-to-bnc female adapte r (Tektronix part number 015-1018-00) . 4

b. The 2nd LO range is from 714.5 MHz to 723.5 MHz

(with t he cover off). 719 MHz is the optimum center frequency . Frequency of the oscillator is controlled b y the Tune Volts from the 25 MHz Phaselock ci rcuit (located at ΤΡ 1011) whic h varies from +5 V (low end) to +11 .9 V (hig h end) with +6.75 to +7 .5 V as the limits for operation at 719 MHz. Set the digital voltmete r to measure 12 V th en connect it between ΤΡ1011 (Fig . 4-12) and ground. ε. Disconnect the 100 MHz referen ce from the 3rd Converter by unp lugging Ρ235 (Fig . 4-12) . The oscillator s h ould go to its up pe r limit a nd th e voltmete r indicate about 11 .9 V . d. Connect the 75 MH z-1000 MHz input of the frequency counter throug h α 50 Ω coaxial ca ble to the frontp anel 2nd LO OUTPU T connector. e. The 719 MH z oscillator frequency is α function of the length of the printed 1/4 wavele ngt h transmission li ne. Minor adjustments to the oscillator frequ ency are made by shortening the U -shaped transmission line stub, off the main li ne. Graduation ma rk s (see F ig . 4-12) along the si de of the stub provide α guide to calculate frequency correction. Eac h mi nor mark f rom the end or cut across the stub, re presents an approximate change of 2 MHz.

ε. Turn t he assembly over and remove the cove r fo r t he I F sectio n.

C heck t he frequency by noti ng th e read ing on t h e frequency co unter. If above 723 .900 MHz, the stub must b e length e ned. Solde r α br idge ac ross th e cut a nd rech eck frequen cy. N ominal frequency for an uncut stub is 710 MHz.

d. To troubleshoot or calibr ate the circuits, set the assembly at α location so the input powe r plug Ρ4050 ca n be

f. Shorte n th e li n e so the frequency is near 723.500 MHz. Fo r example : Th e frequency d ifference be-

4- 2 0

REV AUG 1981

Maintenance-492/492P Service Vol . 1 (SN Β030000 & up)

2 ττ7-iss

Fig . 4-12 . LO section of 829 MHz con verter showi ng test poi nts a nd co nn ecto rs. tween desired and actual, divided by 2 MHz, eq uals the nu m ber of mi n or d ivisio n s from the line e nd for th e new cut. M a ke α cut across t he line an d chec k th at t he n ew frequency is between 723.100 an d 723.900 MH z. Repeat as necessary. Cover t he 719

MHz oscillator cavity

MH z Converte r cover, press down to en sure good sh ield i ng, an d note t he frequency readout of t h e cou nter . Freq uency sho uld fall within 723 .600 an d 724 .400 MHz. g.

wit h the 829

h. Reconnect Ρ234 (100 MHz) a nd Ρ237 (2182 MH z)

a n d confirm t h at ph aseloc k is operating b y noting th at t he

REV A U G 1981

voltage on ΤΡ 1011 is between 6.75 and 7.5 V. Th is comp letes the adj ustme nt of t he 719 MHz L O. Replace th e cover and rein stall the 829 MHz converter assem bly .

4 . 829

MHz

Coaxial

B andpass F ilte r A dju stme n t ΝΟΤΕ

This procedure is necessary if th e position of one of the va ria ble capacitor loops (tabs) has been altered, changing the bandpass characteristics of the filter.

4- 2 1

Maintenance-492/492P Service Vol . 1 (S N Β030000 & up) α. Test equipment required: Spectrum analyzer with tracking ge nerator.

492/492Ρ Spectru m Analyzer with T R 503 trac king Ge nerator ; or 71_13 with α T R 502 Tracking Generator.

Freque ncy Co unter

TEKTRONIX DC 508

Return Loss Bridge

Wiltron Model 62 BF50

b. Un solder an d reconn ect the j um per, on th e 829 MH z Am plifier board , to the test Peltola jack J1029 (see Fig . 4-13).

ε. Co nnect the spectrum analyzer, tracking generator, an d frequency counter toget her as α system, with the frequency counter connected to the Auxiliary RF Output of the trac king generator (see Fig . 4-14). d . Connect the spectrum analyzer/t racking generator system through the return loss b ri dge to the Peltola j ack (J 1029) on the 829 MH z am plifier board (see F ig . 4-14). Reconn ect Ρ235 (100 MHz reference signal) and Ρ237 (2182 MH z input) to the L O section of the converte r. Terminate the 110 MH z Output (J232) connector with 50 Ω, u si ng α bnc-to-Sealectro ada p ter and 20 d B bnc atte nuato r. Pull the IF SELECT li ne h ig h by switc hing to band 2 (1 .7-5 .5 GHz) .

829 MHz Co nverter

2727-156

Fig . 4-13 . Location of test j ack and jumper on t he 829 MHz A mplifier boa rd .

4- 22

REV AUG 1981

Maintenance-492/492P Service Vol . 1 (SN Β030000 & up)

J 232

Test Oscilloscope

J 233

2727-157

F ig. 4-14. Test equipme nt setup for alig ning the 829 MHz filter. e. Set the test spectrum analyzer Reference Level to -20 dBm, Vertical Display mode to 2 dB/div, Resolution Bandwidth to 300 kH z, and Fre q Span/Div to 20 MH z. Tune th e Center Fre quency for α readout of 829.00 MHz on the freque ncy counter. f. Ad ju st the 1/4 wavelength lines in the filter in sequence, starting with the reso nator at the 829 1 MH z in p ut (see F ig . 4-15) . Adj ustment is made by shorti ng the adj acent resonator to ground with α low inductance conductor, such as α broad blade screwdriver, then b end the loop or ta b of the respective stub with α non-metallic tuning tool to change the series ca pacitance of the resonator.

REV AU G 1981

g. W it h th e adjacent resonator (second) shorted to groun d, adju st the series capacitance by bending the tab so t he response on the spectrum analyzer display is cen tered at 829 MH z (see Fig . 4-16Α).

h. Now move the shorti ng strap (screw driver) to the next resonator and adjust the tab of the second resonator for α respo nse as indicated i n Fig . 4-16 Β. i. Remove the short from the third reso n ato r an d short the fourth resonator . Adjust th e third resonator for α response similar to that shown in Fig . 4-17 Α.

4- 23

Maintenance-492/492P Service Vol . 1 (S N Β030000 & up)

Fig . 4-15 . Filte r tun e ta bs in the 829 MHz co nverter. j. R epeat t he p roced ure for the fi n al (fourt h) resonator for α response similar to that shown in Fig . 4-17 Β.

k. Ch ec k t h at th e return loss is equal to or greater than

12 dB .

Ι. Disconn ect the return loss Device Un der Test lead to the Peltola jack J1029 on the 829 MH z Amplifier board, then unsol der and reconnect the ju mper to the am plifier output . m . Replace the 829 MH z Co nverter cover and reinstall the assembly in the 492/492Ρ.

4- 24

Troubles hooting a n d Calibrating the 2182 MHz Ph aseloc k e d 2 nd L O The assembly contains α microstrip ph aselock ed 2182 MH z oscillator and its ph aseloc king circuits . The 1422 MHz Ph aselock board is contained in the mu-metal h ousing; the 2182 MH z Oscillator, 2200 MHz Reference, and 2200 MH z R eference M ixer are contained in t he machined alumi nu m h ousing . The 2182 MH z M icrostrip Oscillator an d th e 2200 MHz Reference M ixer co ntain critical length printed elements . Wh en d amaged , these elements are difficult to repair; therefore, the board should be replaced. If either t he var actor

REV A UG 1981

Maintenance-492/492P Service Vol. 1 (SN Β030000 & up)

Α. 1st

Β.

2 nd

Resonator

A. 3rd Resonator

Response

Β. 4t h Resonator

Resonator Res ponse

a nd

Filte r 2727 -160

2727-159

Fig. 4-16 . Ty pical r es ponse when t he fi r st and second resonato rs of the 829 MHz filter are adjuste d correctly.

Fig. 4-17 . Typical res ponse when the third and fourth resonato rs a re tuned correctly.

d iode or t he oscillator transistor for t he 2182 MH z Oscillator is rep laced and t he oscillator frequ ency is b eyond adjustment with the frequency ad just ta b, desc ribed in this procedure, the circuit b oard must be replaced.

b oard, we recomme nd sending the instrumen t or assem bly

Eve n t houg h rep laceme nt boards are precalibrated at the factory and re pair ca n be accomplished by replacing the

REV AUG 1981

to your Te ktronix Service Cente r for re p air.

The 2182 MHz Ph aseloc ked 2nd LO should only re qu ire calibratio n when α component within the assemb ly has been replaced. This procedure is in two parts, the LO sectio n a n d th e phaselock sectio n. Equipment requ ire d to cali brate the LO section is listed in Table 4-3 and the equ ipment requ ired to cali brate the phaseloc k sectio n is listed in Table 4-4.

4- 25

Maintenance-492/492P Service Vol. 1 (SN Β030000 & up) Oscillator Section Ta ble 4-3

EQUIPMENT RE QUIRED F OR 2nd LO CA LIBRATIO N Test Equipme nt

Characteristics

Recommended Type

Spectr um Analyzer

Frequ ency range to 2.5 GHz

TEKTRONIX 492, 492Ρ or 71_13 M OD 139U

Signal Generato r

Calibrated 100 MHz with frequency accuracy within ±20 kH z and an am plitude settable to 0 dB m .

H ewlett-Pac kard Model 8640 Α/Β.

Digital Voltmeter

Measures to within 0.01

TEKTRONIX

Varia ble

Power Supp ly

Te rmi natio ns (2)

__1 MQ .

V, impeda nce

TM 500-Series DM 502A, DM 505

DM 501 A,

0 to -12.5 V, accurate to 0.1 V

T EKTRON IX ΤΜ 500-Series PS 501-1

50 Ω, 3 mm conn ectors

Te ktronix Part No . 011-0049-01

1 . Preparatio n α. Test equi pment setup is shown in Fig . 4-18 . Turn the

P OWER off. P lace the 492/492Ρ Spectrum Analyzer u pside down so the RF deck is ex posed. U se α 5/16 inch wrench to loosen an d remove the two semi-rigid ca ble connections to the assembly. Remove the flexible coaxial cable co nnection to the 100 MH z input.

f. Connect α test spectrum analyzer to the 2182 MHz unbuffered o utp ut port, Ρ210. Set the test a nalyzer C ENTER FREQUENCY to 2182 MHz, FRE Q SPAN/DIV to 20 MH z, DISPLAY M OD E to 10 dB /Div, and t he REFEREN CE LEVEL to +10 dBm. Do not position any of the cables over the 2nd LO assembly oscillator section because they can affect the freque ncy of the oscillator .

b. Remove the 14 screws that h ol d t he cover on th e mumetal section a nd remove the cover. Unsolde r th e leads to feedt hr oug h ca pacitors C2203 and C2204. (These are the ce nter two feedth roug h s th at feed th ro ug h t h e ci rcuit board , as shown in Fig . 4-22 .)

g. Bend the feedback and frequency adjusting tabs, C1021 and C1022 (see F ig . 4-1), with yo ur fi nger so they are ap proximately 30° above the board surface.

ε. Replace the cover usi ng two or three screws to hold Remove the 2nd LO assembly mo unting screws and carefully remove the 2nd LO assembly so the powe r inp ut co nn ections remain intact . Turn the assembly over so the machined al umi num h ousi ng is up and place the assembly on α flat surface. U se α 5/64 Allen wrench to remove the screws h ol ding the li d on the machined aluminum housi ng. Place the screws in α safe p lace ; then remove the lid for t h e al u mi nu m h ou sing, exposi ng the three RF circuit boards within t h e oscillator section.

α. Switch t he 492/492Ρ POWER an d the variable power supply on . Adjust t h e voltage output from the variable power supply to 5.0 V . Voltage on C2203 should now equal -5 V and α signal should appear on the test spectrum a n alyzer .

the cover in place .

d. Install α 50 Ω terminator on the 2182 MH z b uffered output port, Ρ222, (see Fig . 4-19). Set the variable p ower su pply to 0 V . Connect the plus (+) terminal to the 2nd LO housi ng and the negative (-) terminal to the exposed end of C2203 a nd L2031, t h ro ug h α 1 kΩ resistor. e. Apply α 100 MH z, 0 d Bm signal from the signal ge nerator to t h e 100 MHz Reference input port, Ρ221 . (Freq uency must be within 20 kH z of 100 MHz.)

4- 2 6

2. Adjust and C heck Oscillator Freque ncy (Refer to 4-19)

F ig.

b. Check for α collector voltage across C2023 of +10.0, ± 0.7 V . ε. Check Vbe at ΤΡ 1015 . If Vbe is greate r than +0 .5 V, pu sh the feedbac k adjustment ta b dow n slightly and if less than -0 .3 V, lift the tab. If Vbe is greate r than +0 .8 V, replace the microstrip oscillator board. If Vbe is more negative than -1 V, check t he b ias circuitry . Adjust V fo r +0 .15 V, ±0 .05 V at ΤΡ 1015 . Do not to uch t he feeAac k tab wh ile measuring voltages . d . Check fo r an oscillator frequency of 2182 MH z, ±5 MH z. Bend the freque ncy adjustment ta b C1022 to

REV AUG 1981

Maintenance-492/492P Service Vol. 1 (SN Β030000 & up) Volt m ete r

ο to -12.5 ν Power S upp ly

2182 MHz fr om Unbuffe red Out put Port 100 MHz Reference I nput 2nd LO Asse mbly :.:.:::;.;

f"

17MIJ 492/492Ρ S pectrum Analyzer (in verte d)

οοοο 3783-35 (3481-31)

Fig. 4-18. Test equ i p me nt setup for cali brati n g the oscillator section of th e 2182 MHz Phaseloc k e d 2 nd Lo. (Bend t he ta b up to i ncrease f req uency a nd dow n to lower frequen cy.) If unable to bri ng t h e oscillator frequency within r a nge, replace th e 2182 MHz microstri p oscillator board .

b ri ng th e oscillator wit h i n tole rance .

3. Measure Output Power

ΝΟΤΕ

Before making power measurements, ensure th at the unused port is terminated into 50 Ω. Un terminated ports will degrade both frequency and power measurements .

REV A U G 1981

4- 27

Maintenance-492/49213 Service Vol. 1 (SN Β030000 & up)

Fig . 4-19. Adjust me n ts a nd test point locations within th e oscillator sectio n. for out α. Check 0 dBm ±3 dB put p ower at the un buffe red port, Ρ220. b. Connect the test spectrum analyzer to Ρ222, terminate Ρ220, t hen c h eck for an output level of +10 dB m ±3 dB from th e b uffere d port . 4. Ch eck th e 2200 MHz Reference M ixer

α. U se α probe, consisti ng of α short le ngt h of semi-rigid coaxial cable with α d o block (see Fig . 4-20), to connect the output of the refere nce mixer (C204) to the input of the test spectrum analyzer. Ground the outers hield of th e coaxial ca ble against the 2nd L O housing .

b. Confirm that the output signal frequency is 18 M Hz, ±1 MHz. Adj ust the tab (C1022) for t h e 2182 M Hz M icrostri p Oscillator, to bring the 18 MH z within the 1 MH z tolerance . c. Confirm that the output level of the 18 MH z signal is app roximately -36 dB m. If the level is below -46 d Bm, c h eck t he signal levels from the 2200 M Hz Reference M ixer and the 2182 MHz M icrostrip Oscillator (-28 dBm, ±8 d B f rom t he 2200 MHz R eference M ixer and +8 dBm, ±3 d B f rom the oscillator).

4- 28

5. Chec k t he Tu ne R an ge α. Adjust t he variable supply to vary the voltage to the 2182 MH z tu ne line from 0 to -12.5 V and note the freque ncy change at C2204 (output of the 2200 MHz Reference M ixer).

b. Frequency change or tune ra nge should equal 20 to 35 MHz for α voltage change of 0 to -12 .5 V on t he tune li ne. 6. Reassembly α. Disconnect and remove the connections from the variable power supply and the test spectrum analyzer.

b. Replace the lid for the oscillator housi ng and install the 26 sc rews. Install the sc rews loosely, then tighten them starting from the ce nter of the lid and progress along the edges toward the corners to insure that no gaps exist between the lid and the h ousi ng. Any ga ps will allow RF leakage that can p roduce spurious responses. c. Reinstall t he assembly on the RF deck . R emove the 50 Ω terminations a n d reconnect the cables. Use α 5/16 inch o pen-end wrench to tighten th e semi-rigid coaxial connectors to 8 to 10 inch-pounds.

REV AUG 1981

Maintenance-492/492P Service Vol . 1 (S N Β 030000 & up)

NUT

DC BLOC K

#OSM 201-21

3783-37

Fig. 4-20. Construction of α coaxial test probe fo r t he 2182 MHz Ph aseloc ked 2nd LO.

d. Remove the mu-metal lid and reco nn ect t h e leads to feedthro ugh capacitors C2203 and C2204, on the Phaselock board . Replace the li d and install the 14 screws . Tighten the screws from the center toward the corners of the lid to prevent ga ps between the lid and the h ou sing . Do not overtighte n because the screws are easily stripped .

Troubleshooti ng and Calibrating the 14-22 MHz Ph aseloc k Section of the 2n d LO Assembly

T his si de of the assembly co ntains th e 14-22 MH z Ph aseloc k circuit board . Replacing oscillator components in t his sectio n may alter sweep linearity and freque ncy of the 14-22 MHz oscillator . The following checks and cali bration s hould aid in re pairi ng and retu rning the assembly to satisfactory operation.

Ta ble 4-4

EQUIPMEN T REQUIRE D FOR CALIBR ATING THE 14-22 MHz PHAS EL OC K CI RCUIT

Test Equipme nt

Cha racter istics

Recomme nded Type

Digital Voltmeter

Accuracy within 0.01 V

T EKTRONIX TM 500-Series DM 501 A,

Frequency Counter

Frequency to 40 MH z

TEKTRONIX TM 500-Series DC 503Α, DC 508Α, or DC 509

Service Kit E xtender board

REV AUG 1981

DM 502Α, or DM 505

Te ktronix Part No . 672-0865-00

4- 29

Maintenance-492/492P Service Vol . 1 (S N Β030000 & up) 1 . Prelimin ary α. Test equipment setup is shown in Fig . 4-21 . Remove an d install the Center Frequency Co ntrol board on an extender board.

b. Switch POWER on and set the FREQ SPAN/DI V to

1 MHz.

ε. Switch POWER on, then check the internal regulate d voltages (+12 V, ±0 .4 V, at C2201 ; -12 V, ±0 .4 V, at C2202; and +5 .2 V, ±0 .25 V, at ΤΡ 1018). 3. Check Tune Linea rity ΝΟΤΕ This check should only be used to verify linearity of previously calibrated assemblies. if varactor CR 1075 has been replaced, go to Step 4, Coarse Linearity Adjustment.

2. Chec k Voltages

α. Set the front panel co ntrols as follows: α. C heck all input voltages at the feedthro ugh ca pacitors in t he h ousing wall . Refer to Fig . 4-22 or t he voltages printed CEN TER FREQUENCY 10 MH z on the lid. Voltage at t he swee p and tun e input lines should 100 N/DIV kHz FREQ SPA equ al 0 V ±0 .05 V with the FREQ SPAN/DIV _-100 kH z. On AUTO RESO LU TION Vertical Display 10 dB/DIV REF LEVEL -20 dB m b. Turn the POWER off. Remove the lid for the mu-metal ΤΙΜΕ/DIV AUTO h ousing assembly to gain access to internal circuitry.

R4040

0

0

0

2ND LO

DIGITAL VOLT ME TER

CEN TER FREQUENCY

CONTROL BOA RD ON EXTEN DER

DIGITAL COUNTER

TIME MARK G ENERATOR

492/492 Ρ SPE CT RUM ANA LYZ ER (on side)

3783-38(3481-33)

F ig. 4-21 . Test equipme nt setup fo r calibrating the phaselock section of the 2182 MHz Phaselocked 2nd LO.

4- 30

REV AUG 1981

Maintenance-492/492P Service Vol . 1 (SN Β030000 & up)

Fig . 4-22. L ocation of test points a n d componen ts associated with calibrating th e 14-22 MHz Phaselock circuit.

b. Apply 5 Ειs markers from α time mark generator to the RF NPUT and tune one of t h e markers to center screen . Reduce the FR E Q SPAN/DIV to 50 kHz. Adjust the REF LEVEL for α signal level of 2 to 3 di v isions .

I

c. Turn the FREQUENC Y control counterclockwise until the center freq uency stops tuning ; the n turn clockwise until α marker signal is one major divisio n from the left ed ge of the graticule. An other signal, one major division from the right edge, should also be displayed . Spacing bet w een t he left and r ight markers should be approximately eight divisions. d. N ote the spacing b etween th e left and right marker signals to the nearest 0.5 minor division . e. Turn the FREQUENCY control clock w ise, to increase center frequency, until the next marker signal is one division in from the left edge and agai n note the spacing between this marker and the marker near the right edge . f. Continue this process of tuning up in f req uenc y u ntil the center frequency sto p s tuning, noting the signal spacing at each check point .

REV AUG 1981

g . If the total spacing variation is two minor divisions or less, the linearity is satisfactory and you can p roceed to part 6 (Check Center fre quency of the 14-22 MHz Oscillator) . If the error was more than two minor divisions, contin u e with part 4 (Coarse Linearity Adjustment) .

4. Coarse L inearity Adjustment

The sha ping circuit h as α wide ra n ge of adjustment to compensate for variations in the tuning varactor characteristics . This range of adjustability, however, makes the circuit calibration tedious. This coarse adjustment procedure presets the component values to make it easier to perform the fine adjustments. α. Replace select resistors, R 2063 (Gain) with α 10 k Ω R 1070 (2nd Order Shape) with α 5 kΩ potentiometer, and R 1068 (3rd Order Shaper) with 2 k Ω p otentiometer (see Fig . 4-22). Center all potentiometers . Install α wire j umper between T1 077 and T1 075 in the normal p osition as illustrated i n Fig. 4-23 . Increase the sweep sensitivity by con n ecting α 750 Ω resistor from the 2nd LO Sweep input (at C222) to the standoff at the junction of R2063 and pin 2 of U2063 .

potentiometer,

4- 3 1

Maintenance-492/492P Service Vol . 1 (S N Β030000 & up)

Normal + 1 .7 MH z

Normal +700 kH z

Normal ju mper positio n

Normal -400 kHz

Norm al -1 .1 MHz

Normal -1 .6 MHz 3783-40

Fig . 4-23 . Ju mper position s between Τ1077 and Τ1075 versus freq uency co mpensation fo r t he 14-22 MHz Oscillator. b. App ly 1 As markers from the time mark generator to the RF NPUT. Set the Center Frequency to 10 MHz and adjust th e REF LEVEL to display th e comb of mark ers. Set the FRE Q S PAN/DIV to 100 kH z and ce nter α ma rk er on t he dis play with th e center FREQUENCY co ntr ol . R educe t he FRE Q S PAN/DIV to 50 kH z.

I

ε. Adju st t he Gain potentiometer R2063 so there is approximately one marker signal per d ivision near the display ce nte r. The 2n d LO is now being swept beyond its normal tuning ra nge ; the actual span is approximately 1 MHz/division . If the sweep linearity of the 2nd LO is satisfactory, each mark er over t he ce nter eight divisions will alig n with α g raticule li ne. d. Observe the center eight divisions of the display and adjust li nearity as follows: 1 . Adjust R1070 so th e spacings between mark e r signals are equal at the rig ht and left sides of the d isplay . Decrease the resistance if the marke r spacing on t h e right side is less than th e left and increase th e resistance if the spacing is greater on the rig ht than the left side. Adj usti ng R1070 will change the 2n d LO center frequency causi ng the cen ter ma rk e r to s hift p osition . In crease th e FRE Q S PAN/DIV to 100 kH z, recenter the mark er, then return t he SPAN/DIV to 50 kH z. 2. Dec r ease R1068 if th e spacing b etween markers at th e center of the d is play is closer than the ma rkers at the rig ht or left edge . Increase the value if the spacing at ce nter screen is wider .

4- 32

3. Adjustment of either R1070 or R1068 will affect span/div . Readjust R2063 fo r o n e marker/divisio n near t he center part of the display. 4. R epeat parts 1-3 until the best u niform signal spacing over t he cente r eight divisions of the d isplay, is obtained . e. Remove the 750 Ω resistor between the 2nd LO Sweep nput and the junction of R2063 and pin 2 of U2063 (part b of this procedure) . This completes the coarse li nearity adjustment.

I

5. F ine L inearity Adju stment α. Apply 5 As markers from the time mark ge nerator to the RF I NPUT. Center th e frequen cy of t h e 2nd LO b y switching the FREQ SPAN/DIV to 100 kH z then down to 20 kH z.

b. Center α pai r of ma rk ers on the display with the FREQUEN CY cont rol . c. Change the Vertical Display to 2 dB/DIV, FREQ SPAN(DIV to 20 kH z, and adjust the REF LEVEL fo r α signal amplitude of two to thr ee divisions. d . Adjust R2063 (Gai n) so the signals are se parated exactly six major divisions.

REV AUG 1981

Maintenance-492/492P Service Vol . 1 (S N Β030000 & up) e. Rotate the CEN TER FREQUENCY control cou ntercloc kwise u ntil the analyzer stops tu ni ng, th e n rotate the control clockwise to ce n ter α pair of markers on the dis play. Adj ust the REF LEVEL as needed . f. Note the spacing of t he mark ers to the nearest 0.5 mi nor divison. E nter this data on α graph of spacing versus marker pair num ber . g. Tune the freque ncy up to the next p ai r of markers and center on the display. N ote the spacing an d agai n plot on the graph .

h. Repeat this measurement p rocess for each suc-

cessive marker pair un til the end of the tuning ra nge is reac hed . (T his requires app roximately 38 measurements .) The finished p lot depicts the tuni ng sensitivity variation over the tuni ng range of the 2nd L O. Aberrations or ripp le in the p lot with α period of two to four points and am plitude of about one mino r division peak-to-peak a re due to discrete gain brea kpoi nts in the shaping ci r cuit . Α single la rge discontinuity (approximately 2.0 mi nor division s pea k-to-peak) ind icates α d efective shaper resistor or d iode. i. Note the mean slope of the plot . Disconnect one end of R 1070 a nd carefully measure its resistance with the digital meter. R ecord th is value on the tun ing plot . j. Increase the value of R1070 approximately 10% if the

p lot h as positive slope. Decrease the value if the slope is n egative. Record t he new value and r econn ect the

potentiometer.

k. Ma ke α new plot as outlined in parts b throug h g and compare the slope of the n ew plot agai nst the previous p lot. Interpolate or extrapolate from the two slopes and the resistance values to determine the resistance n ecessary to obtain zero average slope. Ι. If the plot is co nvex (upward curvatu re toward the ends), decrease the resistance of R 1068 . Increase the value if the curvat ure is d ownward. The procedu re for this adjustment is similar to that d escribed fo r R 1070 in parts h an d i. Change the r esista nce of R 1068 approximately 10%; then rerun the plot and i nterpolate th e resistance value until you h ave minimized curvat ure. This adjustment may affect the slope b ecause of interactio n; therefore, it may be n ecessary to repeat the adjustment of R1070 . When R1068 and R1070 are p roperly adjuste d, the tuning plot should approach α straig h t li ne with zero slope. Peak-to-pea k va riation across the plot s hould n ot exceed two minor divisions, includi ng brea kp oi nt ripple. Shape of the plot is not impor-

REV AUG 1981

ta nt if the total excursions do not exceed two mi n or divisions (p-p). An S-shaped plot is not u ncommon. m. Measu re the resistance of t he potentiomete rs for R 1068 an d R1070 and replace with standa rd value 1%, 1/8 W resistors. Do not replace R2063 at this time . β. Set the Ce nter Fr eque ncy of the 14-22 MHz Oscillator

α. Switch t he FREQ S PAN/DIV to 100 kH z or more ; t hen connect α fr equency counte r to the 18 MH z output port Ρ224.

b. Select th e j umper tap combination as shown in F ig . 4-23, so th e center frequency is within 500 kH z of 18 MH z. 7. Chec k a nd Cali brate Tun e Se nsitivity α. Set the FREQ SPAN/DIV to 100 kH z then to 0. Verify that the tu ne voltage at ΤΡ4044 on the Ce nter Fr equency Co ntrol board is 0 V, ±50 mV.

b. M easure the 14-22 MHz Oscillator freque ncy at the 18 MHz out put port (Ρ224) to the nearest 10 kH z and record t he frequency . ε. M onitor th e voltage at ΤΡ 4044 on the Ce nter Fr equency Con trol board and turn the FREQUENCY control cloc kwise until the voltage stops changing . d. Adjust the Fine Tu ne Range, R4040, on the Ce nter Frequency Control boa rd for α voltage of -9 .38 V at ΤΡ 4044 . e. Adjust the Gain resistor, R2063, on the 14-22 MH z Phaselock board so the co unter frequency is 2.25 MH z greater than t he nu mber recorded in part b. f. Remove t he potentiometer fo r R2063 an d measure its r esistance; then re place it wit h t h e nearest standa rd 1%, 1/8 W resistor.

8. Concl usion α. Replace the housi ng li d with its 14 screws .

b. Tighten the screws seque ntially, starting from th e ce nter of the lid an d progressing toward the corners to pr eve nt gaps between the lid and the hou sing . Use ca re to not strip the screws as you tighten th em .

4- 33

Maintenance-492/492P Service Vol. 1 (SN Β030000 & up) ε. Remove the exte nd er for the Center Fr equency Control board and rei nstall the board in the instrument.

d. Refer to the Calibration section to recalibrate the 2nd LO spans and identify fu nctions .

Troubleshooti ng Ai ds for th e 2182 MH z Ph aseloc ked 2 nd LO

ΝΟΤΕ If the Phaselocked 2nd LO assembly is in the instrumen t, it may be desirable to set the FREQ SPANIDI V to 100 kHz or greater so the 2nd LO is not swept or tuned.

T he d iffere nce frequen cy from the 2200 MHz Reference M ixer is am plified and fed to output port Ρ224. N ominally,

the signal at Ρ224 is 18 MH z with an approximate output level of -5 dBm into 50 Ω. T his port is co nvenie nt for monitoring the operation of t he 14-22 MHz voltage co ntrolled oscillator. When the phaselock is operating, the difference frequency exactly equals the frequency of the 14-22 MHz VCO . If the lock loop is not functioni ng properly, the diffe rence frequency signal will either disappea r completely or tune to its r ange limits at approximately 4 MH z or 32 MHz. Note th at wh e n the loop is un locked , RF leakage from the 14-22 MHz oscillator bu ffer can be seen at Ρ224, with α level of ap proximately -35 dBm. Output from th e oscillator can be mo nitored more d irectly, if d esired, at ΤΡ 2032 by using α h ig h im pedance probe with α do block. Similarly, the am plified d ifference frequency can be monitored at ΤΡ 2035 .

4- 34

Anot her check of phaselock operation ca n be made b y measuring the do voltage on the 2182 MHz tu ne li ne, at feedthroug h capacitor C2203. Nominally, this voltage is approximately -5 V when phaseloc ked. U se α FREQ SPAN/DIV of 100 kH z or greate r before ma king the measurement. If there is no d iffe rence freque ncy signal, the voltage at C2203 will be approximately 0 V . Α voltage of approximately -13 V at C2203 may ind icate loss of sign al from t h e 14-22 MH z oscillator.

N arrow-ban d noise on t h e 2nd LO signal may be due to noise modulation of the 14-22 MH z V CO . M onitor the signal at Ρ224 to see if the 14-22 MH z oscillator is noisy. Noise on this oscillator is ofte n caused by noise on the + or - 12 volt supplies . U se α d iffe rential oscilloscope, with 1 Hz to 300 H z b andwidth limits to check su pply noise. M easure the ac d ifferential between t h e su pp ly and t he 2nd LO housi ng. Less than 5 ,ιV ρ-ρ n oise is typical, while 50 μV ρ-ρ of noise will cause noticeable performa nce degradation. Outpu t noise from t he s h ap er, at the junction of R1067 and R 1068, is ty pically less th an 5 μV ρ-p .. Tuning problems may be caused by defective operational amplifiers in the shaper. When t he voltages on t he sweep and t une li nes are 0 V (i .e ., span/div of 100 kH z or greater), there should b e 0 V at pin 6 of U 2063 and p ins 1 and 7 of U1062 . Wh en mak ing power measurements of microwave circuits at circuit board interfaces, use α coaxial probe with very little stray indu ctance (see Fig . 4-20). Ground the outer condu cto r of the probe to the ci rcuit h ousi ng within α few tenths of an inch of the measureme nt point. Disco nnect other ci rcuit loads from the meas ur ement point.

REV AUG 1981

Maintenance-492/492P Service Vol. 1 (SN Β030000 & up)

MIC ROCO MPUTER SYST EM MAI NT EN A NC E p roblems t hat do n ot sh ow up in t h e first mo d e, b ut p reve n t n ormal inst rument ope ration b eca u se of α b reakdown in

Several mainte n a n ce ai d s are b uilt i nto t he microcom p ute r system . T h ese are microcomputer operati ng mod es th at d emon strate correct performance o r indicate the locatio n of α pro b lem, if any.

commu n ication .

Some notes on operation of several versio n s of i n strume nt firmware conclu d e th e d iscussion of microcompute r system mainten ance .

Switch es that set up two of t hese test modes are desc ribe d first, followe d b y i n structions for th e t hree test modes. In t h e first mode, the microcomputer executes α self-test that verifies, i n so far as possible, correct operatio n . RA M , R OM, a nd interface ada pters a re ch eck e d ; any failure foun d is indicated .

Memory Board O p tio n Switc h

S1033 on t h e M emory boa rd informs th e mic r ocom pute r w h et her to configure itself at power-up for sever al test modes, for instrument modifications, and for Option 08 . Fig-

T h e second mode h ardwires t he microcprocessor to exec ute an i n struction th at toggles the address bu s; th is mode requires less of th e system to ru n, so may be used to tro ub les h oot problems t h at disa b le th e first mo d e.

u re 4-24 shows t he correct setting of th e in dividual switc hes

in S1033 .

T h e microcomp u ter reads t h ese switc h es only at powerup . For α c h ange i n α switc h positio n to take effect, t he in st ru men t mu st be powered-up afte r t h e switch is c h a nged.

Th e th i rd mode gets at commu nicatio n between th e micr ocom p uter a nd t he rest of t he in strumen t. Th e microcom puter exercises t h e instrument bu s to h el p isolate

00 = N o rmal oper atio n .

01 = Power-up sel f test.

10 = N ot defined. 11 =

OFF

ι

Ope n (1) f or Front Panel board 670-ΧΧΧΧ-00, closed (0) for subse qu e nt boa rds.

ι

(open) = 1

In strum en t bu s chec k.

O p en f or O ptio n 8

ΟΝ (closed ) = 0 all switches a re i n th e closed (0) position exce pt as follows: #1 Open (1) position for Option 08 . F o r n o rmal o p e ration ,

#4 Open (1) fo r 492 Ρ to ca u se

powe r on SR O . I n stru me nts shi pped with

#4 closed (0) .

#5 Open (1) fo r 492Ρ to ca use i n st rum e nt to re port settin gs (no wave forms) in TALK O NLY mo d e. I n st rum e n t sh i pp e d with #5 closed (0) so both settings and waveform s are sent in TA LK O NL Y mo d e. 2 m-74Β

Fig. 4-24 . T he Memory b oard optio n switch ba nd S1033.

REV AU G 1981

4-35

Maintenance-492/492P Service Vol . 1 (SN Β030000 & up)

Power-Up Self-Test Mo d e The microcom puter enters α self-test mode when t he instrument is turned on if th is mode is selected (Fig . 4-24). In this mode, the instrume nt does n ot operate normally . The microcomputer performs the following steps, stop ping the test to indicate t h e source of any problem found by blin king an LE D on the Processor board. Addr esses are specified as h exadecimal nu mbers in this

description .

Step 1 . At power-up, the microcomputer vectors to the self-test in t he ROM at the to p of address space U 2028 on the Memory board . The microcom pute r first verifies the chec ksum of U 2028 . If the routine for this step run s, but does not obtain t he correct checksu m for the R OM, the routine halts and blinks the ROM 8 LE D, DS1044 . This step u ses only U 2028 and no ot her memory ; so if the test, d oes not blink t he LE D and does not p roceed to step 2, U 2028 is probably the culp rit. Consi der first, h owever, that the correct ROM must b e installed, bot h ph ases of the cloc k on the Processor board must be present, and the microcomputer system (exclusive of the instrument bus or GPI B) must be operating correctly. If in doubt about the 6800 microprocessor, its bu s, or the microcomputer b us, skip to the instructions under M icrocomputer Test M ode, to exercise the microcom pu ter in α more simple manner. Step 2. The microcom pute r n ext chec ks the conditio n of RAM . This step does n ot rely on the RAM being o k to execute. The proced ure is : the microcomputer loads the bit p atte rn 01010101 into α RAM location, reads the locatio n, and compares what is retur ned to what was stored. The microcom puter then repeats this test with the pattern 10101010 . The microcom puter attempts to test all RAM add resses . If it finds an error on the M emory b oard, it stops the test and pulses the RAM LE D, DS1042-once for an error in 02035, twice for an error in U 2032, and t h ree times fo r an error in both RAM IC's ; these IC's are on the M emory board . If the microcomputer finds an error on the GPI B board , it pu lses the LE D 7, 8, or 9 times in α similar manner fo r low RA M-01046 and U1037-or 9, 10, or 11 times for h ig h RAM-01042 and U1032 . The microcom puter co ntinues to repeat the number of p ulses after an error is found. Step 3. The microcom pu ter proceeds to chec ksum all the R OMs. Α c hec ksum is stored in the header of each ROM . This is compared to α chec k sum formed by the successive 8- bit sum of each byte in the ROM starting at the fo urt h location in the ROM. The upper eight bits of the ROM's

436

address (stored at the fi rst location) are also added to the c h ecksum. Thus, if α ROM is installed in the wrong socket, it's checksum does n ot verify . The ROM sockets, including those on the GPI B boar d, are chec ked starting at the lowest address (01012 on the Memory board) . The c hec k starts b y looking at the M SB i n t he first and fourth locations in t he ROM's address range. If bot h bits are one, it is assume d t hat no ROM is installed. Wh en α defective ROM is found, the routine d isco ntinues the test and pulses repeatedly the ROM LE D, DS1038, to indicate t he ROM socket where an error was fo und : ROM Socket

B oa rd

Pu lses

01012 01017 01023 U 1028 U 2012 U 2019 02025 02031 U 3012 U 3019 U 3025 03019 U 2012 U 2017 U 2023 02028

Memory Memory M emory M emory

1 2 3 4 6 7 8 9 10 11 12 13 14 15 16 17

GPIB GPIB GPIB GPIB GPIB GPIB GΡΙΒ GPI B M emory M emory M emory M emory

If this step fails, it can be forced to continu e ch ec king ROMs; just tu rn power off and unplug the d efective R OM, then turn power on to restart the self-test. Step 4. The microcomputer chec ks part of the instrume nt bus ΡΙΑ, U 3016 on the Processor board . F irst the microcom puter writes to the Α control register and then reads bac k from the register . N ext it re peats these operations wit h the Α data direction register . If either of these attempts fail, the routine stops and pulses the b us LE D, DS1036 . Step 5. This step checks part of the GPIA, U 2047 on the GPIB board (if installed). The microcom pu te r resets the GPIA an d c hecks to see that the GPIA is not addressed to talk or listen. The GPIA is th en set to listen-only mode an d chec ked to see that it is addressed to listen . Then the GPIA is set to talk-only mode and checked to see that it is addressed to talk. If any part of th is step fails, the test stops and pu lses re peatedly t h e GPIB LED, DS1034 .

REV A UG 1981

Maintenance-492/492P Service Vol . 1 (S N Β030000 & up) If the test completes successfully, the microcom puter pulses re peatedly the OK LE D, DS1032, to indicate the number of em pty memo ry bloc ks fo und. The LE D b li nks Ν +1 times, where Ν is the nu mber of empty R OM soc kets (the memory b lock 1600-1800 is not used). If the GPIB board is not installed, its eight ROM sockets are counted as empty. If the LE D b li nks more than Ν +1 times, α R OM (o r ROMs) failed to respond in Step 3; look for α possible p ro blem on the chip-select line or on th e MS B (bit 7) d ata li ne. If th e microcom pu te r seems to test ok, b ut does not co ntrol the instrume nt, s kip to th e Inst ru ment B us Chec k, where microcom pu te r communication with t he rest of the instrume nt is exercised .

Mic rocom puter Test Mode Α microcom puter test mode is selected by moving ju mper P1 020 on the Processor board to the TEST positio n. Th is hardwires the 6800 d ata li nes to h ex 5F. As α result, t h e 6800 co nti nuo usly executes α CLRB instructio n, repetitively cycling thro ugh all of its address space. Th e in strument does not fun ctio n n t his mode . Rather it sets up α known pattern on the microcomputer address, d ata, an d control li nes and at the output of add ress decoder s . This mode allows an attack on problems th at prevent the microcom puter from running its self-test chec k.

i

ΝΟΤΕ If CR2025 on th e Processor board is missing, it may be added as shown on the Processor diagram to ma ke the correct instruction on the data fines.

Fig . 4-25 . Α15 thr oug h Α 12 in microcompute r test mo de. be evident only while that d evice is addressed; compare α problem that occurs only during α portion of the Α15 cycle to the add ress decode r outputs p ictured below .

Pr ocesso r Address Deco ders. Address decoder U 2044 on the Processor board sets its outputs low in turn to access b lock of memory space. See F ig . 4-26, where the YO thro ugh Υ2 outputs are com pared to Α15 . Th e ot h er ou tputs follow i n se que nce with simila r pu lse widths. The selftest i nd icators conn ected to the d ecoder outputs b li nk i n sequence as the microcom pu ter cycles throug h its add ress space.

M ic rocom pu te r Bus. As the microcom puter cycles through its address space, it toggles the address lines. The MSB, Α15, h as α period of about 1540 ms ; t he period of All 4 through AO is divided by two from t h e li n e above down to the LSB, AO, with α period of about 4.7 As . The fo u r h ig horder lines, All 5 thro ug h All 2, are shown in Fig . 4-25 . Ig nore the narrow pulses th at may be evident during the low p ortio n of eac h cycle . The d ata lines on the microp rocessor side of U 1013 on th e Processor b oa rd a re static ; D7 and D5 are low, the othe rs are h ig h. In the TEST p osition, Ρ1020 disables U 1013 . On the other side of this b uffer, the data li nes are bei ng driven by the various memory d evices on t h e bus as th ey are add ressed . U2044-Υ2 Examining the data lines ca n locate shorted or open li nes-lines inactive at h ig h, low, or in-between states or changing in unison, usually to indetermi n ate logic levels of +1 to +2 V . Α problem related to α partic ular d evice may

REV AUG 1981

ίι

2727-76Α

Fig . 4-26 .

A15 and YO thr ough Υ2 of address d ecoder U2044.

4- 3 7

Maintenance-492/492P Service Vol . 1 (SN Β030000 & up) Α portion of one address b lock , decod e d by U 2044, is f u rt he r decoded by U1 037B . F igu re 4-27 s h ows t he U1 037B e n able li n e on to p and below it in rder, YO th rough Υ2. Υ3 is similar in width and follows in se q ue nce .

o

o

T he n a rrow pulses evi d ent duri n g t he time eac h u tput of U2044 a n d U 1037 B is asserted resu lt from address lines toggli n g between microcomp uter cycles .

Cloc ks and Cont rol L i nes . T h e 6800 cloc k lines are complementary, n on overlapping square waves wit h periods of abo ut 1 .17 As . VM A, RESET, ΝΜΙ, and R/W s h ou l d be h ig h (logic one) . I R O may b e eit her h ig h r low, de pending on h ow assem b lies on t h e in s ru ment bus p owered up .

o

M emory Add ress Decod e rs. Add ress decod ers U 1036 and U 1038 on t h e M emory board set th eir o utputs low to access b lock s of ROM ad dresses. Th ese out p uts are s h ow n in relatio n to Α15 in Fig . 4-25 . T he RAM (02035 and 02032) chi p-select li nes a nd ption switch register (01033) en able line a re also decoded on th e M emory board as sh own in p art d of Fig . 4-28 . T he narrow pulses whic h may be evi d e n t dur ing t h e time each ut pu t is asserted can be igno red for t he reason noted a bove un d er Processor Address Decod ers.

Fig . 4-27 . U 1037Β.

Enable a nd

YO t hro ugh Υ2 of address d eco der

o

o

GP I B B oard A ddress Decod er s. Address decoder 01021 on t h e GP I B board sets its out p uts low i n sequence while t h e 492Ρ is o p erating i n th e microcompu ter test mode. YO throug h Υ2 a re sh own i n relation to Α15 in F ig . 4-29 . Alt ho ugh not shown, Υ3 th roug h Υ7 are asserted i n order with th e same p ulse wi d t h . U 1028 furt her decodes two add ress d ecoder sign als from t h e Processo r board . On e ena b le a nd two outpu t sign als are s h ow n in F ig . 4-30 . T h e ot h e r outp ut, ASR , is n ot shown, but loo ks t he same as P G S: they appea r to be as serted at t h e same time . Th ese two sig n als can be compared fo r correct operation by s peed i ng up the sweep and n oting th at t h ey toggle in α com p lementary fashion du ri n g t he time t hey a ppea r to b e low in t he figu re.

Bu s Ch eck Mod e If t he microcompute r perfo rms th e power-up self-test, b u t fails to con trol th e in stru ment properly, th e inst ru ment b us c h eck may u n cover the pro b lem. Th e i n strument bu s chec k mode may be selected by settin g t he option switch as s how n i n Fig . 4-24 . In th is mode, th e microcom pu ter conti n uou sly writes to th e instrumen t b us to exe r cise it i n α repetitive manner . Conse q uently, t h e instrument does not

T h e p attern on th e instr u me n t bus toggles DATA VA LID an d POLL and exercises the address and data li n es at separate times. Th e address lines change wh en DATA VAL ID is low and th e d ata lines c h a nge wh e n DATA VALID is h ig h . T here may be an exception on DB 4 th rough BO; th ese lines may continue to ch ange after DATA VAL ID goes low if an assem b ly on t h e bu s is requ estin g service because of the way it powered up . In th is case, an assembly or assem blies may respo nd to th e h ig h state of P OLL a nd t he c han gi n g state of ΑΒ 7 a nd attem pt to report status .

D

Th e pattern for the u pper address an d data lines is sh own i n Fig . 4-31 . E ach lower o rd er li n e ch anges at α rate t hat is twice th e n ext h ig h er line, res ulti n g i n 128 cycles on t he L S B lines . Th e initial p u lse on t h e u pper fou r d ata li nes is not part of t h e divi de- by-two pattern a nd is not repeate d on t he lowe r four data lines. By com paring t he li n es to t hose i n Fig . 4-31, c hec k i ng t hat they d ivide-by-two, it is possi b le to discover open or shorted li n es . Look fo r lines that stay h ig h or low, c hange toget her or at wrong times in th e p attern, or go to in d etermi n ate logic levels (-1 to -2 V) .

Instru ment

operate normally .

4- 38

Firmwa re Op erati n g N otes Th e followi n g a re exce ption s to n ormal i nstrumen t operation t h at relate to t he differe n t fi rmware versions. The inst rument d is p lays its versio n n umber du ring power-up for about two secon d s. To see th e message, tu rn power off then on ; th e version message will ap pear at t he u pper center of th e sc ree n .

REV A U G 1981

Maintenance-492/492P Service Vol. 1 (SN Β030000 & up)

Β. Α15, U1036 out put Υ6, and U1038 outputs Υ4 and Υ5.

5Υ

C. Α15 a nd U1038 outputs Υ6 an d Υ7.

Fig. 4-28 .

5Ν

100S .

D. Α15, R AM ch ip-select, and option switch en able li nes. 2727-78Α

A15 and Memory board address decoder ou tpu ts.

1 . The external M ixer bias is tu rned off for bands 1 thro ugh 5 wh e neve r freque ncy span o r band is changed; however, the indicator remains lit. If an external mixe r is used for t hese band s, EXT ERNAL MIX ER must b e ca ncelled and t hen reactivated after every FREQUEN CY SPAN/DIV or b and change .

3. The REFERENCE LEVEL may hang up above +30 dBm in the AA mo de. For example: with α REFERENCE LEVEL of +30 dBm in MIN DISTO RTION mode, select AA mode and increase the REF LEVEL for α readout of +1 .00 dBm, then switch o ut of AA mode by cancelling F INE . The analyzer will not respond now to changes of REF LEVEL. N ormal operation can be restored by selecting either 10 dB /DIV, L IN, MIN N OISE or E XT ERNAL M IX ER .

2. The microcom puter may n ot maintai n α cali brated display when AUTO RE SOLU TION and AU TO ΤΙΜΕ/DIV a re selected if α WIDE or N ARR OW VID EO FI LTER is also selected . This is evident when t he UN CA L indicato r lights. Ch a nge the RE SO LU TION BANDWIDTH o r increase ΤΙΜΕ/DIV (if not set to AUTO) for α cali br ated display.

4. The inp ut attenuator may not set to 60 dB on powerup, even though the RF ΑΤΤΕΝ readout shows 60 dB . The attenuator is correctly set, however, when the REFERENCE LEVEL is changed an d it now matc hes the readout.

E xceptions fo r Firmware Version 8.2

@ AUG 1981

4- 39

Maintenance-492/492P Service Vol . 1 (S N Β030000 & up)

Fig . 4-29 . Α15 and YO through Υ2 of address d ecoder U 1021 on t he GPIB boa rd .

Fig. 4-30 . One enable and outputs L ORAM, H IRAM, and GPS of address d ecoder U 1028 on t he GPIB boa rd .

E xceptions for F irmware Versions 8.2, 8.7, an d 8.8 1 . EXT ERNAL M IX ER c hanges (on or off) ca use the microcomp uter to restore the vi deo filter that was in at the last frequency range change . The front-panel V ID EO F I LTER indicato rs will not ind icate this change if one is made. To ensu re that the desired filter is activated, afte r c hangi ng EXT ERNAL M IX ER selection, reselect the desired filter. 2 . An erro r 57 message may be d is playe d when the FREQ SPAN/DIV is 2 kH z or less and t he FREQUENCY is tun ed to the end of the 2nd LO ra nge (the 2nd LO frequency is tuned for narrow spans) . To validate an erro r 57 message in narrow spans, tune the FREQUENCY in t he opposite direction at least five turns. If the message remains, it indicates α hardware fail ure .

4- 40

Fig. 4-31 . Inst rume nt bu s chec k.

E xceptions fo r Version 1 .1 in the 492P only

1 . The sense of the parallel poll is reversed when t he 492Ρ responds to p arallel poll .

2. The E XT MXR response is not omitted in the SET query res ponse for Option 08 instruments. As α result, t h e instrume nt re ports an error and does not execute the SET q uery response . Recommend removing the EXTMXR message u n it before t r a n smitting th e SET query response to an Option 08 instrument.

@ AUG 1981

Maintenance-492/492P Service Vol . 1 (S N Β030000 & up)

Exceptio ns for Versions 1 .1 and 1 .2 in the 492Ρ

o nly

The INC and DEC arguments fo r the TIME command do n ot operate if the d is play is uncali brated (UNCAL indicator lit) . Also, if 0 or α negative nu mber is u sed as an argument for the TIME command , no error will be reported and t he command is not executed.

Changes inco rp orated in Version 1 .2 fi rmware:

1 . ΙΝΙΤ resets the display data pointer to its power-up value: 500,225.

2. Pressi ng RE SET TO LOCA L while α message, including α REPEAT command, is executing, limits message executio n to 256 times, if the message contains WAIT. Α SIGS WP command preceding WAIT in the message is ignored afte r RE S ET TO LOCAL button is presse d. The REPEAT loop, t herefore, completes faster. 3. T he command DELFR OFF is inserted after FI NE O FF at the beginning of SET qu ery respo nse . The DELFR response is also sent after the FREQ response. These changes remove the uncertai nty in how the SET query is executed with various comb inations of instrument settings .

TROUBLE S HOOTI NG ON THE I NSTRUMENT BU S I n stru ment Bu s Data Transfers

The 492Ρ can execute two commands a nd q ueries to ai d t roubleshooti ng of circ uit fun ctions that are interfaced to the inst rument bus . These functions are co nfigured by data se nt from the microcomputer or respond with data fo r the microcomputer; in either case, the data is transferred over the inst rument bu s. Th e commands and queries provi ded for this pu rpose a re:

492Ρ.

Command

Query

ADDR DATA

ADDR? DATA?

Action Sets, returns add ress for DATA command Sets, returns data on 492Ρ instrument b us

B ecause the DATA command can c hange the status of intern al functions, its use may prevent normal operatio n of the U sing α 4050-Series controller, th ese commands and queries are transmitted to th e 492Ρ with the PR INT statement:

L INE

@ A UG 1981

α

PRINT

GΡΙΒ PR I MA R Y

ADDRESS

492 Ρ MESSAGE

3784-159

4-41

Maintenance-492/492P Service Vol. 1 (SN 0030000 dι up)

For t he GPIB PR IMARY ADDRE SS, enter the decimal equ ivalent of the GPIB ADDRESS switc h settings on the 492P

rear panel .

The 492 Ρ response to α qu ery is input with the INPUT statement:

Α stri ng variable is formed by adding α dollar sign ($) to α variable n ame such as Α or Χ1, mak ing: Α$ or X1$ADDR (in st rume nt bus address) command:

1 ι; ι7

0

HEX D I G I T

DI GI T

0

φ

HEX D I GI TI-~ΗΕΧ D I G I T

φ

HEX

3784-165

HEX. DIGIT: Α c haracter in the sequence 0 through 9 and Α t hrough F representi ng α hexadecimal digit. The two digits (in order) form α number to represent α location on t he instrument bus. If α character is not α hexadecimal digit or part of α pai r of d igits, it is n ot used in executing the ADDR command and an er ror is reported. ADDR (instrument bu s address) query:

3784186

Response to ADDR query:

HEX D I G I T

HEX D I G I T 3784-167

442

@ AU G 1981

Maintenance-492/492P Service Vol. 1 (SN Β030000 & up) The two digits form the hex . address that ap plies to succeedi ng DATA commands or q ueries. DATA (i nstrument bus d ata) comman d :

HEX. DIGITS : As with ADD R, α p air of digits forms α hex . number. The nu mber is α data value to be stored at the instru ment bus location specified by the last ADDR command. Th is allows inte rnal 492Ρ parameters to be set fo r servicing; these parameters control f unctio n s b y setting the status or mode of 492Ρ circuit assemblies . Up to 16 p ai rs of characters are accepted to set α functio n to α new value repeatedly. If α character is n ot α hex. digit or part of α pair of d igits, the data byte formed by t h e pair is n ot execute d a nd an error is reported. Also, an error is reported when data is sent to an invali d a ddress. DATA (instrument b us data) query:

Response to DATA query :

HEX

DI GI T

HEX

DI GI T

3784-163 Combined ADDR command

@ A UG 1981

a nd DATA command:

4-43

Maintenance-492/492P Service Vol . 1 (SN Β030000 & up) The address command may precede α data command or query to identify the instrument b us location as part of the same message. Errors related to ADDR and DATA commands :

E rror 41 42 Instrument Bus Registers

Registers provide the link between t he instrument bus and microcomputer-controlled functions. The registers are defined here in order according to the number of the diagram where the register appears. The d efinitions are provided to h elp in constructing DATA commands (see above) and interpreting responses to DATA queries. The d ata is presented here as binary. In some cases the data occupies the entire register width, as does α value in digital storage, for instance. In other cases, α single b it or group of b its in the register con veys α code . The upper five bits in the sweep rate and mode register indicate the sweep time/division, for instance . The meaning of the d ata is not fully defined h ere ; refer to the description of the circuit module in Section 5 for details. To use the b inary data and codes presented h ere with

the DATA command and query presented above, you must convert binary to h exadecimal . This takes three steps:

1) group the lower four bits and t he upper four bits (break the data b yte in h alf) ; 2) convert each g roup of four b its to α hex . digit. Hex . digits range from 0 to F in t his sequence : 0123456789ABCDEF ;

3) group the two hex . digits together, k eeping their respective p laces-upper and lower.

F or example, binary code 01001011 would be trans-

formed by :

1) 01001011 = 0100 1011 2) 0100 = 4 and 1011 = Β (8+0+2+1 =13) 3) 4 and Β make the two-digit h ex . number 4Β. Variable Resolution Mother Board #2 (refer to diagram 19). There are two variable resolution registers that the microcomputer writes to, although both a re addressed at 3F (see Table 4-5) . The d ata M SB steers the other bits that are d efined into the desired register . When DB7 equals 1, it steers DBO through DB2 to select the resolution

4-44

ADDR a nd DATA COMMAND ADDR/DATA argument invalid ADDR not compatible for DATA command bandwidth. When DB7 equals 0, it steers DB6 through DBO to select the amount of gain added in t he VR section and the band-leveling gain (gain adjustment related to front-end response in each band). These two functions are addressed and set together b y the same data byte, although t hey are broken into two portions of the table below to show the portions of the data byte that form the codes for t he two functions.

Table 4-5 VARIABLE RESOLUTION DATA REGISTER (3F) Resolution Bandwidth DB7=1 DB7

DB2

DB1

1 1 1 1 1 1

0 0 0 0 1 1

0

Ι

DBO

Selects

1

1 MHz 100 kHz 10 kHz 1 kHz 100 Hz F or future use

J ___6__

1 0 0 1

1 1 1 0

Ι

Gain, Leveling DB7=0

Leveling

DB7

DB6

DB5

DB4

DB3

0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 1 1

0 1 0 1 0 1 0 1 0 1

0 0 1 1 0 0 1 1 0 0

0 0 0 0 1 1 1 1 0 0

DB7

DB2

DB1

DBO

Gain

0 0 0 0 0

0 0 1 1 1

0 0 0 0 1

0 1 0 1 1

OdB 10 dB 20dB 30dB 40 dB

B and 1 B and 2 B and 3 B and 4 B and 5 Band 6 Band 7 Band 8 Band 9 Ι Band 10

@ AUG 1981

Maintenance-492/492P Service Vol . 1 (SN Β030000 & up)

L og and Video Am plifier (refer to diagram 22). Two registe rs receive data from t h e microcomputer (see Ta ble 4-6) ; one controls vi deo offset (78) and the ot her co ntrols d isplay modes and vertical scale factor (79) . Ta ble 4-6 LOG & VID EO AMP RE GISTER S (78 AND 79)

Bit

Functio n/Mode

Digital Storage (refer to diag ram 24). Two registers (at 7Α an d FA) on th e Vertical Digital Storage board transfer display data to and from the microcom pu ter for 492 Ρ GPIB operations . Anot her register (at 7Β) controls digital storage fu nctions (see Table 4-8) .

Ta ble 4-8 DIGITAL STORAG E RE GIST ER S (7A, FA, AND 7B)

Video Offset (78)

L SB = 1/4 dB, total range = 63 .75 dB

DB 7-DBO

Functio n

V ideo offset,

Modes and Scale F actor (79)

Digital Storage Input (7Α) Data values fo r digital storage. Α write to 7Β clears the address counte r so values are stored for points on display starting at left and proceeding to right in order.

DB 7-DBO

P ulse stretcher on/off (1 /0)

DB 7 DB 6

Identify offset on/off (1/0)

DB5

DB4

0 1 0

1 0 0

Digital Storage Output (FA)

Full-screen deflection

Digital Storage Co ntrol (7Β)

Log vertical scale factor in dB/div

Video Processor (refer to diagram 23). Α register (7C) co ntrols out-of-band clampi ng, video filtering, and leveli ng (see Table 4-7) . Table 4-7 VID EO PR OC ESSOR CO NTROL (7C)

Bit

Function

DB 5

DB6

DB7

Out-of-Band Clamp

1 1 1 0

1 0 1 1

0 0 1 0

No clamp Clam p upper 5 div Clam p lower div Clamp lowe r 5 div

DB4

DB3

DB2

DB1

V ideo

0 0 1 1 0 1 1

0 0 0 1 0 0 1

0 0 0 0 1 1 1

0 1 1 1 1 1 1

Off 30 kH z 3 kH z 300 H z 30 H z 3 Ητ 0.3 H z

DBO

Data values from digital storage. Α write to 7Β initializes output to begin at left of trace an d proceed to rig ht.

DB7-DBO

Lin Log

DB 3-DBO

@ AUG 1981

B it

DB6

DB7

1 1 0

DB5 1 0 1

DB 4 DB3 DB2 DB 1 DBO

H alt/ru n (0/1) storage acqu isition PEAK/AVERAGE cursor Kn ob positio n PEAK AVERAG E MAX H OLD on/off (1/0) VI EW Β -Α on/off (1 /0) V IEW Β on/off (1/0) V IEW Α on/off (1/0) SAVE Α on/off (1 /0)

Filter

B ase-li n e Leveling on/off (1 /0)

4-45

Maintenance-492/492P Service Vol . 1 (SN 13030000 & up) Ζ-Axis/ RF Interface (refer to d iagram 27). Α register on the Ζ-Axis/ RF nterface board enables Z-axis and RF attenu ator control (see Table 4-9) .

Crt Rea dout (refer to diag ram 29). One register (5F) controls crt readout and data steeri ng. Another register (2F) acce pts d ata from the microcom puter (see Ta ble 4-10).

Ta ble 4-9 Z-AXIS AND RF DECK CO NTROL (4F) B it Functio n

Table 4-10 CRT READOUT RE GIST ER S (5 F AN D 2F)

I

B aseline clippe r on/off (1/0)

DB 7 DB 6

13132

DBO

1 1 0 1 1 0 1

1 1 1 0 0 0 1

1 0 1 1 0 1 1

DB 5 DB4 DB3

RF atte nu atio n Od B 10 dB 20 dB 30 dB 40 dB 50 dB 60 dB 1 = 829 MHz 2nd Co nverter 0 = 2 GHz 2nd Converter 1 = ΕΧΤ M IX ER 0 = RF NPUT Set to 0 for 100 ms to switch atte nu ator

I

B it

Crt Cont r ol (5 F) DB3 DB2 D B1 DBO

1 = max span dot 0 = center freque ncy d ot 1 = error or GPI B RDO UT message (page 2) 0 = normal readout (page 1) 1 = data se nt to 2F is character address 0 = data sent to 2F is character co de 1 = readout on 0 = readout off-requ ired to load c haracters Ad dr ess/Data (2F)

DB1 DB 6-DBO DB1 13137 DB6 DB 5-D B O

4- 46

Function

in 5 F = 1 Address in readout RAM. Up per line is 0-31 . Lower li ne is 32-63 (page of R AM selected by DB2 at address 5F) in 5 F = 0 1 b lank s character (used for space) 1 s hifts character down 1/2 screen (used for upper readout only) L ower 6 b its of ASCII code for character

Οα AUG 1981

Maintenance-492/492P Service Vol . 1 (SN Β030000 & up) Front P anel (refer to d iagram 30). Writing to register 74 loads d ata into shift registers that drive all the lights on the front panel, including the one for t he crt graticule (see Table 4-11). F our 8-bit shift registers store the data, requiring eight writes of four bits each time (one bit for each register) to update the front-panel lights . The table below shows the order t hat data is entered to control the lights . Α 0 turns on the light (except in t he case of the crt graticule) ; α 1 turns off the light. Reading from F4 accesses the k eyboard encoder and t he FREQUENCY knob encoder . Table 4-11 FRONT-PANEL REGISTERS Write

D B4

Num be r

DB2

DBO

DB 1

Writi ng data to sh ift registers fo r lig hts (74)

1

MAX HOLD

ZERO SPAN

2

CLIP

REMOTE

3

ADDRESSED

10 d Β

4

READOUT

20 dB

5

AF

FINE

LIN

READY

N ARROW

LINE

WIDE

IDENTIFY

SINGLE SWEEP

Β -SAVE Α

EXTR

MIN NOISE

FREE RUN

VIEW Β

AUTO RESOLUΤΙΟΝ

PHASE LOCK

ΙΝΤ RUN

V IEW Α

PULSE STRETCHER

UNCAL

ΕΧΤ TRIG

6

M IXER

7

8

I

GRAT LLUM

CAL

T RIG

SAVE Α

Α 1 on DΒ3 initializes encoder (power-up)

Bit Reading DΒ7 D136-DI3O

Functions

d ata from switch e ncoders (F4) Ι FREQUENCY down/up (1/0) Ι Switch codes (see Table 5-χχ)

Sweep (refer to diagram 33). T he microcomputer writes to two registers (OF and 1 F) to control sweep rate, mode, h oldoff, interrupts and triggering (see Table 4-12). Table 4-12 SWEEP REGISTERS DB6

DB7

DB4

DB3

Time/Div

Sweep Rate and Mode (OF) 1 1 1 0 0 0 1 1

1 0 0 1 0 0 1 0

0 1 0 0 1 0 0 1

0

1

0

1

0

0 0 1 1 1 0 0 0 1 0

0 0 1 0 0 1 0 0 1 1

0

1 0 0 1 0 0 1 0 1 1

1 1 1 1 1 1 0 0

1 1 1 1 1 1 1 1

20 μs 50 As 10011s 200 As 500 μs 1ms 2 ms 5 ms

0

1

20 ms

0

1

0 0 0 0 0 0 0 0 1 1

1 1 0 0 0 0 0 0 1 1

10 ms

50 ms 100 ms 200 ms 500 ms 1s 2s 5s 10s Manual External

Α 1 οη 13132 sets single-sweep mode Α 1 on DBO sets trigger in single-sweep mode

Bit

Function Holdoff, Interrupt, Trigger ( I F) 1 enables end-of-sweep interrupt

DB7 `DB6

DB5

ο 0 1

ο 1 0

DB4

DB3

0 0 1 1

0 1 0 1 DBO

(gl AUG 1981

DB5

Sweep Holdoff

s hort

Medium

Long

Trigger M ode

Free run Internal E xternal Line

Aborts sweep

4-47

Maintenance-492/492P Service Vol . 1 (S N Β030000 & up) Span Attenu atoι (refer to diagram 35). Two registers (75 and 76) co ntrol the span atte nu ator (see Table 4-13). Ta ble 4-13 SPAN ATTENUATOR RE GIST ER S (75 AND 76)

B it

1st LO Driver (refer to d iagram 36). One register (72) controls functions on the 1 st LO Driver board . Anot h er register (7 Ε) is added for th e 492Ρ to ma ke the PEAKING control p rogrammable (see Table 4-14).

Function Span Magnitud e (75)

DB7-DBO ~

Lower 8 bits of 10-bit attenu ation code (000 is max atte n uatio n)

Span Mag n itude a nd Attenuator (76) Sweep ± (1 /0) to match ± mixing

DB7

1 st Bit DB7 DB6

DB5

Sweep d ecade attenuator

DB5 DB4

0 0 1

0 1 0

Χ 1 .0 Χ 0.1 Χ 0.01

DB3

DB4

DB3

Output select and cali bration

0 0 1

0 1 0

1 st LO main coil 1st LO FM coil 2nd LO

DB1-DBO

For futu re use Upper two bits of attenuation code

Functio n 1st L O Driver Functions (72)

DB6

DB2

Table 4-14

L O DRIVER REGISTERS (72 AND 7E)

N ormal/max span mode (1/0) Connect/ disconnect swee p voltage to driver (1/0) Driver off/on (1/0)-off fo r degauss F ilter on/off at d river output (1/0)-on for unphase-locked narrow spans External mixer disconn ect/co nnect (1/0) ; connected in band s 1-5 if external mixer selected ; always con n ecte d in hig her bands

DB 2

DB1

DB O

Internal M ixer B ias for

1 1 1 1 0 1

1 1 1 0 1 1

0 0 0 1 1 1

B and 1 B and 2 B and 3 B and 4 B an d 5

Selects no internal mixer b ias

PE AKING Co ntrol (7 Ε) DB7 DB6 DB5-DBO

4-48

0 steers DB4-DBO to upper latch 0 steers DB5-DBO to lower latch 1 sent to DB4 of up per latch disa bles front- panel PE AKING control ; DB3-DBO of upper latch and DB5-DBO of lower latc h form 10-bit input to DAC for programma ble PE AKING voltage

@ AUG 1981

Maintenance-492/49212 Service Vol . 1 (S N 13030000 & up) Preselecto r Driver (refer to d iagram 37). Α register (77) controls functions on the Preselector Driver (see Ta ble 415). Α single bit, DB3, responds on the data bus to indicate the boa rd is installed when t he microcom puter performs α read at F7. Ta ble 4-15 PRES ELECTOR DRIVER CO NTROL (77) Functio n

Bit DB7

DB6

0 1 0

1 0 0

829 MHz offset - conversion + conversion 829 MH z IF not used Driver output filter on/off (1/0); on for narrow spans LPF/preselecto r switch (0/1) 1st LO FM coil n ot-swept/swept (1/0) Driver on/off (1/0)-off for degauss 3 rd /1st h armonic 1st LO co nversion (1/0)

D135 DB4 DB3 DB2 DBO

Ce nte r Frequency Co ntrol (refer to diag ram 39). Registers are provided for control fu nctions (70) and data values for cente r frequ ency DAC(s) (71) . Α read (FO) r etur ns the results of α com parison of the DAC output voltage and α memory voltage (see Table 4-16). Table 4-16 CENTER FREQUENCY CO NTROL RE GIST ERS (70, 71, AND FO) Function/Mea ning Co ntrol (70) DB7 DB6 DB5 DB4 DB3 DB2 13131 DBO

Ph ase L ock Co ntrol (refer to d iagram 40). Α register (73) accepts data to preload the = η counter and control the sy nthesizer. Successive reads fr om another register (F3) obtain status and coun ter outputs (see Ta ble 4-17). After resetti ng the counter outp ut register selector, three rea d cycles return stat us b its a nd co unter bits in the most significant byte an d remaining counte r bits in following bytes . Ta ble 4-17 ELOCK CO NTROL REGIST ERS (73 AND F3) PH AS

B it

Function/Mea ning

Ι

Wr ite (73) 1 cloc ks d ata on DBO into α latch

DB7 DB6 DB5 D134

0 (unused)

1 clears the co unters 1 transfers DBO serial data to cont rol latch outputs 1 resets the cou n te r o utpu t register selector For futu re use 1 transfers DB O serial d ata to synthesizer Ν latc h o utp uts Serial data for control of synthesizer Ν latches

DB3 DB2 D131 DBO

Rea d ( F3)-Most Significant Byte DB7 DB6 D B5 DB4 DB3 D132-D BO

1 = error voltage below α preset amount 1 = error voltage above α preset amount Always 1 1 when ph aseloc ked 1 when valid co unt is in counters U pper three bits of counter o utp ut; th e remaining 16 b its are in the following two bytes

1 st L O storage gate open/close (1 /0) 0 steers DAC data to 1 st LO h ig h byte 0 steers DAC d ata to 1 st LO mi d byte 0 steers DAC d ata to 1 st LO low b yte 2n d LO storage gate open/close (1/0) 0 steers DAC data to 2nd LO hig h byte 0 steers DAC data to 2n d LO mid b yte 0 steers DAC data to 2n d LO low byte DAC Data (71)

D137-D BO ~ Data for center frequency DAC(s) stee red by control register Ce n te r Freq uency Co ntrol Rea d (FO) DB7 DBO

@ AUG 1981

1st LO DAC stored voltage comparator 2nd L O DAC stored voltage comparator

4-49

Section 5-492/492Ρ Service Vol. 1 (SN Β030000 & up)

THEO RY O F O PERATION This section of the manual d escribes the circuitry in the

492/492Ρ Spectrum Analyzer. The description begins with α general and functional d escription related to α b lock diagram of the major systems within the 492/492Ρ. This is followed with α detailed description of the circuitry within each section ; for example, the Display section.

T he number in t he diamond refers to the corresponding schematic diagram number . N ote that these same numbers are included on diagrams. Schematics of all major circuits are in Volume 2, section 8.

FUNCTIO NA L A ND G ENER A L DESC RI PTIO N What It Does

T he 492/492Ρ Spectrum Analyzer accepts an electrical signal as its input and displays the signal's frequency components on α crt. Signals can be applied directly to the RF INPUT or, if the analyzer is equipped for external mixer operation, to an external mixer, which extends the measurement range of the 492/492Ρ. The display of the frequency components of the input signal appears on t he crt as α graph where the hori zontal axis is frequency and the vertical axis is amplitude. The display can also be p lotted on α chart recorder using rear-panel connectors . The 492/492 Ρ, when equipped with Option 02, can transmit the display digitally via the IEEE 488 bus. Manual operation of the 492/492Ρ Spectrum Analyzer is accomplished through the front-panel k nobs and switches . The 492Ρ may also be operated via the IEEE 488 bus using α straightforward language format.

How It Works The F unctional Block Diagram is located at the front of the Diagrams section. It relates the major sections in the instrument and shows the main signal paths . Refer to the diagram while reading this general description . The 492/492Ρ operates as α swept, narrow-band receiver . As it sweeps α r ange of frequencies, it moves the crt beam h orizontally. When it detects α frequency component of the input signal, it d eflects the beam vertically. The center

REV AUG 1981

frequency of each span is set by the FREQUENCY control. The frequency range of each s pan is set by the SPAN/DIV control. The power level represented by the vertical deflection is set by the REFERENCE LEVEL control ; this control causes the microcomputer to change the input RF atte ηuator or F gain, or both, to bring signals within t he d isplay range.

I

F irst, Second, and Third Converters In the 492/492Ρ Spectrum Analyzer, this swept-frequen-

cy analysis is achieved with α triple-conversion superheterodyne technique.

Each of the three frequency converters consists of α mixer, α local oscillator, and appropriate filters. Only one frequency can be properly converted in each mixer and pass through all bandpass filters and reach the detector. This analysis frequency can be changed simply b y changing the frequency of any of the local oscillators in the converters. The first converter, usually referred to as the front end, converts the input signal frequency to an intermediate frequency (IF) which may be either 829 MHz or 2072 MHz depending on which band is in use. Although the internal mixer covers signals from 50 kHz to 21 GHz, an external mixer may b e u sed for a nalysis through t he millimeter wavelengths (unless this capability is deleted by Option 08). If the 492/492Ρ is equipped with Option 01, α preselector and α lowpass filter attenuate unwanted signals when t he internal mixer is u sed. This prevents most images and s purious responses .

Theory of Operation-492/492P Service Vol . 1 (SN Β030000 & up)

There are actually two second converters in the 492/492Ρ; t he appropriate converter is selected automatically for each band so the input frequency range does not overlap t he first IF frequency. Each second converter has its own local oscillator (LO), mixer, and ilters . Both convert the signal to 110 MHz a nd send it to the third converter.

f

The third converter amplifies the 110 MHz IF signal and converts it to the final intermediate frequency of 10 MHz. The third converter passes the signal to the IF section for detection. IF Section

The IF section a nalyzes how much power is present in the frequency component that has been converted to 10 MHz. Three functions are performed h ere: 1) weak signals can be amplified by α set of switchable amplifiers so that they may be analyzed . By amplifying the signal, the vertical window (dynamic display range) is shifted up or down . The REFERENCE LEVEL control selects the gain (and input RF attenuation as α pair) to frame this window ; 2) the signal is bandpassed by any of several 10 MHz b andpass filters selected by the RESOLUTION BANDWIDTH control. The greater the selectivity, the better two closely-spaced signals can be resolved, but n arrow b andwidths require longer sweep times. The microcomputer selects the best combination of bandwidth a nd sweep time, unless overridden by the operator; 3) the remaining signal is detected by α combination of α logarithmic amplifier and α linear amplitude d etector. The output of this combination is α voltage that corresponds to the signal strength in decibels . This amplitude detector output is sent to the vertical channel of the display section to show the strength of the particular component. Display Section

The display section draws the display on the crt screen . Vertical deflection of the b eam is increased as the output of

the amplitude detector increases. The horizontal position is controlled by the frequency control section and corresponds to the frequency analyzed at that instant. As the 492/492 Ρ sweeps from low frequencies to h igh frequencies during its analysis, the beam is swept from left to right. Any time α signal is encountered during the analysis, α vertical deflection shows the strength of the signal at the horizontal position corresponding to the frequency. The result is α display of amplitude as α function of frequency. The video amplifier scales the output of the detector for vertical deflection in dB/div or performs α log/linear conversion, depending on the vertical display mode . The video processor filters the video if either the wide or narrow filter is selected .

5- 2

The display section displays control settings on the crt based on data from the microcomputer .

The sweep is often rapid enough to give α flicker-free

d isplay, but at times the sweep must be slowed below the flicker rate. With Option 02, the display can be recorded and refreshed at α flicker-free rate by the digital storage section. The 492/492ΡΡ can read out the display data from digital storage through t he IEEE 488 interface.

Frequency

Control Section

The instantaneous frequency being analyzed is controlled by the frequencies of the local oscillators. To analyze another frequency, α local oscillator frequency is changed so that the new frequency is converted by the three converters to 10 MHz and passes through the IF section. Each converter section has its own local oscillator. Only the local oscillators of the first two converters are changed to vary the frequency being analyzed ; the 3rd LO remains fixed. The 492/492Ρ periodically sweeps and analyzes α frequency range centered about α frequency set by the FREQUENCY k nob. The FREQUENCY knob tunes the first and second local oscillators . The analyzer sweep is generated b y the sweep generator and the span attenuator . As the sweep generator sweeps through its range, the trace is d eflected across the screen on the front panel . The frequency sweep is controlled by the span attenuator, which scales the sweep according to the current SPAN/DIV . The output of the span attenuator drives the 1 st LO to sweep wide spans and the 2nd LO to sweep narrow spans. Option 03 adds phase-lock circuitry to stabilize the 1 st LO in narrow spans. If the 492/492Ρ is equipped with O ption 01, the frequency control section tunes the preselector to track the signal frequency being d etected. Digital Control Section Internal functions are controlled f rom the front

panel

through α microcomputer. An internal instrument bus allows communication between the microcomputer and all parts of

the instrument . Front-panel control d ata goes to the microcomputer on this bus. The microcomputer controls circuit functions such as ; the span attenuator, IF gain, and crt readout on this bus. The microcomputer also receives information from circuit functions such as, the sweep a nd phase lock circuitry on this bus . The 492Ρ may be controlled remotely through t he IEEE 488 bus, which interfaces to the microcomputer through α General Purpose Interface Bus (GPIB) board. The IEEE 488 connector is located on the rear panel of the instrument . The control language corresponds closely to front-panel operation of the 492Ρ.

REV A UG 1981

T h eory of Operation-492/492P Service Vol . 1 (SN Β030000 & up)

board are also connected to t he moth er board t hrou g h

Ot h e r Systems T he power s upp ly system provides reg u lated d o power fo r all parts of t he i n strume nt. The switchin g supp ly is capable of regulatio n over wide li n e frequen cy and line voltage ranges. T he cooli n g system con sists of an i n ta ke on t h e b ottom of the case, air passages withi n t he instrument, α fan, a nd α rear p anel ex h aust . Air is rou ted to all sections of t he instrument in proportio n to t h e heat generated by th at sectio n . I nter nal tem perature r ise is small for relia b le operation. Signal, powe r , a nd co nt rol con n ectio n s between sections a r e accomp lis h ed by α mot h e r board distribu tion system . Most ci rcu it boards p lug onto the moth e r board fr om t he top side. Components on th e RF dec k un de rn eat h th e moth e r

smaller con necto r s.

Fo r

Further I n formatio n

T he systems in t he 492/492Ρ a re desc r ibed in ni ne section s as s hown by th e Functional B lock Diagram. N i ne block d iag rams represe nti ng t hese systems follow t he Fu n ctio nal B lock Diagram.

Fo r more detailed i n formation, t he i n strume nt is divided

in to circuit diagrams for each assembly or part of an assembly . E ach sc hematic is accomp a n ied by α detailed block d iagr am an d α parts location ill u stratio n . These a re pr inted i n

the Diagrams section with look-up tables to aid i n fi nd i ng com po n e nts on either t he sc hematic or parts location ill u stration .

D ETAILE D DESCRI PTION Th e followi n g description is a rran ged b y section s o r systems ; such as 1st Co nverte r, 2nd Converte r , etc., followed by ci rcuit analysis of th e ci rcu its wit h i n that section . Eac h system/sectio n is i n trod uced wit h α d esc riptio n of the sys-

tern using the b lock diagram fou n d i n t he Diagrams sectio n of the manual . This is th en followed with α d escription of each circ u it board or major circuit wit h i n the system .

nector, an d 1st M ixer. (The 1st LO signal passes t hro ug h

1ST CO NVER T ER CI RC U ITS Th e 1st Co n verter mixes t h e i ncoming RF signal with α tunable local oscillator sig n al to produce i ntermodulatio n pro du cts. All of these are filte red ou t exce pt th e 2072 MHz and 829 MH z I F signals, wh ic h are app lied to th e 2 n d Co nverte r ci rcuit . Th e 1 st Converter consists of t he followi n g major segments : 1) th e RF Attenuator, wh ic h sets t h e i nput power to t h e a nalyzer ;

2) th e Pr eselector (O ption 01 only), whic h provi d es t he selectivity re q ui red to elimin ate spurious respon ses a n d image fre qu e n cies ; 3) t he 1st LO ( Local Oscillator), wh ich provides α t u na b le sig n al for the 1 st M ixer ;

4) th e P owe r Divider, wh ich splits t h e sig n al from t he 1 st LO for app lication to t he 1 st LO OUTPUT front- p a nel con-

REV A U G 1981

the Ph ase Gate to t h e 1st M ixer if Option 03 is i ncl uded);

5) th e Phase Gate, wh ich couples α portion of th e oscillator sig n al to α p hase gate that com pares th e phase of the oscillator signal agai n st α stro b e sig n al from t he ph aseloc k system ; 6) the Transfer Switc h , wh ic h pe rmits th e u se of an exte rnal mixer wit h the analyzer ; 7) the Filte r and Di plexer ci rcu its, wh ich select only the 2072 MHz and 829 MHz I F signals for app lication to t he 2 nd Con verter ; 8) the RF I n terface circuits, whic h select th e input RF attenuation , con trol t h e selection of the I F frequen cy (2072 o r 829 MHz), and co n trol t h e t r ansfe r switch .

T h e input RF is fed th roug h α 0 to 60 d B decade atte n uator to t he 1 st M ixer (if Optio n 01 is not included) via α 3 d B attenuator. The atten u ator matc hes mixer im pedan ce and protects th e mixer diodes f rom spurio us or static sig n als.

5- 3

Theory of Operation-492/492P Service Vol . 1 (S N Β030000 & up) The 1 st LO feeds signal to the M ixer i n o ne of two ways : di rectly from the P ower Divi der, or t hro ugh t he Ph ase Gate and Bias Return if Option 03 is installed. (The Ph ase Gate and Bias R eturn stages incur very little loss.) Th e Ph ase Gate couples off α small amount of sign al (approximately 0 dB m) to com p are with α strobe sign al from the ph aselock system . Th e outp ut is an erro r sign al th at is used by the ph aseloc k system for determining the FM tun ing current fo r t he 1st LO. Th e B ias R et ur n provides h ig h-pass filtering for the 1 st LO and α do return for the 1 st M ixer diodes . The current tune d 1 st L O output is mixed with t he incoming RF, and t he IM (intermodulation) products are route d t hro ugh t he Transfer Switch to the 2.072 GHz Directional Filte r. (O ption 08 deletes the Transfer Switch.) This filter is broa db an d, an d provides α constant match to the 1 st M ixer outpu t at all frequencies . The filter couples the 2.072 GHz IF to the 2nd Co nverter t hroug h α 4.5 GHz lowpass filter and d irectly couples ot her IM produ cts to t h e Diplexer . Th e lowpass filter removes odd m ulti p les of 2.072 GHz t h at are re-entrant modes of the Direction al Filter. The Di plexer provides do p ath for mixer bias an d rejects frequencies above 829 MHz. Th e si ngle b ala nced 1st M ixer affo rd s less IM products than an unbalanced mixer, so the conversion loss is inherently less . It also cancels local oscillator signal feed-through to the RF in pu t port . In standa rd i nst ru ments, an external mixe r port and Transfer Switch are included. Option 08 deletes these features . The external mixer feat ure permits an external mixer to be connected to the instrume nt to serve as the 1st IF so urce. This feature is p rimarily u sed for waveguide mixers .

For Option 01 instrume nts, α Preselecto r o r 1 .8 GHz lowpass filter is inserted in the RF sign al pat h. Th e sign al passes throug h α low-band/high-band switch, wh ich selects the Preselector or th e 1 .8 GHz lowpass filter . The 2 GHz Limiter protects the 1st mixe r diodes from signals 2 GHz a nd above by reflecting RF energy back to the input source. The 1 .8 GHz lowpass filter attenuates signals above 1 .8 GHz to reduce spu rious responses ca used by RF sign als above 1 .8 GHz feeding throug h to the 1st mixer. The P reselector is the signal pat h for frequ encies from 1 .7 to 21 GHz. The P reselector is α t un able filter that tracks with the 1st local oscillator . This prevents ot her RF signals from feeding through to the 1 st mixer and eliminates spurio us responses from external so urces . From the Preselector the signal passes through α 3 dB attenuator, which im proves the retur n loss of the Pr eselector, to th e 1 st M ixer .

5- 4

RF IN TERFAC E

CI RCU ITS

I ntrodu ctio n

Refe r to the b lock diagram adjacent to Diagram 27 . The RF I nterface circuits receive address and instructio n data from the M icrocomputer, decode it, and co ntrol the RF Atte nuator, Transfer Switch , and I F selection . The circuit consists of the Digital co ntrol circuits, which decodes the address and co ntrol the input d ata to the b uffer. The RF Interface section also includes the driver circuits, which furnish t he current required to d rive the three fu nctions me ntioned at the first of this paragraph .

Digital Control Address decoder U 2045 enables the d ata at the input of U 3046 whenever address 4F is selected by the M icrocomputer. Table 5-1 lists t h e purpose of each data line from the b uffer.

Transistors 02025 and Q3028 are en abled by α negative pulse from the microcomputer. The two transistors r aise the V cc of the three attenuator drivers (U3034, U3029, and U3038) to +16 V for about 100 ms ; this furnishes sufficient voltage to energize the attenu ator solenoids. E ach of the attenuator driver output li nes is p rotected by α d iode from the inductive k ick that occurs when the solenoids change state.

Tran sfe r Switch Am plifier U4023, transistors Q3025 and Q3024, plus related components form the driver circuit for the Transfer Switch. To select the external mixer, the microcom pu te r sets line Q5 h ig h. The change is coupled through C4026 an d R4012, which hold U 4023 at α low output state for α few millisecon ds. This lets Q3025 co nduct, and t he Transfer Switch selects the exte rn al so urce. If the microcom pu ter selects the inte rn al mixer, it pu lls line Q5 low, switc hing U4023 in the opposite direction , which ca uses Q3024 to co nduct . The Transfer Switch energizes in the opposite d irection, and the internal mixer is p art of the ci rcuit . Diodes CR3018 an d C R3017 protect the transistors from voltage sp ikes induce d by the Transfer Switch when it c h anges state.

Timer Μ1019 is an electrochemical timer. The current throug h R1015 causes the copper b and to progress along the scale that is calibr ated for α du ration of 5000 operating h ours .

REV A UG 1981

Theory of Operation-492/492P Service Vol. 1 (S N Β030000 & up) Ta ble 5-1 RF I NTERFAC E LINES

L ine

Purp ose

Q1

En ables 10 d B attenu ator

02

No connectio n

Q3

Enables 30 dB attenuator

Q4

Enable current dr ivers 02025 and Q3028

Q5

Enables transfer switch driver

Q6

Selects 829 MH z IF (hig h state) or 2072 MH z I F (low)

Q7

Enables 20 dB attenuator

08

Enables b aseline cli pping

RF

CIRCU IT R Y

I ntrodu ction

Refer to the block diagram adjacent to Diagram 12 . Th e in put signal is processed through α cali brated 0-60 d B attenuator (10 dB steps) and app lied to the 1 st M ixer. Option 01 instrume nts add α limiter and α 1 .8 GHz lowpass filter, or α current-tu ned preselector, between t he attenuator and the 1 st M ixer to improve selectivity. The IF o utput of the 1st mixer is se nt through Transfer Switch S13 to α directional filter where 2.072 GHz and 829 MHz intermediate frequencies are selected for the 2072 MHz 2n d Converter or 829 MHz 2n d Converte r. The 2072 MHz IF is fed through α 4.5 GHz lowpass filter (to rej ect the re-entrant modes of the directional filter) to the 2072 MH z 2nd Converter . The 829 MH z signal is fed through α di plexer and α 4.5 GHz filter before it is applie d to th e 829 MH z I F stages . The 4.5 GHz filter is used to reject th e re-entrant modes of an internal filter to the 829 MH z 2n d Converter . Two intermediate freque ncies a r e u se d in t he analyzer to prevent b aseline r ise du e to local oscillator feedthrough and crossover i ntermodu lation products. The 2072 MH z IF is selected for bands 1 and 5, p lus the waveguide bands. The 829 MHz IF is selcted for bands 2-4. With Option 01 installed, band 1 frequency range is limited to 1 .8 GHz, du e to α lowpass filte r. Α tunable preselector is u sed instead of the lowpass filter when bands 2 through 5 are used . Refer to Diagram 12 while readi ng the following description. RF Signal P ath The 0-60 dB step atte nu ator consists of three sections (10 dB, 20 dB, and 30 d B), which are co ntrolled by relays that receive drive signals from the RF Interface ci rcuit . The

REV A UG 1981

output of the atte nuator is conn ected directly to the 1 st M ixer th roug h α 3 dB attenuator in analyzers n ot equipped with Option 01 . The atte nuato r protects the mixer diodes from excessive input voltages and static d ischarges. In analyzers eq uipped with Option 01, the Preselector and relate d circuitry is placed between the step atte nu ator an d the 3 dB attenuator .

1 st

Mixer

The 1st M ixer receives the RF signal throug h t he 3 dB atte nuator, and generates th e intermodulation pr oducts that are filtered to provide th e low an d hig h I F signals. The mixer is α single b alance d design, which has less conversion loss in comparison with unbalan ced mixers . The local oscillator input is split through α broadband multi-sectio n coupler, whose outputs are equal in power but 90 °s out of ph ase. An add itio n al 90 ° ph ase shift is cascaded with t he appropr iate signal to create α 180 ° phase difference that is ap plied ac ross α pair of series-connected Schottky diodes . The result is t hat th e diodes are alternately switched on and off as the local oscillator cycles . The node b etween the two diodes is isolated from the 1st LO input by about 30 dB, so th e RF input is app lied to this n ode. The b locking ca p acitor at the input co nnector permits broadb and signal application f rom the RF port, while b locking do diode bias from appearing at the analyzer in put . Dc ret urn for the mixer is by way of the Transfer Switch, Di rectional Filter, Diplexer, an d 4.5 GHz filter t hrough the 829 MH z IF circuits . Th e mixer b ias voltages arrive at the mixer through the same path.

N ot counting the IF filtering ci rcuitry, the fundamental conversion loss of the 1st Converter is about 14 dB ; third harmonic conversion loss is about 24 dB . The Schottky d iodes are mounted in α removable assembly that can be extracted or in serted in the main mixer modu le .

Power Divi d er

The P ower Divider s plits the outpu t of the 1st L O (YIG oscillator) to isolate the 1 st M ixer from the 1 st LO OUTPUT front-panel connector. The unit is essentially two multisection di rectional couple rs that are multi-port cascaded to produ ce two ports h aving equal power. The isolatio n betwee n output ports is greater than 15 dB at operating frequ ency . The Power Divider also provides an improved load to the local oscillator .

1st Local Oscillator

The 1st LO is α YIG (Yit rium-Iron-Garn et) oscillator t hat h as α tun ing ra nge of 2.072 to 6.35 GHz. The oscillator as-

semb ly includes the interface circuit board that couples operating an d t un ing voltages from the 1st LO Driver, Spa n Atte nuator, an d Error Am plifier circuits to th e oscillator.

5-5

T heory of Operation-492/492P Service Vol . 1 (S N Β030000 & up) The +15V1 voltage provides op erating bias for the oscillator. The supply is protected b y VR 1010, C1016, and R 1011 . Th e second s upply, +15V2, is for future app lications. CR1018 and C R1019 stop transient voltages from enteri ng the tu ne voltage coils. It also protects the driving circuits from the transients induced when degaussing. Relay K1 015 is closed when the FM Coil is used to tune the oscillator . To prevent the tune volts coil from movi ng the oscillator frequency while the FM Coil is in operation, C1012 and C1014 are connected across the tu ne coil . Th e h eate r kee ps the YIG sp here at α constant temperat ur e for best stability.

Transfer Switch

The Transfer Switch is α three- port coaxial switch that permits application of 1st IF signals from inside or outside the analyzer. This feat ure is primarily u sed for by- passing the 1 st Converter circuitry. The function is controlled by circuitry on the RF Interface b oard . It is automatically actuated when waveguide band s are selected , or the front-panel ΕΧΤ M IX ER push button is p ressed . Di r ection al

F ilte r

The Directional Filte r (FL 16) couples the 2072 MH z signal

to the 2nd Co nverter via the lowpass an d bandpass filters . As intermo du lation products (IM) flow throug h FL 16, they induce α selected current into α one-wavelengt h distributed ring, which couples the 2072 MH z I F signal out to FL 11, the lowpass filter . The remainder of the IM products p ass on through, since the ring is excite d only with 2072 MH z signals. The bandwidth of this unit is approximately 45 MH z. The u nfiltered signals are passed on to the Di plexer.

1 .8 GHz lowpass filter, α 1 .7-18 GHz filter, an d α 3 dB attenuator. Coaxial relays S10 and S11 switch the stage input and output to select either the lowpass filter and Limiter or the Preselector and 3 dB attenu ator. The relay coils a re d riven by circuitry on the Preselector Driver board. The lowpass filter path is used only on band 1 ; the Preselector ope rates on all the ot her b ands . The 2 GHz Limiter operates from 100 kH z to 2 GHz. It has α li near two-port tra n sfer characteristic of unity (minu s 1 dB) un til the inp ut exceeds +5 d Bm. Above this point, the intern al d etector diodes conduct, reflecting part of the RF input energy back to the source . As the input level rises, the limiter reflects more signal, t h us limiti ng the amou nt that can p ass t h roug h. The 1 .8 GHz lowp ass filter stri ps4he incoming signal of any frequencies above 1 .8 GHz and passes the signal below 1 .8 GHz on to the output segment of the selector switch (S11). The Preselector is α 1 .7-18 GHz YIG Filter that provides h ig h selectivity and image-freq uency rejection. Tuning cur re nt, whic h is near 500 mA at 21 GHz, is provided by the P reselector Driver circ uits. The P reselector operates on ban ds 2, 3, 4, and 5 . The signal from the Preselector passes th rough α 3 dB attenuator to the output sectio n of the Filter Selector switch. The attenuator isolates the P reselectoι, which is sensitive to loading on its output.

H ig h IF Filte rs

T he 2072 MHz sign al from the Directio nal Filte r is passed

2 ND CO NVERT ER

t hrough FL 11, α lowpass filter that rejects all signals above

CI RC U ITS

4.5 MH z. The secon d filter, FL 14, rejects inte rmodu lation products bot h above and b elow 2072 MH z. Di plexer and Filte r

T he Diplexer filters the 829 MH z IF signal from the mixer output and sends it to the 2nd Converter throug h FL15 . The Di plexer also provides α good match to the 1 st M ixer IF port at frequencies above 1 GHz. This match is important for the overall flatness and freq uency response of t he analyzer.

Two 2nd Converter systems are u sed in the 492/492Ρ Spect rum Analyzer . One converts 2072 MHz to 110 MHz; the ot her co nverts 829 MHz to 110 MHz. Only one converter is operational at any time, and is selected as α fu nction of the meas urement band being u sed. The selection of the IF for each band is shown in Table 5-2 along with t he ce nter freque ncy range and the local oscillator frequ ency range . Note that this ta ble includes Option 01 characteristics.

Preselector

T he Preselector, which is included when Option 01 is installed, consists of two selector switches, α 2 GHz limiter, α

5-6

Two IF's are used by th e 2nd Co nverter for the following

reaso ns:

REV AUG 1981

Theory of Operation-492/49213 Service Vol. 1 (S N Β030000 & up) 1) to elimi nate I F feedt hrough in band 2 a nd reduce or eliminate h ig her orde r sp u rs in band s 3 a nd 4; 2) because of th e limited tune range of t he 719 MHz LO, th e lowe r F cannot be u sed above ba nd 4;

I

3) if α measureme n t ban d were to i ncl ud e the first intermediate fre qu ency with in its r ange, it is p ossible for some input signals admitted b y t he preselecto r to pass th rough th e 1st Co n verter (wit ho ut conve rsio n ), i n to t he 2nd converter at t h e 1st intermed iate frequ ency . Th e resultant spurious outpu t will ca u se the baseli n e level on t h e screen to rise, and co uld possibly o b scure real signals. By usi n g two selectable 2 n d Converte rs, t h e analyzer can h ave over lapp ing measurement b ands that do not inclu de th e first intermediate freq uency, a nd completely avoid the pro b lem. Th e 2072 MH z 2nd converte r mixes the 2072 MHz from the first con verter with t he outp ut f rom α cavity oscillator. Th is local oscillator is swept ove r α 7.5 MHz ra nge . At t he co n verter i nput, α fo ur-cavity ban dpass filter is u sed to pass only t he 2072 MHz 1st I F sig n al and preve n t unwante d signals gen erate d within the 2nd Converte r from passing back through to t he 1 st Co n verter. Α diode mixer is used to mix th e 2072 MH z F input a nd the local oscillator signals to gene r ate th e 110 MHz secon d F output. The 110 MHz out-

I

I

put passes thro ugh α 110 MHz lowpass filter that b lock s h ig h er f req uency sig n als from t he mixer. T he 829 MH z 2nd Converte r uses α phase-lock ed voltage con trolle d oscillator to produce th e 719 MHz sig n al that is mixe d wit h t he 829 MH z fi rst I F sig n al . Th e swept 2182 MHz 2nd local oscillator is used as α refere n ce fo r t he 719 MHz local oscillato r . Th e 719 MH z oscillator is desig ned so t hat it can be d isabled upon command from t he microcomp uter i n t he I F selection process. T he phaselock circuit maintai n s α co nstan t relation s h ip between th e two local oscillators as the 719 MH z oscillator is swept over α 2.5 MH z ran ge . Α four-sectio n coaxial ba ndp ass filter is used befo re the mixer to exclu d e a ny RF sig n als other th a n t h e d esired 829 MHz fir st I F . Again, α diod e mixer is used to mix the 829 MHz input a nd local oscillator signals to produce the 110 MH z second I F o utp u t. Selection between the two I F signals also tak es p lace within t he 829 MHz converter system . Under command of t he microcomp uter ( by way of the RF nterface circu its) α d iode selector switching netwo rk con nects o ne of th e two 110 MHz second IF signals to the outp ut for application to t he 3rd Converter .

I

Ta b le 5-2 2 ND CO NVER T ER IF SELECTIO N

Fr equ ency B a nd

Cente r Frequ ency Ran ge

1 2 3 4 5 6 7 8 9 10 11

0-1 .8 GH z 1 .7-5 .5 GH z 3.0-7 .1 GH z 5.4-18.0 GH z 15.0-21 .0 GHz 18.0-26.5 GHz 26.5-40.0 GHz 40 .0-60.0 GH z 60 .0-90.0 GH z 90 .0-140.0 GH z 140.0-220.0 GH z

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Local Oscillator Freque n cy (MHz) Ra n ge 2182 719 719 719 2182 2182 2182 2182 2182 2182 2182

±3 .75 ±1 .25 ±1 .25 ±1 .25 ±3 .75 ±3 .75 ±3 .75 ±3 .75 ±3 .75 ±3 .75 ±3 .75

Co n verte r System IF 2072 829 829 829 2072 2072 2072 2072 2072 2072 2072

MHz MHz MHz MHz MHz MH z MH z MH z MHz MH z MHz

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Theory of Operation-492/492P Service Vol. 1 (S N Β030000 & up)

2072 MHz 2 ND CONVERTER

0

The 2072 MHz 2nd Co nverter converts the 2072 MHz signal output from the 1 st Converte r to 110 MHz for eventual ap plication to th e 3rd Converter . The assembly consists of α low-loss narrow- band four-cavity filter con n ecte d t hrough an internal ca ble to α low co nversion loss narrowband diode mixer, α 110 MHz lowpass filter, a nd α mixe r b iasing ci rcuit that will d isable the mixer wh e n directed by the microcom puter.

F our-Cavity F ilte r

The F our-Cavity (bandpass) F ilter, whic h is depicted on Diag rams 11, 12, and 13, is designed to p ass only the 2072 MH z IF signal to the mixer and to r eflect any other f requencies back to the 1st Converter for te rmi nation. In add itio n, the filter keeps the converte r LO and mixe r products from enteri ng the 1 st Converter. This filter is desig ned for α 1 dB bandwidth of 15 MH z and an insertion loss of 1 .2 dB. Eac h end resonator is capacity co up led to exte rnal circuits through α coupling h at pl ugged into α 3 millimeter co nnector. Intercavity co up ling is provided by coupling loops that p rotrude from the machined filter to p. The r esonant freque ncy of eac h cavity is d etermined primarily by the depth of α gap in the u nderside of the

CO UPLIN G HAT

filter top, an d is fine tu ned with α t uning screw on the side of each cavity . All of the tight machining tole rances are confined to the to p. Thu s, the main cavity milling need n ot be α high precisio n part . Wh en properly tuned, using α network analyzer, the filter return loss is g r eater than 25 dB from either end (i n α 50 Ω system). F igure 5-1 shows α c ross sectional view of the filter; F ig . 5-2 s hows the eq uivalent electrical ci rcuit .

Mixer Ci rcuit

The M ixer circuit in the 2072 MHz 2nd Co nverter is of the single- bala n ced, two-diode type, and co nsists of the mixer, an operational am plifier bias ci rcuit, α delay li ne, an d α lowpass filter. In opertion, both diodes of the mixe r are turn ed on and off b y the output signal from the 2181 MH z Cavity 2nd Local Oscillator, through coaxial co nnector Ρ183. N ote that, alth oug h the d iodes are connected fo r opposite polarity, both are tu rned on at the same time because of the 180° phase shift d elay line in the input line to t he uppe r dec k. Also n ote that the diodes are matc hed an d must both be replaced if one fails. 2072 MH z RF from t he Four-Cavity Filter ente rs the mixer, where it is switch ed on and off at α 2182 MHz rate by th e mixer diodes. Conduction of the diodes is conrolled by the much stronger 2181 MHz LO signal . Several mixi ng products r esult; one, th e diffe rence frequency of 110 MHz, is separated from the ot hers b y α low-pass filter fo r use as the I F o utput .

CO UPLI NG LOO P

FREQUEN CY DETERM I NIN G GAP

2727-101

Fig. 5-1 . Filter cross-sectio n view.

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Theory of Operation-492/492P Service Vol . 1 (SN Β030000 & up)

2727-102

Fig . 5-2. Filter equ ivalent ci rcuit . The two inductors and one ca pacitor at the output of the mixe r fo rm α lowpass filter t hat passes 110 MHz unattenuated to th e 829 MH z 2nd Converter via coaxial co nnecto r Ρ182. Capacitors at each of the thr ee in puts to the mixer function as do blocking capacitors to keep the d iode b ias from bei ng im pressed upon the RF an d local oscillator lines. The bias ci rcuit, whic h consists of operational am plifier

U 1014 and t he associated components, establis hes the b ias fo r t he mixer diodes and also provi des the means for effec-

tively switching the mixer off (u nder co ntrol of the microcom pu ter) . Wh en the mixe r is active, each diode has approximately 2 mA of forward bias. For t his co ndition, the I F SELECT signal from the Ζ Axis/ RF Interface circuits (applied through feedthrough capacitor C182) is low. This causes the output from U 1014A to be at +14 V and the output from U 1014 B to be -14V . Diodes CR1014 an d CR1018 are thereby reverse-biased . Thus, the ser ies resistances of potentiometer R1019 an d resistor R1014, an d potentiometer R1010 and resistor R1017 provide forward bias to the d iodes . The potentiometers provide for balancing the b ias levels . In operation s in which the mixer is not active, the IF S ELE CT signal is h ig h. This r everses the states of the U 1014 outpu ts and forward-biases diodes CR1014 and CR 1018 .

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th ese diodes co nducti ng, resistors R1014, R1016, R1017, and R1018 form two voltage dividers that set the reverse b ias to the mixe r diodes at 5 V . This effectively turns the mixe r off, and atte nu ates the 110 MHz signal by about 55 dB . W it h

P recision E xternal Ca bles T he external cable that connects the F our-Cavity F ilter output to the mixer circ uit and t he extern al ca ble that connects the cavity 2nd Local Oscillator to the mixe r ci rcuit are both c ritical length ca bles. Th e reasons th e length is critical are as follows: The 4-Cavity F ilter-to- Mixer i nput cable : Seve ral produ cts and harmo nics of the local oscillator and RF input frequ encies are allowed to exit the mixer via the RF in put port of th e mixe r. Two significant products are the image (RF in p ut minus the 2n d Local Oscillator) and the sum (RF inpu t p lus the 2nd Local Oscillator). There is enough energy in these two signals to warrant efforts to recove r that energy .

Only the RF signal at 2072 MHz can pass throug h t he Four-Cavity F ilter. Thus, any other frequency applied to the

5-9

Theory of Operation-492/492P Service Vol . 1 (SN Β030000 & up) filter (t hat is, sig n als exiti n g th e mixer via t he RF port) is r eflected back to th e mixer by the filte r. If t he cable betwee n t he filte r and t h e mixer is t he correct len gth , th e most sig n ificant reflecte d signals (that is, th e image and the s u m) can be returned to th e mixer in p h ase an d con verted i nto a dd itio nal energy at th e intermediate f re q uency. Th is techn i q ue is called "image enhancement mixing" a nd typically impr oves conversion loss by a pproximately 3 d B at th e design freque n cies . Th e image frequen cy in t h is i n stan ce is very near the RF freque n cy . Α very s h a r p cut-off filter is t hus req ui red to p ass the RF, yet reflect t he image. Th e Fo u r-Cavity F ilter performs this fu nction . T h e Cavity 2 n d Local Oscillator-to- M ixer LO i nput cable : T h e image a nd su m products a re also present at t h e L O port of t he mixer. T hese signals leave th e mixe r via the cable to the 2nd LO and are reflected back to t he mixe r b y th e LO cavity . T he oscillators resonator appears h ig h ly reflective to th e image an d sum signals because it is t u ned to t h e LO frequency . Again , the len gth of th e ca b le from th e Cavity LO to t he mixe r LO port is adju sted so t he image and sum signals are reflected bac k to th e mixer in the prope r phase for re-co nversio n to su pply add itional e nergy at th e I F frequ e ncy .

2182

MH z PH AS ELOC KE D 2 N D LO 38

Α

&

38 Β

Ge n e ral Descri ptio n Th e 2182 MHz Ph aselock ed 2nd LO assembly contains α tunable microwave oscillator, f re q ue ncy reference circuitry, and phaselock circ u itry, wit h in α two-section housi ng. M ic rowave circu itry is p ac kaged wit h in t he mach i n ed aluminum portio n of t h e ho using . Low fre q ue n cy p h aseloc k ci r cu itry is wit h in the mu-metal com p artment. In the microwave or LO portion of the assembly, th e 2182 MH z M ic rost r i p Oscillator generates 2182 MHz for t h e 2nd converters a nd t he 2 nd LO i nternal refere n ce ci rc u itry. T h e 2200 MHz R efere n ce ci rc u it receives α 100 MH z drive signal from t he 3rd converte r crystal oscillator a n d produ ces 100 MHz h armo n ics. The 22nd h a rmo n ic or 2200 MH z is mixed wit h 2182 MH z from t h e microstri p oscillator in t he 2200 MHz Referen ce M ixer circuit . Th e difference frequency of 18 MH z is th e n fed to th e ph aselock side of t h e module . Α ph ase/frequency detector, on t he 14-22 MHz Ph aseloc k circ u it board, compares th e 18 MH z d ifference fre qu e ncy wit h α signal from α linearize d t u ni ng 18 MHz voltage cont rolled oscillator. T he d etector o u t put tu nes t h e

5- 1 0

2182 MHz M icrostr ip Oscillator s u ch t h at t he difference frequ e ncy exactly matc hes t h e frequ e n cy of th e 18 MHz refe r e nce V CO . Sweep a nd tune sig nals from t h e S p a n atten uator and Ce nter F requency Control circuits t une t he 18 MHz VCO . T he out p ut voltage from t he p h ase/freq uency d etector forces t h e M icrost rip Oscillator to tu n e the same amount.

2182

MIC R OST R I P

OSCI LL ATO R

_ _

Β T his oscillato r co n sists of α p ri nted 1/2 wavele ngt h resonator driven by α common-emitter feedb ac k amplifier (01021). Th e b ase of 01021 is capacitively tapped i nto th e resonator. T h e resonator serves as α t uned ph ase inverte r an d im ped an ce transformer, co nnected betwee n t he b ase a nd collecto r of Q1021 . P art of t h e base feed bac k ca p acita nce is provided by α be ndable tab (C1021). Th is allows fine adj ustme nt of t he total feed b ack . T h is feed bac k RF signal is d etected , by t he base-emitter junctio n of 01021, to produce α ch ange i n bias voltage th at is related to th e amount of fee dbac k . The base voltage can b e mon itored at ΤΡ 1015 with α hig h im pedance voltmeter without sig nificantly distu rbi n g th e oscillato r. T he do collector voltage and curren t for 01021 is regulated by an active feedbac k circu it containing tra n sisto r 02021 . Voltage at the junctio n of R2023 and L2023 is α function of Q1021 collector cu rre nt. Th is voltage is se nse d by 02021, wh ic h alters t he b ase curre n t to Q1021 t hereby reg u lati ng th e collector current an d mai ntai n i n g +10 V do on t h e resonator. Decou pling an d control of bias loop d y namics a re p rovi d ed b y C2104. Resistor R 2016 swa mps t he negative base resista n ce of 01021 to provide sta b ilizatio n . Resisto r R 2015 protects th e b ase-emitte r ju nction of Q1021 from excessive reverse bias in t he eve nt th e +12 volt sup ply fails. T he oscillato r is t u ned by varacto r diode CR 1028, connected to on e end of the reso n ato r. Decouplin g for th e varactor is provided by th e low-pass elemen ts in t he tun e li ne. Bend a b le ta b C1022 can be used to fi ne tun e the oscillato r center freq uency . T hree output ta p s are coupled to t he resonator t h roug h printed capacitors under t h e reso n ator. On e outp ut s upp lies 2182 MHz t h roug h α 6 d B attenuator to th e H armonic M ixer i n t h e 829 MH z 2 nd Converte r. T he ot he r two o u tp u t taps couple L O power t hroug h 6 d B atte nuators to bu ffer amplifie r s 01031 a nd Q1011 . T he amplifie r s provide approximately +10 d Bm to the 2072 MHz 2 n d Co n verter and +8 dBm to t he Reference Mixer .

REV AU G 1981

Theory of Operation-492/492P Service Vol . 1 (SN Β030000 & up) Since the two buffers are n early id entical, only the 2nd Converter bu ffer is desc ri bed. Gain is pr ovided b y α si ngle common-emitte r transistor (Q1011). Printed elements provi de inp ut a n d output impedance matching . Out-of-band dam ping is provided by R 1011 in series with α 1/4 wavelength s h orted stub . Dc is b locked by C1014 and C1011 . Α 1/4 wavelength open stub is u sed at the outpu t to reflect on e of the 2nd Converter's image freque ncies at 4254 MHz (the other buffer does not u se n or need this st ub ). Collecto r bias for 01011 is provi ded t hroug h R1012, L 1011, the 1/4 wavelength s horted stub, and R1011 . The 1/4 wavelength shorted stub is grou nde d through C2011 (C2011, C1013, and L1011 are also u sed for deco u pling). Collector voltage is determined by divide r R1013 and R2013 ; this controls the do feedb ack to the collector-base junctio n of 01011 . The bias network is decoupled from the RF path by L 1014 . Diode CR2013 protects the b ase of Q1011 from excessive reverse bias if the +12 volt supply fails.

2200 MHz Reference B oard This circuit generates harmonics of the 100 MH z in put . Th e 22 nd h a rmonic or 2200 MH z is u sed by the Reference M ixer. The input 100 MH z signal is applied throug h α matc hing network (co nsisting of L 1034, L1025, C1036, C1029,

and C1025) to α differential amplifier (Q1024 and Q2024) . The emitters of this amplifier are ac coupled t hrough C2026, reducing low frequency gain and ensuring balanced operation . Α snap-off diode (C R2014) is driven by the am plifier, via transformer Τ2015, to generate multiple h armonics of the 100 MHz signal including the 2200 MH z reference . The output passes throug h α 3 d B attenuator, fo r isolation, to the Reference M ixer ci rcuit .

2200 MHz Refe r e n ce Mixer Signals from the 2200 MHz R eferen ce ci rcuit are filtered

by α printe d 2200 MHz ba ndpass filter. Diod es CR1011 and

CR1012 are the switch ing elemen ts of α single-balanced mixer. The microstrip oscillator output is applied to CR1011 and through α 1/2 wavelength delay line to CR1012 . The delay li ne s hifts the oscillator signal 180° so both diodes switch together. M ixing the 2200 MH z with the oscillator 2182 MHz signal produces the d iffe rence frequency of 18 MHz. T h is 18 MHz signal is fed t hroug h α 37 MHz lowpass filter to the 14-22 MHz phaselock circuit. The lowpass filter p revents unwanted products, such as 82 MH z (produ ct of 2100 MH z an d 2182 MHz), from passing into the p haselock circuit.

14-22 MHz Phaseloc k Boa rd T his board contains regulated power supplies, α 1422 MHz (18 MH z n ominal) voltage controlle d oscillator with li nearizing circuitry, and α ph ase/frequ ency d etector circuit.

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Its main fu nctio n is co ntrol of the 2182 MHz M icrostrip Oscillator. The enti re ci rcuit board is housed in α magnetic shield to reduce spu rio us effects of extern al ac fields . All power su pply and control inpu ts enter the circuit board via feedthroug h capacitors in t he housi ng wall . All connections with the microwave ci rcuitry are through feedthrough capacito r s C2200-C2204, in t he floor of the h ousi ng. The +15 V, -15 V, and +9 V inputs supply power to operational amplifier type regulators that produce +12 V, -12 V, and +5 .2 V o utputs, respectively. Α zener diode (VR2021) serves as α stable -6 .2 V refe rence fo r U2014B, which regulates the -12 V supply through emitter-follower 02021 . The -12 V s upply, in turn , provides bias curr ent for VR 2021 . Diodes CR2015 and CR2018 protect the operational am plifier output and Q2021 du ring supply s h utdow n. Inverting am plifiers U 2014A/Q1012 and U 1015/Q1022 u se the -12 V su pply as α reference to p rodu ce the +12 V and +5 .2 V supplies, respectively . The 2nd LO sweep a nd tune inputs are summed by differential am plifier U2063 . Grou nd potential of the Span Atte nu ator ci r cuit is sensed t hro ugh R2057 and s ub tracted from the sweep signal to reduce effects of grou nd potential variations. Provisio n is made for se nsing the ground potential of th e Ce nter Fre qu ency Control ci rcuit b oa rd throug h R2059 ; however, the present interface requires that the Fine Tune ground input be grou nded to the 2nd LO assembly through W2059 . Swee p and tune sensitivities are set by selectable resistor R2063. The combined swee p and t une signals, at the outp ut of U 2063, are applied to α non-linear s haping circ uit, th e gai n of whic h varies as α fun ction of in pu t sign al voltage. Outpu t voltage from the shaper ci rcuit co ntrols the b ias of varactor d iode CR1075 . This bias tu nes the 14-22 MHz oscillator. Non-linear tu ning characteristics of the oscillator are compensated by reciprocal non-linearity in t he shaper. As the input voltage to non-inverting amplifier U 1062 B becomes

more positive, it successively exceeds the tap-point voltages of α series of p ositive voltage d ividers. Diodes in U 2051, connected to th e divider tap points, are successively forward biased to add increasing shunt conductance to the amplifier's feedback path. Feedback prog ressively d ecreases and forward gain of the am plifier increases with positive excu rsions. Α similar am plifier, U 1062A, u ses negative voltage dividers and t he diodes in U1051 to increase the gai n prog ressively with negative voltage excu rsions. Outputs of the two amplifiers are summed at R1068, which is selected to match the gain shaping requ irements of the 1422 MHz oscillator. One of the varactor bias resisto r s, R1070, is also selected as part of the linearity adjustment. The 14-22 MHz oscillator consists of α differential amplifier with transforme r feed bac k. The emitters of the amplifier transistors 02073 and Q2078 are ac coupled through

5- 1 1

Theory of Operation-492/492P Service Vol . 1 (SN Β030000 & up) C2077. Transforme r T1 077 serves as th e am plifier feed back path and also as part of the oscillator reso nator . Tuning va ractor CR1075 provides virtually all of the resonator capacitance to allow α wi de tu ni ng r ange . Transformers T1 077 and T1 075 constitute the resonator inductance that may be selected by using differe nt tap combinations to interconnect the two coils. Resonato r in ductance is adjusted to center the oscillator's tun e r ange near 18 MHz. R2076 a nd R2079 enh ance the amp lifier h ig h frequency stability. Α d iscrete two-stage am plifier pr ovides an unsaturated voltage gain of appr oximately 43 dB for th e d iffe rence frequ ency signal from the 2200 MHz Reference M ixer. The output of 01036 drives α differential am plifier consisting of 01037 and 01038. The d ifferential stage limits the output swing to ECL compatible levels . Dc bias for the amplifier is provided by Ο1036, which has do collector- base feed back via voltage d ivider R1039 and R1041 . ECL li ne receive rs U 2036D an d U2036B buffer signals from the d iscrete amplifier and the 14-22 MHz oscillator, respectively . Output signals from these amplifiers are app lied to t he phase/frequ ency detector for comparison. Α pair of E CL D-type flip-flops (U2027A, U 2027 B) comprise the ph ase/freq uency detector. The flip-flop outputs are wi red and connected to the input of U 2036C, wh ic h serves as α common reset . The cloc k input to U 2027 B is the 1422 MHz V CO signal, and the cloc k input to U 2027A is the amplified difference signal from the Refere nce M ixer. If the two cloc k signals are of identical phase an d frequency, both flip-flop sections set then reset together. If the ph ase of the Reference M ixer signal leads the 14-22 MHz signal, U 2027A will r emai n set lo nger tha n U 2027 B. If the signal lags, U2027 B will set fi rst and remain set longer. The signal that leads in ph ase or has the h ig her freq uency will cause t he associated flip-flop to remain set α h ig her perce ntage of t he time . The average differential output voltage of the two flip-flops t herefore indicates wh et her the Reference M ixe r sig n al leads, lags, or differ s in frequ ency from t he 1422 MHz VCO reference . Out put of the detector is filte red by an RC lowpass filter, then app lied to differential amplifie r 01028, which tunes the 2182 MHz oscillator. The ph aselock circ uit adj usts the M icrostrip oscillator frequ ency such t hat the Reference M ixer output always matches the frequency of the 14-22 MHz V CO . The M ic rostrip Oscillator is therefore locked to α f requency equal to that of the 2200 MHz reference minus that of the 1422 MHz VCO . If the 14-22 MHz Oscillato r is swept or t uned, the M icrost rip Oscillator sweeps a nd tu nes an equal amou nt. Within the control bandwidth of the lock loop, the M icrost rip Oscillator FM noise is reduced to that of the reference circuitry . The phaseloc k loop band widt h is controlled by R 1024, C1026, and R1025, C1023. Un ity gain fo r the ph aseloc k loop occurs near 200 kHz with α gain slope of -6 dB /octave. The gain slope b reaks to -12 dB /octave for freque ncies below 16 kH z. Resistors R1030 and R1031 d i-

5- 1 2

vi de a nd offset the output of U 1028 so the M icrost rip oscillato r tu ne voltage r anges between 0 and -12.5 V.

CAV ITY 2 N D

L OCA L

OSCI LLATO R

Refer to the b lock diagram adj acent to Diagram 38 . The Cavity 2nd Local Oscillator generates the 2182 MHz sign al that is :

1) mixe d with t he 2072 MH z signal from the 1st Co nverter to produce the 110 MHz interme diate frequency in the 2072 MHz 2n d Converte r; and 2) u sed as α reference in the h armo nic mixer in th e phase lock ci rcuit of the 829 MHz 2nd Converte r.

The oscillator is α low noise cavity oscillator that freeruns at α n omi n al frequency of 2182 MHz, but is tun able over α r ange of 8 MHz. Α relatively large resonant cavity with very high Ο allows the oscillato r to operate at low noise levels and with α power output of +10 dBm. The cavity itself operates in the ΤΕΜ mode and utilizes α foreshortened vertical post to fo rm α coaxial st ru cture. Two equ ivalent sc hematic d iagrams are shown in Fig . 5-3, α direct connectio n represe ntation, and the RF equivalent. As shown in the RF equivalent d iagram, transistor Ο1 operates as α common emitter oscillato r with positive feedbac k in the collecto r circuit. It is biased to operate with an emitter current of approximately 30 mA . Th e collector is coupled to the tunable r esonant cavity by α co upli ng sc rew . Line le ngt h between the transistor collecto r and the coupling screw is set b y an adjusta ble wire stra p.

Ene rgy d istribution i nside the cavity is such t hat Ε fiel ds are at the to p of the cavity and magnetic (Η) fields circulate at the bottom. Ene rgy is extracted from the ta nk circuit (cavity) by inductive co upling near t he bottom of the cavity . The out put co nnectors, with attached co up li ng loops, are rotated to adju st the power outpu t level from the oscillator. One connecto r is adjusted to provide +10 dB m of output, a nd the other is set to provide 0 dBm of output power . Tun ing of the oscillator frequency is by means of α va ractor diode th at is co ntrolled by α 15 to 40 V bias signal from the Shaper and B ias ci rcuit . This signal va r ies the oscillator frequency over an 8 MHz range. Th e diode is located near the top of the cavity and is coupled to th e cavity post by α capacitive co up li ng h at (E-field co up li ng). RF energy in t he coup ling h at is d ecoup led from the va ractor bias feedthιoug h by an ind uctor. The spacing between the h at and the post dete rmines the sensitivity for the d io de tuning. REV AUG 1981

Theory of Operation-492/492P Service Vol . 1 (SN Β030000 & up) (This is an adjustment that is performed dur ing manu factu re. No attempt should be ma de to readjust spacing because diode p ackage cracking may occur.)

829 MH z Diplexer Circ uit

The Di plexer passes sign als at 829 MHz with mi nim um attenu ation (approximately 1 d B) an d has α pass-band of approximately 200 MH z. All frequ encies outside the passband, f rom approximately 50 kH z to 2 GHz, are term inated in 50 Ω loads with α matc h of at least 10 dB . Figure 5-4 shows α simplified sc hematic of the d iplexer. At 829 MHz, the se ries resonators pr ovide α low-impedance path from inp ut to output. (Note on Diagram 15 that th e inp ut is from the 1 st Converter through coaxial connector Ρ231 .) deally, none of the signal is lost in the 50 Ω resistors beca use there is α zero impedance path a rou nd those resistors. The parallel resonator appears as an open circuit at 829 MHz.

I

DI RE CT CO NNECTIO N EQUIVALENT

RF EQU IVALENT Fig. 5-3. 2182 .0 MHz Cavity LO equ ivalent circuits. Α tuning screw is added to the cavity to allow frequency

adjustment of the oscillator without removing the LO from the instrument. F ig ure 5-3Α s hows the two cavity 2nd LO e quivalent circuits.

829 MH z 2 ND CO NVERT ER IF Sectio n Refer to the b lock diag ram adj acen t to Diag r am 15 . The 829 MHz 2 nd Converter converts the 829 MH z signal outpu t from t h e 1 st Converte r to 110 MH z fo r application to the 3rd Converte r, and provi des the switching capability for the microcom pu te r controlled selection of either the 2072 or the 829 MH z co nverter system . The co nverter ci rcuits consist basically of an inp ut d iplexe ι, an am plifier, α bandpass filter, α mixe r, and α diode switch.

REV AUG 1981

At frequ encies above or below the p ass- band , th e series resonators appear as large reactan ces, shifting the primary signal flow through the 50 Ω resistors. Also, the out-of-band impeda nce of the parallel reson ator is small compared to 50 Ω. T hus, the resisto rs are esse ntially grounded at one end, te rmi nating both the in pu t and out p ut ports. Α wide bandwi dth is used to mi nimize losses in t he resonators and to eliminate adjustments . Relative bandwidths of the series and parallel resonators are optimized to provide reasonable match at the b and edges. As shown in Diagram 15, the d iplexe r co ntains compone nts not show n in Fig . 5-4 . Two p airs of 100 Ω resistors (111012, R1015 and R 1011/R1012) are u sed in parallel to fo rm each 50 Ω termin ation. This redu ces load inductance. Α small ca pacitor is conn ected across each load (C1010 and C1013) to improve impedan ce match at freque ncies above the p ass-band . Th e inductor in the parallel resonator is α prin ted lengt h of transmission li ne that is ta pped to esta blish th e correct bandwi dth. One end of this inductor is grounded through four capacitors (C1017, C1016, C1019, and C1018) so th at do bias from the 1 st Local Oscillator D river ca n be i n t roduced to the mixer through the diplexe r. Four capacitors a re use d in parallel to minimize inductance variations and circuit Q degradation. Α lowpass filter is included in the bias line to k eep noise from the 1st converter. The diplexe r is followed in the signal path by α prin ted ci rcuit five-element lowpass filter t hat consists of three shunt capacitors and two se ries inductors. Cutoff frequency of this filter is approximately 1 .2 GHz. 829 MH z Am plifier Circ uit

T he 820 MHz Am plifier provi des approximately 18 dB of signal gain at 829 MHz and consists of two n ea rly identical am p lifier stages in cascade (Q1017 and Q1025), p lus α 3 dB

5- 1 3

Th eory of Operation-492/492P Service Vol . 1 (SN Β030000 & up)

SER I E S RESO NATO R 1ο = 829 MHz

SER I E S RESON ATOR 1ο = 829 MHz

O UTPUT

INPUT

Τ

PARALLEL

RESONATOR 1ο = 829 MHz

2727-104

Fig .

5-4. Di

p lexer

n uator. The overall noise figure is approximately 2.8 dB . n stages are desig n ed as gen eral purpose, u ncond itio n ally stable am plifiers for u se in α 50 Ω system . Operation atte

h

T e gai

of α stage can be most easily und erstoo d if th e ac and do signal p at hs are descr ibed separately. R efer to F igs . 5-5 and 5-6 for simplified sch ematic diagrams of t h e ac a nd d o signal pat h s. In t he ac ci rc u it of F ig . 5-5, capacitor C1 a nd printed ci rc u it inductors L 1 and L2 form the input matc hing networ k . (In the fi rst stage, i n ductor L 1 is act u ally t he series inductance of d o b lock ing capacitor C1016.) Th e collector ci rcu it is matched to 50 Ω by i nductor L4 a n d capacitor C2 . Gain is controlle d p rimarily by pr inted circ u it emitter i nd uctor L3. H ig h f requency sta b ility is en hance d by resistors R1 and R2. Th at is, at f req ue ncies well above 829 MHz, resisto r R 1 e n su res low common base gain and resisto r R 2 h el p s to dampe n t he collector circu it. In the do circu it of Fig . 5-6, negative fed back through th e voltage divid e r co n sisti n g of resistors R3 an d R4 sets t h e collector voltage as α fixed proportion of t he -12 volt refere n ce sup p ly . Collector cu rre n t is d etermin e d b y resistor R5. Less current is used i n t h e first stage than in t he second because t he fi r st stage requires less intermo du latio n d istortion pe r formance . Reve rse brea kd own of t he base-emitter ju n ctio n can degrade the tra n sisto r performance, so α d iode base clamp is provided n each circu it (C R 1013 a nd

i

5- 1 4

sim

plifie d

sc

hematic.

C R 1022) su

fo

pp ly .

r

protectio n

n

i

the abse nce

of

h

t e

+12 volt

N ot s how n in F igs . 5-5 and 5-6 are an i ndu ctor and α capacito r in t h e base ci rcuits ( L 1014 and C1014 for 01017; L 1021 a nd C1023 for Q1025) an d α ca p acitor i n th e collector circu its (C1013 for 01017 ; C1027 fo r Q1025) . These components perfor m decou pli ng fun ctio ns to isolate t h e signal path from t he bias netwo rk . T h e 3 d B atten uator assists i n maintain i n g α wideband 50 Ω i nterface between the second am p lifie r stage and t he 829 MHz b a ndp ass filter. It consists of resistor s R1026, R1027, R1025, a nd R1029 . Α test point (J 1029) at t he output of the atte n uato r is used to ve rify amplifier performan ce a nd to aid i n adju stment of t h e following 829 MHz ba n d pass filter . From th e atteun ator, th e signal is app lied to t he 829 MH z 2 nd Con verter M ixer circ uit . 829 MH z

Mixe r Circ u its

Refer to Diag ram 15 . Frequen cy co nversion from 829 MH z to 110 MH z occu rs on th e 829 MHz 2n d Co nverter boa rd . The board con tai n s α coaxial b and pass filter , α 1 .3 GH z low p ass filter, α 3 d B attenu ator, a nd α two-diode, sin gle- b alanced mixer with associated freq uen cy diplexi n g ci rcuitry .

REV AU G 1981

Theory of Operation-492/492P Service

Vol .

1 (SN Β030000 & up)

-820 pF

I NPUT

'PR I N T E D CO MPONEN T

2727-105

Fig.

5-5 . Amplifier signal

path .

829 MHz 1st IF signals from the 829 MHz Amplifier, enters the converter through an 829 MHz bandpass filter . The filter blocks unwanted inputs, primarily the 609 MHz image signal . Α 1 .3 GHz printed element lowpass filter blocks h igh frequency signals that would otherwise be admitted at the re-entrant frequencies of the b andpass in excess of 2 GHz . The function of the 1 .3 GHz lowpass filter is shared by the 1 .2 GHz lowpass filter located on the 829 MHz Diplexer b oard . Α 3 dB attenuator on t he 829 MHz Amplifier board and one following the 1 .3 GHz lowpass filter help ensure consistent 50 Ω nterfaces for the 829 MHz bandpass filter.

i

The 829 Mhz bandpass filter is composed of four quarter-wave, coaxial-type resonators mounted on the 829 MHz 2 nd Converter board . The end resonators are tapped near their grounded end to facilitate the filter's input and output coupling . Inter-resonator coupling is provided by printed "through-the-board" capacitors that connect between the resonators at their high-impedance end . Α b endable tab is located at the h igh-impedance end of each resonator for fine adjustment of resonant frequency . The bendable tab acts as α small, variable capacitance from the end of the resonator to ground, making fine adjustments of resonant frequency possible . When properly tuned, the filter presents an nput return loss of at least 12 dB at 829 MHz and an nsertion loss of about 2 dB .

i

i

Fig . 5-6. Amplifier signal p ath . REV A UG 1981

5- 1 5

Theory of Operation-492/492P Service Vol. 1 (SN Β030000 & up) 829 MHz enters the mixer d iodes through α 450 MHz

highpass filter . The lowpass filter blocks the lower IF signals

generated within the mixer. The mixer diodes are transformer-driven with 719 MHz local oscillator . The large amplitude L O signal (+12 dBm) drives the diodes into and out of conduction, effectively switching the smaller 829 MHz signal on and off at α 719 MHz rate. Several mixing products result, the largest of which are the d ifference frequencies, (110 MHz) and the sum (1548 MHz) . The 110 MHz product is allowed to leave the mixer by way of α 300 MHz lowpass filter that blocks LO, RF, and h igher frequency products . The 1548 MHz product leaves the mixer via the 450 MHz lowpass beyond w hich it is reflected by the 829 MHz b andpass filter and returned to the mixer in-phase with LO harmonics to increase energy of the 110 MHz signal. Α printed d elay line between the 829 MHz bandpass and 1 .3 GHz lowpass filters control the phase delay. The net result of this "image enhancement" is low conversion loss and good inter-modulation distortion performance. Inclusion of the 3 dB attenuator reduces the image enhancement effect considerably but allows line lengths and filter c haracteristics to be non-critical . Overall conversion loss from 829 MHz to 110 MHz is about 8.5 dB, including 2 dB from the 829 MHz bandpass filter and 3 dB from the attenuator.

When t he IF S ELECT signal input is h igh, amplifier 01011 is turned on and shunt d iode switches CR2012, CR2013, and CR1015 turn off. This allows the 110 MHz F signal from the 2072 MHz 2nd Converter to be applied to the output port . Series diode switch C R2011 also turns off to prevent signal loss into the inactive 829 MHz 2nd Converter . Isolation for the 829 MHz 2 nd Converter is not critical when that converter is inactive, because the 719 MHz local oscillator is also turned off by the IF S ELECT signal . This eliminates most spurious outputs. The switch and amplifier logic is summarized in Table 5-3.

I

As d escribed above, diodes are used as the basic switch elements . When forward biased, with c urrent of several milliamps, the diodes present only α few ohms of series resistance to RF signals. When reverse biased, the diodes p resent essentially an open circuit. The control signal from switch d river 02015 is connected in α series path t hrough t he four diodes (CR2011, CR2012, CR2013, and C R1015) and inductors L 2011, L2013, and L2019 so that 02015 supplies only α small current to forward bias all four diodes . This same d iode b ias current is u sed to turn off amplifier Q1011 .

The 110 MHz F Select circuits select the 110 MHz IF signal from either the 829 MHz 2nd Converter or t he 2072 MHz 2nd Converter for transmission to the 110 MHz IF Amplifier. The 110 MHz F signal from the 829 MHz Converter is applied directly to the select switch circuit; the 110 MHz IF signal from the 2072 MHz converter is applied (via coaxial connector Ρ233) through α controlled amplifier to the select switch circuit. The switch circuit diodes are CR2011, CR2012, CR2013, and CR1015 .

Diodes CR2012 and CR2013 are incorporated into α pitype matching network consisting of inductors L 2011, L2013, and capacitor C2012 so that both switches shunt the signal at moderately h igh impedance points . In a ddition, when the switch diodes are turned on, p arallel resonance, between inductor L 2011 and capacitor C2012, presents virtually an open circuit to signals p assed by switch diode CR2011 . Switch diode CR2013 is located at the h igh impedance node created by series resonant inductor L 2019 and capacitor C2017. Diode CR1015 directly shunts the output from amplifier Q1011 .

When t he IF S ELECT signal input to the 829 MHz 2 nd Converter (via feedthrough C236) is low, series diode switch C R2011 turns on, allowing the 110 MHz IF signal, from the 829 MHz 2nd Converter, to be applied to the output port . At the same time, shunt d iode switches CR2012, CR2013, and C R1015 turn on . Amplifier 01011 turns off, thus isolating the output port from spurious 2072 MHz 2 nd Converter o utput signals.

Transistor 01011 operates as α common-emitter amplifier for the 110 MHz F signal from the 2072 MHz 2nd Converter. its gain and impedance match are controlled p rimarily by feedback resistors R1011 and R1012 . Resistors R1013 and R1018 attenuate the output by approximately 6 dB for enhanced control of match and stability characteristics . Dc collector current from Q1011 develops α voltage across resistor R1017. B ias control transistor

110 MHz IF Select Circuits

I

I

I

Table 5-3 SWITCH AND AMPLIFIER SELECTION S UMMARY

5- 1 6

IF Select L ine

Series Switch

S hunt Switch

Amplifier

H igh Low

On Off

On Off

Off On

Ι

Ι

11 0-MHz IF Source Ι

829 MHz 2nd Conv . 2072 MHz 2nd Conv .

REV A UG 1981

Theory of Operation-492/492P Service Vol . 1 (S N Β030000 & up) 01012 then compares this voltage with the fixed voltage of the divi de r, co nsisti ng of resistors R1015 and R1016 . Any va riation in the Q1011 collecto r current is thu s se nse d by 01012 and cancelled b y α res ulting change in t he Q1011 base current. Collector current in Q1011 is fixed in this manner at approximately 15 mA . When control current is drawn through t he switching d iodes by driver 02015, α voltage is developed across resistor R1017 that exceeds the control limits of 01012, effectively removing the base bias from am plifier 01011 and turning off that transistor. N egative curren t su pplied through resistor R1014 ensures that Q1011 can be tu rn ed off by the loss of positive base drive. Diode CR1011 protects the base of 01011 from excessive reverse bias. Voltage across R1017 is appr oximately 3.4 V when 01011 is turned on and approximately 4.4 V when it is t urn ed off. Overall gain for th e 110 MHz path is appr oximately 12 .8 dB when the am plifier is turned on .

From the diode switch ci rcuit, the 110 MH z IF signal is transmitted via coaxial co nn ector Ρ232 to the 110 MHz IF Am plifier. 829 MH z, 2nd Converter,

L O Section

Refer to th e block diagram adj acent to Diag ram 14 . The 829 MHz 2nd Converter Local Oscillator provides the

719 MH z frequency that is mixe d with t he 829 MHz IF signal to produce the 110 MHz IF signal that is supplied to t he 3rd Converter. (in the following description , th e circuits a re referred to as the 719 MHz LO.) The 719 MHz LO co nsists of α ph aselock loop, α 719 MHz output ci rcuit, and α 2 nd LO front panel output ci rcuit . R efer to Diag ram 14 while reading the following description. Ph aseloc k Circ uit The phaseloc k circ uit receives reference frequ ency inputs and uses phase/frequ ency d etection techniques to use those signals in controlli ng the output frequency of the 719 MHz oscillator. The circuit co nsists of α voltage controlled oscillator (VCO), α ph ase/frequency detector, α harmo nic mixer, and various amplification stages and power s plitters. When the 719 MHz LO is enable d, the 2182 MHz Local Oscillator output freque ncy is used as α swept reference to derive the 719 MHz freque ncy . The VCO is controlle d so that the third h armonic of its outp ut frequ e n cy is α co nstant d iffe rence from t he 2182 MHz refe rence . This control is accom plish ed by th e ph aselock loop . Refer to Fig . 5-7 . In the ph aselock loop, th e h a rmonic mixe r generates α freque ncy that is the difference betwee n the swept 2182 MHz input refe rence and the third harmonic of the VCO output frequ ency. Ideally, this difference is 25 MHz. T hat frequency, in turn, is compared with the 25 MHz t hat is

719 MHz VO L TAG E CO NTR O LLE D OSCI L LATO R

7 719 MHz

OU TPU T

2727-107

Fig .

REV

A UG 1981

5-7 . Simplified block diagram of the phaselock ci rcuits.

5- 1 7

Theory of Operation-492/492P Service Vol. 1 (S N Β030000 & up)

d ivided d ow n from the 100 MH z oscillator output supplied

from the 3rd Converter. This comparison is done by the ph ase/f requency detector ci rcuit. Its output is α co rrection voltage th at is app lied to the VCO to dr ive the frequency in t he required direction to maintain t he nomi n al output frequ e ncy at 719 MHz. This completes the loop that causes t h e VCO to trac k t he 2182 MHz reference .

Because the third h armo nic of 719 MHz oscillator frequ ency is locked to the 2182 MHz reference, the tu ning range of the 719 MHz oscillator is only o ne third of the swept ra nge of the reference . Since that swept ra nge is 8 MHz, the 719 MHz oscillator range need be only 719 ± 1 .33 MHz. The 719 MH z VCO, 02014, uses α Colpitts configuration with α printed ci rcuit quarter-wavelength transmission line resonator to achieve h ig h spect ral purity and good thermal stability. Co rrection voltage is applie d to varacto r diode CR1011 (which is conn ected at the midpoint of the tra nsmission line resonator) to vary the resonant frequ ency of the transmission li ne over α 2 .66 MHz r ange . Α tunable transmission line (also pr inted) adj acent to the p ri nted resonator compensates for variatio ns in component tolera nces and resonator dimensions. This adju stable transmission li n e is cut at factory cali br atio n to the co rrect length for proper V CO operation . Α scale with mi nor d ivisio ns every 2 MHz is printed n ext to the adj ustable li ne to aid in cali bration. The output from the oscillator is extracted near on e en d of the qu arter-wavelength li ne through two printe d inductors and applied to outpu t am plifiers through α powe r s p litter. Note th at the 719 MHz VCO is enabled o r disa bled under microprocessor co ntrol, d epende nt upon t he frequ ency band being analyzed . When the oscillator is disabled, the 719 MHz signal is no lo n ge r availa ble for conversions with 829 MHz RF. This is controlled by the IF S ELECT signal from the RF Interface through co nnector C231 . If this signal is low, t ransistor Q2017 is cut off, whic h cuts off transistor Q2016. This, in turn, cuts off transistor Q3015 (which is the cu rrent source for oscillator transistor 02014), thu s cutting off the 719 MH z oscillator. From t he oscillato r, the +6 dBm 719 MH z outpu t signal is app lied to isolation am plifier 01021 through α powe r divider that consists of resistors R1021, R1022, and R1020 . (From the other si de of this powe r divider, the signal is applied to an outp ut am plifier fo r transmission to the 829 MHz

M ixer

circuit .) Α second isolation am plifier 2 nd Con verter (03021) iden tical in con figu ration , provi d es the necessary isolation between t h e 719 MHz oscillato r o ut p ut and

o rd er products . Two in particula r, those at 744 MH z and

694 MHz, are se parated from the 719 MHz oscillator frequency by only 25 MHz. Were it n ot for t he isolation provided by amp lifiers 01021 and Q3021, these two p roducts could be converted in t he 829 MH z mixe r an d would thu s appear as real signals on the screen. The isolation am plifiers provide sufficient attenuation in the reverse di rection to prevent this occ urrence . To p rovide maximum reverse attenuatio n in each amplifier circuit, external RF feedb ac k is kept to α mi nimum . An output matching LC network , consisti ng of capacitor C1025 an d α printed inductor for Q1021, a n d capacitor C3021 and α p rinted inductor for Q3021, presents an optimum load impedance to the collector of each transistor to allow maximum power transfer to the attenuator t h at precedes the h armo nic mixe r. An in pu t L C matc hing network consisting of capacitors C1023 and C1022, plus α printe d inductor for 01021 and capacitors C3023, C3022 plus α printed ind uctor for 03021, establishes the 50 Ω input impeda nce to each transistor. Α 3 dB atte nu ator consisting of resistors R3021, R3022, R2021, and R3023 at th e outpu t of the seco nd isolatio n am plifier (03021) provides α non-reflective so urce impedance to the mixer. Without the attenuator, mixer co nversio n loss could vary from un it to unit . The h armonic mixer, co nsisting of diodes CR2022 and CR2021, inductor L2014, and α h alf-wavelength (at 2182 MHz) tr ansmission li ne, produces the d ifference frequ ency b etween the third h armonic of the 719 MHz oscillator fre qu ency and the 2182 MH z reference frequency (nominally 2157 MHz) . N ote t h at the 2182 MH z signal is supplied from the 2182 MHz Cavity Oscillator through coaxial connecto r Ρ237 and the power divider consisting of resistors R1021, R1023, and R 1022 to the h alf-wavelength transmission line. The V CO input to the mixer switches diodes CR2022 and CR2023 at α 719 MH z rate. The 2182 MHz reference acts as the RF and is app lied differentialy to the d io des from the transmission li ne. The resultant 25 MHz intermediate frequency is di plexed from the mixer through t he 100 MHz lowpass filter consisting of ca pacitor C3014 and inductor L3014 . (Diodes CR2022 a nd C R2021 are mounted in printed circuit board cut-outs to relieve any necessity of bending the diode leads. Lead bending may fracture the d iode case.) Inductor L2014 provides α b ias retur n path to allow t he diodes to switch at α 719 MH z rate .

From the h a rmonic mixe r, th e signal is applied t h ro u g h

u nd esired h armonic mixer products.

the above mentioned

T he harmo nic mixer prod uces not only the required 25 MHz d ifference frequency, bu t also many ot her h ig her

mixer out p ut signal to α level appropriate to drive the ph ase/frequency detector. Am plifier IC U 1053 co ntains two d iffe re ntial am plifiers in cascade; amplifier IC U 1044 con-

5- 1 8

lowpass filter to cascaded amplifiers

U 1053 and U 1044 B. These am plifiers boost the -32 dBm

REV AUG 1981

Theory of Ope ratio n -492/492P Service Vol . 1 (SN Β030000 & up) tains only o ne differential am plifier and acts as α buffer . Wh en th e loop is fi rst acq ui r i ng lock , such as at power-on, t he nominal 25 MHz I F may be as h ig h as 34 MH z. Two stages of am p lificatio n are necessary to ensure enoug h gai n for the phase/frequ e n cy detecto r to drive the I F b ack to 25 MHz; t he buffer is necessary to provide E CL levels to th e detector. T he second i nput to th e ph ase/fre que ncy detector is th e 100 MH z frequency from the refe re nce oscillator in t he 3 rd co nverte r via coaxial conn ector Ρ235. This sig nal is app lied t hrou g h two am plifier stages, U 1022A a nd U102213, to a divide-by-four circ u it, U 1036 A an d U 1036 B. These two flipflo p s divide th e 100 MHz freq u ency to 25 MHz for ap p lication to the ph ase/f requency detector . (Two stages of amplification are used to isolate t he 100 MH z refe re nce bus f rom sig n als, ge nerated in the local oscillator sectio n of t he 2nd Con verter .) This sta b le 25 MHz referen ce out p ut is used to lock t he differen ce frequency f rom th e harmo n ic mixer at 25 MHz. Th e ph ase/f req uency d etecto r effectively measures t h e ph ase differen ce betwee n t he 25 MHz refe re nce a nd th e I F from t h e h armonic mixe r, a nd determi nes t h e correctio n voltage t h at is to be applied to t h e 719 MHz VCO . T h is circu it consists of two D-type fli p -flops, U 2047A and U 2047 B , a nd α d ifferen tial amplifier stage used as α N AN D-gate ( U 1044A) . T he 25 MH z reference sign al f rom the fre qu ency divider is a pp lied to t he cloc k inp ut of flip-flo p U 2047 A; th e n ominal 25 MH z signal from the h a rmo nic mixer is a pplie d to the cloc k i npu t of fli p -flo p U 2047 B . Th e risi n g edge of th e in pu t sig n al to each fli p-flop causes t he Q outputs to retu rn to t he low level only after bot h fli p-flo p s h ave been cloc ked .

T he nomi n al swing of t he U 3053 out p ut is from +12 to -12 volts. Si n ce t h e compensation am plifier is ca p a b le of co n siderably mo re output swi ng t han is needed to co n t rol th e oscillato r , α voltage d ivider is u sed to limit the out pu t a nd reduce amp lifie r relate d noise . T his voltage divider , consisting of resistors R2053, R2054, R3051, a n d R3052, redu ces the p ossi ble ±12 volt swi ng to +5 V to +12 V, as req ui re d b y varactor diode CR 1011 . N omi n al voltage i n α loc ked co n dition is +6 .75 to +7 .5 V. T h us, d epe n dent upon wh et her t he h a r monic mixe r output frequency is above o r below 25 MH z, t he co rrection voltage a pplied to diode CR 1011 is higher or lowe r than n ominal to d rive th e oscillato r fre qu e ncy i n the req uired direction .

Fro nt Pa n el 2n d Local Oscillato r Out p ut Circ u it

T he 829 MHz 2n d Converter also provides α sam ple of each 2nd local oscillator f req uency at t he a n alyzer fron t panel . This output is provided for external accessory eq ui pmen t such as α tracki n g generator . Eac h local oscillato r (719 MHz and 2182 MHz) output is obtai n ed t h rou gh α power d ivider and applied to α power com b i ne r for a pplication to the 2nd LO OU T con nector (Ρ236) on t he f ront panel . The divide r for th e 719 MHz signal con sists of resistors R1021, R1023, and R 1022 . From t hese two power dividers, t he sig n als are applied throug h filters to t he com bi n er, wh ich consists of resistor s R2025, R2024, a nd R2026, then to t he fron t p anel connectors . Two additional filters are re qu ire d to attenu ate u ndesired sig n als and p revent those sig n als from reac hing t he 829 MHz mixe r . Α 2.2 GH z ban dpass filter, con sisti n g of two ad jacent q uarter-wavelen gth printed ci r cuit t ransmission li n es, is use d i n the 2182 MHz li n e to atte n uate undesired mixer products . The second filter, α 1 GH z lowpass circu it, attenuates t h e 2182 MHz sig n al a n d preve nts it from reach i n g t he 829 MHz mixe r. T h is filter co n sists of cap acitors C1021, C1022, C1023, C3023, C3024, a nd C3025 a nd th e th ree associate d printed i n d uctor s.

If t he h armonic mixe r out p ut fre qu ency is below 25 MHz, (o r if its phase lags t h at of t h e 25 MH z referen ce) th e 0 ou tput of fli p-flo p U 2047A will be h ig h longer t h a n th at of fli p-flop U 2047 B . If t h e h armonic mixer o ut pu t f r equency is above 25 MHz (or if its p hase lead s), t he opposite will be true. When th e two flip-flo p s a re cloc ked at t he same frequency an d ph ase, t h e two out p uts will be h ig h fo r the same amo unt of time . From the two flip-flops, t he 0 outputs are ap pliedsig to compensation amplifier U 3053, α differen tial amlocal 2n d oscillator n als, 2182 MHz a nd B ot h plifier th at dete rmines whic h output is h ig h for α lon ger time . 719 MHz, are present at th e fro nt p a nel when the 829 MHz 2 nd con verter is selected . Compen sation am plifier U 3053 provi d es p art of the loop gai n to ensure t hat t he gai n will be high e no ug h to cause t he 719 MHz oscillator to trac k th e swee p of th e 2182 MH z refere n ce oscillator . In add ition , t he compen sation am plifier limits t he loop b a nd widt h to 100 kH z to make certai n th at the loop will not oscillate. N ote t h at the d iffe rential i nputs to the a mplifier eac h i n clude α lowpass RC filte r ( R3041 a nd C3042 for t h e minu s i npu t; R2048 an d C2055 for the pl u s in put) to atten uate th e und esi red h ig h fre qu ency cloc k pulses from t he ph ase/frequ en cy d etector .

REV A U G 1981

719 MHz Outp ut Ci rc u it

Th e 719 MH z 2nd L ocal Oscillator gen erates t h e sig n al t hat is app lied to t h e 829 MH z mixe r to derive t he 110 MHz I F sign al . As desc ri b ed in th e phaselock circuit, th e 719 MHz V CO out pu t is coupled t hrough divider resistors R 1020, R1022, R1021, R2021, R2023, an d R2024 to t h e first isolation am plifier . T he secon d o utput from th is powe r d ivide r is a pp lied to amplifier Ο2021 to p rovide gain for α 12 dB m

5- 1 9

Theory of Operation-492/492P Service Vol . 1 (SN Β030000 & up) o u tp u t level to dr ive th e 829 MHz mixer . T he o u tp u t of th e am plifier incl ud es α 3 dB atten uator (co n sisti ng of resistors R2027, R2028, a nd R 2029), to ensure α 50 Q non-reflective source impedan ce . An RF test poi nt, J 2026, is provided at t he amplifier output . The level at t h e test poi nt is ty pically -6 dB m.

110- MH z I F A MPL I F I ER A N D 3rd CO NVER TER

110 MH z I F AMPLI F I ER The 110 MH z I F Am p lifie r con sists of three stages of amplification and an atte n uato r. Since the first two mixe rs in the RF system offe r no high fre qu e n cy gai n , it is importan t that th is ampllifier ex h ib it low n oise ch aracteristics. Also, it mu st be relatively free from t h i rd-ord e r i n te rmοdulation distortion. Signal i nput to th e am plifier is f r om the 2nd Converte r

through coaxial connecto r Ρ321 . This sig n al is nominally

The 110 MH z I F Amp lifie r and 3rd Converter acce p t the 110 MH z out put from t he 2n d Co n verters, amplify and convert th e sig n al to α 10 MH z I F sig n al wh ich is applie d to the resolution ci rcuits in th e I F sectio n . Th e 110 MHz signal is amplified in α t h ree-stage gai n block a nd app lied to α t hr eesectio n ba n d pass filte r. T h is filte r u ses helical reso nators a nd has α n omi nal bandwidth of 1 MHz. From the ba n d pass filter , th e signal is applie d to α mixer an d hete rod yned wit h α 100 MH z local oscillato r sig n al to produce α 10 MH z t h ir d F sig nal . T he r esu lti n g sig n al, nominally at α level of -35 d B m at the to p of the sc r ee n , t hen drives t h e Varia b le Resolution circ u its.

110 MH z and is a pplied to an impedance matc hing bandpass filter co nsisting of in ducto r L2044 and cap acito r C325 . Th e sign al is i njected into t h e p arallel tuned ci rcuit through α ta p in t h e i nd uctor and ta ken o ut at t h e h ig h impedance si d e through an ot h er varia b le capacitor , C2047. Inductive inp u t provi d es for con verting to h ig h imped a n ce with i n t he tu n ed ci rc u it ; the ext ra capacito r on the output provides for converti ng back to 50 Ω nomin al . T he primary tuning capacitor (C325) adju sts t h e reson a n t point; t he output capacitor (C2047) is a dju sted in combi nation wit h C325 for good im ped ance matc h at 110 MHz. T his is do ne using α retu rn loss br idge . The nomi n al return loss is 35 dB. The Q of th e i nput filter is approximately 20 .

I nitial gain for th e an alyzer is provided b y t h e 110 MHz I F Amp lifier. T h is gain compensates for sig n al level losses in t he t hree mixers . Th ree stages of am p lificatio n are u sed, plus α p i n diode con trolled attenuator that allows for adj ustmen t of t he gain . Typical gai n for th e am p lifie r is 21 dB. From t he am p lifie r, th e 110 MH z sig n al is a pplied to the 3 rd Co nverte r t hroug h α b an dp ass filter .

From the input filte r, t he sign al is a pplie d to Q4053, the fi rst stage of amplificatio n . T h is is α broadband feed b ac k am p lifier to provide good input a n d out put impedance and co n t rolled gain . All fee dback is through r eactive compon e nts (t r a n sforme r Τ3054) not resistive components . T hus, t he impedance a nd gai n ca n b e co nt r olled wit ho u t sig n ifica nt n oise pro b lems .

T he filter is α three sectio n u nit u si n g h elical reso n ato rs. Its ban dwi d t h of 1 MHz defi nes the broadest resol u tion b a ndwidt h of t h e an alyze r, provi des good image rejection, a nd limits n oise in t he frequen cy spectr um i n whic h d esirable signals a p pear .

T h e second amplifier stage, 04037, is esse ntially the same as t he fir st, with only mino r b ias d iffe re nces. Gain through eac h of t hese stages is approximately 9 d B. The output is applie d thro ug h α 3 d B atten u ator, to preserve the impedance figure, to the br idged Τ adjustable atte nuato r . T he 3 dB atte nuator consists of resistor s R2039, R2038, and R 2043 .

I

Co nsisti n g of α mixer, an oscillator, and va r ious outpu t amplifier s, t he 3rd Converter co n verts t he 110 MH z secon d I F signal into th e 10 MHz th i rd F signal . Th e local oscillato r is α crystal controlled circuit t h at gene r ates α precise 100 MHz sig n al . This 100 MH z is a pplied to th e mixer and to ou tput amp lifiers. T he 100 MHz signal is use d in t h e 2 n d Converter and t he phaselock section . It is also fu rn ish ed to α front p a nel CA L OUT con nector for exte rn al use.

I

The mixer is α diode ri ng type t hat is fe d from bala nced d rivers wh ic h a re drive n b y t he 100 MHz oscillato r. From th e mixe r, t h e o u t pu t sig n al, at 10 MHz, is a pp lied to th e Varia b le Resolution section of t he 3 rd Converter.

5- 20

F rom t he 3 d B atten u ato r, t h e sig nal is ca pacitively coupled t hroug h C2037 to t he a dju sta b le atten u ato r. T h is atte n uato r uses two PIN d iodes (C R3030 an d CR 1029) in the mode i n wh ich t he resista nce to RF sig nal flow is controlled by the cu rren t through t he d iod es . Refer to Fig . 5-8 as an aid in und e rsta nd i ng the followi ng descri p tio n . Wit h refe re n ce to F ig . 5-8, if resistor R 1 were set to i nfin ite r esistance and resistor R2 were set to zero resistance, the RF signal p at h would be t hroug h R2 to gro u nd , t h ere b y pro duci n g i n finite signal atten u atio n . If resisto r R 1 were set

REV AU G 1981

Theory of Operation-492/492P Service Vol . 1 (SN Β030000 & up)

Fig . 5-8. Bridged Τ atte nuator equivalent schematic. to zero resistance and resistor R2 were set to infinite resista nce, the RF signal path would be through R1 to t he load, thereby producing almost no attenuation. This, basically, is h ow the adjustable attenu ator operates, except that resistors R 1 and R2 are actually PIN diodes a nd the RF path resista nce through t hese diodes is controlled b y the current through the diodes in an inverse proportio n (higher current results in less resistance to RF).

W it h reference to Diagram 16, resistors R3035 and R2030 esta blish α consta nt current of approximately 2 mA from the -15 volt supply to the diodes . T his current is divided according to the bias on t he diodes . The bias, in turn, is esta blished by gain adjustment R 1015, from the +15 volt supply . If R 1015 is set low (near ground), d io de CR3030 is reverse biased a nd th e 2 mA flows through diode CR1029. This ro utes the RF signal through resistors R2032 a nd R3029 and capacitor C2029, with the impe da nce characteristics of CR1029 added for maximum attenuation.

If R 1015 is set h ig her (nearer +15 V), diode CR3030 is forwa rd biased and starts to conduct . Si nce the 2 mA supply current is relatively constant, this sub tracts from the current through C R1029 . Thus, the impedance of the diodes is relatively consta nt, resulting in α good impedance match over α broad range . Dependent upon the exact amount of current through C R3030, part of the RF signal path is through that diode to the outpu t am plifier and part is through R2032 an d diode CR1029 to grou nd . This results in reduced signal attenuation.

REV A UG 1981

If R 1015 is set to the positive limit, the e ntire 2 mA flows through C R3030 . This routes th e RF signal thro ugh C R3030 (w hich exhibits little resistance with hig h current) to the output am plifier with almost no attenuation. (The insertion loss is approximately 1 dB .) From the adjustable attenu ator, the signal is applied to the final amplifier fλ3018 . This stage is α broadband feed back am plifier that supplies relatively substantial output current a nd ex hibits good intermοdu lation distortion performance. This is provided primarily thro ugh the la rge current ca pacity, by negative feedbac k through resistor R3014, and emitter degeneration through resistor R4029 . These resistors . are sized to p rovide α resonably good impedan ce match at 110 MHz. Nominal gain of the stage is 13 dB. W ith Gain potentiometer R1015 set for maximum gain (least attenuation) the gai n of the 110 MHz IF Am plifier is approximately 26 to 27 dB . The Gain potentiometer is normally adjusted for total gain of 21 dB .

The outp ut signal from the 110 MHz IF Amplifier is applied to the 110 MHz B a ndpass Filter.

110 MHz

BANDPASS F ILTER

000 The 10 MHz B andpass Filte r is α th ree-sectio n filter using helical resonators, th e major fun ction of which is to 5- 2 1

Theory of Operation-492/492P Service Vol . 1 (SN Β030000 & up) determine the widest resolution of the analyzer. Another filter fu nction is to provi de image rejection (that is, to preve nt the mixer from producing 10 MH z outputs from input signal of 90 MHz) . Still a not her function is to limit the noise spectrum appeari ng at the 10 MHz F circuits to those frequencies at wh ich signals also ap pear.

I

Though th e filter is α sealed unit, in the interest of system un derstanding, the following brief descriptio n is provided. The filter consists of three small helical resonators enclosed in cans and t uned with multi-turn trimmer capacitors. For purposes of impedance matching, the filter is symmetrical. The end resonators are connected to external ci rcuits by 10 picofarad ca pacitors attached to ta ps on t he coils. Coupling between resonators is accomplished through holes in the resonator cans. Adjustment of the filte r for minim u m attenuation is performed at calibr ation by setting the three trimmer ca pacitors . I n sertion loss is on t he ord er of 4 to 4.5 dB. From th e filter, the 110 MH z signal is applied to the 3rd Co nverter.

From the oscillator collecto r circ uit, the outpu t is R C coupled to driver stage Q2036. The driver is α feedback amplifier t hat provides output powe r on the orde r of +10 dBm to drive all of the reference amplifiers plus the mixer amplifier. The output is tra n sformer coupled from the collector ci rcuit.

R eference Am plifier Ci rcuits The reference output circu its consist of fo ur identical lowgain common emitter amplifiers with relatively high levels of emitter degeneration . These are transistors Q4018, Q2015, Q3015, 02016 and associated components . The primary purpose of these am plifiers is to provide isolation among the reference outputs and isolation of th ose outputs from the oscillator and mixer circ uits. The output of each is approximately 0 dB m. From am plifier 04018, the output is applied to the 829 MHz IF circuits throug h coaxial connector J2013 . From am plifier 02015, the output is applied to coaxial connector J2012 and is reserved for future u se. From amplifier Q3015, the output is applied to the Ph aselock Sy nthesizer circu its through coaxial connector J1023 . From am plifier Q2016, the output is app lied to coaxial connecto r J 4027 and is reserved for future u se . The 02016 output is also co upled to the Calibr ator O utput Amplifier.

3 RD CONVER TER Refer to Diag ram 4 and to the b lock diag ram adj acent to

Diagram 17 . The 3rd converter co n verts th e 110 MHz IF signal to 10 MHz for application to the Variable R esolution circuits. It also generates t he 100 MHz signal fo r the 3rd Co nverter, th e front panel CA L O UT signal, and the 110 MHz reference for most of t he phaselock loops in the analyzer. The circuits co nsist of an oscillator and d river, four identical reference output am plifiers, α mixer, and α cali brato r out p ut am plifier.

Refer to Diag ram 17 while reading this description . Oscillator/Drive r Circuit The oscillator Q3041 is of the Colpitts configuration with α 100 MHz microwave type crystal operating in the series resonant mode in the feed bac k loop . That the crystal is α microwave type in dicates that it is not only α high-0 type, but that it is mounted at three points to alleviate mec h anical vibration problems . (The components insi de the d as hed line immediately below crystal Υ 3036 in Diag ram 17 are included for future use only and are n ot described here .) Tuning capacitor C3031 in the collector circuit serves to adjust fo r maximum outpu t.

5-22

Mixer Ci rc u it The mixer ci rcuit combines the 100 MH z oscillator freq uency with t he 110 MH z I F signal from the 110 MH z Band pass Filter to produce the 10 MHz IF output signal . From transformer Τ2026 of the d river ci rcuit (02036), the 100 MHz signal is applied to transformer Τ2041, whic h converts t h e single-ended driver output to α balanced signal to d rive the push-pull am plifier that drives the mixer. This amplifier co nsists of transistors 01048 and 02046 and provides α balanced signal, co upled through transformer Τ3053 to diode ri ng mixer C R2054 . The signal level of the 100 MHz, app lied to the mixer, is approximately 100 milliwatts to provide adequ ate intermodulation distortion performance. The 110 MH z IF, t hroug h B andp ass Filter (FL36), is applied through coaxial connector J2058, the impedance matc hing LC circuit that consists of inducto r L 1055 and capacitor C1056, and tran sformer Τ1053, to the mixer. The 10 MHz outp ut from the ce nter ta p of T1 053 is applied through α di plexer and coaxial connector J3057 to the Variable Resol ution circuits . Loss through the mixe r is typically 9 dB. The input level from th e 110 MHz bandp ass filter is n ominally -26 dB m and the output to the Va r ia ble Resolution ci rcuits is nominally -35 dBm. REV A UG 1981

Theory of Ope ratio n -492/492P Service Vol . 1 (SN Β030000 & up) Cali bration Ou tp ut Amplifier

Th e calibrator out p ut amplifier is α d ifferen tial amplifier (02031 an d 01031) t h at is ove rd riven . With low levels of drive, this amplifie r wo u l d operate as α small-sig n al amplifier . Howeve r, wit h t h e h ig h e r positive and negative levels from refe rence amplifie r 02016, th e t ran sistors are eit her driven hard or are n ot conducti n g at all. Si nce the t ra n sistors a re over d riven , th e current in t h e output side (01031) is the do b ias current wh e n t h at side is conducti n g. Ch angi n g the bias c urre nt will t herefore c h ange t he o u tp ut voltage. Th us, th e outpu t is determined by internal d o levels, not i n p ut sig nal levels . Potentiometer R 1045 p rovides for adjustme n t of t hat quiesce n t current. Th e output fre qu e ncy is sta b le an d r ich in h armonics . Thu s, it provi d es α useful sign al comb of 100 MHz markers to approximately 2 GH z. At 100 MH z, th e o utput level is set b y R 1045 for -20 dB m whic h is a pplied to the fron t panel CA L OU T connector t h rou g h coaxial co nnector J 1015 .

In orde r th at each d ivision of sig n al ch a n ge on t h e crt screen be e q ual to that for eac h oth er division and be equ valen t to α simila r signal level c h a nge in dB, α loga r it hmic amp lification of t h e sig nal is required . Th is is done b y α seven stage am plifier th at pro du ces an ou tput th at is proportio n al to th e logar ithm of th e input. Thus, th e sc reen d isplacement can be selecta b le as to amount of c h a nge per divisions, and can be p roportional to th e input level chan ge. For i n stance, i n t he 10 dB per divisio n mode, each divisio n of d isplaceme n t in t he screen represents α signal level ch a n ge of 10 dB regardless of wh et her it is at t he top o r bottom of th e screen .

F ollowi n g t he logarith mic am plifier , an area detector produces α positive-going pulse o ut pu t t h at is applied to th e d isplay section as t h e V ID E O sig n al .

Va riable R esol utio n Sectio n

00*

The Var iable Resolutio n (VR) ci rcuits p rovide selectio n of

resolution bandwidth u n d e r microcom pute r cont rol, an d ap-

IF S ECTIO N The I F section receives the 10 MH z I F sig nal from th e 3rd Converter, establishes t he system resolu tion throug h selective filteri ng, levels t he gai n for all b ands, and logarith mically am p lifies an d d etects th e sign al to produ ce th e vi d eo output to th e Dis play section. System resolution is selecta b le, u n d e r microcom p uter co n t rol, among five bandwidths: 1 MH z, 100 kH z, 10 kH z, 1 kH z, and 100 Hz . (Some 30 H z circuits are included for fu tu re use .) Th is selection is done i n the Variable Resol utio n ci rcuit bloc k by two sets of filte r s. Bandpass filters are also included at th e ci rcu its in put and output . Significan t gai n is provided in th e resol ution ci rcuit block by several stages of amplification . Also, th e capa b ility to add oth er gai n steps unde r microcom pu te r co nt rol is provided b y switching attenuators in o r ou t of t he sig n al path . T hese attenuators, by bei n g switched in combin ation , provide for 10, 20, 30, or 40 dB of additional gain .

Leveling to com pensate for i n strume n t front-en d losses is also included i n th e resol u tion ci rcu it bloc k . Front-end losses occ u r primarily in the h ig h e r frequen cy ban ds ; t herefore, most b and leveli ng am plification is req u ire d in th ose ban ds .

REV AU G 1981

proximately 35 d B of system gain . It consists of two sets of filters a nd various gai n leveling stages . Si nce t he i nput to th e VR ci rcuits is nomi n ally at -35 dBm an d the Log Amplifier input mu st be 0 dB m for f u ll screen , th e VR ci rcuits must provide th e gai n difference . Also, add ition al gain (up to 40 dB) is required for operation in t he 2 dB /DI V or the linear mode plus compensatio n for variation s in front end losses .

Ph ysically, t he VR section co n sists of two su bassemblies th at pl u g onto th e analyzer mot h e r board. Th e input ci rcuits are in on e s ub -assem bly ; the out put section and digital interface are i n t he oth er . E ach of th e sub-assemblies con sists of boards t h at plug onto α four-layer mot her board with α ground plane on bot h outsi de layers. Only power supply and control voltages travel t h rou g h the moth er board. All sig n al interconn ection is via coaxial ca b le . Circ u its fo r t he VR sectio n are con tained on three d iagrams : 18, 19, a nd 20 . Th e followi ng par ag ra ph s descri b e the ci rcuits.

I nput Ci rc u it

I

18

T he VR nput ci r cuit receives th e -35 d B m 10 MH z signal from t he 3 r d M ixe r th rough J 693. This sig n al is applied to α two-pole, 1 .2 MHz bandpass filter th at au gmen ts t he 1 MHz filte r t hat precedes t h e 3 rd Mixer and provides initial selectivity. T h is 1 .2 MH z filte r includes C1037 a nd C1031 an d all of the compon e n ts between . Filter t u ning is p rovided by variable cap acitors C1033 and C1026.

5- 23

Theory of Operation-492/49212 Service Vol . 1 (SN Β030000 & up)

F rom the filter, the signal is app lied to b ιoadband feedb ack am plifier 01023, which is b iased at α relatively substantial output current (a pproximately 50 mA) to exhibit good intermοdu lation distortion performance. This performa nce is provided pr imarily through t he large cur rent capacity, b y negative feedback through resistor R 1025 and by emitter degene ratio n resisto r R1023 . At the outpu t of am plifier Q1023 is α 6 dB attenuator t h at provides α clean 50 Ω output to th e 1 st F ilter Select ci rcuits and reflects α 50 Ω termination back through the amplifier for proper termination of the 1 .2 MHz bandpass filter. The output sign al is transmitte d via jumper Β. 1 at F ilter Select Ci rcu it

T he VR 1 st Filte r Select circuit operates in conj unctio n with the 2nd Filter Select ci rcuit to determi ne the overall system bandwidth t hrough banks of switched filters that are selectable under control of the analyzer microcom puter. Data bits 0, 1, and 2 from the d ata b us are applied to decimal decode r IC U4035, whic h e nables the selected filter b y providing α low signal on the appropriate output pin . Bandwidth selections are 1 MHz to 100 Hz in decade steps. (Note that 100 H z resolution is part of Option 03 .) Th e data bits select α filter bandwi dth accord ing to the following table . Table 5-4

B ANDWIDTH SELECTION Ba ndwi dth

DBO

DB 1

DB2

1

0

0

0

1

0

100 kH z

1

1

0

10 kH z

1

0

0

1 kH z

1

0

1

0

1

1

1 MH z

100 Hz 30 Hz (for future u se)

Selection of filters is d one by PIN diode switching. At the in put and output of each filter is α series an d α shu nt d iode. When α filter is selected, the se ries diodes are biased on and t he shunt diodes are biased off. For the filters t h at are not selected (only one is on at α time), the diode co nd itio ns are opposite . Since th e switching operatio n is the same for all filters, the following description of the 100 kH z filter selection is app lica ble to all with a ppropriate component designato rs. If we assume α co ntent of 010 for t he three data bits, line 2 from U4035 will be low. This will turn on transistors 03019

5- 24

and 03055, whic h operate as d o switches . With input switch 03019 turned on, the current path is through R4012, L3012, CR3010, L3013, R3014, and 03019. This current is determi ned by decoupling resisto r R 3014 a nd resistor R4012, which is common to all filters, a nd is sufficient to turn C R3010 on e noug h th at it appea rs to be merely α resisto r to RF. At the same time, the voltage d rop across R4012 is sufficie n t to reverse-b ias CR3012 . The same operatio nal situatio n exists for th e filter outp ut switch, Q3055. Resisto rs R3057 a n d R1067 establish t he cu rrent to forwar d-bias CR 3061 and reverse- bias CR3060 . Thus, the signal from the Input ci rcuit via j umpe r Β is applied through t he selected filter and transmitted to the 10 dB Gain Steps ci rcuit via ju mper Κ. Nominal loss through t he filter circuit is approximately 8 dB, with slig ht variations among the filters. The output level is nomi nally -27 dBm. In the non-selected filter sections, th e inp ut and outpu t switch transistors are tu rned off b y t h e high ou tputs from decimal decoder U 4035 . The collectors are pυllIed toward -15 V by pu lldow n resistors, th us forward biasi ng the shunt diodes (inp ut : CR3014, CR2013, CR2011, CR1013, and CR1011 ; output : CR3062, CR2066, CR2055, CR 1055, and CR4065). Si n ce one filter is always selected, the voltage drop ac ross the common input and o utput resistors (134012 and R 1067, respectively) provides for back biasing the series d iodes (input : CR3011, CR3012, CR2010, CR1012, and CR1010 ; output: CR4068, CR2062, CR2059, CR1059, and CR4064). N ote that input and output switching is provided on the board fo r futu re use with 30 H z r esolution. Design of the filter for each band widt h is determined by of each band and ranges in com p lexity from no filter at all to α com plex two-cηstal arra ngement .

t he r equireme nts

In the 1 MHz section no filter is used, because this circuit section is preceded by two filters that accomplish t h e requ ired f unction. The fi rst is the 1 MHz filter between the 2nd and 3 rd Co nverters ; the second is the 1 .2 MH z filter in t he VR In put ci rcuit . Instead of α filter, α 6 dB attenuator is contained in the 1 MH z selectio n ci rcuit . This attenuator provides initial leveli ng to compensate for less loss because no filter is used . The 100 kHz filter is α double-tuned LC circ uit that is

d esig ned fo r α good time-domain response shape. Variable

capacitors C3023 and C3035 provide for inp ut and outpu t adjustments . Impe dance matching is accomplished at b ot h inp ut and o utpu t b y series ca pacitors C3020 (i nput) and C3048 (output). The 10 kH z filter uses α p air of two-pole mo nolit hic crystal filters that are interconnected by va riable shu nt capaci-

REV AUG 1981

Theory of Operation-492/492P Service Vol . 1 (S N Β030000 & up) for C2037. In pu t and o utput impedances are matched with broadband tra n sformers Τ3026 and Τ3055 . Α 3 d B attenuator, consisting of 82027, 82026, and 82028, is included at the filter inpu t. The 1 kH z resolution filter consists of α si ngle two-pole mo nolit hic crystal filter, matched to the 50 Ω impedance with broadband transforme rs Τ2035 and Τ2055 . Α 2 dB atte nu ator, consisting of 82024, 82023, and 82025 is also part of the filter. The 100 Hz filter u ses α pair of h ig h Q crystals in α b alanced two-pole ladder config uration . These crystals are matched for both frequency and temperature characteristics . Inp ut an d output im peda nce matc hing is accomplished primarily by transformers Τ1025 and Τ1039 . Two small capacitors in the same transformer ci rcuit as the crystals (C1030 a nd C1035) are adjustable to cancel the parallel capacitan ce effect of the crystals . Also, α 2 dB attenuator is incl ud ed at the filter input and consists of resistors 81026, 81028, a nd 81027. 10 dB Gai n Step Ci rcuit

T he 10 dB Gain circuit provides 10 dB of signal gain when selected b y the microcom puter. The ci rcuit consists of t hree stages of amplification , one stage p rovides variable gain, the other two are fixed gain steps. The n ominal input signal level from the 1 st Filter Select circuit is -26 dB m for α r esolution bandwidth of 100 kHz. (All levels listed in this description relate to the 100 kHz resol ution.) T he inp ut signal is applied through an impeda nce t ran sforme r, Τ3019, to the first am plifier stage co nsisting of α differe ntial pai r (03016 and Q2027) an d an emitter follower output am plifier (01036). N egative feedbac k through 81031 and 82051, provide gain stabilizatio n. An o utput resistor, 82035, increases t h e outp ut impedance of the composite am plifier to approximately 50 Ω. Gain of the input stage is fixed for all resolution b andwidths except 30 H z. (in instru ments that may h ave the 30 Hz resolution bandwidth capability, th e gain for 30 Hz will b e set to α precise level by activating Q2015. Transistor Q2015 is b iased on by α low on p in L. This add s R2025 (30 H z level) across feed back resisto r 82051 . Adj ustment 82025 can now set the gai n of the stage.) The outpu t from the 1 st stage is then app lied to α common emiter stage (02043). Gain of this stage, when transisto r 04039 is turned on, is 10 dB . Wh en t he b ase of 04039 is pulled low b y data b it 0 from Q4035 on the VR mother board #1, the transistor satu rates an d s hunts the emitter load resisto r R3048 with R3038 and th e 10 dB Gain adju stment 83035.

REV AUG 1981

The output of Q2043 dr ives the input of the thi rd amplifier stage. This stage operates the same as th e fi rst stage except for gain variation . Feedback resistor 81060 is shu nted by PIN diode CR1053 . As the current thro ugh the diode increases, the resistance decreases and t he gain of the stage increases. Gain control of th e stage is esta blished b y the setting of the front panel AMPL CA L adjustment. Gain range is about 14 dB. Output impedance of the stage is 50 Ω, set b y resistor 81064. N omi n al output level is -5 dBm fo r α full scree n dis play. This level may be as h ig h as +5 dB m wh en MIN N OISE is active . 10 dB of gain is also removed from the Log Am plifie r to reduce the noise level and must be supplied by the VR sectio n. 20

d S Gain

Steps Ci rcuit

The 20 dB Gain Steps circuit provides -6 dB, +4 dB, +14 dB, and +24 dB of gai n in precise 10 dB steps. The nominal -5 dBm input is supplied through pin Ρ from the 10 dB Gain Steps ci rcuit . This signal is applied to α c hai n of t h ree common-emitter am plifiers, eac h usi ng emitte r degene ration. Changi ng the emitter resistance is u sed to change amplifier gain under the d irection of the microcomputer. T he nominal gain of the complete circ uit is -6 dB, with 02018, 02042 an d Q1062 biased off. This pr ovides α nominal -11 dBm output . In this cond ition, co ntrol p ins V a nd Υ are hig h, causing switching transistors Q2018, 02042, and Q1062 to be cut off.

Wh e n pin V is low, Q2018 and 02042 are saturated, raising the total gain of the first two am plifiers 20 dB . Varia ble resisto r R2025 is used to adjust th e gain shift of the first stage (Q1025) while the gain s hift of th e second stage (01035) is fixed at +10 dB . This adj ustme nt allows the gain shift to be exactly set to +20 dB . When pin Υ is low, 01062 is saturated, raising the gain of t he thir d amplifier (Q1043) by 10 dB. Variable resisto r 81063 allows the gain s hift to be exactly set to +10 dB . Data bits 2, 1, and 0 control the gains of the 10 dB Gain Steps circuit and the 20 dB Gain Steps circuit . B it 2 controls pin V, b it 1 controls pin Υ, and b it 0 controls pin Ν . T he d ata is decoded a nd stored in latc hes on the VR mother boa rd #2 . Table 5-5 s hows the state of b its 2, 1, and 0 an d the gain shifts of am plifier stages 02043, 01025, 01035, and 01043. The output of the 20 d B Gain Steps ci rcuit is attached to coaxial connector J 2031 . The signal is routed t hrough α double coaxial cable to the B and Leveling ci rcuit .

5- 25

Vol .

Theory of Operation-492/492P Service

1 (S N Β 030000 & up) Ta ble 5-5 GAIN STEP CO MB I NATIO NS

R eq u ire d

Data

Gai n Add itio n

Bits

10 d B Gai n Step s Ci rcu it

20 dB Gain Ste ps Circ u it

Pi n

2

1

0

02043

Pin Ν

01025+01035

10 dB

0

0

1

10 dB

0

O dB

1

0 db

1

20 dB

1

0

0

O dB

1

20 d B

0

O dB

1

30 d B

1

0

1

10 d B

0

20 dB

0

O dB

1

40 d B

1

1

1

10 d B

0

20 dB

0

10 db

0

Bon d Leveling

Ci rc u it

The two am plifiers i n t he VR B a n d Leveling circuit co rrect t he gain variations cau sed by th e front en d . Th ese ba nd -tob and va riatio n s a re ca u sed by mixi ng of diffe re nt harmonics i n th e 1st converte r a nd losses from t he preselector . Th e output level of t h is board is -2 dB m wh ile th e nominal npu t is -11 dBm . Th is i nput level occu rs on band 1 (at 100 kHz resol u tion n M i n Distortio n mode) but dec reases i n the higher bands ; the o ut put is k ept con stan t by usi n g th e microcom pu te r to adj ust the amp lification for eac h ba nd .

i

i

Th e two am p lifier b lock s in th is circuit are similar to th e block s i n the 10 dB Gai n Steps ci rcuit . The b lock is α threetransistor circuit usi ng α diffe r ential p ai r co nnected to an emitter-followe r. The gai n is controlled b y alter i ng th e feedback n etwork .

From t he 20 d B Gai n Steps circuit, t h e sig nal is a pplied through α double-shielded coaxial cable an d J 683 . It is se nt through in put t ra n sforme r Τ2013 to th e first amplifier block . The first b lock (Q2015, Q2014, and 01025) h as α gai n ran ge of 13 .5 dB by u si ng α PIN diode (C R2021) i n t he feedbac k loop . T he bias fo r t h is diode comes from an array of varia b le resistors on t he VR mot her board #2, with t he i ndivid u al resisto r selected by th e mic rocomputer .

The secon d block is similar exce p t th at th e gain ch a nge occurs in o ne ste p of a pproximately 12 .5 d B . Th is gai n step occurs only in th e h ig her ban ds and is activated by the microcom pute r throug h use r-selecte d d iod es on th e VR moth e r board #2 . T he 492/492 Ρ is nor mally calibrated wit h t h e ba nd 1 gain

cont rol resistor set fo r minimum gain . Gain is th en added as

5- 2 6

V

01043

re q ui red for the high er b ands . Data band selectio n .

b its 6,

Pin Υ

5, 4, an d 3 con t rol

T he o u t pu t from th e second amp lifie r block is applie d t h rou g h co nnector EE to t he VR 2 nd Filte r Select ci rcu it . 2 nd

F ilter

Select Ci rc u its

* The VR 2 nd F ilter Select circuit ope r ates in conju nctio n wit h th e 1 st F ilter Select circ u it to determi ne t h e ove r all system band wi d t h t hrou g h banks of switch ed filters th at a re selectable und er con t rol of t he a n alyzer microcomputer. Data bits 0, 1, and 2 from t he data bus are a pp lied to decimal d eco der U 3070, whic h ena b les th e selected filter by providing α low sig n al on the app ropriate output p i n . B a nd widt h selection s a re 1 MHz to 100 Hz n decade steps .

i

N ote t h at 100 Hz resolution is p art of O ption 03. Also note that, alt ho ug h th e 2 nd Filter Select ci rc u it is similar to the 1 st F ilter Select ci rcuit, no 30 Hz switch ing circu its a re included on t he b oard fo r futu re use. When 30 Hz resolution is incorporated, t h e 30 H z ba n dwid t h will use th e 1 kH z filter in th e 2n d Filte r Select ci rcuit. Th is can be seen in th e connection b etween p i n s 6 a nd 7 on decimal decoder U3070, th us res u lting in li n e 11 being low for bot h 1 kHz and 30 Hz ban dwidth sectio n s .

T he data b its select α filter b a ndwidt h as described in Ta b le 5-6 . Filte r selectio n is accomp lis h ed as d esc ribe d for t h e list F ilter Select ci rcuit . T hus, t he sign al from th e B a nd Leveli n g ci rcuit via jumpe r EE is ap p lied t hroug h t h e selected filte r and t ra n smitted to t he Post VR Am plifier ci rc u it via jumpe r JJ . Nomi n al loss t hrou g h th e filter circu it is a pproximately 14 d B , with nte rn al adj u stment compe n sation fo r slig h t va riation s amo ng th e filter s. The output level is nomi n ally -16 dBm .

i

REV AUG 1981

Theory of Operation-492/492P Service Vol. 1 (SN Β030000 & up) Ta ble 5-6 PR OGRESSION OF GAIN RE DUCTION Input L evel Χ -10 d B Χ Level Χ +10

dB

Χ +20 dB Χ +30 d B Χ +40 d B Χ +50 d B

Point 2

Point 1

P oint

0.316

0.1

0 .1

0.316

3

4

Beyond L ogging Range 0 .01

0 .00316

0.316

0.01

F-0.684 1 .0 0.316 F0.684 F-0.684 -----~ 1 .684 1 .0 --I F- 0.684 -~ F- 0 .684 1 .684 2.368

0.1 0.316 ~- 0.684 1 .0 3.16

0 .316

0 .1

0 .0316

1 .0

1 .684 2 .368 3.052

0 .216 }0 .684 }0.684 ~0.684 10 .684

B eyond Logging Range

Switching in the othe r, non-selected filter sectio ns, is accomplished as described in the 1 st Filte r Select ci rcuit paragraph s. Also as described in th ose p arag raphs, the d esig n of the filter for each ba ndwidth is determined by the requirements for eac h band a nd ranges from no filter at all to α complex two crystal arrangement. An important design d ifferen ce is that the 2nd Filter Select ci rcuit contai n s α variable resistor in the attenuator that follows the input switch in all exce pt t he 100 kH z ci rcuit. The pu rpose of this adjustment is to allow cali bration of all ot her ci rcuits to matc h t he 100 kH z circ uit . The Band Leveling circuit furnis hes compensation gain to obtain equal signal levels for all ban ds . Thus, the cali bration is required only to remove variatio ns between t he filters by adjustments R1065, R3035, R3025, and R3015 . It is in the 1 MH z sectio n that no filter is used . This is because this ci rcuit sectio n is preceded by the 1 MHz (wide) filter between the 2nd and 3rd Converters an d t he 1 .2 MH z filter in the VR np ut circuit . Those filters accomplish t h e required fun ctio n. Thu s, instead of α filter, an attenuator that incl udes the calibratio n adjustme nt is contained in t he 1 MH z selection circuit . This atten uato r compensates (offsets) the gain loss associated with α filter in the other resolution circuits.

I

The 100 kHz filter is α double-t uned LC ci rcuit that is designed for α good time-domai n respo nse shape. Va riable capacitors C2050 and C5055 p rovide for filter tu ning. Α 6 dB attenuato r (resistors R2048, R2047, and R2049) is included at t h e filter in pu t. This atte nuato r and the filter form α reference to which the levels of the other ci rcuits are calibrated. Impeda n ce matching is accomplished at both input an d output by series ca pacitors C1047 and C6052.

REV AUG 1981

P oi nt

The 10 kH z filter uses α two-pole monolithic crystal filter . The impedan ces at the inp ut and o utput are matched to 50 Ω by Τ4044 and Τ7050 . An attenuator t hat contains the cali br ation adju stme nt is incl uded at the filter inp ut fo r filter va riation compensation . The 1 kH z filter also uses α two-pole monolit hic crystal filter with impeda nce matc hing transfo rmers Τ4030 and Τ7038 at the input and outpu t. An attenuato r t hat contains the cali bration adju stment is incl uded at the filter inpu t for filter variation compensation . The 100 H z filter uses α pair of h ig h-0 crystals in α balanced two-pole ladder config uration. These crystals are matched for bot h freque ncy and temperature characteristics . Input and output impeda nce matc hing is accomplished primarily by transformers Τ4019 and Τ7015 . Two small capacitors in the same transformer ci rcuit as the crystals (C6011 and C7011) are adjustable to ca ncel the p arallel capacitance effect of the crystals . An attenuator that contains the cali bration adju stment is incl uded at the filter input for filter variation compensation .

P ost VR Am plifier Circ uit

Th e P ost VR Amplifier ci rcuit provides the fi nal VR system gain to bring the signal to the required output level and provides the fi nal bandpass filtering to assure clea n performance. The ci rcuit consists of two stages of gain followed by α filter. Fr om the 2n d Filter Select ci rcuit, the signal is applied

through jumpe r JJ to the input of common emitter am plifier

5- 27

Theory of Operation-492/492P Service Vol . 1 (S N Β030000 & up) transistor 02056. The circuit incl ud es potentiometer R2038 in the emitte r circuit to allow for a dj usting the post VR amplifier gain. The outpu t is transformer coupled by T1 059 to the b ase of feedbac k am plifier transistor Q1048 . Th is circuit incl ud es emitte r dege ner ation t hrough resistor R2042 and collector-to-base feedbac k th roug h resistor 81052. The collector feedb ack is used in th is in stance to hel p provide α well-defined output impe dance of 50 Ω. I nput impedance to this stage is defined by tr a n sforme r T1 059 and resisto r 81058 across the primary. This final VR am plifier stage is biased for relatively h ig h output current. This is required because the VR system is

sometimes driven at an increased o utpu t level of +10 dBm, and more current is required to prevent gain compression. Α h ig her output level is required i n low n oise or low intermodulation distortion operation to compensate for the 10 dB of gain that is switched out of the Log Amplifier .

From t h e fin al amplifier, th e signal is app lied through the 1 .2 MHz b andpass filter th at consists of ca pacitors C2033 a n d C2018 an d the compo n e nts betwee n. Th is filter is α d ou ble-t uned design and h as an i nsertion loss of approximately 2 dB . As an aid to understandi ng the overall VR system functions, it is helpful to un de rstand some aspects of filter design. When designing α wide-bandp ass filter, on the order of te n perce nt or g reater, stop-band attenuation becomes α severe pro blem in two-pole filters. The result is that α given filter design will dege nerate into either α h igh-pass or α lowpass filter . The desig n of the filter i n the P ost VR Amplifier ci rcuit degenerates into α low-pass un it . H owever, since the VR system incl udes α bandpass filter at both the inp ut and the output, and since the input filter in the VR Input circuit degenerates into α high-pass unit, the overall VR system exhibits clea n stop-band performa nce. The output signal from the filter is applied t hrough coaxial co nnector J682 to the Log Am plifier. The output level is nominally at 0 dBm. Digital Co ntrol Ci rcuits

19

The Digital Control circuits provide address and data decoding for the bandwi dth and gain step selection and band identification for the b and leveli ng gain control, and provide the control signals to the ot her sectio ns of the VR system to accomplish those tasks. Address and data valid li nes from t he analyzer address bu s are applie d to address decoder U4022 through connector Ρ 1049 p ins 9, 10, 12, 13, 14, and 20. Data bit 7 is also applied through P1 049 pin 7 as α suppleme ntal address b it to select between the latc h that stores data for band widt h

5-28

selection, and the latch that stores data for band identification and gain step selection. Data li nes from the analyzer data bus are applied through connector P1 044 p ins 1, 2, 3, 4, 5, 6, and 8 to d ata latc hes U3010 and U 3017 . Note that only data bits 0, 1, and 2 are a pplied to latch U3010 .

Latch U3010 stores th e data that selects among the filters in th e 1 st and 2nd Filter Select circuits. Outputs from p ins 2, 19, and 16 of U 3010 are applied to the decimal d ecoders in th e filter select circuits through edge connecto r p ins G, F, and Ε to control the filter selection. Decoding is do n e within th e filter select circuits because it results in fewer lines betwee n circuits and provides extra buffering to reduce noise transmission between ci rcuits.

Latch U3017 stores the d ata that select among the various gain steps and that identify the selected f req uency band for control of the b and leveling fu nction. Outp uts from pins 2, 5, and 6 (corresponding to d ata bits 0, 1, and 2) are applie d to inverter t ransistors 04035, Q3035, and 04037, respectively . From Q4035, the output signal is app lied through co nnecto r P1 049 pi n 32 to the 10 dB Gain Steps circuit to control gain switching. From Q3035, the output signal is app lied t hroug h edge co nnector pin 25 to the 20 dB Gai n Steps circ uit to con trol switching of the 10 dB gain switch; from Q4037, the output signal is applied through edge conn ector pin 27 to the 20 dB Gain Steps circuit to co ntrol switching of the 20 dB gain step. Outputs from latch U3017 pins 15, 16, 19, and 12 (correspo ndi ng to data bits 3, 4, 5, and 6) are applied to band decode r U3025, an open collector deco de r. If b and 1 is selected, pin 1 output is low. Th ese outputs are used i n conjunction with α 7 .5 volt reference source, provi ded by operatio n al am p lifie r U 3038 B a nd d river transistor 03036, to produce sign als th at are applied to α seco nd operatio nal am plifier ( U 3038A) . These signals correspond to th e amoun t of gain that must be su pplied fo r each band to level the output for all bands. The analog output from U 3038A is applied through edge conn ector pin BB to the gain control PIN diode in t he Band Leveling circuit . For example ; if b and 1 were selected (U3025 pin 1 low), the current p at h is through potentiometer R2031 and the emitte r of 03036. From the potentiometer arm, the voltage is app lied through resistor R2033 to the summing junction at the input to operational amplifier U3038A, d riving that ju nction more negative. This s hifts the output from U 3038A mo re positive to increase the current through band leveli ng PIN diode CR2025. Potentiometer R2031 provides for cali br ating the current through the PIN diode for band 1 . In simila r fashio n, the ot her potentiometers (83034, 83030, 83019, 83022, 83024, 83026, 83032, 83029, and 83025) allow fo r adjusti ng the current fo r each of the other bands.

REV AUG 1981

Theory of Operation-492/492P Service Vol. 1 (S N Β030000 & up) Also, for b ands 4 through 10, α diode may b e connected to each decoder output to transmit that low signal via edge connecto r pin DD to the gain co ntrol transistor in t h e Ban d Leveling ci rcuit to increase the gain in each of those bands. Those diodes are CR3022, CR3023, CR3024, CR3025, C R3031, C R3027, and C R3026, and are installed dur ing final i nstru ment calibratio n.

t h at gain was reduced to u nity, the total gain reduction is 70 dB . Wit h further increases in input signal level, three more gain change steps take place . T he gain of the fi rst t hree stages is reduced below u nity approximately 7 dB for each stage. This reduction starts with the first stage and proceeds to the thir d, to provide an additional gai n reduction of approximately 20 dB .

5 Volt R eg ulator Circuit

Thu s, as th e input signal increases from -90 dB m to +10 dB m, the gain through t he am plifier dec reases loga rithmically so that the output signal is exactly proportional to the loga rit hm of the in pu t. This is accomplished t hro ugh α system of series d iode limiti ng in each stage, with α second set of diodes fo r extra limiti ng in each of the first three stages . Refer to Diagram 21 while reading the following.

The 5 Volt Regulator ci rcuit (U3041) su pp lies the required 5 volt source fo r use in several sections of the VR system . This is required because of noise in the 5 volt supply .

L OGA RIT HM IC A MPLI FI ER AND D E T E CTO R * Refer to the block diag ram adjacent to Diag ram 21 . The

Logarit hmic (Log) Amplifier and Detector accepts input signals from the VR ci rcuits, with α d y n amic ran ge to 90 dB . It

then am plifies these signals so th e outpu t is proportional to the logarit hm of t h e input, an d ap plies the signals to α linear detector to produce the video outpu t signal . B y controlling th e compression curve characteristics, each d B of change in the input signal level results in an equal increment of change in the output. Th us, in the 10 dB/division mode, each divisio n of displacement on the screen represents 10 dB of input sign al level change .

L og

Amplifier Ci rcuits

The following desc ription of α simple three-stage log amplifier with one gain step i n each stage is p rovided as an aid to understandi ng the concept of α loga rithmic am plifier. For t he exam ple am plifier s hown i n th e following th ree figures and described i n the text, the gain of eac h stage is 3 .16 V (10 dB) up to an o utput level of 1 volt peak, then u nity for output levels greater than 1 volt pea k; that is, eac h stage uses one breakpoint. The breakpoint voltage is use d for ease of illustration; the actual b reakpoint voltage is significantly lower.

Figure 5-9 ill ustrates th e amplifie r an d the in pu t signal source . F o r pu rposes of disc ussion , assume that the source h as α step attenuator at the outpu t that will allow incrementing the inp ut signal in 10 dB steps. Ta ble 5-6 shows the p rogression of gain reductio n above 1 volt at each am plifier stage outp ut. N ote that with each i nput level change of 10 dB, the output change at point 4 is 0.684 volt . Th e gain curve for one stage is illustrated in Fig . 5-10 . Also n ote, when the level at point 1 is increased beyond 1 volt it is beyond t he logging range of the am plifier . Similarly, if t he input level is decreased 10 dB below t he nomin al mi nimum input level, the output increment is different. Α curve of t he en ds of the logging range is shown i n Fig . 5-11 .

The Log Amplifier circuits logarithmically amplify the input signal from the VR ci rcuits and apply the outp ut signal to the Detector circuit. These circ uits co nsist of seven ac co up led am plifier stages . Eac h stage h as two gain val ues that d epen d on signal amplitude. In addition, th e first three stages have an extra automatically selected gain val ue. The combined circuits provide high gain for low-level signals and low gain for h ig h-level signals. F or the output signal to be proportio n al to th e logarithm of the input, mo re gain is r equired for α c h a nge fr om -90 dB m to -89 dBm than α c h a nge from -1 d Bm to 0 dBm. Thus, fo r α given stage of the seven, the gain starts at approximately 10 dB for α lowlevel signal and decreases to unity as th e input signal level in c reases. In the first three stages, the gain becomes less than u nity as the signal am plitud e furt her increases.

From the VR circuits, the signal is app lied to inp ut preamplifier Q3105 in th e Log Amplifier circuits through coaxial connecto r Ρ621 . The input p reamplifier provides tran sfer from 50 Ω in put to the h igh impedance inp ut of the 1 st amplifier stage. The inp ut signal is also applied to tran sistor 02105, α common-base am plifier, that acts as α b uffe r to su pply the 10 MH z IF signal to the rear panel conn ector.

Input signal levels nominally range between -90 dB m an d 0 dB m. As the signal level increases, the gain decrease begi ns with the final stage and p roceeds in succession back through the remaining six stages to the first. Since each stage produced ap proximately 10 dB of gain initially, and

F rom t h e input preamplifier, the signal is app lied to the fi rst of seven cascaded am plifiers that consist of 03100/ 01095, Q3090/Q1080, 03075/Q1020, Q3055/Q1050, Q3045/01035, Q3030/01025, an d Q3015/Q6010, pl us the associated ci rcuitry . These stages are similar, exce pt that

REV AUG 1981

5- 29

T heory of Operation-492/492P Service Vol . 1 (SN Β030000 & up)

POINT 1

POINT 2

POINT 3

POINT 4

L OAD

SIGNAL SO UR CE

2727-109

Fig. 5-9. Three-stage log amp lifier.

+1 .Ββ 4 VOLTS OUT +1

-1

BREAKPOI NT

-0.318 +0.31 β

+1

VOLTS IN

-1 .884

Fig . 5-11 . Ends of loggi ng range . τ7τ7-11 ο

Fig . 5-10 . Log amplifier gain cu rve s howing breakpoi nt.

the fi rst three contain an extra set of diodes for α second gain step . The following desc ription of the last stage is typical. The seco nd step gai n c hange in t he fi rst three stages is descr ibed afterwar d.

5- 30

Wh en the in pu t level to transistor Q3015 is less than approximately 60 millivolts pea k-to- p eak , t h e transistor co nducts enough to maintain forward bias on both series limiting d iodes, CR4015 and C R4012 . T he RF signal path at t hat level is throug h the diodes, capacitor C5014, an d resisto rs R4010H , R4010 B, R4015, and R4010D, to commonb ase am plifier 06010. The gain of the stage is ap proximately 10 dB under these co nditions. As the input

REV AUG 1981

Theory of Op eration-492/492P Service Vol . 1 (S N Β030000 & up) sig n al voltage increases, more current flows t hrou g h C R 4015, to i n c r ease th e reverse bias of CR 4012 . T his sharply re duces the stage gain to u n ity. T he signal curre n t t hen flows only in R4010 B , R4015, an d R 4010D. T his ch ange tak es p lace du ri n g the positive-goi ng portion of each cycle. T h e o pp osite occurs during th e negative-going portio n of the sig n al above t h e minim u m i np ut level. As the i np ut sig n al in c reases beyond t he point at wh ich t h e gain of t he final stage decreases to u n ity, t he same seq uence occurs i n t h e precedi n g stage, Q3030/Q1025, and so on i n succession, bac k to t h e fi rst stage, Q3100/Q1095. Sig n al levels above t h is point activate the secon d tier of gain redu ction in th e first t h ree stages. E ach stage i nco r porates α secon d set of diodes t h at reduces t h e gain b y another 7 d B . In the first tier of gai n reduction, reductio n starte d at t h e last stage a nd proceeded to t he first ; i n th e seco nd tier, th e reductio n starts at t h e first stage an d proceeds to th e t h i rd. In th e fi rst stage, diodes CR3089 an d CR2087, are forward biased wh e n t h e stage is in the u n ity gai n mode. L imiting occu rs i n the same manner as descri be d above with α furthe r increase i n i nput sig n al level, and res u lts i n less th an unity gai n thro ug h th e stage (a pproximately 1/3) . Th e o ne, two, th ree reductio n sequen ce is esta b lish ed by th e values of pull-down resistors R3082, R 2076, and R2066 .

half cycle is ta ken as the out put (from CR 5027). Th e o utput

from th e collector of transistor 04035 is applied to th e d iodes throug h ca pacito r C5035. Ac coupling is u sed on both sides of t he detecto r to prevent tem p eratu re coefficient effects of th e operatio n al amplifier from affecti n g t he detector output . Th is isolatio n provides t hat t h e detecto r ch arges and d isc h a rges capacito rs C5035 a nd C5024 by t he c urre nt i ndu ced in eac h h alf cycle of the sig n al wit hout c h a nging voltage level. T h is detector operates as an area (aver age) d etector des pite t h e fact t h at th e Log Am plifier ci rcuits ope rate on pea k princi p les. It is possible to u se an aver age detector becau se of some very selective tailoring in t he Log Amplifier ci rcuits. Fo r i nsta n ce, resistor exam ple R5021 in t he fi nal log am plifier stage is sized to red u ce t he amoun t of current standing in th e fi n al stage ou tput d iodes, th us taperi ng t he c urve very slig htly to improve linearity at t he lower e nd of the c urve. Log Gai n adj ustme n t R4020, in the final am p lifier stage, is adj usted for inc reased li n earity at th e top of t he curve. As s h own in t he diag r am, th e positive-goi n g outp ut signal, from the d etector, is a pplied thro ug h α low-pass filter co n sisting of capacitors C7024, C7014, C7021, C7011, and in du ctors L 6011, L 8021, to th e V ideo Am p lifier.

Detector Ci rcu it Th e Detector circuit detects and filters the Log Am p lifier ci rcuit o utp ut signal and prod uces t he V ID E O signal th at is transmitted to th e Video Amp lifier ci rcuits. The circ u it consists of an operational amplifier wit h α diode detector in th e feedb ack pat h a n d α low-pass filter at th e ou tput. Act u ally, t h e ci rcuit calle d an operatio n al am plifier is not easily recog n ized as su c h . It is ma d e up of grounde d emitte r amplifie r Q4025 an d α diffe rential amplifier co n sisti ng of Q4030 and 04035. The s u mming node for the negative input is the b ase of 04025 (t h e positive input is at th e gro unde d emitter of Q4025) . Also, t h e d ifferential am p lifier is desig ned for h ig h impedance ou tpu t to allow t h e current t h at is available from 04025 to d rive the operatio n al amplifier very rap idly d uring t he perio d wh en both detector d iodes (C R 5033 a n d CR 5027) are effectively o p e n circuited ; that is, wh en t h e outpu t is near 0 volt . Wh e n n eit her dio d e is conducting, it is necessary t h at t he ou tput c hange ra pi d ly through t hat zone . N ote that t he n etwork con sisti ng of resistors R5032, R5029, R5020, an d capacitor C5029 is i ncluded to sta b ilize t h e do operati ng point .

Fig ure 5-12 shows α sim plified sch ematic diag ram of t h e d etector circuit. As s hown i n t h is d iagram, two detector diodes (C R 5033 a nd C R 5027) are used, but only t h e p ositive REV A U G 1981

DIS PLAY S E CTIO N

FUN CTIO NAL DE SC R I P TIO N T he display section performs several fu nction s: 1) it acce pts t he V ID EO sig n al from t he I F section , an d processes the signal, and provi d es th e vertical crt plate d rive signals; 2) it processes the sweep voltages from t he swee p section a n d produces t h e h orizontal crt p late d rive voltage. (If Option 02, Digital Storage is incl ud e d i n the i nstrument, vertical a nd h orizo n tal signals are furt her processed by th at ci rcuit g roup;)

3) it accepts c h a racter i nfor mation from th e i n strume n t data bu s and ge n e rates crt plate drive sig n als to dis play al ph a and nu meric c h aracters ; 4) it acce pts con trol levels from front panel beam controls a n d gener ates u n blan k i ng signals to co n trol dis play p rese nce, brightness, and focu s. Vi d eo sig n als f rom t he I F sectio n are a p plied to the V ideo Amplifie r . In th e logarithmic mode, t h e sig nal is amplified

5- 3 1

Theory of Operation-492/492P Service Vol . 1 (SN Β030000 & up)

R 6034

2727-112

Fig. 5-12. Simplifie d d etecto r circu it . linea rly a nd applied to th e V i d eo Processor . In the linear mod e, amplification is expo nential to convert th e logarithmic characteristic to linear functio n . In either mo d e baseline compe nsation , f r om t h e V ideo Processor, is applied to th e vi d eo sig n al to compensate fo r any u nflat ness in t h e f ron tend response . Also at t he ou tpu t of th e Video Am p lifie r, α pu lse stretc h circuit alters n arrow p ulses so data can be dis played by the Digital Storage logic i n instru ments th at incl ude Option 02 .

F rom t h e Video Am plifier , th e outp ut is a p plied to the Video Processor. T h ree functions are performed by t he V ideo Processor . Th e fi rst is u nflatness compensation for f ronten d respo n se variations . V ideo filtering, t h e second function performed b y this circuit block , allows for selection of six vi d eo b a ndwid t hs (30 kH z, 3 kH z, 300 H z, 30 H z, 3 Hz, and

5- 32

0.3 Hz) u nder co n trol of t he instru me n t mic rocompu ter . T he th i rd f unction is out-of-ba nd blank ing. T h is bla nk s t h e upper an d lower e nds of th e local oscillator swe p t frequen cy ra nge to provide α selected wi ndow for the d is p lay. Th is is also co n t rolled b y th e mic rocomputer. In inst rumen ts equi pped wit h Optio n 02, t he Digital Storage logic provi d es ope rator selection of various dis p lay modes for observing t he signals from t he V ideo Processor . T hese mo d es are: MAX H OLD, SAVE Α, Β-SAVE Α, VI EW Α, a nd V I EW Β and sig n al averaging or peak level d is p lay. Th e circuit b lock co n sists basically of : 1) vertical ci rcuits t h at digitize signals at 512 p oi n ts ac ross t h e dis p lay and store th ose digitized d ata for display or processing, and

REV AU G 1981

Theory of Operation-492/492P Service Vol . 1 (S N Β030000 & up) 2) h or izontal ci r cuits th at translate th e sweep sig nal i nto memory address i n to wh ich the sig n al data are stored . Th e stored sig n als a re th e n u sed fo r th e va riou s processi ng as req ui red by o p e rator d is p lay selection, and for recreation of t he disp lay. From th e Digital Storage logic, hor izon tal a nd vertical sig n als fo r t h e recreated displays are applie d to th e Deflectio n Amplifie r s. Th e Deflection Amplifiers receive vertical signals from th e Digital Storage (i n Op tio n 02 i n strume nts), or t he V i d eo Processo r , an d swee p voltage from th e Sweep section, along with readout data from t he Crt Rea d ou t ci rcuits a nd pro duce sig n als to d rive th e crt fo r t he d is p lay. In Op tio n 02 inst r uments, t he Digital Storage or Vi d eo Processor vertical outputs may be selected . In non-Option 02 inst ru me n ts, t h e Video Processor o u tpu t is d isplayed . Lik ewise, h orizo n tal sig n als from eit her the Digital Storage logic or th e Sweep section can be selected . Duri ng the display segmen ts i n wh ich d igital crt reado ut is re qu i re d , t he Deflection Am plifie rs input signals are s u pplied by th e Crt Readout logic. T he amplifier contains the switching circ u its to perform the a bove selection fu nctions, and am p lifier stages to produce th e p late drive signals. Crt rea d out data is controlled by t he Crt Read out logic. T hese ci rc u its generate letters and num bers for dis play under co ntrol of the microcomputer . U sing d ata received from th e d ata bus, α ch a racter memory an d generato r circ u it derives eac h characte r. Digital signals, desc ri b ing each character, a re th en tran slated i n to deflection sig n als by digital-toanalog con verters. Th ese sig n als are a pp lied to t h e switch ing logic i n th e Deflection Am p lifiers.

Beam i ntensity, n ominally from t h e fro n t panel, is im p lemented in the Ζ-Axis logic. Unblanki n g for display of eit her sig nals or readout data, and b aseline cli ppi n g is also im p lemented in the Ζ-Axis logic. Control of unblank ing is by signals f rom t he Swee p section , th e Crt Reado u t logic, t he Deflection Amplifiers, and th e Digital Storage logic.

VID EO A MPL I F I ER

REV AU G 1981

The Log M od e circuits acce pt the VID E O signal from the Log Amplifier an d pr ocess t h at signal to add offset for selecti n g th e segment of the log amplifier gai n curve to be d isp layed. It also allows fo r selection, under p rogram co n t rol i n the 492 Ρ, of display gain steps of 1 to 15 d B per division on the screen . (Only 2 d B a n d 10 d B/Div ar e selectable from t he front panel . Th e 492Ρ can select all steps u nder program control .) The signal from t h e Log Am plifier is a pplied to pream plifie r U 4090A. T h e V ID EO 1 signal from the V i d eo Processor is also applied to U 4090A. Th is sig n al compensates for flatness erro rs i n the fro nt-end ci rcu its b y offsetti ng t he VID EO signal in the opposite di rection equ al to th e u nflatness. T h e two sig n als a re summed at t h e input of U 4090 B with th e reference level set by In p ut Reference Level p ote n tiomete r R 4071 (t h is reference level will be descri b ed late r) a nd wit h t h e ou t pu t from digital-to-analog converter U 5041 . Converter U 5041 converts the microcom pute r comma nd s to an offset sign al whic h selects that portio n of th e Log Am p lifie r curve on wh ich to place th e display. T he concept fo r t h is offset is as follows (refer to Fig . 5-13).

T H IS 16 dB S E GMENT

MAY BE MOVE D TO ANY POSITION

LIN OU T

ON LOG CURVE

40

Refe r to th e block diagram a dj acent to Diag ram 22 . T he p rovide for t h e selection of either logarith mic or linear dis play mo d e, for th e selection of d B pe r division in loga rith mic mode, for selectio n of pulse st retc h i ng i n n arrow peak sig n al ope rations, an d for offsetting the signal amplitude dur ing th e sig n al ide ntify mode . These circuits con sist of t he log mode amplificatio n and dB/d iv switc h i ng circuits, the linear mode am plification and gain cont rol circuits, the pu lse stretch circ u it, a nd th e various digital co n t rol ci rcuits. V ideo Am plifier ci rc u its

Log Mode Ci rc u its

dB IN

2727 113

Fig. 5-13. Selection of dis p lay positio n on log scale. If t h e d is p lay is in d B/div, ch an gi n g the POSITION control, wh ic h is located after t he log amplifie r , is th e same as ch a ngi ng th e signal level, or gai n , b efore th e log am p lifie r. T h us, instea d of using α large amou n t of li n ea r gain c h a nge

5- 33

Theory of Operation-492/492P Service Vol . 1 (SN Β030000 & up) befor e t h e log am plifier , α digital-to-a n alog con verter is used to effectively move t h e display up or down th e log curve. This process is called "offset" and it accom p lis h es t he same effect as moving t h e POSITIO N control, exce p t that th e dis play on screen does n ot change, only t h e sig n al level req ui red to reach th e reference level c h a n ges. Sin ce t he non-programmable 492 allows selection of eith e r 10 dB per d ivision or 2 dB per d ivisio n , and t h e programma b le 492Ρ allows selection of 1 to 15 dB per d ivisio n , th e system must allow th e gai n to ch an ge wh ile k eepi n g t he top of t he screen constant, a n d must allow any 16 dB segment (in 2 dB/d iv mode) to be d is p layed . Nominally, th e Log Am p lifier operates with 0 dB or at t he top of th e screen . Th e ou t put of pream plifier U 4090A is equivale nt to 20 mV/d B . Full screen is always 2.2 V . At 2.2 V, th e o u t pu t of va r ia b le gai n log am p lifier U4090 B is 0 volt, t he only voltage at whic h the resistors in th e switching n etwork in the feed b ack circuit of p ream plifier U 4090 B can be switched without changi n g t he output voltage. (T he switc h i ng networ k will be d esc ribe d later .) T h e 2.2 volt out pu t of U4090A is ad j usted du ring cali bration to full scree n b y I nput Ref L vl (i nput reference level) potentiometer 84071 .

The gain switch i n g network provides for switch ing 15 resista nce values into t h e feedbac k path of variable gain log am plifier U 4090 B , and co n sists of four FET switc hes (Q4075, Q4070, Q5070, a nd Q5075) and four resistors (87071, 86074, 86073, and 86082) . T he FE T switch es, co ntrolled by data bits 1, 2, 3, an d 4 from th e analyzer data bu s, connect feedbac k resisto rs for U 4090 B i n 15 value combinatio n s as determined by t h e b i n ary conten t of the four d ata bits . In t he non-programmable 492, on ly the 10 d B per d ivisio n an d the 2 d B pe r divisio n selectio ns a re available and are cont rolled b y front panel switch es throug h t he analyzer microcomputer In t h e p rog rammable 492Ρ, th e full 15 combi n ations are selecta ble thro ug h prog ram control .

L i nea r M ode Circuits

T he L inear Mode ci rcuits acce p t t he out p ut f rom log preamplifier U 4090A an d rescale th e signal level to linear val ues . Since no switch ing is provided i n the Log Am plifier (t h at is, all sig n als a re logarithmically scale d ), to operate t he system i n li near mode req uires th at t h e sig n al level b e reexponen tiated . T h us, h ig h gain is requ ired at t h e to p of t he screen a n d low gain is req uired at the b ottom of the scree n to offset the characteristics of th e Log Am plifier .

From U 4090 B , th e output sig n al is a pplied th rough FET 05090 (if that t ransistor h as b een turned on by data b it 6 wh e n 6 is h ig h or α 1) to ou tput ope ratio n al am plifier U4090C, t h en th ro ug h emitter follower Q4100 to t he Video Processor via the fron t panel LOG CA L potentiometer . T h e Out pu t Ref Lvl (ou tpu t reference level) poten tiomete r, R4081 i n th e inpu t ci rcu it to U 4090C, is u sed to adj ust t h e ou tput to provide α f u ll sc reen disp lay after I npu t Reference Level pote ntiometer R4071 is set for no c h a nge i n t he output of U 4090 B when switc h ing from 10 to 2 dB or vice versa.

In ad d itio n to t h e signal path d esc ribe d i n t he Log Mo d e ci rc u its, th e output from preamp lifier U 4090A is also a pp lied to linear mode am plifier U 4090D, an operational amplifier with α successive resistor netwo rk in th e feedb ack path. From this am p lifie r , th e o ut p ut sig n al is applied thro ug h FET 05095 (if th at tr ansisto r has been t ur ned on b y data bit 5 f rom th e analyzer data bus being α 1) to th e sum min g n od e at the in p ut to outpu t am plifier U4090C. After th is poi nt, th e signal pat h is as described i n the Log M ode ci rcuits desc ription .

As an ai d to understa nd i n g t h e system operatio n , it is proba b ly usefu l to u nder stand t h e basic cali b ratio n sequence th at includes th e above two controls. T h e sequ e nce

Starting at t he sig n al level that represents th e to p of the scree n (0 volt) at the o ut p ut of linear mode amplifier U 4090D, t he oper atio n of the n etwork is as follows.

is as follows:

1) th e d igital-to-analog converter o ut p ut voltage is cali brated by adj usting t he front pa nel AMPL CAL control so th at the output is a pp ropr iate for 10 d B per divisio n ;

2) th e Log Am plifier detecto r circu it gai n is adj usted so the Log Amplifier output ag rees wit h t h e digital-to-a n alog converter output ; 3) inp ut Ref Lvl potentiometer 84071, is ad ju sted for no change i n output level fr om U 4090 B when alternately pressi n g th e 10 dB and 2 dB selector switches on the fro nt pa n el ;

4) output Reference L evel potentiometer R4081 is adj usted for α full sc reen dis play.

5- 34

Wit h α 0 dBm in p ut from t h e Log Amp lifier to the V ideo Am plifier , th e output of U 4090D is 0 volt . At t h at level, t he feedb ack path is t h roug h only resistor 86104. Th e other feedback path resisto rs (87079, 87076, 87092, an d 87093) are n ot i n t he pat h because t he switch tran sistors a re b iase d off by t he bias network con sisting of resistors 87082, 87081, 86085, 87086, and 87095, p lus diode CR 7095 . (T he diode is i nclude d for temperatu re compe n sation purposes.) As the dis play moves away from fu ll screen, th e out p ut of U 4090D rises positive and transistor Q6115 is biased on, th ere b y placin g R7097 i n parallel with R 6104 a nd reducing t he gai n of U4090D. Fu rt her i ncreases i n the out-

REV AU G 1981

Theory of Operation-492/492P Service Vol . 1 (SN Β030000 & up)

p ut of U 4090D cause transistors 06110, Q6090, and

06095 to co nduct in se que nce and add resistors R7096, R7092, and R 7095, respectively, in parallel to the feedbac k path. The sequential add ing of resistors into the feedbac k path effectively reduces the gain of U 4090D exponentially . Although it may appea r that such α system wo uld result in steps of gain resolution, the reaction characteristics of t he transistors smooth t he transitions and result in α smoot h exponential gain curve. Pu lse St retcher Circ uit Th e Pulse Stretc h ci rcuit, u nder co ntrol of the a nalyzer microcom puter widens narrow pea k sign als to allow the Digital Storage ci rcuit time to acquire such sign als. If this is not done, the 9-microsecond digitizing r ate of th e Digital Storage circuits is too short to acquire very n arrow signals. The circuits accomplish t his function by stretching the fall time of fast pu lse signals. The circuit consists of FET switch 07110 an d the associated com ponents in the feedbac k pat h of the output operational am plifier U4090C. Wh en p ulse st retch mode is not selected (by data bit 8 from the analyzer data bus being α 0), FET switch Q7110 is off. W it h 07110 off, capacitor C7104 is not in the ci rcuit and the n ormal feed back pat h for U4090C and extra pulldow n cu rrent is p rovided thro ugh resistor R5108 . This allows the U 4090C output to fall as fast as it rises. When pu lse stretc h mode is selected (by data bit 8 being α 1), FE T switch Q7110 is turned on an d ca pacitor C7104 is in serted into the feedb ack circuit to slow the fall of th e outpu t. Also, the only pulldown current is through resisto r R5086 . Diode CR7101 serves only to isolate the p ulse stretch circ uit from the output ci rcuit of the output am plifier. Diode CR5101 turns on at low levels to prevent the am plifier output from going too far negative and slowing the response when the inp ut changes. Wh en the output of Q4100 swings positive, the d iode CR5101 disconnects . The primary adva ntage of this circ uit is that the operational am plifier removes offsets by controlling very closely the voltage at the emitte r of 04100. The Identify circuit permits the operator to check displayed signals as true or spurio us. This feature is implemented elsewh ere in the analyzer, except for an offset that is applied in th e Vi deo Am plifier. The test is accomplis hed b y changi ng t he frequencies of the 1 st LO and the 2nd LO an equal and o pposite amount related to the h armonic n umber used. If the signal is true, it will n ot move . As α c heck, the display b aseline of the signal that results from the frequency is shifted about one division so the alter n ate d isplay is right below the ot her display. Thus, if the display is two similar signals se p arated in

amplitude, the signal is true . This offset is inserted from the REV A UG 1981

analyzer d ata b us throug h latch U6050 and buffer U6060 to t h e summing node of the output am plifie r U4090C. Digital Co ntrol Ci rcuit The Digital Control ci rcuit provides t h e cont rol signals for selectio n of the various V ideo Amplifier functions and consists of add ress decoding, data latching, and buffering circuits. F rom the analyzer data bu s, address data and the DATA VALID signal are applied to the address decoder U6070 through edge connecto r pins 30, 26, 25, 27, 28, and 31 . The decoder p rodu ces two enable signals that a re applied through inverter U 5070 to gain latc h U6040 an d mode latch U6050 . The Gain latc h IC U 6040, is an eight- bit latch th at supplies comman d data to eight-bit d igital-to-analog converter U5041 to offset the Log Am plifier ou tput signal . Mode latc h U6050 is an eight- bit latch t hat supplies command d ata thr ough bu ffer U 6060 to select the resistors in the dB per division switch ing ci rcuit an d to select identify, pu lse stretch, and log or li near mode.

VID E O PR OCESSO R Refer to the bloc k diagram adj acent to Diagram 23 . The Processor ci rcuits pe rform b and leveli ng, video filtering, and b lank ing. The circ uits that perfo rm these functions are d escribed in the following paragraphs. V ideo

Video

Levele r Circ uits

Video leveling compensates for those characteristics of the analyzer front-en d microwave circuits t h at cause un flat response in band 4 (5 .4 to 18 GHz) . Since band 4 is α multiplied band, any unflatness is accentuated. This leveling is accomplis hed through α programmable pert urbatio n of t he display baseline that is opposite in direction from the flatness e rror in the front-end circuits . As analyzer signal power output decreases, the b aseline rises an equal amoun t in compensation ; or, as power output increases, the b aseline falls an equal amount. The perturbation signal is actually produced by α n ormalizes integrated ci rcuit that produces 19 evenly spaced values of the inp ut voltage, but with each value corrected to compensate for u nflat ness. The PRESELECTOR DRIVE signal from the 1st LO Driver circuits, is applied t hroug h edge connector pin 54 to an inp ut translation ci rcuit that co nsists of two current drive rs (U3045A a nd h alf of 03038, p lus U 3045 B and the othe r half of 03038) . Si nce the PRESELECTOR DRIVE signal is d irectly related in amplitude to displayed analyzer f req uency, the nomi nal +10 V to -10 V excu rsion voltage ve rsus frequ ency cu rve in maximum span , r elates to the full ban dwi dt h. This 20 volt maximum excursion is scaled to α

5-35

Theory of Operation-492/492P Service Vol. 1 (SN Β030000 & up) precise current that ranges from 1 mA at +10 V to 0 current at -10 V for application to the normalizer IC to generate the baseline perturbation signal . Actual signal scaling is d one by the U 3045A/03038 current driver . The output signal is applied to the normalizer SWP IN input, p in 5. The second current driver, U 3045B/Q3038, generates α 2 mA reference current for the normalizer . H orizontal Freq adjustment R1069 in the input translation circuits allows for shifting the 19 evenly spaced points up or down in frequency for compensation flexibility.

Normalizer IC U2039 operates as α s haper and contains 19 b i-polar transistors that turn on then off in α sequence as the current input to p in 5 decreases from 1 mA to 0 mA . The collector of each of these IC transistors is connected to α potentiometer that allows for output trimming as shown on Diagram 23 . Potentiometer R1061 is active with no current; R1013 is active at 1 mA . The trimming operation will be described later in t hese paragraphs . From the n ormalizes, the output is applied through α jumper switch to buffer amplifier U 2055B, which has α gain of five, then to offset amplifier U2055A. This amplifier h as α gain of two, but its primary purpose is to offset the 0 to +5 V (normal) ; 0 to -5 V (invert) buffer output to the levels required by the Log Amp circuits . The r ange required b y the Log Amp is -5 V (min). The output voltage is α series of linear interpolations of the voltage between adjacent trimming resistors at the outputs of the normalizer. Compensation adjustment R1065 allows for setting correct interpolation .

M inor compensation is required for band 1 only when p reselection is specified (Option 01). With Option 01, α mi-

nor slope caused by the 1 .8 GHz lowpass filter and 2 GHz limiter is corrected by adding two resistors in series between the PRESELECTOR D RIVE signal input and the VIDEO 1 output signal . These two resistors, R4023 and R3026 (note that R4023 is selected at factory calibration), form α voltage d ivider with R4046 and are inserted by connecting pins 6 and 7 of switch U3025 . This switch is controlled by inverter 04025, which is, in t urn, activated by data bit 6 being α 0. As shown in t he V IDEO BLANKING table on Diagram 23, data b it 6 is α 1 except when Option 01 is selected .

V ideo F ilter Circuits V ideo filtering provides selection of one of six bandwidths, u nder the control of the analyzer microcomputer. As shown i n the V IDEO F ILTER table on Diagram 23, d ata bits 1 through 4 select any of six bandwidths: 30 kHz, 3 kHz, 300 Hz, 30 Hz, 3 Hz, and 0.3 Hz . Either wide or narrow-band filtering is selected at the front panel (30 kHz, 3 kHz, and 300 H z are defined as wide-band; 30 Hz, 3 H z, and 0.3 H z are d efined as n arrowband), and the microcomputer makes the selection, b ased on such factors as sweep rate and total dispersion . With no video filtering (all d ata bits equal 0), the video system bandwidth is 500 kHz, as determined by circuits that follow the V ideo Processor, which has an internal bandwidth of 3 MHz.

Jumper switch Ρ2060 selects the input side of buffer amplifier U2055B . This provides the means to invert the buffer output . During calibration, the procedure is as follows: Leveler Disable jumper Ρ3035 is removed, α test signal with α normal uncorrected baseline waveform is displayed and stored, the Mode jumper (Ρ2060) is removed and reinstalled in t he invert position, the disabled j umper is reinstalled, the stored waveform is displayed with t he normalizeι output waveform superimposed, and the 19 potentiometers are adjusted for exact compensation . The Mode j umper is then removed and reinstalled in the normal mode position . Thus, the output on the V ideo 1 line is opposite in polarity and equal in amplitude to the undesired variations .

Two signal inputs can be applied to the Video F ilter circuits: ΕΧΤ V IDEO and NTL VIDEO. The ΕΧΤ V IDEO signal, from the rear panel auxiliary connector, is applied to pin 15 of switch U3063 through edge connector pin 53 . The INTL VIDEO signal from the V ideo Amplifier circuits (via the front p anel LOG CAL control) is applied to pin 2 of switch U3063 through edge connector pin 51 . Note that the two left sections of switch U3063 are normally held e nergized (pins 2 and 3 connected, p ins 15 and 14 d isconnected) by the +5 V supply through resistor R3064 . If the ΕΧΤ VIDEO SELECT line (also from the rear panel auxiliary connector through edge connector pin 55) is grounded, those switch sections are de-energized and the External Video signal is applied t hrough, or around, the filter to become the V IDEO F ILTER O UT signal at edge connector pin 57 . This is shown in the simplified schematic diagram of Fig . 5-14 .

As stated previously, significant compensation is required only on band 4. Selection of band 4 is indicated by data bit 0 switching to α 1 (see the leveling table at the top right corner of Diagram 23). When DBO is α 1, pins 3 and 2 of switch U2015 are connected and the output from the offset amplifier (U2055A) is supplied out as the V IDEO 1 signal at edge connector pin 49 .

As shown i n t he figure, when no filtering is selected (all data b its equal 0), either t he internal or external signal is applied around the filter because the two right sections of switch U3063 are not energiz ed by d ata b it 1 . When data b it 1 is h igh (1), filtering of some value will be selected by bits 2, 3, and 4, which control three sections of switch U2015 to add o r delete filter time constant .

5- 36

I

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Theory of Operation-492/4921 2 Service Vol . 1 (SN Β030000 & up)

2727-114 Β

F

ig. 5-14.

Video

r

filte

p lified

sim

sc

hematic .

From b uffer U 2066, the sign al is applie d through contacts 7 and 6 of switc h U3063 and edge conn ector pin 57 as the Video Filte r O ut signal .

The filter co nsists of resistors R 2023, R 2021, R 2022, and capacitors C3026, C2016, conn ecte d between two comparators (U3062 and U2066). Table 5-7 lists t h e co mponents t h at are in the circuit fo r each of th e six b andwidths. N ote that data bits 2, 3, and 4 are app lied to switch U2015 p ins 8, 16, and 9, respectively, to select components.

Table 5-7 MP ONENT CO MBINATIO NS FILTER CO

D B=1

R2023

C3026

R 2021

R2022

30 kH z

1

Χ

Χ

Χ

Χ

3 kH z

1,4

Χ

Χ

Χ

300 H z

1,3,4

Χ

Χ

30 Hz

1,2

Χ

Χ

3 Hz

1,2,4

Χ

Χ

0.3 H z

1,2,3,4

Χ

B andwi dth

REV A UG 1981

Ι

Χ

Χ

Ι

C2016

Χ

Χ

Χ

Χ Ι

Χ

5- 37

T heory of Operation-492/492P Service Vol . 1 (SN Β030000 & up) Video

Bla nking Circuits

T he V ideo Blank ing circuits allow for selective blan king of the lower and upp er e nd s of the local oscillator ra nge . This is required because the local oscillator sweeps full span mode regardless of the prescribed band limits . Thus, the video system is designed to effectively open α display window only du ring the time for display. Data bits 5, 6, and 7, u n de r co ntrol of the microcom puter, select the appropriate amount of d isplay for each band . Since the vi deo filtering is on the Video Processor board, and the PRES ELECTOR DR IVE signal (which provides freque n cy information, in voltge form) is also available, this board is α logical place for vi deo b lanking. Switch U3063 in cor porates α disa ble function that, when provided α low input, opens all switch sections regardless of individual section input. U sing this feat ure, the V ideo Filter Out sig nal may easily be b lanked at will . Co ntrol fo r t his d isable function is from α comb inatio n of outputs from two comparators, U3015A and U 3015 B . Inputs to these comparators are from t he PRE S ELECTOR DR IVE signal and α combination of voltage divi ders t h at are switch selected un der con t rol of data bits 5, 6, and 7 . The PRESELECTO R DR IVE signal is applied from edge connector pin 54 to the mi nu s input side of U 3015A through divider resistors R4013 and R4012, and to the p lus input side of U3015 B t hroug h divider resistors R4014 an d R4011 . These dividers redu ce th e +10 V to -10 V excursion of the drive sign al to +2 .5 to -2 .5 V, the maximum input level to the comparato r s. In put to the p lus side of U 3015A is from α divi der that co nsists of resisto rs R3011, R3012, R4024, and R4015 . Note that the excursion of R 4024 is co ntrolled by data b it 5 thro ugh pins 15 and 14 of switch 03025, and that t he inclusion of R4015 is controlled by data bit 7 thro ugh p ins 2 and 3 of the same switch. Thus the junctio n of divider resistors R3011 and R3012 may be co nn ecte d to -10 V through R4024 or to grou nd through R4015 . Refer to t h e VID E O B LANK I N G table on Diagram 23 for d ata bit states for d iffe rent bands . Input to the minus si de of U 3015 B is from α d ivider that consists of r esistors R4018, R4017, and R3028 . N ote the inclusion of R 3028 is controlled b y data bit 6 through pins 10 and 11 of switch 03025 . Ad ding resistor R3028 connects the ju nction of R4018 and R4017 to +10 V thro ugh R3028 . This arra ngeme nt of switching negative and positive levels for comparison with t he redu ced PRESELECTOR DR IVE signal, enables the top and bottom extremes of the frequency excursion to be b la nked by activating the disable fun ction of switch 03063. This blanking is u nder t he co ntrol of t he microcomputer.

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DIGITA L STO R AG E Th e addition of Option 02 to the b asic 492/492Ρ provides t he operator with t he capability of selecting the method for displaying and processi ng info rmation contained in t he digital storage memories . Th is allows operations such as determining t h e h ig h est am p litude that occurred duri ng α selected per iod (MAX H OLD mode), storing α signal for later examination (SAVE Α mode), sub tracting one signal from anot her (B -SAVE Α mode), averaging signals (AVERAGING mode), and comparing signals (V IEW Α, V I EW Β modes) . Two memories are used ind ependently in these operations to store two complete signals that are each digitized at 512 poi nts across the sweep. Thus, two signals may b e observed simultaneously or processe d in va rious ways . In MAX H OLD mode, the h ig hest am plitude at each of the 1024 points in successive swee ps is stored and d isplayed . In SAVE Α mode, α signal is stored in o ne memory for later examination, and is n ot updated. In the Β-SAVE Α mode, the Α signal is stored and n ot updated, then arithmetically sub tracted from th e Β signal, whic h is stored and co nti nually u pdated . In th e AVERAGING mode, the display area is divided b y α horizontal cursor . Above the c ursor, signals are peak detected a nd displayed; b elow the cu rsor signals are averaged . In the V I EW Α and VI EW Β modes, the contents of the selected memory or memo ries are displayed . Grap hical presentation of mathematic functions or experimental data is common to day . One class of such g raph s is those that have α single Υ value for each Χ value. An alternate presentation of the data in this graph wou l d be α table in which the Χ coordi n ate values were simply listed along with α correspon d ing Υ value for eac h Χ value. In furth er simplification, if the fi rst Χ value and the spacing betwee n Χ values (assuming that all spacings are equal) were known, the two column table co uld be redu ced to α si ngle column with the Χ value implie d by the position of the Υ value in t he colu mn . Th is then is th e essence of d igital storage: to convert α vertical analog voltge (Υ coordinate value) to α b inary number and i nsert that nu mber in α stored table. The location of the Υ value in the ta ble is determined by converting to binary the analog swee p voltage (Χ coord inate value) . Once the table is created b y storing α set of b inary numbers representing values across α waveform, the waveform can be recreated at any time by converting the table values (Υ) and positions (Χ) back to analog voltages representing am plitude and sweep position . The d igital storage system u se d i n the 492/492Ρ uses two tables : Α an d Β. Table Β is always upd ated on every swee p. Ta ble Α is changed unless SAVE Α mode is selected . There are 512 Α values and 512 Β values . The spacing b etween values is the same throughout both ta bles, but the

REV AU G 1981

Theory of Operation-492/492P Service Vol . 1 (S N Β030000 & up) starti ng point for table Β is shifted slightly so th at when bot h tables are being read, t he readout val ues a re in ter laced. Wh en the signals are recreated, the operator has the option of displayi ng either Α or Β, or bot h Α and Β. If bot h a re to be d isplayed, and SAVE Α mode is also selected, the co ntents of bot h ta ble Α an d table Β are drawn, each display in its own trace. If SAVE Α mode is not selected, the contents of both table Α a nd table Β are dis played on one trace, 24 with 1024 value positions across the screen . Α third trace option is also available. In the Β mi nus Α mode, the displayed values are those resulting from an arit hmetic operatio n an d a re the diffe rence between the co nte nts of ta ble Α an d ta ble Β fo r each Χ value of analog swee p voltage. Since α sign al waveform is co ntinuous and α table has

d iscrete Χ values, an algorithm is u sed to determine the Υ value to be stored for α p articular Χ value. Th is allows the

operator to select one of two methods for determi ning Υ values : peak or average. The Υ analog voltage is contin uously sampled , with t he sampling rate dependent upon swee p spee d. For each Χ value, there are always at least two samples and there may b e as ma ny as 2" samp les. F rom this set of samples then, the use r may select either t he la rgest sample value (pea k value) or t he mean of all the samples (average value) . Selection between pea k and average is co ntrolled by the front p anel PEAK/AVERAGE control, which sets α do level that is compared with t he analog vertical input to produce the PEAK/AVERAGE logic signal . Wh en the inp ut signal is below the level selected b y the front panel co ntrol, the signal is averaged ; when the input is above that level, the peak signal is d isplayed . The do level appears on the d isplay as α positionable h orizontal li ne. This marker li ne is created by switching the do level to the analog output line duri ng th e marker cycle to produce t h e M ARKER logic cont rol sign al . Superim posed on th e mark e r line is an intensifie d spot called t he UP DATE MARKER, whic h i nd icates the Χ value at whic h new Υ values are being computed for display update . The update marker is forme d by comparing the analog sweep input to the d is play analog Χ o utpu t. Wh en the two are the same value, the sweep is forced to pause, thu s increasi ng the marker intensity at that poi nt. Refer to the block diagrams, adjacent to Diagrams 24 and 25 . Central to th e 492/492Ρ digital sto rage system are two specially designed and ma nu fact ured IC's ; U 1023 and 02032. Vertical section IC U 1023 contains the vertical acquisition an d display logic, and peak detection, signal averaging, Z-axis bla nk ing, and special Υ-value processing circuits. Horizontal section IC U 2032 contains the horizontal acqu isition add ress co unter, h orizontal d isplay counter, 10bit RAM address multiplexer, and α p rogrammable logic array system co ntrol matrix . The remainder of the digital storage control circuits consists of two 8-bit digital-to-αηα-

REV AUG 1981

log converters, two 10-bit digital-to-analog converte r s, one 10-bit latch , 8k bits of rand om access memory, and vario us ancillary ci rcuits. Timi ng is controlled by cloc k pulses from the microcomputer b oard to pin 1 at app roximately α 1 MH z rate . The two primary IC's, U 1023 and U2032, are described as app ropriate at the beginn ing of the vertical an d horizontal section detailed desc riptions that follow .

Ve rtical Sectio n Vertical Control . (Refer to Fig . 5-15 .) The vertical analog voltage is converted to α Υ b inary value using an 8- bit successive approximation register. N ine clock cycles are requ ired for each Υ conversion. After the co nve rsion has ta ken place, the successive approximation register pro du ces the negative-going SYNC signal . M ost functions on both t he vertical and h orizontal co ntrol IC's are sy nchronized b y this signal . On the n egative-going transition of SYNC, the successive approximation register is reset to 10 00 00 00 (binary) and the next conversion cycle b egins. Incoming d ata bits are latched i nto the successive approximation register on the negative-goi ng clock transition . F rom the register, the output data are applied to the peak and the averaging ci rcuits. The averaging circuit consists of three groups of circ uits: those that accumulate the grand total of all of the Υ values fo r α given Χ value (this total is called the numerator), those that co unt the number of samples that make up the nu merator (this total is called the denominator), and those that su btract and s hift to perform the d ivision p rocess . As each new Υ value is converted, it is added to the eight least significant bits of th e n umerator . Eac h carry from th e most significant bit of this ad dition is counted by α 17-bit ripple counter. The contents of this counter and the 8-bit sum a r e cascaded to form α 25-bit grand total. E ach time α new sample is added to the numerator, α second 17-bit ri pple cou nter is incremented to prod uce the d e nominator. Α division cycle is initiated when t he h orizontal control IC 02032, located on Diagram 24, detects α change in the Χ value. At that time, U 2032 produces the ST DI V (start divide) signal . U po n receipt of this signal, and in synchronization with the SY NC signal, vertical co ntrol IC U 1023 performs several functions (refer to Fig . 5-15): 1) it latclκs the cu rr ent n umerator in α 25-bit latch (25 to 1 data co nce ntrator in the b lock diagram), and latc hes the denominato r in α 17-bit latc h (17 to 1 d ata co ncentrator in the block diagram);

2) it clears the numerator add er circuits (25-bit summation register i n t he b lock diag ram);

3) it performs α 17-bit prio rity encode on the denominator and loads α 1 in the app ropriate cell of the 25-bit shift register;

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Th eory of Operation-492/492P Service Vol. 1 (S N Β030000 & up)

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AUG

1981

Theory of Operation-492/492P Service Vol . 1 (SN Β030000 & up) 4) it loads the latch ed nume r ato r and denomin ator serially into the divi de ci rcuit (s ub tractor in the block diagram) using the co ntents of the 25-bit shift registe r as α mask ; 5) it clears the denominator ripple coun ter (17-bit coun te r in the block diagram) to zero . Te n clock periods are required to load t he numerator and denominato r into the d ivide circuit . The cycle starts on α SYNC pulse and the fi rst b it of the q uotient is available shortly after the fi rst clock pulse following the next SYNC pulse. Division is performed by repeate d su btract and s hift operation s. The q uotient is a rrived at serially with the most significant bit first . Only 8-bit accuracy is required, so, by using th e priority encode r outpu t as α mask, the divider circuit is loaded with the 8 most significant bits of th e denominator and the 16 most significant bits of the n ume rator. (Ripple borrow for α 17 by 25-bit subtractor wou l d be so lo ng as to be im pr actical.) The peak circuit consists of α peak detector and an 8- bit peak shift registe r. In operation, the previous peak Υ value from the last set of samples is still stored in the peak shift register at the start of α conversion cycle. At that time, the peak detector, which is α serial compare ci rcuit, is set to the state that will question whether the old or new nu mber is larger. Each bit of the new value is then com pared with t he corresponding bit of the old value, most significant bit fi rst . Whe n o n e value is found to be la rger, α flip-flop is set and the smalle r numbe r is gated out of th e shift register. The start d ivide logic signal bei ng true th en fo rces t he peak detector to select the new value and ignore the num ber in the shift register. The peak/average selector, α multiplexer, selects either average value to be routed to the memories und er control of the P EAI VAVG signal . Th e selector outpu t is routed through the max hold ci rcuit, whic h fu nctions in the same manner as th e pea k d etector. When the MAX H OLD signal is h ig h, the value that is routed to the out put multiplexer is the larger of two values : the cu rrent memory value at the subject Χ coordinate or the previously selected peak or average value.

the peak o r

Timi ng for setting up the divide operation and clearing t he numerator, denomin ator, and pea k ci rcuit is controlled by α 10-stage J ohn so n counter. NOR-gate taps are tak e n from appropriate stages to d evelop t he necessary clea r a nd latc h timi ng pulses . Because the denominator is loaded into the divide ci rcuit u sing α priority encoder, the most significa nt bit is always α 1 . Space and power were saved by modifying the subtractor and not storing this 1 . All data enter a nd leave the memory serially . Data read from memory enter an 8-bit shift register, and timed by

REV A UG 1981

SY NC, are transferred to the vertical d isplay output latch (display register on the block d iagram). The same shift register is used for ot her purposes, so th e DISPLAY ENABLE signal prevents non-display information from bei ng transfe rred to the output latches . An example of d ata moving through t his shift register is that during the Β minus Α display mode . The Α value is first read from memory and stored in t he shift registe r. As the Β value is read, the su btraction is do ne serially and the answer is ap plied to the shift register. Since the sub traction m ust b e performed least significant b it first, α set of exclusive-OR gates change the orde r of extracti ng Β from memory. The direction of shift fo r the shift register is reversed also to present the most significant bit to the p roper d isplay latch. The shift register outpu t is also applied to the output mu ltiplexer. In the subtraction, the operatio n performe d by the se rial calc ulator is not merely Β mi nu s Α. T he actual ex pression implemente d is (13- A) + Κ, where Κ is α serial input external consta nt specified b y the user. This permits zero to b e p laced anywhere on t he screen. To avoid confusion, when (B-A) + Κ results in an off-scree n position, the subtractor b lanks the display . Th is is do ne by examining the carry bit a nd borrow bit when the most significant b it is calculated . If either bit is α 1, the sc reen is b la nked. Wh en SAVE Α mode is not selected a nd both Α and Β are being displayed, maximum resolution is obtained (1024 points across the d isplay) . If this display includes α very narrow p ulse, it is possible that the top of the pu lse is only as wide as α si ngle Χ coordinate (2 to 2" samples) . If this maximum value were in the b table and SAVE Α mode were selected and Β turned off;-Uιβre would be an apparent drop in amplitu de. For this reason, wh e n SAVE Α mode is selected, α special set of ci rc uits in U1023 com pares all Α and Β values that h ave the same Χ value a nd stores the large r in table Α. T his is accomplished by first reading the Β value and storing it in the d isplay shift register . Then, as the Α value is read, it is compared with the Β val ue and the large r of the two is loaded into the dis play shift register. Finally, the n umber in the shift register is written into memory from th e shift register. This operation is performed o nce each time that SAVE Α mode is selected. Vertical co ntrol IC U 1023 also contai ns α 3-bit synchronous coun ter t hat identifies the specific bit of an 8-bit vertical value that is to be read from memory or written into memory . T his is the only memory addressi ng that is performed by the vertical control IC . All other ad dressing is un de r control of the horizontal con trol IC (U2032). Digitizing Circuits. The inp ut vertical signal, VID FLTR

OUT, coupled through edge connector pin 60 is applied

through b uffer

U2033 to sample an d hold switch U1033, which is controlled by flip-flop U1011 B. Flip-flop U 1011 B generates the sample pulse and is enable d during the clock

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Theory of Operation-492/492P Service Vol. 1 (S N 13030000 & up) cycle afte r the last sample as indicated b y the least significant b it from the successive approximatio n register in 01023. The switched sam ple is then a pplied thro ug h b uffer 02032 to α s ummi ng j u nction, at which point t he output cur re nt from the digital-to-a nalog co nverter (02024) that is supplied from the successive approximatio n register is subtracted from the sample current, and the difference current is applied t hroug h com parator U1031 B to pi n 18 of 01023 as the UP /D WN signal . Thus, the combin atio n of the successive approximation register, the digital-to-analog converter, and the sample and hold circuit effectively produces the binary equivalent of th e inp ut sample . Address Decodi ng. The add ress d ecode logic acce pts inputs from the address bus and produces the cont rol signals for read and write operations: CO NT W (con trol write), DATA W (data write), and DATA R (data read). The control write sign al is u sed to gate the control word from the d ata bus into control register U 1022 to ge nerate mode co ntrol signals. This control word consists of five b its that represent fro nt- panel fun ctions . If outpu t 06 is low, α peak operatio n is fo rced: if output Q6 is hig h and 07 is low, an average ope ration is forced. The data read and data write signals are a pplied to the interface logic to control memory read and write operations. Interface Logic. T he interface logic in ge neral performs control and interface functions between the active data ci rcuits in both t he vertical and horizontal sections and the rest of the 492/492Ρ. It allows the microcom pu te r to control the functions of the storage system and to access the digital storage memory, and it contai ns the ci rcuitry fo r serial-toparallel and parallel-to-serial conversion . (The microcomputer uses parallel transfer ; the digital storage memory uses serial transfer .) S hift register U2021 is used to read data from memory to t he data bus . Registe r 01021 is u sed to store information from the data bus for transfer to memory. M ulti plexe r U2016 performs the parallel-to-serial conversion and applies the data output to gate U 2015 B, wh ich acts as α buffer to supp ly either the multiplexer output or the ΜΕΜ OUT (memory output) signal from U 1023 to the memory as the DSDI (digital storage data input) d ata trai n.

T he interface circuit group at the lower rig ht corner of the diag ram is the h and shaking logic th at works with the horizontal control ci rcuits for access to memory and fo r control of when to increment the memory address counter. In either α data read or data write operation (w hen t he co rrespond ing signal goes h ig h), flip-flop U 2014 B is triggered, which in turn releases the BU S RE Q (bus requ est) line, allowing th at sig= ηαΙ to go h ig h. Th is signals the horizontal control ci rcuit that access to memory is required . When the horizontal circuits recognize t h at request, those ci rcuits pull the BUS REQ line low at the same time that SY NC is low. The interface logic detects the BU S REQ an d SYNC low cond ition through U 1013A, U 1013B, U201 1A, and U 2012C, and produces the low BU S GRANT signal to indicate access to memory . The

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BU S GRANT signal then enables shift registe r U2021 to shift data from memory or enable register U1021 and mult iplexer U2016 to shift d ata to memory as indicated by the DATA R an d DATA W li nes . At the en d of α data read cycle, gates U 1012 B and U2023C produce the IN CR AD RS (i ncrement address) signal to increment the address register in the h orizontal circuits .

Maxim um H old. As described previously, whe n MAX HOLD mode is selected, circuits in 01023 compa re the bina-

ry equivalent of t he input signal for α given Χ value with the information in memory for that same Χ value and cau se the la rger of the two to be stored in memory. The control signal that initiates this action is produced from 05 of control register 01022. 1η combination with the VALID sign al from the horizontal circuits, this signal produces the MAX HOLD command to U 1023 through bu ffer U2023 Ε and gate U1025 Α.

Constant Circ uit . As described p reviou sly, in the Β minus Α operation, α constant is used. This consta nt is internally selectable with switch S1014. This switch, in com bination with multiplexe r 01015, supplies the constant to 01023. Multiplexer U 1015 is in turn controlled by address b its 0, 1, and 2 to provide the proper switch signal to U1023 .

Outpu t Circuits. From the U 1023 vertical display register, the parallel data out put is applied to 8-bit digital-to-analog co nverter U 1024 . The converter output is then app lied thro ugh α vector ge nerator, consisting of an integ rator (01032 and C1031) with an associated feedback loop sample and hold circ uit, to the output storage/cursor switch. Integrator U 1032 h as α time constant that provides α ramp lasting between the existi ng sample and the new sample (that is, between sync pu lses). Ci rcuits U 1033A a nd 01034 and capacitor C1038 ma ke up α sample and hold circu it with 01034 acti ng as an output bu ffer . From 01034, the output current through resistor R1032 su btracts from the digital-toanalog converter o utput cur re nt to mo dify the slope of the output ramp. The output of the vector generator is then applied to switch U1033 B, wh ich selects betwee n the stored data and the marker under control of t he buffered ΡΚ/AVG LVL (peak/average level) cont rol signal from U 2034 B and s upp lies the output to the horizontal circuits.

Peak/Average Level Circ uits. The buffered ΡΚ/AVG LVL signal is also supplied as α mode co nt rol signal to 01023 in combinatio n with : the sample and hold up/down output from 02032, the VALID signal from the horizontal circuits, and Q7 of th e control word from 01022 (always α 1), through buffer U1031A, gates U 1025C, U 1025D, U 1025 B, and inverter U 2023D. REV AUG 1981

Theory of Operation-492/492P Service Vol . 1 (S N Β030000 & up)

H o rizontal Section

Α b lock diagram of the H orizontal control IC U 2032 is illust rated in Fig . 5-16 . The h orizontal analog voltage is co nverted to α cu rrent table value th rough t he use of α 10-bit tracking analog-to-digital converter, whic h co nsists of an up/down interloc k and 10-bit up/down counter (02032) and an exte rn al 10-bit digital-to-a nalog converter (02036). As the sweep moves to the right, t h e co unter increments ; as the sweep retraces, the counter d ecrements . E ach time the counter increments, α n ew Χ coordinate value is generated (the digital-to-a nalog co nverter output) and α ST DI V (start d ivide) sign al is generated to start the storage cycle. The increment clock is the SY NC signal, the d ecreme nt cloc k is the basic 1 MH z cloc k divi ded by two. When SAVE Α mode is selected, the cou n te r s kips every other binary nu mber . Thus, only Β coordinates appear as addresses. Intelligence fo r the h orizontal system is p rovided by α p rogrammable logic array ROM state device (ΡLΑ). This

Ρ LΑ determines whic h t race is to be written on the sc reen ,

d etermi nes when to switch from read to write, generates the

Β - Α coordi nation signals for vertical control IC 01023, controls the incrementing of the 9- b it display counter, and processes re quests for the memory bus . Of these, the only function n ot obvious is the memory b us request. When an external device elects to read from or write to memory, it must requ est permissio n by allowing the BU S REQ (bus request) signal to go h ig h. When t hat time b ecomes available, the PLA pu lls th e BU S RE Q line low, signalli ng the start of α request cycle. F or th e next eight clock cycles, the multiplexer output li nes are d riven to the high impedance tristate mo de. T h e com bination of the up/down interloc k, 10-bit up/down register, 9-bit display counter, an d ho rizontal display mu ltip lexer constitute the primary ci rcuits t hat : 1) co nvert t h e sweep voltage to binary fo rm to ge nerate Χ values to be writte n into memory, or 2) read the Χ values from memory by counti ng sync cycles and causing the exte rnal logic to read stored data from memory and produce α vertical signal (Υ value) fo r each correspondi ng Χ value.

During acquisition cycles, the 10-bit up/down counter, co ntrolled by the up/down interloc k, operates in α loop with t he external 10-b it digital-to-a nalog co nverter to derive th e equ ivalent (Χ value) of α sample section of the sweep voltage. F rom the cou nte r, the 10-bit output is applied to the 10bit up/down register . During display cycles, the 9-bit display counter co unts sy nc pulses to derive the Χ value. Eit her the 10-bit up/down register output or the display register outpu t is app lied to th e h orizontal multiplexer u nder control of the SELECT signal from the ΡLΑ. From the multiplexer, the output is applied to the memories .

REV A UG 1981

Address Registers and Bu ffers. Address co unting is accomplished by registers U 2022, 02016, an d 02012. These cou nt INCR AD RS (increme nt addres s) pulses after having been reset to zero by the CO NT W (control write) signal from the vertical section. From th e ad dress register, the out puts are applied to tristate b uffe rs U 1022 and 01016, wh ic h buffer the 10-bits of address from the counters and the DS R/W (digital storage read/write) signal line from the vertical sectio n interface logic and multiplex those signals onto the H D (horizo ntal d isplay) lines and R/W (read/write) li ne to the memories . These buffers are enabled only during the bus grant portion of the cycle fo r display of memo ry data . At all ot her times, h orizontal control IC 02032 outpu ts co ntrol the HD lines to d etermi ne the memory address fo r update of memory data . Tracking Analog-to-Digital Co nverter. As discussed previously, the 10-bit d igital-to-analog converte r operates as part of the loop that d erives α binary equ ivalent of the S WP (sweep) input signal from the Sweep board . Converter U 2036 acce pts the output from the U2032 10-bit up/down counter and converts that outp ut to an analog curre nt that is subt racted from th e swee p signal, whic h is applied at the edge co nn ector p in 60 and through buffer U 2044 B. Th e result of t h is s ub traction is then supp lied to up comparator U 2038A and down comparator U 2038 B, to produce the UP or DO WN signal, as appropriate to co ntrol the di rection of t h e count of the 10-bit up/down cou nter in U2032 . The counter then counts in the app ropriate direction, thereby c hanging the d igital-to-analog converte r output to reflect the proper value. Overflow detector U 1032 and und erflow d etector U1034 prevent the counte r from co unting too h ig h or too low.

Update Mark er Ci rcuits. F rom U 2032, the H D (horizontal d is play) signals a re also applied to 10-bit latch es 01024 and U 1018 . Th e outputs of these latc hes are applied to 10bit digital-to-analog converte r U2034 . From the converter, the output current is app lied through buffer U2044A, where it is co nverted to α voltage, to comparator U2042, wh ich compares it wit h t h e sweep voltage and applies the outpu t voltage to d igital one-shot U 1014 A. The period of this onesh ot is determined by counter U 2024 under control of the low DISP ENBL (display enable) signal from the ΡLΑ in t he ho rizontal co ntrol IC U 2032 . DISP ENBL, when hig h, indicates that valid data are to be transferred . Co nversely, when DISP ENBL is low, the lack of valid d ata indicates retrace. One-shot U 1014 A produces t he INTEN SITY signal t h at is u sed to temporarily prevent co unti ng by the 9-bit d isplay co unter in U2032, thereby effectively stop ping the beam for α s hort time and causing α b right spot on the marker trace (curso r) to indicate the Χ poi nt being updated . Also n ote that b uffe r U2044A also produces the H ORIZ SIG (horizontal signal) t h at is sent to the Deflection Amplifie rs.

Fast Ret race Blanking. B etween the display of the Β memory co ntents and d isplay of the Α memory co ntents, α 5-43

Theory of Operation-492/49213 Service

Vol .

1 (S N Β 030000 & up)

BUS REQUEST INTENSITY D IS PLAY Α DISPLAY B DIS PL AY Β - Α

SAVE

Α

SY N C

C L OC K

DOWN

UP

τιτ7- e

F ig .

5-44

5-16. Horizon tal co ntrol IC block diag r am.

REV AU G 1981

marker the also U7055, bits Filter, pins pin display line 47 retrace U1014B, SWEEP Digital between the points panel blanked AUG buffer so signals CR4052, buffer memory to high, low, is 3through This during also of divider applied POS 49 is 84058, inputs HORIZ display then to U7055, the the drive and When cycle lines by 1981 random pulled Amplifier under connector used and Storage the from of the occurs U7073 the network Section (from U7073, voltage address drive for are these which memory Digital divided shape This Integrated HORIZ address memory the R7051 51, HORIZ to block R/ CR4051, resistor When R/ 84057, SWEEP non-linearity (cursor), in the low, from control the access signals the the auto-focus are is two This isfrom selects OFF signal circuits, signal Readout Storage tristate correction accomplished diagram via transmitted the consists down SIG Sweep the and other digital controlled update applied sample SIG and signals data 84062, R2053 of retrace, signal circuits edge isCR4058, HORIZ isfor the memory Horizontal STORAGE (from from is AMPLIFIERS R7081 the floating signal the from not section from storage buffers applied circuits selects in and the circuits, front circuit), adjacent portion to connector of of isis isSTORAGE display the the 84061, required the U1026 factor unlike by switch controlled 1crt R/ selected through the resistors applied among by is and panel for V/div or and crt by Readout the U1022 Digital of plates, selected to system Sweep, either through through horizontal OFF pulled signal of blanking storage deflection switch enable buffered that to and CR3058 and most IC relates via to the to shaper pin several to the Diagram line Storage U7055 OFF and when 0edge by 83051, be and HORIZ following 83059, U2026 high, is the circuits 48 Readout, Addressing edge significant edge switch The signal U7055 the isapplied selected of seen V/div control U1016 signal generate by network shaper to control The floating characterthe connector the Note the inputs R/ One selected connec26 circuits) connecprovide the SIG U7073 83052, plus circuit and during Selecline by signal the along when 1024 from durOFF Vidto flipThe that half cirbit recrt IC dito or isis to

of Operation-492/492P mA calibrate an the at V, 84033 sensitivity do base base stage R5029 drop provide through through around V/div inverting is approximately gain for of through can inverting connection either the As horizontal level shaped to deflection set and High-frequency amplifier one of to at horizontal capacitor bias 04047 of 83049, the compensation) C2021 the and plate plate, across signal is the each per provide the the Again, amplifier with by Dc to Q1049 for the U2060 for degenerated 81034 04035 resistor resistor rate current dual current amplifier, emitter the side non-inverting input 85037, feedback Deflection amount signal side and response operates each the amplifier high Q1043 drives rate deflection 83048, low of of high sensitivity R5037 base C5021 amplifiers input 01049 includes feedback Q1049 or 142 are Each side, 200 rise For resistor For current R3031 of in horizontal R3031 from of rate isQ4042 of frequency Service emitter the feedback the the change through of Vresistor then example, increases, V output section and at compensation compensation for Amplifier stage section provides increases Q4025A of the provides provides negative excursion 0output gain-degenerated amplifier other approximately side also drive and Horiz R3048 Vfast change capacitor loop of applied As are operate follower -15 transistor deflection is input, Vol transistor the (Q4038 R3045 isthe provides isthe operates islow, feedback is the for steps biased stage, Gain through to Q4038B approximately C3039 circuits adjustment controlled single-ended the drive V bias parallel consists and R3019 1the resistors and inrate the crt drive the source through Q1043 (SN Q4047 positive with sets C4057 about by adjustment required iscurrent output variable on base as the isEach plate of when connected output couples 2Q1049 and emitter in-phase provided resistors the isof combination and The set this rise These approximately approximately of dual operating through controlled drives 1by connected mA the preamplifier output to of to output transistors drive two One for R5035 by output itfor increases, and feedback capacitor 20 Q4038A Q4025B operating set (for right signal The resistors reaches the transisR1055 deflecEmitter R5020 similar by the &to circuit Inputs (Horiincorresisas temtranoutup) amcurset dethe levcrt by of to at

.

Theory fast memory thus flop of α

Α

. . .

. .

DEFLECTION .

Refer Deflection generate signal Input eo

α .

Ζ-Axis .

From compensate istics . 84059, odes HORIZ pin cuit deflection .

REV

. .

;

.

.5

α

.

. α

. .

Ο Ο

Ο ;

Ο α

.

Input and the Variable sient . capacitor

.

.

Signals sistor the 0 .6 tors When deflection plifier. the deflection sistor The 1 rent the rent rent follower put 81045 level . tor el

. .

.

.

. .

Gain zontal 21 .3 porates perature differential flection

Horizontal Signal and tor of the SWEEP pulled pulled signal sistive From rear is with tion signal, tor . from the

.

The circuits, is to resistors High-frequency series C4057 . C3043 .

Memories .

8k data controlled ing U2032

The U2060 path to tion

Β030000

.) .

α

α ΡΝΡ

α .

Ρ3033. .

.

.

α

.

μs.

. Α .

.5

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α .

5- 4 5

Theory of Operation-492/492P Service Vol. 1 (S N Β030000 & up) T h e above descri p tio n of the rig h t- h a nd (i n verting) section is a pp licable to t he left- h a nd (non-inverting) section except for t he circuit element desig n ation s.

R5041 and R5027 in t he horizontal section to correct for t h e i n creased curre nt i n du al input stage transistor s Q4083 and Q4101 .

Outp ut signals from t h e seco nd h alf of switc h U 7055 are also s upp lied to t he auto foc us am p lifier (IC's U 6093, U 6102, an d t ransistors 07097, Q7103) . Am plifiers U6093 a nd U 6102 p roduce α n egative absol ute value signal t hat is t hree times h ig h er in am p litude t h a n t h e sign al from switc h U 7055 . This amplified signal is t hen used to produce α sh ape d current by tra n sistors Q7097, 07103, and resistors R7102, R7101, R7107, R7108, to apply to t he Ζ-Axis I n terface circuit th roug h edge connecto r pin 48 . Th is sig n al will si nk from 0 to a pproximately 0.8 mA of c u rrent from an external n ode at α voltage of a pproximately 0 V .

Com pa rator U 6024 com pares the level of th e sig n al from b aseline clam p U 6065 wit h α refere nce level set by d ivider R7032 a nd R 7034 to produce th e CLI P sig nal fo r th e Ζ-Axis I nterface circuits . The CLI P li ne is pu lled low wh e n t he Vi d eo signal is more n egative t h a n t h e referen ce level (approximately 1 d ivision above b aseli ne), and pu lled h ig h b y R7021 if the signal is more positive t h an t he refere n ce level.

Vertical Section Sig nal li nes V ID EO FI LT ER S OU T (from t he V i d eo Processor circuits) a nd VERT SIG (from t h e Digital Storage circuits), th rough edge co nnecto r pins 53 and 52 res pectively, are routed th rough switch IC U6055 . One side of U 6055, u nder co n trol of t h e STO R AG E OFF sig n al from t he Digital Storage circuits, selects eith e r V ID E O FI LT ER S OUT or VER T SIG. N ote t h at t h e V ID E O FI LT ER S OUT sig n al is buffe red by IC U 7065 to prevent ch angin g load t ransients from affecti ng the sig n al level. Wh en t h e STO R AG E OFF line is floating or pulled h ig h , t he buffere d V ID E O F I LT ER S sig n al is selected ; wh en t h e line is low, the VER T SIG signal is selected . T h e selected signal is inverted a n d clampe d to g rou nd b y U 6065 . ( Bot h the V ID EO F I LT ER S OUT a nd VERT SIG sig n als are s p ecified at 0.5 V/div with 0 V for t h e baseline and positive voltages above th e b aseli n e. Th e signal is re-i nverte d and offset by buffer U 6073 so ce nter screen re p rese n ts 0 V . F rom bu ffer U 6073, α sample of t h is ce ntered sig n al is app lie d to α rear panel co nn ector via edge con nector p i n 46 . T he signal is also applied to t he ot h er side of switch U 6055 along wit h t h e VERT R/Ο sig n al from t he Readout ci rcu its. Selection betwee n th ese two signals is con t rolled by t h e R/Ο OFF sig n als; also f rom t he Readout ci rcu its. When R /Ο OFF is floati n g or pu lled h ig h th e signal from b uffer U 6073 is tran smitted t h roug h t h e switc h . When th e line is pulled low, t he VER T R/Ο sig nal is selected . T he vertical section s haper (resistors R3061, R4065, R4067, R3071, R 3064, and d iod es CR 4063, CR 4064) and pream p lifier ( U 2062) o p e r ate the same as th e h orizo ntal sectio n . Tran sistor Q4078 limits positive excursion s to approximately o ne d ivision b elow t he to p of the sc ree n to protect th e output stages from bei n g ove rdriven . T he vertical ou tpu t stages are similar to t h e ho rizo ntal stages wit h th e exception of h ig her bias curren t. Current flow of a pproximately 1 mA t hr ou g h resistors R3095 and R3098 r esult i n appr oximately 5 mA in the out put stages . Resisto r s R5081 and R 5099 a re of less resistance t han

5-46

Ζ AXIS CI R CU ITS Refe r to t h e b lock diagram adj ace nt to Diagram 27 . Th e Ζ-Axis circuits ta ke t he vario us beam co n t rol inputs suc h as S WP GAT E , ΙΝΤΕΝ, etc., com b i ne t h em, and fu rnis h t h e d rive curre nts and bias voltages req uired to o p e r ate th e crt elect rod es . Th e Ζ-Axis circuit consists of the Intensity Control Logic circuits, wh ic h con trol t he crt beam current fo r normal signal dis play o per atio ns. It also includes t h e u n b lan king gates wh ic h f urn is h cu rrent to t he Ζ-Axis Drive Amplifie r to drive th e crt co ntrol g rid. The Ζ-Axis ci rcu its also incl ud e voltage-settin g circuits for astigmatism, crt t r ace rotation coil, geometry, and oth er crt electro d e voltages . Ζ-Axis Drive r Am p lifier The Ζ-Axis Drive Am plifier Q3047, 04058, a nd Q4059, is driven b y two so ur ces, excl u sive to eac h ot her : U 2038 B /Q2042 dr ives t h e amplifier during reado u t d is play periods, a nd U 2038A/Q2044 drives t he amplifie r dur i ng sweep d isplay periods. U2039 is an AN D-N OR gate t h at is connected to p rovide t he logic to one i n put of N AN D gate U 2038A wh ich t urn s Q2044 on or off. T he R/Ο OFF li ne a nd t he out p ut of U 2039 must bot h b e h ig h fo r U 2038 A to furnis h curre n t to Q2044. Ta b le 5-8 lists th e co n ditio n s u nder wh ic h U 2039 will output α h ig h to U 2038 A . Ta ble 5-8

J 2039 T RUTH TA BLE U 3046 output (line 28)

0

CL I P

0

0

1

1

1

0

0

0

0 0

0 0

0

0

1

1

1

Ζ Axis B lan k

1

1

1

1

1

1

1

1

1

Sto rage Off

0 0

1

0

0

1

0

0

1

S WP GAT E

1

0

1

1

0

1

1

0

1

U 2034, pin 13

0

0

0 0

0

0

0

0

0

Only t h e com b inations s h own in th e tru t h ta b le pl u s α high on R/Ο line will gate α low out of U 2038A. Wh e n

REV AU G 1981

Theory of Operation-492/492P Service Vol . 1 (SN Β030000 & up)

U 2038A output is low, emitter current is furnished to Q2044, which i n turn will furnish c urrent through R2051 (the input resistance of the Ζ-Axis Driver Amplifier) to Q3047. U 2034 is α single-shot that produces α 3 μs pulse to b lank the crt beam during trace return between readout and signal display .

H igh Voltage Oscillator. This circuit consists of transistor Q1073, transformer Τ2065, and associated components. The output of the oscillator, approximately 200 Vac, is coupled across Τ2065, where it is stepped up for application to the Voltage Doubler, and stepped down for application to the crt filament .

The other source of input current to the Ζ-Axis Drive Amplifier is Q2042. This transistor is turned on b y U 2038B when R/Ο UNBLANK is h igh a nd the R/O OFF is low.

C R4041, CR4035, C4027, C5021, C4024, R3038, and

Q1028 serves as α current source for the d ivider (131030R1025) that sets the operating p oint for Q2042 and Q2044 which sets the int"ity level. Diodes CR1045 and CR1043, connected f rom base to base of Q2042 and Q2044, limit the d isplay intensity b y p reventing the bases from going more p ositive than about 0.6 V above the emitter voltage of 02022. This circuit, which i ncludes the adjustment (81027), sets the maximum current for b oth 02042 and 02044. The Ζ-Axis Drive Amplifier is an operational amplifier consisting of transistors Q3047, Q4058, Q4059, and related components . The input resistance for the amplifier is 82051, and the feedback resistor is 83052. The output is clamped by diodes CR3059 and C R3066, to protect the amplifier from transient surges in case of crt arcing . Transistors Q1017 and Q1015 provide current for the trace rotation coil . The adjustment (81021) sets the current so the displayed trace is aligned with the graticule. Transistors Q3045, Q4063, Q4065, and related circuitry are for use in future applications .

H IGH V OLTAGE S UPPLY Refer to the b lock diagram adjacent to Diagram 28. The H igh-Voltage Supply furnishes the -3860 V to the εrt cathode, the filament voltage for the crt, and provides d o restoration for the Z-AXIS DRIVE signal . The circuit consists of the following :

1) the h igh-voltage oscillator, which produces the crt filament voltage and the 200 Vac that is stepped up and applied to the voltage doubler circuit; 2) the voltage doubler, which rectifies and filters the h igh voltage for a pplication to the crt cathode; 3) the h igh-voltage regulator, which samples the h igh voltage and regulates the operation of the high-voltage oscillator ; 4) the Ζ-Axis clipper and rectifier circuits, which couple the Z-AXIS DRIVE signal to the crt control grid .

REV A UG 1981

Voltage Doubler. The voltage doubler consists of

R 1039 . The output of the d oubler is taken off the anode of

C R4035 and a pplied to the εrt cathode. R eference voltage for the regulator is taken off the end of R 1039 .

H igh-Voltage Regulator. This circuit consists of amplifier U4083 and surrounding components . The h igh voltage is applie d t hrough α voltage divider consisting of R 1017B and R1017C, which is connected through 81042 to +15 V. The sample of the h igh voltage at pin "U" is applied through R4075 to the input of comparator U4083. The correction signal, in the form of do drive, is applied to the base circuit of Q1073 to set the oscillator current. CR4078 and CR4077 at the input to U4083, protect the input against excessive voltage excursions. The circuit consisting of CR4071, 83079, and R4074 protect the oscillator if the +100 V supply should fail . N ormally, CR4071 is backbiased . If the +100 V is not present, CR4071 con d ucts and clamps the input negative ; the output of U 4083 swings negative and 01073 remains cut off. This circuit ensures that Q1073 will begin oscillating only after U 4083 switches . CR3077 (in the output circuit of the regulator) prevents the base circuit of 01073 from going negative . Ζ-Axis Clipper. This circuit consists of d iodes CR1056 and CR1046, p lus associated components . 225 Vac from pin 8 of Τ2065 is coupled through C1058 and 81048 to the j unction of CR1046 and CR1056 . The regulator circuit consisting of VR1041 and 81051, hold the cathode of CR1046 at +110 Vdc. Thus, if the Z-AXIS DRIVE signal is + 110 V dc, the two diodes clip the incoming 225 Vac to α total excursion of 1 .2 V. If the Ζ-Axis peak-to-peak voltage is at groun d potential, the ac voltage at the junction of the two diodes swings from ground to + 110 V. The voltage that passes the clipper circuit is coupled through C1031 to the Ζ Axis rectifier. The Z-AXIS DRIVE signal is also coupled d irectly to this circuit, where it is coupled through C1041 to the crt grid circuit. The clipped Ζ-Axis drive signal is rectified by CR2044 and CR2046, which are the principle components of the second section of the Ζ-Axis circuit. The rectified voltage is then fed to the grid of the crt. C1041 couples the fast changes of drive voltage to the crt grid to speed up the response of the grid circuit. N eons DS2052, DS2057, and DS2058 protect the εrt from high-voltage arcs from external

5-47

Theory of Operation-492/4921 3 Service Vol . 1 (SN Β030000 & up) sources. R1044 a n d R1053 pr otect CR 2046 and CR2044 respectively, from external h ig h voltage s u rges .

C RT RE ADOU T