Uniformly Thinning Contoured Silicon to ±5 µm Tolerance EUFANET Workshop – ESREF 2013 Presenter: Chris Richardson
Company: Allied High Tech Products, Inc.
Introduction Electrical Failure Analysis toolsets (EFA) continue to evolve at a faster pace than Physical Failure Analysis (PFA) sample preparation tools/techniques. Many EFA tools (laser/photon or ION based), require access through the backside of the device. To take greater advantage of EFA toolsets using the latest Solid Immersion Lens (SIL) technology, the device must be prepared to a higher standard and tighter tolerance.
Less remaining silicon thickness variation ±5 µm or less is ideal – Enables high NA SIL (s-SIL or a-SIL) – Reduces risk of damage to device due to changes in laser power – Reduced ION beam processing time for device circuit modifications
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Contoured Silicon Devices Sample preparation techniques utilizing Planar polishing or Conventional CNC leave a non-uniform remaining silicon thickness.
Package/Silicon relaxation may occur during sample preparation process. – CNC machines capable of milling to a contour, and/or milling using thermal relaxation techniques can produce a non-uniform Remaining Silicon Thickness (RST).
When referring to the sample preparation process on contoured devices, it is not uncommon to talk about the preparation in terms of changes to the physical profile, since that’s how the milling machines “see” the device. It is now more important to talk about sample preparation of contoured devices in terms of remaining silicon thickness profile; since that is how the EFA techniques “see” the device. EUFANET Workshop - ESREF 2013
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Device Contour – Planar Polishing One of the key’s to achieving ±5 µm tolerance is having the ability to mill a custom contour based on an RST map. In the case of a flat-topped sample as produced with a platen polishing system – a custom contour can be reintroduced.* Inverting the RST map and reintroducing/ milling the contour back into the device *Reference:
“Putting the Die Contour Back – Methods in Advanced Sample Preparation for 3D and Flip-Chip Devices”, C. Richardson et-al, IPFA 2013.
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±5 µm Tolerance Prep Flow chart shows a simple process flow to achieve a sample with ±5 µm RST uniformity.
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Summary A combination of through-silicon measurement techniques and a highly capable milling machine is used to achieve a uniform remaining silicon thickness to within ±5 µm of the desired target thickness.
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