SPCA506A1 USB A/V GRABBER GENERAL DESCRIPTION The SPCA506A1 provides a single chip solution to the AV-Capture application. It includes image compression and data transaction units.
The compressed data is transferred to the PC side via the USB bus.
The
embedded USB controller is a hard-wired state machine. There is no need to use external microprocessors.
FEATURES Snapshot mode: 640 x 480 YUV 4:2:0 data
Support Decoded TV/YUV 4:2:2 image inputs using Philips SAA7111A or SAA7113 or SAA7114,
EDO DRAM interface: 1M x 16 or 256K x 16
Rockwell BT835 or BT 827B / BT829B TV decoder
PC Interface: USB with built in tranciever EP0: Default Endpoint, control type transaction
chips High Speed Compression support real time image
EP1: Isochronous type transaction for video mode image data (interface 0)
output YUV 4:2:0 Video mode:
EP2: Isochronous type transaction for audio
640 x 480
15 - 20 fps
data (interface 1)
352 x 288
25 - 30 fps
USB Suspend mode available.
320 x 240
30 fps
Serial EEPROM: Vendor ID, Product ID,
240 x 180
30 fps
176 x 144
30 fps
Synchronous Serial Control interface
160 x 120
30 fps
3.3V power supply
Revision#, …
128 pins QFP packages (14 x 20 x 2.75mm)
Sunplus Technology Co., Ltd.
1
Rev.: 1.0
1999.12.21
SPCA506A1 BLOCK DIAGRAM GENERAL DESCRIPTION The system receives and processes image data from TV decoder chips. The image data is then further compressed by the Compression block and stored in the DRAM. The data is then read back from the DRAM and transmit to the USB bus via the USB controller. The Synchronous Serial Control blocks programs the TV decoder chips to generate the appropriate input image format. The detailed function of each block is described in the following subsection. COMPRESSION CONTROLLER Input/Output Image Formats Input image: YUV 4:2:2 input image format. Output image: It may generate various output image formats as list in the following table: Mode
Image Type
640 x 480
YUV 4:2:0 (compression supported)
352 x 288
YUV 4:2:0 (compression supported)
320 x 240
YUV 4:2:0 (compression supported)
240 x 180
YUV 4:2:0 (compression supported)
176 x 144
YUV 4:2:0 (compression supported)
160 x 120
YUV 4:2:0 (compression supported)
640 x 480
YUV 4:2:2
640 x 480
YUV 4:2:0
YUV 4:2:0 type images may be either compressed or non-compressed; while other type images will always be non-compressed. Snap Control A snap picture may be obtained by pulling down the “snapnn” pin of the chip or by writing to an internal snap register in the chip. Besides, two alternating snap control schemes are implemented for snapping a picture: one is software dominated; the other is hardware dominated. The software dominated control scheme is designed for the application software which can not immediately adjust the display window size according to the image type in the property byte of the incoming image frame. Software dominated control scheme (Un-toggle control): When software dominated control scheme is selected, 8 image types are defined. User may select any image type to play a motion picture. When the snap button is pressed, either by pulling down the snapnn pin or writing to the snap register, the IC will keeps playing motion pictures according to the image type selected . The only difference is the snap bit in the property byte for that image frame is set to 1. Then, the application software may detect this snap bit turn on and snap the image frame. Sunplus Technology Co., Ltd.
2
Rev.: 1.0
1999.12.21
SPCA506A1 Hardware dominated control scheme (Toggle control): When hardware dominated control scheme is selected, 6 image types are defined as video modes to play motion pictures and 4 image types are defined as snap modes to capture a single image frame. User may select one image type for video mode and one for snap mode respectively. Video mode and snap mode may toggle dynamically during playing. The IC is default in video mode and playing motion pictures. When one of the snap buttons are pressed, the IC will stop playing motion pictures right after the current image frame is transferred. Then the system will output a still image frame according to the image type previously selected for snap mode. The snap bit in the property byte for this still image frame will be set as 1. After that, the system will immediately resume to play motion pictures according to the image type previously selected for video mode. DRAM CONTROLLER The 1M x 16bit DRAM is used as the temporary buffer for the compression controller and as the ISO packet FIFO for the USB controller. The DRAM controller must schedule all the requests to satisfy the bandwidth and latency time requirements for various image operations in order to get better performance. The contents of the DRAM can also be accessed with the USB vendor commands. The procedure is described below. 1. set the starting row address 2. set the starting column address 3. set the return row address 4. set the return column address 5. set the prefetEn bit in the control port 1 register if the operation is read 6. access the DRAM data port The row and column addresses for the DRAM are internal generated by the chip. USB CONTROLLER There are two USB pipes built-in the chip: the first one is the default pipe which is used to handle the standard and vendor commands. The other one is the ISO-IN pipe that is used to transmit the image data. Pipe 0 The maximum packet size is 8 bytes for pipe 0. All standard commands except SET_DESCRIPTOR and SYNCH_FRAME are supported. All the USB descriptors, except vendor ID, product ID and device release number, are hardwired. The values of vendor ID, product ID and device release number, could be hardwired or loaded from an external serial EEPROM(AT93C66). The selection is done by an IO-trap pin, refer to IO-pin section for further details. The string descriptors are also stored in the serial EEPROM. The details about the data in the serial EEPROM are described in Section 4.7.
Sunplus Technology Co., Ltd.
3
Rev.: 1.0
1999.12.21
SPCA506A1 Video ISO-IN pipe For the video ISO-IN pipe, the host may issue standard commands to change its maximum packet size. To achieve the optimal system performance, the user must adjust the alternative interface setting based on the image size and compression rate. The following table shows the maximum packet sizes for the available alternative interface settings.
Alternative Interface Setting
Maximum Packet Size for ISO IN Pipe (bytes)
0
0
1
128
2
384
3
512
4
640
5
768
6
896
7
1023
Video ISO Packet Property byte: Each image frame stream consists of a set of USB ISO packets. In the first USB ISO packet for an image frame stream, several bytes are defined as property bytes to record the image type, compression scheme, and snap approach for the image frame stream. Thus, software may identify each incoming image frame stream.
There are ten property bytes for the start of frame packet. They are sequence byte, property byte 1, property byte 2,.., property byte 8 and property byte 9. The other packets contains only the sequence byte. The value of the sequence byte in the first packet of an image stream is 0X00, followed by sequence byte 0X01, 0X02, 0X03…, etc. The last value of the property byte is 0XFE. The value will wrap around to 0X00 when it reaches 0XFE. 0XFF is a special value for the property byte which marks a drop packet, i.e. no image data is in this packet.
Property Byte 1: Bit
Field
Att
Description
4:0
ImageType
r
Refer to the compression part in the section “Internal register description”
5
Reserved
6
SnapBit
r
Two alternating definitions for this bit may be selected by SnapControl field. Under software dominated snap control (Un-toggle control): When the hardware snap button or software snap button is pressed, this bit in
Sunplus Technology Co., Ltd.
4
Rev.: 1.0
1999.12.21
SPCA506A1 Bit
Field
Att
Description the property byte of the next coming out image will be set to 1. It will become 0 for the next coming out image. Under hardware dominated snap control (Toggle control): When this bit is 1, the image type of the current coming out image will be one of the 4 snap modes; when this bit is 0, the image type of the current coming out image will be one of the 6 video modes.
7
SnapControl
r
Refer to the compression part in the section “Internal register description”
Property Byte 2: Bit
Field
Att
Description
0
CompEnable
r
Refer to the compression part in the section “Internal register description”
3:2
TurnPoint3A
r
Refer to the compression part in the section “Internal register description”
6:4
Threshold3D
r
Refer to the compression part in the section “Internal register description”
Property Byte 3: Bit
Field
Att
Description
2:0
Threshold2D
r
Refer to the compression part in the section “Internal register description”
6:4
Threshold1D
r
Refer to the compression part in the section “Internal register description”
Property Byte 4: Bit
Field
Att
Description
2:0
Quant3A
r
Refer to the compression part in the section “Internal register description”
6:4
Quant3D
r
Refer to the compression part in the section “Internal register description”
Property Byte 5: Bit
Field
Att
Description
2:0
Quant2D
r
Refer to the compression part in the section “Internal register description”
6:4
Quant1D
r
Refer to the compression part in the section “Internal register description”
Property Byte 6: Bit
Field
Att
7:0
FramSequence
r
Sunplus Technology Co., Ltd.
Description The input image frame sequence number
5
Rev.: 1.0
1999.12.21
SPCA506A1 Property Byte 7: Bit
Field
Att
0
EdgeMode
r
Description Edge enhancement: 0: disable
1
GammaEn
r
Gamma correction enable 0: disable
2
AudioEn
r
1: enable
The audio function 0: disable
7:3
1: enable
1: enable
Reserved
Property Byte 8: Bit
Field
Att
7:0
GPIO
r
Description General purpose IO
Property Byte 9: Bit
Field
Att
7:0
Reserved
Description
USB Power Control According to the USB specification 1.0, no USB device may require more than 100 mA when first attached, a configured bus-powered USB device attached to a self-powered hub may use up to 500 mA and all USB devices must support a suspended mode that requires less than 500A. For the USB power budgeting, there are three states designed in the chip: unconfigured, full-speed and suspend. The chip behavior in the three states are described as follows:
Unconfigured: all output pins, except connecting to the USB transceiver and serial EEPROM pins, are not driven and all bi-directional pins, except the GPIO pins, are pulled-down to 0. Full-speed
: all pins are normally operated.
Suspend
: all output pins, except connecting to the USB transceiver pins, are not driven and the serial EEPROM output pins and all bi-directional pins are pulled-down to 0. The internal clocks are gated and unchanged and the clock driver pin is disabled.
There is a newly adding bit at the bit 15 in the control port 0 to enable the DRAM control. The default value of this bit is zero that means the DRAM control is disabled. So the power for the DRAM must be turned off before this bit is enabled.
Sunplus Technology Co., Ltd.
6
Rev.: 1.0
1999.12.21
SPCA506A1 SERIAL EEPROM CONTENT There is an interface to access the 256x16 serial EEPROM (93c66) that can be used to store some data about the device. Address
Purpose
0
Vendor ID
1
Product ID
I2C INTERFACE The i2c interface is used to program TV decoder IC(SAA7111). The write sequence: S
Slave Address + wb
ACKs
Sub Address
ACKs
Data
ACKs
P
The read sequence: S
Slave Address + wb
ACKs
Sub Address
ACKs
Sr
Slave Address + r
ACKs
Data
ACKm
P
S
Slave Address + wb
ACKs
Sub Address
ACKs
P
S
Slave Address + r
ACKs
Data
ACKm
P
Or
Where S is start condition, ACKs is acknowledge from slave, P is stop, Sr is repeat start condition, and ACKm is acknowledge from master. TV INTERFACE TV interface is used to receive the digital output data from TV decoder. The format is CCIR 601/656 YUV 422. Both single channel and dual channels are supported.
Single channel (TV-Y) : Cb Y Cr Y Cb Y Cr Y ……………… Dual channels : TV-Y : Y0 Y1 Y2 Y3 ………………. TV-UV : Cb0 Cr0 Cb1 Cr1 ……………..
In CCIR 601, the active signals (horizontal active or vertical active or data valid) are needed to inform the active region. In CCIR 656, the active signals can be extracted from data streams according to SAV/EAV code.
Sunplus Technology Co., Ltd.
7
Rev.: 1.0
1999.12.21
SPCA506A1 IO TRAP DESCRIPTION The Output pins ma[0], ma[1], ma[2] and ma[3] are used as IO-trap pins. These signals can be pulled high or low on the system board to configure the SPCA506A1 operation. The hardware setting is as follows:
Trap Pin
Function
ma[0]
The vendor/product ID selection: 0: from the serial EEPROM 1: by hardwire
ma[1]
The USB transceiver selection: 0: internal 1: external
ma[2]
The interface 1 (audio) 0: disable 1: enable
ma[3]
test mode 0: normal mode 1: test mode
INTERNAL REGISTER DESCRIPTION Vendor commands are used to access the internal registers that are categorized to ten groups that are selected by the bRequest byte in the setup packet. The register size in the first three groups are 16 bits and the register size in the other groups are 8 bits. The detailed description for vendor command is shown as follows:
bmReqType
bRequest
wValue
wIndex
WLength
EEPROM
0x41 / 0xc1 (*)
0
data
register index
0 / 2 (**)
Memory
0x41 / 0xc1
1
data
register index
0/2
USB Control
0x41 / 0xc1
2
data
register index
0/2
Global Control
0x41 / 0xc1
3
data
register index
0/1
Compress
0x41 / 0xc1
4
data
register index
0/1
Reserved
0x41 / 0xc1
5
data
register index
0/1
Reserved
0x41 / 0xc1
6
data
register index
0 or 8 / 1 or 8
0x41 / 0xc1
7
data
register index
0/1
TV
0x41 / 0xc1
8
data
register index
0/1
Audio
0x41 / 0xc1
9
data
register index
0/1
Synchronous Serial Control
Sunplus Technology Co., Ltd.
8
Rev.: 1.0
1999.12.21
SPCA506A1 * : 0x41 for write , 0xc1 for read. ** : wLength specifies the data size in the DATA phase of an USB setup transfer. When writing to a register, the data is stored in the wValue. So the value of wLength is always zero. When reading a register, there are one, two or eight bytes data returned in the data phase. If burst writing to a register, the data will be transferred in the other data phase. So the value of wLength is eight. EEPROM CONTROLLER REGISTER Mode
Windex-High
Windex-Low
read
8’h00
access address
write
8’h01
access address
write disable
8’h02
don’t care
write enable
8’h03
don’t care
MEMORY CONTROLLER REGISTER DRAM Access Data Port (0) Bit
Field
Att
15:0
Data[15:0]
r/w
Description The host accesses the data of DRAM.
The Start Row Address of DMA (1) Bit
Field
Att
9:0
RowAdr
r/w
15:10
Reserved
Description The starting row address to access DRAM.
The Start Column Address of DMA(2) Bit
Field
Att
9:0
ColAdr
r/w
15:10
Reserved
Description The starting column address to access DRAM.
The Return Row Address of DMA (3) Bit
Field
Att
9:0
RowAdr
r/w
15:10
Reserved
Sunplus Technology Co., Ltd.
Description The return row address to access DRAM.
9
Rev.: 1.0
1999.12.21
SPCA506A1 The Return Column Address of DMA (4) Bit
Field
Att
9:0
ColAdr
r/w
15:10
Reserved
Description The return column address to access DRAM.
USB CONTROL REGISTER Control (0) Bit
Field
Att
0
ISOEn
r/w
Description The ISO packet machine 0: disable 1: enable
1
PrefetEn
r/w
Prefetch DRAM enable for the USB host 0: disable 1: enable
15:2
Reserved
Test (1) Bit
Field
Att
0
BlkISODPkt
r/w
Description Block ISO drop packet 0: disable 1: enable
1
DPThrSel
r/w
Drop packet threshold selection: 0: the data in ISO FIFO is not greater than four 1: the data in ISO FIFO is not greater than one
15:2
Reserved
Vendor ID in Serial EEPROM (2) Bit
Field
Att
15:0
VID[15:0]
r
Description The vendor ID in the serial EEPROM
Product ID in Serial EEPROM (3) Bit
Field
Att
15:0
PID[15:0]
r
Sunplus Technology Co., Ltd.
Description The product ID in the serial EEPROM
10
Rev.: 1.0
1999.12.21
SPCA506A1 GLOBAL CONTROL REGISTER Addr
Bit
Field
Att
0
0
IDSel
r
Description The vendor/product ID selection 0: auto load from the serial EEPROM 1: hardwire value
1
ExtTrxEn
r
USB transceiver selection 0: internal transceiver
4:2
Reserved
5
Synchronous
r/w
Serial ControlEn 6
AudioEn
Synchronous Serial Control function 0: disable
r/w
1
Reserved
0
BlkUSBReset
r/w
BlkSuspend
r/w
Reserved
r/w
4
DramOutEn
r/w
IntRsmCntEn
r/w
Reserved
2
7:0
Reserved
r/w
3
6:0
GPIOO
r/w
1: enable
Internal resume counter enable 0: disable
7:6
1: enable
The DRAM controller output enable 0: disable
5
1: enable
Block USB suspend 0: disable
2-3
1: enable
Block the USB reset to reset the device 0: disable
1
1: enable
The audio function 0: disable
7
1: external transceiver
1: enable
The general purpose I/O output data bit0: Synchronous Serial Control clock bit1: Synchronous Serial Control data other bit: GPIOO
4
6:0
GPIOOENN
r/w
The general purpose I/O output enable (low active) 0: output enable
5
6:0
GPIOI
r
1: output disable
The general purpose I/O input data bit1: Synchronous Serial Control data other bits: GPIOI
6
1:0
Reserved
Sunplus Technology Co., Ltd.
r/w
11
Rev.: 1.0
1999.12.21
SPCA506A1 COMPRESS REGISTER Addr
Bit
Field
Att
0
4:0
ImageType
r/w
Description The image type to be transferred to PC host for display. Two alternating definitions for this register may be selected by SnapControl field.
Under software dominated snap control (Un-toggle control) Bits [3:0]: 0000: mode 0 --- 640x240 YUV 4:2:0 continuous processing. 0001: mode 1 --- 352x288 YUV 4:2:0, continuous processing 0010: mode 2 --- 320x240 YUV 4:2:0, continuous processing 0011: mode 3 --- 240x180 YUV 4:2:0, continuous processing 0100: mode 4 --- 176x144 YUV 4:2:0, continuous processing 0101: mode 5 --- 160x120 YUV 4:2:0, continuous processing 1000: mode 6 --- Reserved 1001: mode 7 --- 640x240 YUV 4:2:2, discrete processing 1010: mode 8 --- Reserved 1011: mode 9 --- 640x240 YUV 4:2:0, discrete processing else : Reserved Bits [4]: Reserved
Under hardware dominated snap control (Toggle control) Bits [2:0]: 000: video mode 0 --- 640x240 YUV 4:2:0 001: video mode 1 --- 352x288 YUV 4:2:0 010: video mode 2 --- 320x240 YUV 4:2:0 011: video mode 3 --- 240x180 YUV 4:2:0 100: video mode 4 --- 176x144 YUV 4:2:0 101: video mode 5 --- 160x120 YUV 4:2:0 else: reserved
Bits [4:3]: 00: snap mode 0 --- Reserved 01: snap mode 1 --- 640x240 YUV 4:2:2 10: snap mode 2 --- Reserved 11: snap mode 3 --- 640x240 YUV 4:2:0 7:5
Reserved
Sunplus Technology Co., Ltd.
12
Rev.: 1.0
1999.12.21
SPCA506A1 Addr
Bit
Field
Att
1
0
SnapControl
r/w
Description 0: Software dominated snap control (Un-toggle control) 1: Hardware dominated snap control (Toggle control)
1
HwSnapButnSta
r
The status for the hardware snap button Set : when the hardware snap button is pressed Cleared : when the register is read
2
HwSnapButnVldChk
r/w
Hardware snap button valid check 0: Disable 1: Hardware snap button valid only when it keeps more than 2.6ms
3
SwSnapButton
w
When 1 is written to this bit, the hardware will emulate the behavior just like the hardware snap button pressed. When 0 is written, no effect. When read, always return 0.
4
Dram1M
r/w
0: means DRAM 256Kx16. 1: means DRAM 1Mx16. (The Compress unit may process the image in the larger DRAM buffer region to get better image quality)
5
Reserved
r/w
6
TVFieldProcess
r/w
0: frame mode: process both fields for each frame. This mode doesn’t support 640x240 TV output. 1: field mode: process only one field for each frame.
2
7
Reserved
0
Line8Image
r/w
0: normal 1: only 8 lines of processed data is output by the compress unit for each image frame, whatever the image type is set.
1
HFiltDram
r/w
0: normal 1: only horizontal processing is activated by the compress unit for each image frame
7:2
Reserved
7:3
7:0
Reserved
8
0
CompEnable
r/w
0: without compression 1: with compression
9
7:6
Reserved
1:0
TurnPoint3A
r/w
3A band normalization 00: T=0 01: T=32 10: T=64 11: T=96
Sunplus Technology Co., Ltd.
13
Rev.: 1.0
1999.12.21
SPCA506A1 Addr
Bit
Field
Att
6:4
Threshold3D
r/w
Description 000: threshold = 0 001: threshold = 2 010: threshold = 4 011: threshold = 8 100: threshold = 16 101: threshold = 32 else: threshold = 0
a
b
2:0
Threshold2D
r/w
Refer to Threshold3D field.
6:4
Threshold1D
r/w
Refer to Threshold3D field.
2:0
Quant3A
r/w
000: quantization factor = 1 001: quantization factor =2 010: quantization factor = 4 011: quantization factor = 8 100: quantization factor = 16 else: quantization factor = 1
c
6:4
Quant3D
r/w
Refer to Quant3A field.
2:0
Quant2D
r/w
Refer to Quant3A field.
6:4
Quant1D
r/w
Refer to Quant3A field.
SYNCHRONOUS SERIAL CONTROL REGISTER Addr
Bit
Field
Att
0
7:0
DATA[7:0]
r/w
Description
Default
The data buffer for Synchronous Serial Control
8’h00
transfer. Writing this buffer will initiate Synchronous Serial Control write sequence. 1
7:0
ADDR[7:0]
w
The register address
8’h00
2
7:0
PREFETCH[0]
w
Writing this bit will initiate Synchronous Serial
1’h0
Control read sequence Synchronous Serial Control’s repeat start condition when rsta is high,
RSTA[1]
1’h0
otherwise Synchronous Serial Control will stop then start.(only work in Synchronous Serial Control read) 3
7:0
BUSY[0]
r
Busy is high when Synchronous Serial Control
1’h0
read or write. 4
7:0
SLA[7:0]
Sunplus Technology Co., Ltd.
w
The slave address
14
8’h00
Rev.: 1.0
1999.12.21
SPCA506A1 Note: 1. For write programming: write SLA -> write ADDR -> write DATA 2. For read programming: write SLA -> decide RSTA -> write ADDR -> write PREFETCH -> polling BUSY -> read DATA TV-IN REGISTER Addr
Bit
Field
Att
0
7:0
Parm0[0]
r/w
Description
Default
Select PAL or NTSC TV system. High for PAL
8’h42
and low for NTSC. Parm0[1]
Select single channel or dual channels operating mode. High for signal channel and low for dual channels. Select external field signal or internal generated
Parm0[2]
field signal. High for external field and low for internal field. Invert field signal. High is active.
Parm0[3]
Select first pixel of Cb Y Cr Y in single channel or
Parm0[5:4]
Cb Cr in dual channels.
1
7:0
Parm0[6]
Reserved
Parm0[7]
Add/sub 128 for Tvi output data. Low is active
Parm1[0]
r/w
Active region is decided by hdvalid and vdvalid
8’h3d
when bit is set, otherwise hdvalid and dvalid are used. Parm1[1]
Pixel rate clock is generated from double pixel rate clock when bit is set. Field signal is decoded from ccir656 data when bit
Parm1[2]
is set. Active signal is decoded from ccir656 data
Parm1[3]
When bit is set. Parm1[4]
Active region is decided by hdvalid when bit is set.
Parm1[5]
Vdvalid will not be used when bit is set. Test mode control
Parm1[7:6] 2
7:0
Parm2[7:0]
Sunplus Technology Co., Ltd.
r/w
Reserved
15
Rev.: 1.0
1999.12.21
SPCA506A1 AUDIO CONTROL REGISTER Control (0) Bit
Field
Att
Description
0
AudioEn
r/w
When high, the audio function is enabled.
1
AudOutReg
r/w
When low to high, the value in the output address and data (only in the write mode) will be transmitted
2
AudInRegClr
r/w
When high, the valid bit for the audio in register will be cleared.
3
WRstCodec
r/w
When high, the audio reset pin will be forced to the low state and the audio will be into warm reset state.
4
CRstCodec
r/w
When high, the audio sync pin will be forced to the high state and the audio device will be into cold reset state.
5
ATETest
r/w
When high, the audio data out pin will be forced to the high state and the audio device will be into ATE test state. The audio reset pin must be forced to low state before the audio data out pin is in high state and must be forced to high state after the audio data out pin is from low to high.
6
AudFIFOTest
7
Reserved
r/w
When high, the CPU can directly read or write audio FIFO.
Output Address(1) Bit
Field
Att
7:0
AudOutAddr
r/w
Description 7: ( 1 = read, 0 = write) 6:0 The output address to read/write audio register
Write Data Low byte(2) Bit
Field
Att
7:0
AudWrData
r/w
Description The data to write audio register (low byte)
Write Data High byte(3) Bit
Field
Att
7:0
AudWrData
r/w
Description The data to write audio register (high byte)
Input Address(4) Bit
Field
Att
6:0
AudInAddr
r
7
Reserved
Sunplus Technology Co., Ltd.
Description The register address in audio input frame
16
Rev.: 1.0
1999.12.21
SPCA506A1 Input Data Low Byte(5) Bit
Field
Att
7:0
AudInData
r
Description The register data in audio input frame (low byte)
Input Data High Byte(6) Bit
Field
Att
Description
7:0
AudInData
r
Bit
Field
Att
0
AudOutBusy
r
When high, it indicates the process to out audio register is still going.
1
AudInVld
r
When high, it indicates there is valid data in the audio input address and data
The register data in audio input frame (high byte)
Status(7) Description
registers and the following input register data will be skipped. 7:2
Reserved
PIN DESCRIPTION Mnemonic
PIN No.
Type
uvdd
1
Pusb
dm
2
B
dp
3
B
uvss
4
Pusb
tvuv[0]/
5
BL
dpo
PIN Description
Initial
Suspend
TV UV data bus / test
OUT when
signals /External USB
ma[1] trap 1 ma[1] trap 1
Register Enable
AP Consider.
OUT when
transceiver dpo tvuv[1]/
6
BL
dmo
TV UV data bus / test
OUT when
OUT when
signals /External USB
ma[1] trap 1 ma[1] trap 1
transceiver dmo tvuv[2]/
7
BL
usboenn
TV UV data bus / test
OUT when
OUT when
signals /External USB
ma[1] trap 1 ma[1] trap 1
transceiver usboenn tvuv[3]/
8
BL
suspend
TV UV data bus / test
OUT when
OUT when
signals /External USB
ma[1] trap 1 ma[1] trap 1
transceiver suspend tvuv[4]/
9
IH BH TV UV data bus / test
dpi
signals /External USB transceiver dpi
Sunplus Technology Co., Ltd.
17
Rev.: 1.0
1999.12.21
SPCA506A1
Mnemonic tvuv[5]/
PIN No. 10
Type
PIN Description
Initial
Suspend
Register Enable
AP Consider.
IL BL TV UV data bus / test
dmi
signals /External USB transceiver dmi
tvuv[6]/
11
IL BL TV UV data bus / test
din
signals /External USB transceiver din
tvuv[7]
12
IL BL TV UV data bus / test signals
gvdd
13
Pglob
gvss
14
Pglob
tvy[0:7]
15-22
ILBL TV Y data bus/ test signals
gvdd
23
Pglob
tvhref
24
ILS
TV horizontal reference signal
tvvref
25
ILS
TV vertical reference signal
tvfield
26
ILS
TV field odd/even
tvdvalid
27
ILS
TV data valid signal
tvck
28
IL
TV clock (x1, 13.5M Hz)
IC2x2 tvckk
29
IL
TV clock (x2, 27M Hz)
IC2x2 tvvd
30
ILS
TV vertical sync signal
tvhd
31
ILS
TV horizontal sync signal
dvdd
32
Pint
dvss
33
Pint
gpio[0]/
34
BS
scl
General purpose IO
Tri
Tri
Rgpio,
External pull high
Ri2c
port / Synchronous Serial clock
gpio[1]/
35
BS
sda
General purpose IO
Tri
Tri
Rgpio,
External pull high
Ri2c
port / Synchronous Serial data
Sunplus Technology Co., Ltd.
18
Rev.: 1.0
1999.12.21
SPCA506A1
Mnemonic gpio[2:4]
PIN No. 36-38
Type BS
PIN Description
Initial
General purpose IO port Out 0
Suspend Out 0
Register Enable Rgpio
AP Consider. External pull low used to turn off power
ovss
39
Pio
ovdd
40
Pio
gpio[5:6]
41-42
BS
General purpose IO port Out 0
Out 0
Rgpio
External pull low used to turn off power
ma[0:3]
43-46
B
DRAM address
Tri
Tri
Rdram
Hardware trap pin
Trap function:
external pull
ma[0] -- 0: ID select
high/low
from EEPROM; 1: ID
tri-state during
select from internal
DRAM power off
default settings ma[1] -- 0: internal USB transceiver; 1: external USB transceiver ma[2] -- reserved ma[3] -- reserved ma[4:9]
47-52
TO B DRAM address
Tri
Tri
Rdram
Tri-state during DRAM power off
rasnn
53
TO
DRAM row address
Tri
Tri
Rdram
strobe dvdd
54
Pint
dvss
55
Pint
casnn
56
TO
DRAM power off
DRAM column address Tri
Tri
Rdram
strobe moenn
57
TO
DRAM data output
58
TO
Tri-state during DRAM power off
Tri
Tri
Rdram
enable mwenn
Tri-state during
Tri-state during DRAM power off
DRAM data write enable Tri
Tri
Rdram
Tri-state during DRAM power off
md[0:5]
59-64
BL5
DRAM data
Tri, L
Tri, L
Rdram
Tri-state during DRAM power off
ovss
65
Pio
Sunplus Technology Co., Ltd.
19
Rev.: 1.0
1999.12.21
SPCA506A1
Mnemonic
PIN No.
Type
ovdd
66
Pio
md[6:15]
67-76
BL5
PIN Description
DRAM data
Initial
Tri, L
Suspend
Tri, L
Register Enable
Rdram
AP Consider.
Tri-state during DRAM power off
dvdd
77
Pint
dvss
78
Pint
ecs
79
BL
EPROM chip select
Tri, L
EPROM will be tristated during power-on reset period; while not tri-stated during suspend
esk
80
TO
EPROM clock
Tri
edi
81
TO
EPROM data input
Tri
edo
82
IL
EPROM data output
test[4]
83
TO
Audio reset to Codec
Tri
Tri
aurstnn
Tri-state during audio chip power off
test[3]
84
TO
Auiod sync to Codec
Tri
Tri
ausync
Tri-state during audio chip power off
test[2]
85
IL5
audin test[1]
Codec 86
IL5
aubclk test[0]
Audio data input from
Audio bit clock from Codec
87
TO
audout
Audio data output to
Tri
Tri
Codec
Tri-state during audio chip power off
xtalin
88
XI
Crystal pad
xtalout
89
XO
Crystal pad
dvdd
90
Pint
dvss
91
Pint
rstnn
92
IS
Oscil.
Global reset signal to
Out 1
External pull high
the chip snapnn
93
IS
Sunplus Technology Co., Ltd.
Snapshot signal
External pull high
20
Rev.: 1.0
1999.12.21
SPCA506A1
Mnemonic
PIN
Type
No.
PIN Description
Initial
Suspend
Register Enable
nc
94
ILS
External VD
nc
95
ILS
External HD
nc
96-99
TO
Reserved
Tri
Tri
Rtg
ovdd
100
Ptg
nc
101-102
TO
Reserved
Tri
Tri
Rtg
ovss
103
Ptg
nc
104-110
TO
Reserved
Tri
Tri
Rtg
ovdd
111
Ptg
nc
112-116
TO
Reserved
Tri
Tri
Rtg
gvdd
117
Pglob
gvss
118
Pglob
nc
119-128
IL
AP Consider.
Reserved
Note. PAD type symbol definition: I:
input (need external pull high/low)
TO: tri-state output
O:
output
BL: bi-direction, pull low
B:
bi-direction (need external pull high/low)
BS:
P:
power pad
BL5: bi-direction, pull low, 5V tolerant
XI:
crystal input pad
Ptg: power pad for output
bi-direction, smith trigger
XO: crystal output pad
Pio: power pad for I/O buffer
IL:
input, pull low
Pint: power pad for internal core logic
IH:
input, pull high
Pglob: power pad for both I/O buffer & internal core logic
IS:
input, smith trigger
Pusb: power pad for USB
ILS: input, pull low, smith trigger
AC/DC CHARACTERIZATION ABSOLUTE MAXIMUM RATINGS Symbol
Value
Unit
Voltage on any pin relative to VSS
VT
-0.4 to 4.0
V
Supply Voltage relative to VSS
VDD
-0.4 to 4.0
V
Short Circuit Output Current
IOUT
50
mA
Power Dissipation
PD
0.2
W
Operating Temperature
TOPT
0 to +70
C
Storage Temperature
TSTG
-55 to 125
C
Parameter
Sunplus Technology Co., Ltd.
21
Rev.: 1.0
1999.12.21
SPCA506A1
RECOMMENDED DC OPERATING CONDITIONS Symbol
Min.
Typ.
Max.
Unit
Supply Voltage
VDD
3.1
3.3
3.45
V
Input low voltage
VIL
-0.3
-
0.3VDD
V
Input high voltage
VIH
0.7VDD
-
VDD+10%
V
Parameter
DC CHARACTERISTICS TA = 0C - 70C, VDD = 3.3V 5%, VSS = 0V Symbol VOL
Parameter Output low voltage
Min.
Typ.
Max.
Units
-
-
0.4
V
Test Condition 4mA buffer IOL = 4mA
8mA buffer IOL = 8mA
12mA buffer IOL = 12mA VOH
Output high voltage
2.4
-
-
V
4mA buffer IOH = -4mA
8mA buffer IOH = -8mA
12mA buffer IOH = -12mA IDD
Power supply current
-
80
-
mA
fop = 48MHz
Power supply current
-
100
-
mA
fop = 48MHz
Power supply current
-
10
-
uA
Input leakage current
-
10
-
A
(unconfigured) IDD (normal) IDD (suspend) IIL
VIN = 0V
Notes: (1) All DC electrical characteristics are measured at 25C
Sunplus Technology Co., Ltd.
22
Rev.: 1.0
1999.12.21
SPCA506A1 AC CHARACTERISTICS 1. DRAM Single Read Timing : RASNN
tRP tRCD tCAS
CASNN tASR tRAH row address
MA OENN
tASC column address
tCAH
tROD
tROD tCAC
MD
Symbol
valid data
Parameter
Min.
Typ.
Max.
Units
tRCD
RAS to CAS delay
-
60
-
ns
tRP
RAS recovery time
-
40
-
ns
10
20
-
ns
tCAS
CAS pulse width
tASR
Address to RAS setup time
-
40
-
ns
tRAH
RAS to address hold time
-
40
-
ns
tASC
Address to CAS setup time
-
20
-
ns
tCAH
RAS to address hold time
-
20
-
ns
tROD
RAS to OE delay
-
40
-
ns
tCAC
CAS to valid data delay
-
-
30
ns
Notes
2. DRAM Page Mode Read Timing : RASNN tCP
CASNN row address
MA
column address 1
column address 2
OENN MD
Symbol tCP
valid data 1
Parameter
Min.
Typ.
Max.
Units
-
20
-
ns
CAS recovery time
Sunplus Technology Co., Ltd.
valid data 2
23
Rev.: 1.0
Notes
1999.12.21
SPCA506A1 3. DRAM Single Write Timing : RASNN
tRP tRCD tCAS
CASNN tASR tRAH row address
MA
tASC column address
tCAH
tDH
tDS
MD
valid data
WRNN
Symbol
Parameter
Min.
Typ.
Max.
Units
tRCD
RAS to CAS delay
-
60
-
ns
tRP
RAS recovery time
-
40
-
ns
tCAS
CAS pulse width
-
20
-
ns
tASR
Address to RAS setup time
-
40
-
ns
tRAH
RAS to address hold time
-
40
-
ns
tASC
Address to CAS setup time
-
20
-
ns
tCAH
RAS to address hold time
-
20
-
ns
tDS
data to CAS setup time
-
20
-
ns
tDH
data to CAS hold time
-
20
-
ns
Notes
4. DRAM Page Mode Write Timing : RASNN tCP
CASNN row address
MA
column address 1 tDS
column address 2 tDH
tDS
valid data 1
MD
tDH
valid data 2
WRNN
Symbol
Parameter
Min.
Typ.
Max.
Units
tCP
CAS recovery time
-
20
-
ns
tDS
data to CAS setup time
-
20
-
ns
tDH
data to CAS hold time
-
20
-
ns
Sunplus Technology Co., Ltd.
24
Rev.: 1.0
Notes
1999.12.21
SPCA506A1 5. Refresh Cycle Timing : CASNN
tCAS tCSR
tCHR
RASNN
Symbol
Parameter
Min.
Typ.
Max.
Units
tCAS
CAS low pulse width
-
80
-
ns
tCSR
CAS to RAS setup time
-
40
-
ns
tCHR
RAS to CAS hold time
-
40
-
ns
Notes
6. Serial EEPROM Timing :
ECS tCSS
tSKH
tSKL
tCSH
tCS
ESK tDIS
tDIH
EDI tPD0
tPD1
tDF
EDO (Read) tSV
tDF
EDO (Program)
Symbol
Parameter
Min.
Typ.
Max.
Units
tSKH
ESK High Time
-
2.5
-
us
tSKL
ESK Low Time
-
2.5
-
us
tCS
Minimum ECS Low Time
-
5
-
us
tCSS
ECS Setup Time
-
2.5
-
us
tDIS
EDI Setup Time
-
2.5
-
us
tCSH
ECS Hold Time
-
2.5
-
us
tPD1
Output Delay to 1
0
-
2.5
us
tPD0
Output Delay to 0
0
-
2.5
us
tSV
ECS to Status Valid
0
-
5.0
us
tDF
ECS to EDO in Z
0
-
5.0
us
Sunplus Technology Co., Ltd.
25
Rev.: 1.0
Notes
1999.12.21
SPCA506A1 PACKAGE ASSIGNMENT AND DIMENSION
nc nc ovdd nc nc nc nc nc nc snapnn rstnn dvss dvdd xtalout xtalin audout aubclk audin ausync aurstnn edo edi esk ecs dvss dvdd md15 md14 md13 md12 md11 md10 md9 md8 md7 md6 ovdd ovss
PACKAGE Assignment
111 99999999998888888888777777777766666 000 98765432109876543210987654321098765 210 ovss nc nc nc nc nc nc nc ovdd nc nc nc nc nc gvdd gvss nc nc nc nc nc nc nc nc nc nc
103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 122 124 125 124 126 127 128
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39
128 pin package
123456789
md5 md4 md3 md2 md1 md0 mwenn moenn casnn dvss dvdd rasnn ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 gpio6 gpio5 ovdd ovss
11111111112222222222333333333 01234567890123456789012345678
gpio4 gpio3 gpio2 gpio1/sda gpio0/scl dvss dvdd tvhd tvvd tvckk tvck tvdvalid tvfield tvvref tvhref gvdd tvy7 tvy6 tvy5 tvy4 tvy3 tvy2 tvy1 tvy0 gvss gvdd tvuv7 tvuv6/din tvuv5/dmi tvuv4/dpi tvuv3/suspend tvuv2/usboenn tvuv1/dmo tvuv0/dpo uvss dp dm uvdd Global power/ground IO buffer power/ground internal cell power/ground USB cell power/ground
Sunplus Technology Co., Ltd.
26
Rev.: 1.0
1999.12.21
SPCA506A1 PACKAGE Dimension D D1 D2
E
E1
SUNPLUS SPCA506A1
E2
e
b
YYWW
A2
A
Symbol
Min.
Nom.
Max.
A
-
-
3.4
A2
2.5
2.72
2.9
E
17.20
17.20
17.20
E1
14.00
14.00
14.00
E2
12.50
12.50
12.50
D
23.20
23.20
23.20
D1
20.00
20.00
20.00
D2
18.50
18.50
18.50
e
0.50
0.50
0.50
b
0.17
0.20
0.27
Unit: millimeter
NOTE: SUNPLUS TECHNOLOGY CO., LTD reserves the right to make changes at any time without notice in order to improve the design and performance and to supply the best possible product.
Sunplus Technology Co., Ltd.
27
Rev.: 1.0
1999.12.21
SPCA506A1 DISCLAIMER The information appearing in this publication is believed to be accurate. Integrated circuits sold by Sunplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. SUNPLUS makes no warranty, express, statutory implied or by description regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. FURTHER, SUNPLUS MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. SUNPLUS reserves the right to halt production or alter the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal commercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by SUNPLUS for such applications.
Please note that application circuits illustrated in this document are for
reference purposes only.
Sunplus Technology Co., Ltd.
28
Rev.: 1.0
1999.12.21
