The silicon area of large memory cells is dominated by the size of the memory core, it is thus crucial to keep the size of the basic storage cell as small as possible.
Storage elements • The silicon area of large memory cells is dominated by the size of the memory core, it is thus crucial to keep the size of the basic storage cell as small as possible • The storage cell area is reduced by: – reducing the driving capability of the cell (small devices) – reducing the logic swing and the noise margins
• Consequently, sense amplifiers are used to restore full railto-rail amplitude
Paulo Moreira
Storage elements
2
Read-only • •
Because the contents is permanently fixed the cell design is simplified Upon activation of the word line a 0 or 1 is presented to the bit line:
Vdd
Vdd
Bit line
Bit line
Stored 0
Stored 1
– If the NMOS is absent the word line has no influence on the bit line:
• The word line is pulled-up by the resistor • A 1 is stored in the “cell
– If the NMOS is present the word line activates the NMOS:
Word line
• The word line is pulled-down by the NMOS • A 0 is stored in the cell
Paulo Moreira
Storage elements
3
Read-only •
In practice a “always on” pull-up device is never used because: –
–
•
•
In practice pre-charged logic is used: – –
Eliminates the static dissipation Pull-up devices can be made wider
The bit lines are first precharged by the pull-up devices –
•
VOL would depend on the ratio of the pull-up/pull-down devices A static current path would exists when the output is low causing high power dissipation in large memories
Vdd Φ pre-charge
Pull-up devices
WL[0] GND WL[1]
WL[2] GND
during this phase the word lines must be disabled
WL[3] BL[0]
BL[1]
BL[2]
BL[3]
Then, the word lines are activated (word evaluation) –
during this phase the pull-up devices are off
Paulo Moreira
Storage elements
4
Nonvolatile R/W • The same architecture as a ROM memory • The pull-down device is modified to allow control of the threshold voltage • The modified threshold is retained “indefinitely”: – The memory is nonvolatile
• To reprogram the memory the programmed values must be erased first • The “heart” of NVRW memories is the Floating Gate Transistor (FAMOS)
Paulo Moreira
Storage elements
5
Nonvolatile R/W • A floating gate is inserted between the gate and the channel • The device acts as a normal transistor • However, its threshold voltage is programmable • Since the tox is doubled, the transconductance is reduced to half and the threshold voltage increased
Paulo Moreira
Floating-gate transistor (FAMOS)
Storage elements
Floating gate D
Gate S
tox tox n+
n+ p-substrate
6
Nonvolatile R/W •
Programming the FAMOS: – A high voltage is applied between the source and the gate-drain – A high field is created that causes avalanche injection to occur – Electrons traverse the first oxide and get trapped on the floating gate (tox = 100nm) – Trapped electrons effectively drop the floating gate voltage – The process is self limiting: the building up of gate charge eventually stops avalanche injection – The FAMOS with a charged gate is equivalent to a higher VT device – Normal circuit voltages can not turn a programmed device on
1) Avalanche injection +20
10V S
Storage elements
D
2) Charge trapped on the floating gate 0V
0V
-5V S
D
3) Trapped charge higher VT 5V
-2.5V S
Paulo Moreira
5V
D
7
Nonvolatile R/W • The non-programmed device can be turned on by the word line thus, it stores a “0” • The word line high voltage can not turn on the programmed device thus, it stores a “1” • Since the floating gate is surrounded by SiO2, the charge can be stored for many years
Paulo Moreira
Vdd
not programmed
Vdd
programmed
Word line
Storage elements
Bit line
Bit line
Stored 0
Stored 1
8
Nonvolatile R/W • Erasing the memory contents (EPROM): – Strong UV light is used to erase the memory: • UV light renders the oxide slightly conductive by direct generation of electron-hole pairs in the SiO2
– The erasure process is slow (several minutes) – Programming takes 5-10µs/word – Number of erase/program cycles limited (
The CMOS inverter. ⢠Technology. ⢠Scaling. ⢠Gates ..... For acceptable phase margin. Place the zero 1/Ï .... Add VCO phase noise. Update the VCO period ...
D. A. Johns and K. Martin, âAnalog Integrated Circuit Design,â John Wiley & Sons 1997, ISBN 0- ... B. Razavi, âA Study of Phase Noise in CMOS Oscillators,â IEEE Journal on Solid-State ... http://www.ife.ee.ethz.ch/~ichsc/ichsc_chapter11.pdf.
Design of Analog Integrated Circuits and Systems by Kenneth R. ... Design of Analog CMOS Integrated Circuits ... CMOS Circuit Design, Layout, and Simulation.
Clock skew control and frequency multiplication. Ext. CLK. Clock pad. PLL ...... Algorithm: ⢠Slice the time in very thin intervals (much smaller than T vco. ).
An active low pass filter. ⢠A charge-pump and a capacitor .... Can we run the starved inverter infinitely slow?. ⢠... Signal and the Inverted signal available.
that of a DLL you notice some similarities but as well some very fundamental differences: .... 3rd always buffer the VCO signal to make the transfer ..... âMonolithic Phase-Locked Loops and Clock Recovery Circuits Theory and Design,â ..... In one
... pattern to the wafer surface. â Process the wafer to physically pattern each layer of the IC ... (photo resist: light-sensitive organic polymer). ⢠The photoresist is exposed to ultra violet light: ... active by an rf-generated plasma anisotr
NRZI non-return to zero invert on ones. â Manchester and Bi-Phase Mark. â 3B/4B, 5B/6B and 8B/10B, done in groups of bits before serialization. BiPhase Mark.
CMOS power budget: â Dynamic power consumption: ⢠Charging and discharging of capacitors. â Short circuit currents: ⢠Short circuit path between power rails ...
... CMS tracker analogue data link. â The CMS tracker data path. â The linear laser-driver ... Monitoring. Serial/Parallel. Local. Address. Control & Data. Interface.
Tx. Detector channel. LHC clock (40MHz). Gain. 82 728 chan n e ls (barrel +. 2 en d caps). Radiation hard environment. CMS Electromagnetic Calorimeter.
Dec 17, 2004 - M.J.M. Pelgrom et al., âA 25-Ms/s 8-bit CMOS A/D Converter for Embedded Applicationâ, ... components can be attributed to two classes of effects. .... Technical Digest of the IEEE International Electron Device Meeting 1997, pp ...
May 20, 2007 - Below an excerpt form correspondence with Hans Camenzind: ..... This means that any spectral content of the phase noise that is above 10 ...
in the vernier scale (lower) lines up with a tick mark in the reference scale (upper). [36]. 38 ..... Almasi, L. et al., New TDC electronics for a PesTOF tower â in NA49, ... Mota, M., A high-resolution Time-to-Digital Converter â users manual, C
Dec 17, 2004 - The definition of âMoore's Lawâ has come to refer to almost anything related to ..... The following data are taken from the design manuals of different CMOS technologies. N. D. Arora et al., "Modeling the Polysilicon Depletion Effe
possible then, the speed limitation should come from the switching transistor themselves, in ..... found in practical circuits makes it a circuit to be avoided. .... depends on the phase detector gain, which depends on the power supply voltage Vdd.
