Some examples of SPICE compact

modeling for design of advanced analog integrated circuits in CEA-Leti Patrick Martin [email protected]

CEFIPRA/IFCPAR Indo-French seminar on “New Trends in Electron Device Modeling”, Indian Institute of Science, Bangalore, March 30 - April 1, 2015 http://www.dese.iisc.ernet.in/ifwdm/

Grenoble MINATEC campus

Indo-French seminar on “New Trends in Electron Device Modeling”, P. Martin | 2

Simulation & Compact Modeling Laboratory

Materials Properties

Devices Characteristics

 “Physics” & Backgrounds Gate stack (atomistic approach) Quantum transport (NEGF, Wigner) Mobility (MC, Kubo-Greenwood)

 TCAD  Process  Devices  Small circuits (ring oscillator, SRAM, etc.)

IC Performances

 SPICE for circuit design  Compact Modeling  Parameter extraction

experimental data Technological & Nano-Characterization platforms  Improving “Physics” understanding  Technological support (choice of technological options, device optimization, …)  Performance evaluation (from device to IC)  New ideas or concepts, innovation (challenge anticipation) Indo-French seminar on “New Trends in Electron Device Modeling”, P. Martin | 3

Main application fields

Memories

Power devices

Split-Gate

Silicon platform

Resistive RAM (OxRAM, CBRAM)

Advanced CMOS

Phase Change Memory Physics/TCAD/SPICE

FDSOI

3D integration Nanowire

RF Active and Passive Carbon based electronics Physics & SPICE

Physics/TCAD/SPICE

Photonics Back-end applications (wave-guide)

III-V on silicon Automotive & Photovoltaic applications TCAD/SPICE

Photovoltaic Multi-crystalline silicon Hetero-junctions Nanodots Physics/TCAD

SPICE

Indo-French seminar on “New Trends in Electron Device Modeling”, P. Martin | 4

SPICE compact modeling: some examples

1 - MOSFET compact modeling for design of mixed analog/digital circuits at cryogenic temperature (MOS-AK workshop*, Rome, Italy, 2010) 2 - HSP: A surface-potential-based compact model of AlGaN/GaN HEMTs power transistors (MOS-AK workshop, Bordeaux, France, 2012)

3 - Development of Verilog-A models for silicon photonics devices and implementation in a standard EDA environment (MOS-AK workshop, London, UK, 2014) * http://mos-ak.org/

Other examples: MOS-AK workshop, Grenoble, March 12, 2015 Indo-French seminar on “New Trends in Electron Device Modeling”, P. Martin | 5

SPICE compact modeling: 1st example

1 - MOSFET compact modeling for design of mixed analog/digital circuits at cryogenic temperature (MOS-AK workshop*, Rome, Italy, 2010) 2 - HSP: A surface-potential-based compact model of AlGaN/GaN HEMTs power transistors (MOS-AK workshop, Bordeaux, France, 2012)

3 - Development of Verilog-A models for silicon photonics devices and implementation in a standard EDA environment (MOS-AK workshop, London, UK, 2014) * http://mos-ak.org/ Indo-French seminar on “New Trends in Electron Device Modeling”, P. Martin | 6

1 - MOSFET compact modeling for design of mixed A/D circuits at cryogenic temperature  Why cryogenically cooled CMOS?

0 4.2 K L4He

100 K 77 K LN2

Dry ice 200 K

300 K

- 40°C

400 K + 125 °C

Room Temperature Read-out circuits for high performance infrared (IR) imagers Hybrid circuits (flip-chip)

Automotive electronics & low perf. uncooled IR imagers

T

3.5 m diameter mirror

0.3 K: far IR detection for astronomy (L3He + L4He)

Herschel Space Observatory/PACS (European Space Agency) Indo-French seminar on “New Trends in Electron Device Modeling”, P. Martin | 7

1 - MOSFET compact modeling for design of mixed A/D circuits at cryogenic temperature  CMOS cooled at Ultra Low Temperature (ULT) Ariane 5 launch: 14 May 2009 End of mission: 29 April 2013

LT ASIC: 2 K stage

ULT ASIC: 0.3 K stage (from Si bolometer arrays 2560 px)

 Electrical characterization at 0.3 K and 4.2 K  Low frequency noise meas. at 4.2 K  CMOS ≡ PD-SOI severe floating effects (kink)  Lack of MOSFET model  No complete parameter extraction  “Simple” but robust read-out circuit: mainly PMOS source-followers and switches  0.5 µm commercial CMOS process

Test module Indo-French seminar on “New Trends in Electron Device Modeling”, P. Martin | 8

1 - MOSFET compact modeling for design of mixed A/D circuits at cryogenic temperature  CMOS cooled at Low Temperature (77 < T < 200 K) Many standard effects:  e.g. standard INW (Inverse Narrow Width) effect in PMOS  Temperature scaling to be improved for precise analog modeling in a wide range: 77 - 300 K

Some specific effects:  Anomalous INW effect in NMOS  Negative gate transconductance Gm at high Vgs  Degradation of weak inversion slope  Freeze-out effect in LDD regions

 Energy subbands quantization effect Indo-French seminar on “New Trends in Electron Device Modeling”, P. Martin | 9

1 - MOSFET compact modeling for design of mixed A/D circuits at cryogenic temperature  Freeze-out effect in LDD regions meas.

sim. with EKV3 (modified Verilog-A code)

 Fair agreement obtained with the Hafez model with impact ioniz.  Strong impact of these regions during characterization traditionally made in the linear regime (Vds  50 mV)  artifacts in Vth (L) extractions Indo-French seminar on “New Trends in Electron Device Modeling”, P. Martin | 10

1 - MOSFET compact modeling for design of mixed A/D circuits at cryogenic temperature  Energy subbands quantization effect Peak in Gm for moderate inversion, only on lightly doped and long NMOSFET (< 8 1016 cm-3)  Subbands quantization effect 1.5E-04

NMOSFET 1.8 V LVT at 77 K Gm peak Gm valley

Gm (S)

1.0E-04

5.0E-05 (Ando, 1982)

-Vbs=0 to 1.8 V step 0.6 V Negative Gm W/L=20/20 Vds=50 mV

0.0E+00

-5.0E-05 0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

Vgs (V) Indo-French seminar on “New Trends in Electron Device Modeling”, P. Martin | 11

1 - MOSFET compact modeling for design of mixed A/D circuits at cryogenic temperature Subbands quantization effect: numerical 2D simulations with Atlas (Silvaco)

1 0.30

Poisson-Schrödinger simulations:  Si (100) ; mL=0.916 m0 ; mT=0.19 m0  degeneracy: gL=2 ; gT=4  NA=5x1016 at/cm3 ; T=200 K ; Tox=3.3 nm

Si (100) 200 K Na=5E16 cm-3 Tox=3.3 nm Vgs=0.2 V Vbs=0 V

Energy (eV)

0.25 0.20 CB

0.15 E3L

0.10 E2L E1T 0.05

Ten lowest energy subbands

E1L

2

4E11 electrons/cm

3

0.00 0

0.01

0.02

Depth (µm)

40

80 Vsb=0 V

0.6 V

E1L

1.2 V

60 50

Vsb

40 30 20

E1T

E2L

10 0 0.00

0.25

0.50

0.75

Vgs (V)

1E-04 E1L subband

35

Vsb = 0 - 0.6 - 1.2 V

30

8E-05

25 6E-05

20 15

4E-05

Gm (S)

Occupancy (%)

70

dOccupancy/dVgs (%/V)

2

10 5

2E-05

0 -5 0.00

0.25

0.50

0E+00 0.75

Vgs (V)

Occupancy  Drain current

dOccupancy/dVgs  Gm

Indo-French seminar on “New Trends in Electron Device Modeling”, P. Martin | 12

1 - MOSFET compact modeling for design of mixed A/D circuits at cryogenic temperature Toward compact modeling of the subbands quantization effect

En

 qF  2 m  s



i L ,T

Nn

Fs: surface electrical field

2 3

1 3

Ai n

 g i mi  EF  En  kT Ln 1  exp  2   kT  

Q inv  q  N in

  

n 1

Q b  2 q  Si Nch  s  Vsb  η Q inv  Q b Fs  ε Si

Exact Fs?

n-MOSFET energy band diagram From F. Prégaldiny, PhD U. Strasbourg (2003)

no

yes

  0 Ids Lin 

Q

QC   QC Qinv 

 2

inv



A. Emrani, PhD INP Grenoble (1992)

W 2L Vds 1L Q1invL  1T Q1invT   2 L Qinv  ... L

Indo-French seminar on “New Trends in Electron Device Modeling”, P. Martin | 13

1 - MOSFET compact modeling for design of mixed A/D circuits at cryogenic temperature  LF noise: physical mechanisms Normalized drain current power spectral density WLSId/Id2

1st term: Standard McWhorter carrier number fluctuations (ΔN)

Ghibaudo model:

Id 2 2 SI d  [1   µ C ox ] G m SVfb f  Gm

[A2/Hz]

2nd term: Correlated mobility fluctuations (Δµ) at high current Indo-French seminar on “New Trends in Electron Device Modeling”, P. Martin | 14

1 - MOSFET compact modeling for design of mixed A/D circuits at cryogenic temperature  Matching of MOS transistors

Relative drain current fluctuations vs. Id 100

MC analysis with ELDO after EKV parameter extraction

10

 I d  1   VT0  Id n Ut

Plateau in weak inv. 0.44x0.5 µm² 0.7x0.7 µm² 1.3x1.3 µm²

1

0.1 1E-10

1E-09

1E-08

1E-07

1E-06

(Eq. 1)

13x13 µm²

PMOS 3.3 V LVT 295 K Vds=-3.3 V 1E-05

1E-04

- Id (A)

 Fair agreement between measurements and MC simulations (for relative mismatch higher than ~ 0.5%)  Higher current mismatch at low temperature

1E-03

1E-02 1000 Measurements MC simulations Eq. 1

100

Id) / Id (%)

Id / Id (%)

Measurements MC simulations Eq. 1

10 0.44x0.5 µm² 0.7x0.7 µm² 1.3x1.3 µm²

1

13x13 µm²

PMOS 3.3 V LVT 77 K Vds=-3.3 V 0.1 1E-10

1E-09

1E-08

1E-07

1E-06 - Id (A)

1E-05

1E-04

1E-03

1E-02

Indo-French seminar on “New Trends in Electron Device Modeling”, P. Martin | 15

1 - MOSFET compact modeling for design of mixed A/D circuits at cryogenic temperature  Design of high performance hybrid infrared CMOS image sensors working at low temperature Bispectral IR imager from CEA-Leti

 Format=256 x 256, pitch=30 µm  Complex CMOS circuit, approx. number of transistors: 530,000  0.35 µm / 3.3 V CMOS process  Full parameter extraction at intermediate temperature (77 - 200 K): DC, AC, LF noise, matching and temperature parameters Indo-French seminar on “New Trends in Electron Device Modeling”, P. Martin | 16

SPICE compact modeling: 2nd example

1 - MOSFET compact modeling for design of mixed analog/digital circuits at cryogenic temperature (MOS-AK workshop*, Rome, Italy, 2010) 2 - HSP: A surface-potential-based compact model of AlGaN/GaN HEMTs power transistors (MOS-AK workshop, Bordeaux, France, 2012)

3 - Development of Verilog-A models for silicon photonics devices and implementation in a standard EDA environment (MOS-AK workshop, London, UK, 2014) *

http://mos-ak.org/ Indo-French seminar on “New Trends in Electron Device Modeling”, P. Martin | 17

2 - Leti-HSP, a Surface-Potential-Based Compact Model of AlGaN/GaN HEMTs Power Transistors AlGaN/GaN HEMT schematic structure Gate length (L)

aSi=0.54 nm aGaN=0.32/0.51 nm (a/c axis) Important Δa/a

ILD

n-doped AlxGa1-xN layer (thickness dd)

Drain

Lattice constants:

Source

Schottky Gate

Undoped AlxGa1-xN (thickness di)

Undoped GaN 2D electron gas

Thermal conductivity: KSi=150 W/m.K KGaN=130 KSiC=320

Buffer Silicon substrate Indo-French seminar on “New Trends in Electron Device Modeling”, P. Martin | 18

2 - Leti-HSP, a Surface-Potential-Based Compact Model of AlGaN/GaN HEMTs Power Transistors Leti-HSP model flow Parameters

Voff

Drain current (Id)

Polarization effects (SP, PZ)

Electrostatics Φss, Φsd, Φ, Φsm

Access resistances Self-heating

Temperature modeling

Mobility

Incomplete donor ioniz.

Velocity Saturation

DIBL Effect

Channel Length Mod.

2DEG charge (Qi) Charge partitioning (Qs/Qd) Parasitic cap.

VBA and Matlab code development Verilog-A code implementation Parameter extraction + literature data Circuit simulation using ADS (Keysight Tech.) Schottky gate current (Ig)

HSP compact model flow Indo-French seminar on “New Trends in Electron Device Modeling”, P. Martin | 19

2 - Leti-HSP, a Surface-Potential-Based Compact Model of AlGaN/GaN HEMTs Power Transistors Results: DC current and self-heating Verilog-A code + ADS simulation

L=1 µm and W=75 µm

Indo-French seminar on “New Trends in Electron Device Modeling”, P. Martin | 20

2 - Leti-HSP, a Surface-Potential-Based Compact Model of AlGaN/GaN HEMTs Power Transistors Compact Modeling Coalition (CMC): Selection of a power GaN HEMT model

 Process for standardization in 4 phases  10 models selected during phase 1  4 models still in phase 2:    

ASM: University of California, Berkeley, USA MVSG: Massachusetts Institute of Technology, USA Angelov: Chalmers University, Sweden HSP: CEA-Leti, France

Indo-French seminar on “New Trends in Electron Device Modeling”, P. Martin | 21

SPICE compact modeling: 3rd example

1 - MOSFET compact modeling for design of mixed analog/digital circuits at cryogenic temperature (MOS-AK workshop, Rome, Italy, 2010) 2 - HSP: A surface-potential-based compact model of AlGaN/GaN HEMTs power transistors (MOS-AK workshop, Bordeaux, France, 2012)

3 - Development of Verilog-A models for silicon photonics devices and implementation in a standard EDA environment (MOS-AK workshop, London, UK, 2014) *

http://mos-ak.org/ Indo-French seminar on “New Trends in Electron Device Modeling”, P. Martin | 22

3 - Verilog-A models for silicon photonics devices and implementation in a standard EDA environment CMOS Process Design Kit (PDK) and ASICs design flow Resistor, diode, transistor, etc. but no waveguide, no photodetector, no laser diode, no light modulator, etc.

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3 - Verilog-A models for silicon photonics devices and implementation in a standard EDA environment Photonics PDK and Application Specific Photonics ICs (ASPICs) design flow Waveguide, photodetector, laser diode, light modulator, etc.

Indo-French seminar on “New Trends in Electron Device Modeling”, P. Martin | 24

3 - Verilog-A models for silicon photonics devices and implementation in a standard EDA environment

Photonics device modeling

To simulate a device we need:

 The optical/electro-optical model (optical losses, phase shift, electrooptical effect): coded in Verilog-A  The optical and electrical I/O: optical I/O are described by an optical bus of 9 lines  The electrical model (R-L-C-G from electrical contacts, extrinsic elements due to BOX and HR substrate in the Leti SOI photonics process, etc. ): described by a macro-circuit inside a SPICE netlist

Indo-French seminar on “New Trends in Electron Device Modeling”, P. Martin | 25

3 - Verilog-A models for silicon photonics devices and implementation in a standard EDA environment Photonics device modeling Popt: optical power, pol: light polarization, Φ: optical phase Driving circuitry Popt1= GE/O(felec, fopt, pol) Popt0 (fopt, pol, f) Popt1(t) x uin(t) x Popt0 (fopt, pol, f) CW  MZI modulator (bias) laser GE/O(felec, fopt, pol) Popt2= Gpassive(fopt, pol, f) Popt2(t) x GE/O(felec, fopt, pol) Passive device (e.g. WG) x uin(t) x Popt0 (fopt, pol, f) Gpassive(fopt, pol, f) i(t)= GO/E(Popt, fopt, felec, pol) Photo-Detector (bias) x Gpassive(fopt, pol, f) GO/E(Popt, fopt, felec, pol) x GE/O(felec, fopt, pol) Given T (°C) x uin(t) x Popt0 (fopt, pol, f) uin(t)

i(t)

Reading circuitry (e.g. TIA)

uout(t)

uout(t)=Z x i(t)

Indo-French seminar on “New Trends in Electron Device Modeling”, P. Martin | 26

3 - Verilog-A models for silicon photonics devices and implementation in a standard EDA environment

Optical bus The optical signal is represented by 9 variables: • one variable is the wavelength λ • 2 x 2 x 2 = 8 other variables to describe the optical field

2 possible directions

2 possible polarizations

Real part and imaginary part (in W1/2)

Waveguide (WG) 0

IN

1 2 3

ReX ImX ReY ImY

OUT

6

7 8

OUT

λ

4 5

Re(Ax) Im(Ax) Re(Ay) Im(Ay)

ImY ReY ImX ReX

Im(Ay) Re(Ay) IN Im(Ax) Re(Ax)

• Ax and Ay are the complex amplitude of the two polarization modes

• Complex amplitude more practical than power & phase (linear equations, no discontinuity, less equations) • The wavelength is the same for every devices connected together. It’s the central wavelength of the simulation, usually chosen as the laser wavelength

Indo-French seminar on “New Trends in Electron Device Modeling”, P. Martin | 27

3 - Verilog-A models for silicon photonics devices and implementation in a standard EDA environment Influence of SOI process integration (MIEL conf. 2014) Cmetal

Cmetal

G

S Rs

Cjunction

G Cbox2

Crib

Rrib

Cbox

SiO2

Cbox Rsub

Csub

Si

Macro-model: R, L, C = f (Larm, Ljunction, Tbox, TSi, etc.) Rsub

Rrib

Cmetal

Cbox

Crib

K Rmetal Lmetal Cmetal

Cbox2

Rs

K’

Cbox Cjunction

R, L=f (Frequency)

A

Csub

Vmod=VA-VK’

Indo-French seminar on “New Trends in Electron Device Modeling”, P. Martin | 28

3 - Verilog-A models for silicon photonics devices and implementation in a standard EDA environment SPICE toolbox of passive and active silicon photonics devices / Symbols

Indo-French seminar on “New Trends in Electron Device Modeling”, P. Martin | 29

3 - Verilog-A models for silicon photonics devices and implementation in a standard EDA environment Example: Building an optical link like a Lego® game

Optical Source (OS)

Waveguide (WG)

Photodiode (PD)

A K λ ReX

ImX 1

1

ImX

ReY 2

2

ImY 3

3

ImY

lambda 4

4

lambda

8

ReY ImX ReX

0

0 ReX

1

1 ImX

2

2 ReY

3

3 ImY

4

4 lambda

OUT Elec

5 IN Right

7

ReY

ImY

5 6

OUT Right

0 IN Left

ReX 0

OUT Left

IN Elec

A K

6 7 8

Indo-French seminar on “New Trends in Electron Device Modeling”, P. Martin | 30

3 - Verilog-A models for silicon photonics devices and implementation in a standard EDA environment Example: TRAN simulation of an optical link (ADS simulator from Keysight, Eldo simulator from Mentor Graphics)

A

B

C

D

Indo-French seminar on “New Trends in Electron Device Modeling”, P. Martin | 31

3 - Verilog-A models for silicon photonics devices and implementation in a standard EDA environment Example: Variability study in a purely passive optical device, such as a waveguide, with an electrical simulator (Eldo, Mentor Graphics) Monte Carlo analysis / Number of runs=1000 Optical input power=1.000 W / λ=1.55 µm / T=25 °C / WG_LENGTH=1m DEV/GAUSS=10 % m=0.955 W σ=4.4 mW (0.46%)

Frequency

SOI WG, propagation loss: 2 dB/cm

Optical output power (W) Indo-French seminar on “New Trends in Electron Device Modeling”, P. Martin | 32

Conclusion

SPICE compact modeling is sometimes a very difficult task due to physics (and mathematics!) but

is a prerequisite to design innovative ICs

Indo-French seminar on “New Trends in Electron Device Modeling”, P. Martin | 33

Some references Rosette Nebula (image captured by Herschel)

Reference on cryogenic CMOS: “ MOSFET Modeling for Design of Mixed Analog/Digital Circuits at Cryogenic Temperature ”, P. Martin, MOS-AK workshop on compact modeling, April 8-9, 2010, Rome (Italy). http://www.mos-ak.org/rome/talks/T04_Martin_MOS_AK_Rome.pdf References on power transistors: “ HSP: A Surface-Potential-Based Compact Model of AlGaN/GaN HEMTs Power Transistors ”, Patrick Martin and Rereao Hahe, 10th MOS-AK/GSA ESSDERC/ESSCIRC Workshop, September 21, 2012, Bordeaux (France). http://mos-ak.org/bordeaux/presentations/T07_Martin_MOS-AK_Bordeaux_2012.pdf “ A Surface-Potential-Based Compact Model of AlGaN/GaN HEMTs Power Transistors ”, P. Martin, R. Hahe and L. Lucci, Nanotech Conference, May 12-16, 2013, Washington DC, USA. Technical Proceedings of the 2013 NSTINanotechnology Conference and Trade Show, Nanotech 2013, vol. 2, pp. 544-547. “ A Compact Model of AlGaN/GaN HEMTs Power Transistors Based on a Surface-Potential Approach ”, P. Martin and L. Lucci, 20th Int. Conference Mixed Design of Integrated Circuits and Systems (MIXDES), Gdynia, Poland, June 20-22, 2013. References on silicon photonics: “ Development of Verilog-A models for silicon photonics devices and implementation in a standard EDA environment ”, Patrick Martin, Fabien Gays, Edouard Grellier and Sylvie Menezo. http://www.mos-ak.org/london_2014/presentations/02_Patrick_Martin_MOS-AK_London_2014.pdf “ Modeling of Silicon Photonics Devices with Verilog-A ”, P. Martin, F. Gays, E. Grellier, A. Myko and S. Menezo, Proceedings of the 29th Int. Conference on Microelectronics (MIEL 2014), pp. 209-212, Belgrade, Serbia, 12-15 May 2014. http://dx.doi.org/10.1109/MIEL.2014.6842123 Indo-French seminar on “New Trends in Electron Device Modeling”, P. Martin | 34

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