3G: The Evolution of the Serial Digital Interface (SDI) By John Hudson and Nigel Seth-Smith

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John Hudson

Nigel Seth-Smith

SMPTE and the International Telecommunications Union (ITU) have both recently adopted new standards for a 3-Gbit/sec (nominal) SDI interface using 75 coaxial cable and BNC connectors. The interest in these interfaces is driven by a desire to be able to transport 1080line progressive format video over a single-link interface, rather than the dual-link interfaces currently used. The implementation of this interface with existing infrastructure components such as patch panels, connectors, coax cable types, and such, has been studied, and key components have been realized in silicon. The results of this work and key design guidelines are discussed in this paper.

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hen television broadcast networks were first established 70 years ago, video signals, which were then analog baseband, were distributed on 75 coaxial cables and terminated with BNC connectors. Twenty years ago, when the video signal transitioned to the serial digital interfaces (SDI) (SMPTE 259M),1 the same 75 coax infrastructure was retained. Coaxial cable has many advantages over other cable types, including support for high frequencies, its physical robustness, and simple connectivity. As new facilities were built, higher grades of compatible coaxial cable were introduced, resulting in facilities with greater amounts of performance margin in their cabling infrastructure. Ten years ago, when HD-SDI (SMPTE 292M)2 was introduced, the existing cable was once again retained. Today, there is a need for even higher speed interfaces. Can this transition to a higher speed interface be achieved while retaining the existing cable infrastructure?

Why a Higher Capacity Interface Is Required In North America, the dominant broadcast HDTV standards are 720p/60 and 1080i/60. The European Broadcast Union (EBU) has recently decided to support both 720p/50 and 1080i/50 HDTV formats. It is probable that many production facilities will want to distribute their program material in both formats—perhaps broadcasting in 720p but producing a DVD in 1080i. This places many production facilities in a quandary when trying to decide on a common production format. One possible solution is to produce content in a 1080line progressive format, which can be easily converted to either emission format with minimal quality degradation. In addition, there is a growing desire and need to

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3G: THE EVOLUTION OF THE SERIAL DIGITAL INTERFACE (SDI) produce high-definition content at higher bit depths (12 bits per component), and to provide support for R'G'B' and 4:4:4:4 processing. Another application that is driving the need for a higher capacity interface is digital cinema. For example, the proFigure 1. Required bit rate to transmit various video formats. posed SMPTE 428-x, “Digital Cinema Distribution Master (DCDM) Image Characteristics Level 3—Serial Digital Interface Signal Formatting,” defines a 2048 x 1080p/24, 4:4:4 (X'Y'Z')/12-bit format.3 Note: At time of writing, SMPTE 428-x is in development within the DC28 technology committee. Unfortunately, the bandwidth requirements to transmit these video formats in serial digital form exceed the capabilities of a single SMPTE 292M interface (Fig. 1). All of the above applications could be addressed by using two or more SMPTE Figure 2. Insertion loss for 100 m of two different coax cable types. 292M 1.5-Gbit/sec links. Indeed, and the success of SDI is due in no small part to a numSMPTE 372M4 provides a standardized method for the ber of specific characteristics: carriage of such higher capacity signals over a dual-link • Ability to transport uncompressed signals interface, providing an aggregate bandwidth of 2.97 • Low latency Gbits/sec. However, such dual-link interfaces are very • Cost-effective implementation expensive and awkward to implement. • Robustness and reliability The use of mezzanine compression would allow high• Seamless interoperability er bandwidth signals to be squeezed into a single 1.5 • Reuse of existing infrastructure Gbit/sec link. This mandates the addition of codecs at The last point has been one of the critical success every input and output. Except for cost considerations, factors for SDI and is characterized by the ability of the the compression scheme needs to be carefully interface to evolve over time, while retaining the use of designed to minimize image degradation and latency. the installed base of cabling, patch panels, and BNC The use of high-speed optical interconnect would connectors. This characteristic is very important, as also provide sufficient bandwidth to address the above much of the cabling in a facility is routed through walls applications and more. Although such interfaces are and conduits, making it prohibitively expensive to technically feasible, they are still very expensive to change. An ideal higher capacity transport interface implement and require different capabilities, in terms of should embody all of the characteristics identified system design, installation, and maintenance, comabove, building on the evolutionary success of SD and pared to the traditional coax and BNC infrastructure HD SDI. common today. To this end, new standards for a 2.97-Gbit/sec SDI The Ideal Transport Interface interface using 75 coax cable and BNC connectors has now been adopted by both SMPTE (SMPTE 424M SD and HD SDI have become the ubiquitous interface and 425M) and the ITU (ITU-R-BT.1120-3-2005).5 standards within the professional broadcast industry, SMPTE Motion Imaging Journal, November/December 2006 • www.smpte.org

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3G: THE EVOLUTION OF THE SERIAL DIGITAL INTERFACE (SDI) quency of the signal it carries. Figure 2 shows the insertion loss of a 100-m section of two different types of coaxial cable used in broadcast applications. To properly receive a signal that has traveled a length of cable, a cable equalizer must be used. This device is a filter with a frequency response that is the complement of the response of the cable. In most video applications, the equalizers used are “adaptive” in that they automatically adjust the amount of equalization applied to match the total loss in the cable to which they are connected. To design a cable equalizer that will recover a 3Gbit/sec signal after it has been attenuated by a length of cable, a high-pass filter must be designed. Typically, the high-pass filter realized has a frequency response with a gradient of approximately 6 dB/octave. Careful design with regard to the placement of the poles and zeros of the filter is required to ensure that an approximation of the desired 1/root f response is achieved. Figure 3 shows the equalizer frequency response, along with the cable insertion loss for 100 m of coaxial cable. As shown, the equalizer is able to compensate for cable loss at frequencies greater than 1.5 GHz, thus making it suitable to be used with 3-Gbit/sec data. Despite the fact that the input signal is not completely restored by the equalization filter, restoration is sufficient to allow the DC restorer, digital slicer, and output buffer of the device to recover the entire signal. This is illustrated in Fig. 4, which shows a screen shot of the input and output of the GS2974 multi-rate (DC to 3 Gbits/sec), adaptive cable equalizer. The diagram illustrates equalization of 100 m of Belden 1694A cable with a data rate of 3 Gbits/sec (PRN-23 signal).

Table 1—Source Image Formats Supported in the 3-Gbit/sec SDI Standards

3-Gbit/sec SDI Standards ITU-R-BT.1120-3, “Digital Interfaces for HDTV Studio Signals,” was revised in 2005 to include support for the transmission of 1920 x 1080 50p and 60p Y'C'BC'R 4:2:2 10-bit data over a 2.970 or 2.970/1.001 Gbit/sec SDI interface. The 3-Gbit/sec interface standard from SMPTE is defined in two documents: SMPTE 424M6 for the physical interface and SMPTE 425M7 for data mapping. The SMPTE standards cover a wider scope of applications than ITU-R-BT.1120-3, as shown in Table 1. In addition to support for the above image formats, SMPTE 425M also provides a standardized means to transport two SMPTE 292M-compliant signals over a single 3-Gbit/sec SDI interface. In support of these standards, semiconductor devices are now commercially available that enable a 2.97Gbit/sec SDI interface capable of operating over existing HD-SDI cabling and plant.

3-Gbit/sec Cable Equalization One of the major limiting factors for sending highspeed data over copper cables is the skin effect, which results in increased attenuation as the frequency of the signal increases. Other factors such as dielectric loss and impedance mismatches at connectors also limit cable-length performance at high bit rates, but beyond about 20 m or so at the frequencies being discussed in this paper, losses are dominated by the skin effect. This effect is due to the flow of AC currents mostly on the surface (skin) of a conductor at high frequencies. As a result of the skin effect, the insertion loss of a piece of cable increases as the square root of the fre474

3-Gbit/sec Data Re-clocking As can be seen in Fig. 4, an equalized signal is not necessarily a clean signal, since an equalizer does nothing to remove jitter resulting from noise added on

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3G: THE EVOLUTION OF THE SERIAL DIGITAL INTERFACE (SDI) the link. It would not be possible to use an equalized signal to go any additional distance without first reducing the jitter. Jitter reduction is typically accomplished using a data re-clocking circuit. A SDI re-clocker needs to be specifically designed to meet the unique requirements of the interface. SDI signals are very different from other signals commonly found in the datacom and telecom industries, due to the data rates employed and other unique signal characteristics (pathological signals), resulting from the scrambling polynomial defined in SMPTE 259M, Figure 3. Cable insertion loss and equalizer gain. SMPTE 292M, and SMPTE 424M. can accumulate from unit to unit. The LBW of the receivAt the simplest level, a SDI data re-clocker provides er at each subsequent unit must therefore be wide the means to extract a clock signal from the serial data enough to accommodate the accumulated jitter. Ideally, stream; to lock an extremely low-phase-noise voltagethe re-clocking device should automatically adapt its controlled oscillator to the extracted clock, using a LBW in accordance with the input jitter; otherwise it may phase-locked loop (PLL); and to re-sample the serial be necessary to optimize each receiver in the system at digital input signal with the low-noise clock source. the time of installation. This kind of functionality is diffiWhen designing a PLL for a SDI re-clocker, a tradeoff cult to achieve with a traditional linear PLL-based remust be made between the amount of jitter that can be clocking device; however, other techniques such as the present on the input (input jitter tolerance or IJT) and the slew PLL can be employed to achieve this requirement. amount of residual jitter that is output from the device. Figure 5 compares the jitter attenuation performance Critical to system performance is the setting of the of a linear and a slew PLL. For a fair comparison, the lower band edge of the PLL loop filter or loop bandwidth phase slew of the slew PLL and LBW of the linear PLL (LBW) of the re-clocking device. Generally, more jitter are chosen such that at 0.2 UI (Unit Interval), input jitter attenuation is achieved by lowering the LBW, whereas modulation, both achieve 3 dB attenuation at 1.4 MHz board and system noise immunity is achieved with a modulation frequency. higher LBW. The jitter transfer function is plotted at 2.8 MHz to Another important factor to recognize is that the lower show how the PLL attenuates input jitter at higher frethe loop bandwidth, the longer it will take for the requency. It can be seen that the output jitter of the slew clocker to lock to the incoming source. This is especially important where source switching, for example, in a router, is employed. Taking all of these factors into account, a good compromise is to set the re-clocker LBW between 500 kHz and 2 MHz, with 1.4 MHz being optimal for the majority of serial routing and distribution applications. In multi-pass systems in which the SDI signal is cascaded within a facility, jitter

Figure 4. Input and output of equalizer after 100 m of Belden 1694A cable with a data rate of 3 Gbits/sec.

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Figure 5. Transfer functions of linear and slew PLLs.

PLL attains a maximum and then it is limited. This is an attribute of the nonlinearity present in the slew PLL. In summary, a slew PLL achieves higher jitter attenuation in the presence of large input jitter, while providing small signal VCO/board noise immunity. The capabilities discussed above are especially important in systems operating at the higher data rates of the 3-Gbit/sec SDI interface as system jitter margins are significantly reduced. Figure 6 shows a screen shot of the output of the GS2975—a multi-rate to 3-Gbit/sec slew PLL re-clocker. The diagram illustrates a re-clocked 3-Gbit/sec PRN-23 signal after 100 m of equalized Belden 1694A cable. Figures 7 and 8 show an 11-stage multi-pass configuration. In this demonstration, off-the-shelf cabling, connectors, and a patch panel were combined with 10 prototype re-clocking distribution amplifiers and a prototype 3-Gbit/sec router to represent a system installation. The 3-Gbit/sec FPGA-based SDI signal generator in this system is locked to an NTSC black burst reference using a GS4911B genlock and a GS4915 clock-cleaning device. Just visible in the background of Fig. 8 is a clean and open eye from the serial digital output of the last pass in the system, illustrating 0.25 UI alignment jitter after 11 passes.

Because of the higher data rate of the 3Gbit/sec SDI interface, certain parameters such as rise/fall time, output return loss, and alignment jitter could prove to be challenging from a system design perspective. As long as some basic guidelines are followed; however, (described later) designing a SMPTE 424M-compliant transmitter should not be any more onerous than designing a SMPTE 292M-compliant transmitter. No new or special design techniques are required, and commercial silicon is now available that greatly simplifies the task. Careful design of the transmitter, however, is paramount to good system performance, and perhaps one of the more challenging aspects of SMPTE 424M is the output jitter specification. Although it is not the intent of this paper to present a detailed system jitter analysis, it is worth discussing some general rules of thumb and good engineering practice.

Transmit Jitter Template The jitter template shown in Fig. 9 is derived from the parameters defined in SMPTE 424M. According to the diagram in Fig. 9, the source should produce no more than 2 UI (673 ps) timing jitter in the frequency band from 10 Hz to 15 kHz. Between 15 kHz and 100k-Hz, the timing jitter template rolls off at a slope of 20 dB per decade. The alignment jitter should be no more than 0.3 UI (101 ps) in the

3-Gbit/sec SDI Transmitter SMPTE 424M defines the signal characteristics for a compliant 3-Gbit/sec SDI transmitter, and in many respects, the 3-Gbit/sec SDI standard is very similar to the 1.5 Gbit/sec HD SDI standard. 476

Figure 6. 3-Gbit/sec signal after 100 m of cable, equalization, and re-clocking.

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3G: THE EVOLUTION OF THE SERIAL DIGITAL INTERFACE (SDI)

Sources of Alignment Jitter

Figure 7. Block diagram of multi-pass configuration shown in Fig. 8.

frequency band beyond 100 kHz. SMPTE 424M defines the alignment jitter from 100 kHz to something greater than 1/10th the serial clock frequency. It is very important to make sure that this parameter is met up to 1.485 GHz, as jitter, due to duty cycle distortion in the transmitter, may appear at half the serial-clock frequency. Low-frequency or timing jitter is generally “outside the loop bandwidth” of SDI data recovery devices. The PLLs in a welldesigned SDI re-clocker can typically accommodate (track or pass) up to about 10 UI of timing jitter before the onset of signal errors. In de-serializers—depending on the design— the timing jitter margin can be even larger, due to the serial-to-parallel conversion and the use of parallel data FIFOs and buffers. In general, timing jitter is of little concern in SDI systems. However, designers should be aware that timing jitter will accumulate at each “pass” in a serial digital system; thus it is highly recommended that positive action is taken to attenuate accumulated timing jitter in receiver designs and to minimize the generation of timing jitter in transmitter designs. This is discussed further in the following sections. Alignment jitter has a much more powerful impact on system performance and must be tightly controlled to achieve the expected SDI bit error rate of at least 10-12. Having only 101 ps of alignment jitter places strict demands on the transmitter design.

Bandwidth-limited devices in the signal chain, such as cable drivers, cable equalizers and cross-point switches, serial digital muxes, and buffers, all add jitter. Impedance discontinuities through connectors and transmission line stubs (leading to signal reflections), cross talk, and noise coupling also contribute to jitter. In all of the above cases, the jitter effect is due to some form of signal distortion and cannot be completely eliminated. Thus, the jitter introduced from these effects can be considered systematic and

Figure 8. 11-stage multi-pass 3-Gbit/sec SDI configuration.

Figure 9. Jitter template for SMPTE 424M.

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Figure 10. Notional equipment block diagram.

cumulative (arithmetically additive). Note that in some cases, the jitter so produced could be considered subtractive; however, to build a robust system, designers should consider systematic jitter to be purely additive when deriving a jitter budget. Pathological signal patterns, which are unique to SMPTE signals, can cause poorly designed standard PLL circuits to introduce jitter and bit errors. This is especially true for data recovery circuits, which extract clock from data and are inevitably pattern dependent. The noise in a PLL circuit designed for a serializer device is generally not pattern dependent, because the PLL locks on to a reference clock. However, these devices can be very sensitive to board and power supply noise, which in turn can be data pattern dependent; thus the serializer will also be a source of both systematic and pattern dependent (random) jitter. The jitter generated in even a very careful design can very quickly become significant at 3 Gbits/sec. This means that special attention is required in the design of the system reference clock and serial-to-parallel/parallel-to-serial conversion circuitry.

Example Jitter Budget Calculation— Receiver Consider the notional equipment block diagram in Fig. 10. Assuming a 3-Gbit/sec SDI source operating at the maximum allowable limits of SMPTE 424M and worstcase operating conditions, it can be seen that to achieve robust system performance, an IJT of approximately 0.6 UI is required. The LBW of the de-serializer should be chosen between 3 MHz and 6 MHz to accommodate multi-pass system jitter accumulation and to provide margin for pat478

tern-dependent jitter caused by pathological signals. Example: If the receiver’s LBW is 4.2 MHz and the input source is provided by the output of a router with a LBW of 1.4 MHz, the receiver will follow the jitter of the router during pathological video lines. The phase at the re-clocker in the router with an LBW of 1.4 MHz slews slowly so that a 4.2-MHz receiver will closely track the signal without introducing bit errors, even allowing for worst-case manufacturing tolerances and operating conditions. A number of different FPGA vendors now offer devices with built-in high-speed transceivers. These devices provide a flexible and popular choice when implementing 3-Gbit/sec SDI de-serializers. It should be noted, however, that these devices may not provide sufficient IJT margin or a low enough LBW to accommodate the jitter budget shown in Fig. 10. Therefore, it is recommended that receivers include a 3-Gbit/sec SDI re-clocker in front of an FPGA-based de-serializer, to ensure that the IJT can be achieved. Ideally, a re-clocker should be provided at each input, immediately following the input equalizer. It should also be noted that there is very little timing or alignment jitter attenuation of the processor clock output of the de-serializer, resulting in at least 1 UI (~336 ps) of alignment jitter on the parallel interface. This clock jitter can be further compounded within the parallel processing domain of the equipment, with up to 3 UI of jitter (~1 nsec), typical unless care is taken with clock distribution in the design. Although this is a concern when calculating set-up and hold-time margin between parallel processing devices, it is generally not a major problem in terms of system operation. However, this clock should never be

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3G: THE EVOLUTION OF THE SERIAL DIGITAL INTERFACE (SDI) ally fixed to a single rate. If a piece of equipment is required to address multiple rates, then multiple VCXO/PLLbased genlock circuitry is required, which can be costly to implement. Generic digital clock generators using techniques such as direct digital synthesis (DDS), can be used to provide a greater level of flexibility. However, the clock signals produced by such devices generally have very poor high-frequency jitter performance. While these clock generators are adequate for parallel domain processing, they are not suitable for 3-Gbit/sec SDI transmitters. Figure 11. Jitter spectrum of the GS4911B genlock and GS4915 clock cleaner. Semiconductor devices such as the GS4911B and the GS4915 are used to directly drive an SDI serializer unless that serialdesigned specifically to address the timing and clock izer is able to filter the jitter using a VCXO/PLL. generation requirements for professional broadcast equipment. These devices provide the flexibility of digital Example Jitter Budget Calculation— clock generators with the very low alignment and timing Transmitter jitter available from VCXO/PLL-based designs. Such The diagram in Fig. 10 shows a clean transmit clock devices greatly simplify the task of creating a suitably source-genlocked to a house reference. clean clock signal for 3 Gbit/sec SDI transmitters. The specification for a typical synchronization signal Figure 11 shows the jitter spectrum of the GS4911B is defined in SMPTE 318M8 and a genlock circuit utiliztiming generator and the GS4915 clock-cleaner. In this ing a VCXO should be used with very low LBW (