From September 2009 High Frequency Electronics Copyright © 2009 Summit Technical Media, LLC

High Frequency Design

SYNTHESIZER DESIGN

Practical Developments Using Today’s Fractional Synthesizers By Jim Carlini

I

ntegrated fractional PLL solutions have been available since the late 1990s. Over the past decade the in-band phase noise associated with the fractional processes has been greatly reduced. So have the troublesome fractional spurs. The base noise floor in dBc/Hz for some state of the art, low noise fractional PLLs approaches that of the lowest integer devices. Table 1 shows data for the recently released ADF4150 and the LMX2487E, which was recently reevaluated and found to have a lower noise floor then what’s on the datasheet. The table doesn’t take into account PLL 1/f noise. 1/f noise is a phenomena that increases by 3 dB/octave at some break point close to the carrier frequency, i.e. 1 to 10 kHz. For low noise, narrow span applications this may be a concern. The basic advantage of the fractional PLL is that the value of N by which the VCO is divided can be greatly reduced. In theory every time N is halved the phase noise goes down by 6 dB. However in reality it’s increased 3 dB for every halving of N due to the 10Log(PFD) rule. In reality the situation is more complex, but this is the basic premise for choosing fractional synthesis. However for certain application when a low fixed value of N is used (i.e. as is often the case for a 2nd LO)

This article reviews the design procedures for fractional-N synthesizers, with examples that demonstrate the performance achievable with currentlyavailable PLL IC products

Fractional PLL(Noise Floor) dBc / Hz –219 (ADF4150) –216 (LMX2487E)

an integer PLL could remain the PLL of choice.

Review of PLL Theory A RF-Microwave PLL is a feedback loop that is defined by the following linear equations: Forward Gain, Open Loop Gain and Closed Loop Gain. This article is centered on modern integrated PLLs that use current source-sink charge pumps. The circuit takes the VCO’s output and divides it down by an N counter. The reduced frequency is then applied to the negative input of a phase detector. Here it is compared to that of a stable reference clock, whose signal is applied to the positive input of the phase detector. The phase detector acts as a summing circuit and produces a difference that is proportional to the difference between the divided down VCO frequency and reference clock. This phase error drives a charge pump which sources or sinks a difference current to a lowpass filter. The Lowpass filter charges up to a new DC voltage, retuning the VCO. This retuning continues until phase lock is achieved. Once the loop is locked the charge pump is in a high impedance state. The terms used in the loops transfer function are defined as follows. KΦ represents the phase detector with units in mA/radian. F(s) is the lowpass (loop) filter; the filter design can range from 2nd to 5th order, depending on the spur rejection required. Theoretically each additional pole provides extra 6 dB/octave of spurious attenuation. Kv is the VCO’s tuning Integer PLL(Noise Floor) dBc / Hz –219 (ADF4108) –219 (LMX2434)

Table 1 · Comparison of the noise floor for extremely low noise PLLs. 34

High Frequency Electronics

High Frequency Design

SYNTHESIZER DESIGN

Figure 1 · The PLL block diagram used to derive equations 1-3 and circuit description.

gain in MHz/volt. 1/s is a Laplace term needed for the loop to operate in the phase domain. N is the value of the N divider.

Figure 2 · Recommended circuit for spurious suppression on PLL’s charge pump input.

scope of this article and can be found in Deansbook v4 [1]. Forward Gain = K Φ ∗ F (s) ∗ Kv ∗ 1 / s

(1)

External Noise Reduction Equation 1) is the forward transfer function, without feedback. Open Loop Gain = ( K Φ ∗ F ( s) ∗ Kv ∗ 1 / s) / N

(2)

Equation 2) characterizes the Loops when it is not at equilibrium. This is used to evaluate lock time and loop stability.

Closed Loop Gain =

K Φ ∗ F ( s) ∗ Kv ∗ 1 / s K Φ ∗ F ( s) ∗ Kv / s ∗ N

=

Forward Gain 1 + Open Loop Gain

(3)

Equation (3) characterizes the loop it is phase locked. This function is responsible for shaping the PLL’s inband phase noise and spurs. Detail on how these transfer functions affect the PLL in the way they do is beyond the

Voltages should be applied though a wideband ferrite surface mount part (see Figures 2 and 3). It’s recommended that the ferrite filter’s other end be directly connected to the junction of two capacitors. A capacitor is required whose value can range between (100 to 10 min.) µF, preferably on the higher side if possible. This capacitor should have very low ESR >20 dB/decade of attention to spurs. The fact that (14.925 / 0.011) MHz = 1361.4 results in >136 decades of frequency spacing between the PFD and Fc and speaks for itself. The reference spurs will fall below the noise floor. The phase noise at 10 kHz offset is –91.5 dBc Hz, at 20 kHz offset its –98 dBc/Hz. The 3rd order 11 kHz loop filter provides excellent spurious suppression. The fundamental frac42

High Frequency Electronics

Figure 8 · Plot of PLL phase noise and worse case fractional spurs (nonIBS), frac/mod = 54/199.

Figure 9 · Plot of PLL phase noise and worse case IBS, frac/mod = 1/199.

tional spur is attenuated by >27 dB and is has a level approx. –72.1 dBc. The IBS receives the same attenuation, but was modeled to be 8 dB higher, a realistic worse case scenario. Despite tweaking for low noise the phase margin at Fc is maintained. The improvement in frequency acquisition (locktime) is seen in the frequency error vs. time graph. The PLL is locked at ≈350 µs. CSR results in ≈3 times faster frequency acquisition from Fmin to Fmax. Locktime could be improved by decreasing the PFD, at the expense of phase noise. Note: Every halving of the PFD adds 3 dB noise. Also as the PFD to Fc ratio 31 GHz). Many of his designs were receiver-exciter related, including discretely built PLLs, oscillators, LNAs and down-convertors, as well as the control circuit needed to run the RF circuitry and interface them with baseband. He has also designed

a wide variety of planar circuitry including couplers, summing and power distribution networks, as well as antennas. Jim has served as a Teaching Adjutant for the graduate EM lab at the Rochester Institute of Technology, and has done design, analysis and troubleshooting work for Bosch, RIT, Cybernet Systems and Harris RF Communications. He can be reached at [email protected]

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