OTI012 STANDARD MODE PINOUT Standard Mode Pin-Out Assignment if pin 28 tied to Vss Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Pin Name Vss RAD[6] RAD[7] RAD[8] RAD[9] RAD[10] RAD[11] RAD[12] RAD[13] RAD[14] RAD[15] RWEB Vss ROEB N/C RD[7] RD[6] RD[5] RD[4] RD[3] RD[2] RD[1] RD[0] Vss XIN XOUT TEST1 ENHANCE

Type P O O O O O O O O O O O P O B B B B B B B B P I O I I

29 30 31 32 33 34 35 36 37 38 39 40

DCSEL DLMSEL Vdd DLRCK DSDATA DBCK N/C DC2PO MCK UD[0] UD[1] UD[2]

I I P I I I I O B B B

Comments Vss RA6 RA7 RA8 RA9 RA10 RA11 RA12 RA13 RA14 RA15 /RWE Vss /ROE Unused IO8 IO7 IO6 IO5 IO4 IO3 IO2 IO1 Vss XTAL XTAL TESTA 0-Standard 1-Enhanced CSEL LMSL Vdd LRCK SDATA BCK Unused C2PO MCK D0 D1 D2

Pin 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

Pin Name Vss UD[3] UD[4] UD[5] UD[6] UD[7] URS URDB UWRB UCSB UNITB Vss RESETB HCSB HWRB HRDB HCMDB HWAITB RDTENB HSTENB HEOPB RCSB Vss HD[7] HD[6] HD[5] HD[4]

69 70 71 72 73 74 75 76 77 78 79 80

HD[3] HD[2] HD[1] HD[0] Vdd HSELDRQB RAD[0] RAD[1] RAD[2] RAD[3] RAD[4] RAD[5]

Type Comments P Vss B D3 B D4 B D5 B D6 B D7 I RS I /RD I /WR I /CS O /INT P Vss I /RESET I /ENABLE I /HWR I /HRD I /CMD O /WAIT O /DTEN O /STEN O /EOP O /RCS O Unused P Vss B HD7 B HD6 B HD5 B HD4 B B B B P I O O O O O O

HD3 HD2 HD1 HD0 Vdd /SELDRQ RA0 RA1 RA2 RA3 RA4 RA5

OTI012 ENHANCED MODE PIN-OUT ASSIGNMENT Enhanced Mode Pin-Out Assignment if pin28 is tied to Vdd Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Pin Name Vss RAD[6] RAD[7] RAD[8] RAD[9] RAD[10] RAD[11] RAD[12] RAD[13] RAD[14] RAD[15] RWEB Vss ROEB HA1

Type P O O O O O O O O O O O P O I

Pin 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

Pin Name Vss UD[3] UD[4] UD[5] UD[6] UD[7] URS URDB UWRB UCSB UNITB Vss RESETB HCSB HWRB

Type P B B B B B I I I I O P I I I

Comments Vss D3 D4 D5 D6 D7 RS /RD /WR /CS /INT Vss /RESET /ENABLE /HWR

B B B B B

Comments Vss RA6 RA7 RA8 RA9 RA10 RA11 RA12 RA13 RA14 RA15 /RWE Vss /ROE Host Address 1 IO8 IO7 IO6 IO5 IO4

16 17 18 19 20

RD[7] RD[6] RD[5] RD[4] RD[3]

56 57 58 59 60

HRDB HA0 HDRQ HDRQEB HFBLB

I I O O O

RD[2]

B

IO3

61

HFBC

O

22 23 24 25 26 27

RD[1] RD[0] Vss XIN XOUT EJECT

B B P I O I

62 63 64 65 66 67

RCSB HRSTB Vss HD[7] HD[6] HD[5]

O O P B B B

28

ENHANCE

I

68

HD[4]

B

HD4

29 30 31 32 33 34 35

DCSEL DLMSEL Vdd DLRCK DSDATA DBCK HDACKB

I I P I I I I

69 70 71 72 73 74 75

HD[3] HD[2] HD[1] HD[0] Vdd HSELDRQB RAD[0]

B B B B P I O

HD3 HD2 HD1 HD0 Vdd /SELDRQ RA0

36 37 38 39 40

DC2PO MCK UD[0] UD[1] UD[2]

I O B B B

IO2 IO1 Vss XTAL XTAL Disk Door Eject Switch 0-Standard 1Enhanced CSEL LMSL Vdd LRCK SDATA BCK Host Data Acknowledge From DMA controller C2PO MCK D0 D1 D2

/HRD Host Address 0 Host Data Request Host DRQ Enable Host First Byte Latch Host First Byte Cycle /RCS Reset from Host Vss HD7 HD6 HD5

21

76 77 78 79 80

RAD[1] RAD[2] RAD[3] RAD[4] RAD[5]

O O O O O

RA1 RA2 RA3 RA4 RA5