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Digital Integrated Circuits A Design Perspective Prentice Hall Electronics and VLSI Series ISBN 0-13-120764-4
Introduction [Adapted from Rabaey’s Digital Integrated Circuits, Second Edition, ©2003 Rabaey, A. Chandrakasan, B. Nikolic]
J. 1
Copyright 2003 J. Rabaey et al.
Introduction
Introduction Why
is designing digital ICs different today than it was before? Will it change in future?
2
Introduction
The First Computer The Babbage Difference Engine (1832) 25,000 parts cost: £17,470
3
Introduction
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ENIAC - The First Electronic Computer (1946)
4
Introduction
La Révolution du Transistor
Premier transistor Bell Labs, 1948 5
Introduction
The First Integrated Circuits Logique Bipolaire des Années 60
ECL Porte 3-entrées Motorola 1966 6
Introduction
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Intel 4004 MicroMicro-processor 1971 2300 transistors 1 MHz operation
7
Introduction
Intel Pentium (IV) Microprocessor
8
Introduction
Transistor Revolution
Transistor –Bardeen (Bell labs) in 1947 Bipolar transistor – Schockley in 1949 First bipolar digital logic gate – Harris in 1956 First monolithic IC – Jack Kilby in 1959 First commercial IC logic gates – Fairchild 1960 TTL – 1962 into the 1990’s ECL – 1974 into the 1980’s
9
Introduction
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MOSFET Technology
MOSFET transistor - Lilienfeld (Canada) in 1925 and Heil (England) in 1935 CMOS – 1960’s, but plagued with manufacturing problems PMOS in 1960’s (calculators) NMOS in 1970’s (4004, 8080) – for speed CMOS in 1980’s – preferred MOSFET technology because of power benefits BiCMOS, Gallium-Arsenide, Silicon-Germanium SOI, Copper-Low K, … 10
Introduction
Moore’s Law
In 1965, Gordon Moore predicted that the number of transistors that can be integrated on a die would double every 18 to 14 months (i.e., grow exponentially with time). Amazingly visionary – million transistor/chip barrier was crossed in the 1980’s.
2300 transistors, 1 MHz clock (Intel 4004) - 1971 16 Million transistors (Ultra Sparc III) 42 Million, 2 GHz clock (Intel P4) - 2001 140 Million transistor (HP PA-8500) 11
Introduction
1975
1974
1973
1972
1971
1970
1969
1968
1967
1966
1965
1964
1963
1962
1961
1960
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1959
LOG2 OF THE NUMBER OF
COMPONENTS PER INTEGRATED FUNCTION
Moore’s Law
Electronics, April 19, 1965. 12
Introduction
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Transistor Counts 1 Billion Transistors
K 1,000,000 100,000 10,000 1,000 i386 80286
100
i486
Pentium® III Pentium® II Pentium® Pro Pentium®
8086
10
Source: Intel
1 1975
1980
1985 1990
1995
2000
2005 2010
Projected 13
Introduction
Courtesy, Intel
Moore’s Law in Microprocessors
Transistors (MT)
1000
2X growth in 1.96 years!
100 10
486
1
P6 Pentium® proc
386 286
0.1 8086 8080 8008 4004
8085
0.01 0.001
1970
1980
1990 Year
2000
2010
Transistors on Lead Microprocessors double every 2 years
14
Introduction
Courtesy, Intel
Evolution in DRAM Chip Capacity human memory human DNA
100000000 10000000
64 000 000
4X growth every 3 years!
16 000 000
K b it cap acity/ch ip
4 000 000 1000000
1 000 000 256 000
book
100000
64 000 16 000
10000 4 000 1000
1 000 256
100 64 10 1980
0.07 µm
0.1 µm
0.13 µm
0.18-0.25 µm
0.35-0.4 µm
0.5-0.6 µm
encyclopedia 2 hrs CD audio 30 sec HDTV
0.7-0.8 µm
1.0-1.2 µm
1.6-2.4 µm
page 1983
1986
1989
1992
1995
Year
1998
2001
2004
2007
2010
15
Introduction
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Die Size Growth Die size (mm)
100
10 8080 8008 4004
8086 8085
1 1970
286
386
P6 486 Pentium ® proc
~7% growth per year ~2X growth in 10 years
1980
1990 Year
2000
2010
Die size grows by 14% to satisfy Moore’s Law 16
Introduction
Courtesy, Intel
Frequency Frequency (Mhz)
10000
Doubles every 2 years
1000 100 10
8085
1 0.1 1970
8086 286
386
486
P6 Pentium ® proc
8080 8008 4004 1980
1990 Year
2000
2010
Lead Microprocessors frequency doubles every 2 years 17
Introduction
Courtesy, Intel
Power Dissipation Power (Watts)
100 P6 Pentium ® proc 10 8086 286 1 4004
8008
486 386
8085 8080
0.1 1971
1974
1978
1985
1992
2000
Year
Lead Microprocessors power continues to increase Courtesy, Intel
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Introduction
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Power Will Be a Major Problem 100000
18KW 5KW 1.5KW 500W
Power (Watts)
10000 1000
Pentium® proc
100
286 486 8086 386 10 8085 8080 8008 1 4004 0.1 1971
1974
1978
1985 1992 Year
2000
2004
2008
Power delivery and dissipation will be prohibitive 19
Introduction
Courtesy, Intel
Power Density Power Density (W/cm2)
10000 1000 100
Rocket Nozzle Nuclear Reactor
8086 10 4004 Hot Plate P6 Pentium® proc 8008 8085 386 286 486 8080 1 1970 1980 1990 2000 Year
2010
Power density too high to keep junctions at low temp 20
Introduction
Courtesy, Intel
Not Only Microprocessors Cell Phone Small Signal RF
Digital Cellular Market (Phones Shipped)
Power RF
Power Management
1996 1997 1998 1999 2000 Units
48M 86M 162M 260M 435M
Analog Baseband Digital Baseband (DSP + MCU)
(data from Texas Instruments) 21
Introduction
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Major Design Challenges
Microscopic issues
ultra-high speeds power dissipation and supply rail drop growing importance of interconnect noise, crosstalk reliability, manufacturability clock distribution
Macroscopic issues time-to-market design complexity (millions of gates) high levels of abstractions design for test reuse and IP, portability systems on a chip (SoC) tool interoperability
Year
Tech.
Complexity
Frequency
3 Yr. Design Staff Size
Staff Costs
1997
0.35
13 M Tr.
400 MHz
210
$90 M
1998
0.25
20 M Tr.
500 MHz
270
$120 M
1999
0.18
32 M Tr.
600 MHz
360
$160 M
2002
0.13
130 M Tr.
800 MHz
800
$360 M 22
Introduction
Why Scaling?
Technology shrinks by 0.7/generation With every generation can integrate 2x more functions per chip; Chip cost does not increase significantly Cost of a function decreases by 2x But … How to design chips with more and more functions? Design engineering population does not double every two years…
Hence, a need for more efficient design methods Exploit different levels of abstraction 23
Introduction
Fundamental Design Metrics
Functionality Cost NRE (fixed) costs - design effort RE (variable) costs - cost of parts, assembly, test
Reliability, robustness Noise margins Noise immunity
Performance Speed (delay) Power consumption; energy
Time-to-market 24
Introduction
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Cost of Integrated Circuits
NRE (non-recurring engineering) costs Fixed cost to produce the design – design effort – design verification effort – mask generation
Influenced by the design complexity and designer productivity More pronounced for small volume products
Recurring costs – proportional to product volume silicon processing – also proportional to chip area
assembly (packaging) test fixed cost cost per IC = variable cost per IC + ----------------volume 25
Introduction
NRE Cost Is Increasing
26
Introduction
Die Cost Single die
Wafer Going up to 12” (30cm) From http://www.amd.com
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Introduction
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Cost Per Transistor cost:
¢-perper-transistor
1 0.1
Fabrication capital cost per transistor (Moore’s law)
0.01 0.001 0.0001 0.00001 0.000001 0.0000001 1982
1985
1988
1991
1994
1997
2000
2003
2006
2009
2012
28
Introduction
Recurring Costs cost of die + cost of die test + cost of packaging variable cost = ---------------------------------------------------------------final test yield cost of wafer cost of die = ----------------------------------dies per wafer × die yield π × (wafer diameter/2)2 π × wafer diameter dies per wafer = ---------------------------------- − --------------------------die area √ 2 × die area
die yield
= (1 + (defects per unit area × die area)/α)-α 29
Introduction
Defects
defects per unit area × die area die yield = 1 + α
−α
α is approximately 3 die cost = f (die area)4 30
Introduction
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Yield Example
Example O
wafer size of 12 inches, die size of 2.5 cm2, 1 defects/cm2, (measure of manufacturing process complexity)
O
252 dies/wafer (remember, wafers round & dies square)
O
die yield of 16% 252 x 16% = only 40 dies/wafer die yield !
O
α=3
Die cost is strong function of die area z
proportional to the third or fourth power of the die area
31
Introduction
Some Examples (1994) Chip
Metal layers
Line width
Wafer cost
Def./ cm2
Area mm2
Dies/ wafer
Yield
Die cost
386DX
2
0.90
$900
1.0
43
360
71%
$4
486 DX2
3
0.80
$1200
1.0
81
181
54%
$12
Power PC 601
4
0.80
$1700
1.3
121
115
28%
$53
HP PA 7100
3
0.80
$1300
1.0
196
66
27%
$73
DEC Alpha
3
0.70
$1500
1.2
234
53
19%
$149
Super Sparc
3
0.70
$1700
1.6
256
48
13%
$272
Pentium
3
0.80
$1500
1.5
296
40
9%
$417 32
Introduction
Reliability Noise in Digital Integrated Circuits
Noise – unwanted variations of voltages and currents at the logic nodes
from two wires placed side by side capacitive coupling
v(t)
– voltage change on one wire can influence signal on the neighboring wire – cross talk
inductive coupling
i(t)
– current change on one wire can influence signal on the neighboring wire VDD
from noise on the power and ground supply rails can influence signal levels in the gate 33
Introduction
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Example of Capacitive Coupling
Signal wire glitches as large as 80% of the supply voltage will be common due to crosstalk between neighboring wires as feature sizes continue to scale Crosstalk vs. Technology Pulsed Signal 0.12m CMOS 0.16m CMOS
Black line quiet Red lines pulsed
0.25m CMOS
Glitches strength vs technology
0.35m CMOS
From Dunlop, Lucent, 2000
34
Introduction
Static Gate Behavior
Steady-state parameters of a gate – static behavior – tell how robust a circuit is with respect to both variations in the manufacturing process and to noise disturbances. Digital circuits perform operations on Boolean variables x ∈{0,1} A logical variable is associated with a nominal voltage level for each logic state 1 ⇔ VOH and 0 ⇔ VOL V(x)
V(y)
VOH = ! (VOL) VOL = ! (VOH)
Difference between VOH and VOL is the logic or signal swing Vsw 35
Introduction
DC Operation Voltage Transfer Characteristics (VTC)
Plot of output voltage as a function of the input voltage V(x)
V(y)
V(y)
f
VOH = f (VIL)
V(y)=V(x)
VM
Switching Threshold
VOL = f (VIH) VIL
VIH
V(x) 36
Introduction
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Mapping Between Analog and Digital Signals V “ 1”
V OH
V
V IH
out Slope = -1
OH
Undefined Region V “ 0”
V
Slope = -1
IL
V OL
OL V
IL
V
V
IH
in
37
Introduction
Noise Margins
For robust circuits, want the “0” and “1” intervals to be a s large as possible
VDD
VDD "1"
VOH NMH = VOH - VIH
VIH Undefined Region VIL
Noise Margin High Noise Margin Low NML = VIL - VOL
VOL
"0"
Gnd
Gnd Gate Input
Gate Output
Large noise margins are desirable, but not sufficient …
38
Introduction
The Regenerative Property A gate with regenerative property ensure that a disturbed signal converges back to a nominal voltage level
v0
v1
v2
v3
v4
v5
v6
v2
5 V (volts)
v0
3
v1
1 -1 0
2
4
6 t (nsec)
8
10 39
Introduction
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Conditions for Regeneration v0
v1
v2
v3
v4
v5
v6
v1 = f(v0) ⇒ v1 = finv(v2)
v3
f(v)
finv(v) v1
v1
v3 finv(v)
v2
v0
Regenerative Gate
f(v)
v0
v2
Nonregenerative Gate
To be regenerative, the VTC must have a transient region with a gain greater than 1 (in absolute value) bordered by two valid zones where the gain is smaller than 1. Such a gate has two stable operating points. 40
Introduction
Noise Immunity
Noise margin expresses the ability of a circuit to overpower a noise source
Absolute noise margin values are deceptive
noise sources: supply noise, cross talk, interference, offset a floating node is more easily disturbed than a node driven by a low impedance (in terms of voltage)
Noise immunity expresses the ability of the system to process and transmit information correctly in the presence of noise
For good noise immunity, the signal swing (i.e., the difference between VOH and VOL) and the noise margin have to be large enough to overpower the impact of fixed sources of noise 41
Introduction
Directivity
A gate must be undirectional: changes in an output level should not appear at any unchanging input of the same circuit In real circuits full directivity is an illusion (e.g., due to capacitive coupling between inputs and outputs)
Key metrics: output impedance of the driver and input impedance of the receiver ideally, the output impedance of the driver should be zero input impedance of the receiver should be infinity
42
Introduction
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FanFan-In and FanFan-Out
Fan-out – number of load gates connected to the output of the driving gate O
gates with large fan-out are slower N
Fan-in – the number of inputs to the gate
O
gates with large fan-in are bigger and slower
M
43
Introduction
The Ideal Inverter
The ideal gate should have
infinite gain in the transition region a gate threshold located in the middle of the logic swing high and low noise margins equal to half the swing input and output impedances of infinity and zero, resp. Vout
Ri = ∞ Ro = 0 Fanout = ∞
g=-∞
NMH = NML = VDD/2
Vin
44
Introduction
An Old-time Inverter VOL=0.45V VOH=3.5V VIL=0.66V VIH=2.35V
5.0 4.0
NM
L
3.0
( V)
VM=1.64V o u t
V
NMH= NML=
2.0 VM NM
1.0
0.0
1.0
2.0
H
3.0
4.0
5.0
V in (V) 45
Introduction
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Delay Definitions Vin
Vout
Vin Propagation delay input waveform
50%
tp = (tpHL + tpLH)/2
tpHL
t
tpLH
Vout
90%
output waveform
signal slopes
50% 10%
tf
tr
t 46
Introduction
Modeling Propagation Delay
Model circuit as first-order RC network vout (t) = (1 – e–t/τ)V R
where τ = RC
vout C
Time to reach 50% point is t = ln(2) τ = 0.69 τ
vin
Time to reach 90% point is t = ln(9) τ = 2.2 τ
Matches the delay of an inverter gate 47
Introduction
Ring Oscillator : Delay Measurement
v0
v1
v0
v2
v1
v3
v4
v5
v5
T = 2 × tp × N 48
Introduction
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A First-order RC Network R
v in
v out CL
∞
∞
0
0
Ein = ∫ iin (t )vin (t )dt = V ∫ C L ∞
∞
0
0
EC L = ∫ iC L (t )vout (t )dt = ∫ C L
V
dvout dt = C LV ∫ dvout = CLV 2 dt 0 V
dvout C V2 vout dt = C L ∫ vout dvout = L dt 2 0 49
Introduction
Power and Energy Dissipation
Power consumption: how much energy is consumed per operation and how much heat the circuit dissipates supply line sizing (determined by peak power) Ppeak = Vddipeak battery lifetime (determined by average power dissipation) Pavg= 1/T ∫ p(t) dt = Vdd/T ∫ idd(t) dt p(t) = v(t)i(t) = Vddi(t) packaging and cooling requirements
Two important components: static and dynamic
E (joules) = CL Vdd2 P0→1 + tsc Vdd Ipeak P0→1 + Vdd Ileakage f0→1 = P0→1 * fclock
P (watts) = CL Vdd2 f0→1 + tscVdd Ipeak f0→1 + Vdd Ileakage 50
Introduction
Power and Energy Dissipation
Propagation delay and the power consumption of a gate are related Propagation delay is (mostly) determined by the speed at which a given amount of energy can be stored on the gate capacitors the faster the energy transfer (higher power dissipation) the faster the gate
For a given technology and gate topology, the product of the power consumption and the propagation delay is a constant Power-delay product (PDP) – energy consumed by the gate per switching event
An ideal gate is one that is fast and consumes little energy, so the ultimate quality metric is Energy-delay product (EDP) = power-delay 2 51
Introduction
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Summary Digital
integrated circuits have come a long way and still have quite some potential left for the coming decades
Understanding
the design metrics that govern digital design is crucial Cost, reliability, speed, power and energy dissipation 52
Introduction
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