Electronique Numerique Integree
Digital Integrated Circuits A Design Perspective
Prentice Hall Electronics and VLSI Series ISBN 0-13-120764-4
The Inverter [Adapted from Rabaey’s Digital Integrated Circuits, Second Edition, ©2003 J. Rabaey, A. Chandrakasan, B. Nikolic]
Copyright 2003 J. Rabaey et al.
Inverter
The CMOS Inverter: A First Glance V DD
PMOS V in
V out CL
NMOS
Inverter
CMOS Inverter FirstFirst-order DC Analysis V DD
V DD Rp
V out
V out Rn
Vin = VDD
VGS < VT − > R = ∞ VGS > VT − > R = RON
VOL = GND VOH = VDD VM = f(Rn, Rp)
Vin = 0 Inverter
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Electronique Numerique Integree
CMOS Inverter: Transient Response V DD
V DD
tpHL = f(Ron.CL)
Rp
= 0.69 RonCL V out
V out
CL
CL Rn
Vin = 0 (a) Low-to-high
Vin = VDD (b) High-to-low Inverter
CMOS Properties
Full rail-to-rail swing ⇒ high noise margins Logic levels not dependent upon the relative device sizes ⇒ transistors can be minimum size ⇒ ratioless
Always a path to Vdd or GND in steady state ⇒ low output impedance (output resistance in kΩ range) ⇒ large fan-out (albeit with degraded performance) Extremely high input resistance (gate of MOS transistor is near perfect insulator) ⇒ nearly zero steady-state input current No direct path steady-state between power and ground ⇒ no static power dissipation Propagation delay function of load capacitance and resistance of transistors Inverter
Voltage Transfer Characteristic
Inverter
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Electronique Numerique Integree
The CMOS Inverter : Load Line I Dn = − I Dp
V DD
Vin = VGSn ;Vin = VDD + VGSp
VGSp S
Vout = VDSn ;Vout = VDD + VDSp
G
D
VDSp
V in
V out CL
D Vin
G
Vout
S VDSn
VGSn
Inverter
Review: Short Channel II-V Plot (NMOS) 2,5
X 10-4
VGS = 2.5V
VGS = 2.0V
1,5 1
VGS = 1.5V
0,5
VGS = 1.0V
Linear dependence
ID (A)
2
0 0
0,5
1
1,5
2
2,5
VDS (V) NMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V, VT = 0.4V
Inverter
Review: Short Channel II-V Plot (PMOS) O
All polarities of all voltages and currents are reversed
-2
VDS (V)
-1
0 0
VGS = -1.5V
-0,2 -0,4 ID (A)
VGS = -1.0V
-0,6 VGS = -2.0V
-0,8 VGS = -2.5V
-1X 10
-4
PMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V, VT = -0.4V
Inverter
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Electronique Numerique Integree
Transforming PMOS I-I-V Lines O
Want common coordinate set Vin, Vout, and IDn
IDn
IDSp = -IDSn VGSn = Vin ; VGSp = Vin - VDD VDSn = Vout ; VDSp = Vout - VDD
Vout
Vin = 0
Vin = 0
Vin = 1.5
Vin = 1.5
VGSp = -1
Mirror around x-axis Vin = VDD + VGSp IDn = -IDp
VGSp = -2.5
Horiz. shift over VDD Vout = VDD + VDSp
Inverter
CMOS Inverter Load Lines PMOS
NMOS
X 10-4
2,5
Vin = 0V
Vin = 2.5V
IDn (A)
2 Vin = 0.5V
1,5
Vin = 1.0V
1
Vin = 2.0V
Vin = 1.5V Vin = 2.0V
Vin = 1.5V
Vin = 1V
Vin = 1.5V
Vin = 2V
Vin = 0.5V
0,5
Vin = 1.0V Vin = 0.5V
0
Vin = 2.5V 0
0,5
1
1,5
2,5 Vin = 0V
2
Vout (V) 0.25um, W/Ln = 1.5, W/Lp = 4.5, VDD = 2.5V, VTn = 0.4V, VTp = -0.4V
Inverter
Vout (V)
CMOS Inverter VTC 2,5 2 1,5 1 0,5 0
NMOS off PMOS res NMOS sat PMOS res
NMOS sat PMOS sat NMOS res PMOS sat
0
0,5
1
1,5
2
NMOS res PMOS off
2,5
Vin (V) Inverter
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Electronique Numerique Integree
CMOS Inverter: Switch Model of Dynamic Behavior VDD
VDD
Rp Vout
Vout CL
CL
Rn
Vin = 0
Vin = V DD
Gate response time is determined by the time to charge CL through Rp (discharge CL through Rn) Inverter
Relative Transistor Sizing
When designing static CMOS circuits, balance the driving strengths of the transistors by making the PMOS section wider than the NMOS section to maximize the noise margins and obtain symmetrical characteristics
Inverter
Switching Threshold As a Function of Transistor Ratio VM where VIN = VOUT (both PMOS and NMOS in saturation since VGS = VDS) Velocity-Saturation VDSAT < VM – VT IDn + IDp = 0 V V k nVDSATn VM − VTn − DSATn + k pVDSATp VM − VDD − VTn − DSATn = 0 2 2
VDSATp V VTn + DSATn + r VDD + VTp + k pVDSATp υ satpW p 2 2 ;r = VM = = 1+ r k nVDSATn υ satnWn
VM ≈
rVDD ;VDD >> VT + VDSAT 1+ r Inverter
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Electronique Numerique Integree
Switching Threshold
VM where Vin = Vout (both PMOS and NMOS in saturation since VDS = VGS) VM ≈ rVDD/(1 + r) where r = kpVDSATp/knVDSATn
Switching threshold set by the ratio r, which compares the relative driving strengths of the PMOS and NMOS transistors
Want VM = VDD/2 (to have comparable high and low noise margins), so want r ≈ 1
Inverter
Switching Threshold As a Function of Transistor Ratio V V k nVDSATn VM − VTn − DSATn + k pVDSATp VM − VDD − VTn − DSATn = 0 2 2
k = k'
W L
(W / L )p (W / L )n
=
k 'n VDSATn (VM − VTn − VDSATn / 2) k ' p VDSATp (VDD − VM + VTp + VDSATp / 2) Inverter
Switching Threshold : Example 0.25µm CMOS VDD=2.5V
NMOS PMOS
(W / L )p (W / L )n
L=0.25µm
W=0.375µm
VT0(V) γ(V0.5) VDSAT(V) k’(A/V2) λ(V-1) 0.43 0.4 0.63 115.10-6 0.06 -0.4 -0.4 -1 -30.10-6 -0.1
=
115 ×10 −6 0.63 (1.25 − 0.43 − 0.63 / 2) × × = 3.5 30 ×10 −6 1.0 (1.25 − 0.4 − 1.0 / 2)
(W/L)p = 3.5 x 1.5 = 5.25 for a VM of 1.25V Inverter
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Electronique Numerique Integree
Simulated Inverter VM VM is relatively insensitive to variations in device ratio
1,5 1,4
z setting the ratio to 3, 2.5 and 2 gives VM’s of 1.22V, 1.18V, and 1.13V
1,3
VM (V)
1,2 Increasing the width of the PMOS moves VM towards VDD
1,1 1
Increasing the width of the NMOS moves VM toward GND
0,9 0,8 0 .1
~3.4
1
(W/L)p/(W/L)n
10
Note: x-axis is semilog
Inverter
Noise Margins Determining VIH and VIL 3
By definition, VIH and VIL are where dVout/dVin = -1 (= gain)
2
NMH = VDD - VIH NML = VIL - GND
Vout
VOH = VDD
Approximating: VIH = VM - VM /g VIL = VM + (VDD - VM )/g
VM
1
So high gain in the transition region is very desirable VOL = GND
0 VIL
Vin
VIH
A piece-wise linear approximation of VTC
Inverter
Inverter Gain V k nVDSATn VM − VTn − DSATn (1 + λnVout ) + 2 V k pVDSATp VM − VDD − VTn − DSATn (1 + λ pVout − λ pVDD ) = 0 2 g=
dVout dVin
g=−
k nVDSATn + k pVDSATp 1 1+ r ≈ λn − λ p (VM − VTn − VDSATn / 2)(λn − λ p ) I D (VM )
Inverter
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Electronique Numerique Integree
Inverter Gain : Example
0.25µm CMOS
VDD=2.5V
W=0.375µm
NMOS PMOS
L=0.25µm
VT0(V) γ(V0.5) VDSAT(V) k’(A/V2) λ(V-1) 0.43 0.4 0.63 115.10-6 0.06 -0.4 -0.4 -1 -30.10-6 -0.1
I D (VM ) = 1.5 ×115 ×10 −6 × (1.25 × −0.43 − 0.63 / 2 )(1 + 0.06 × 1.25) = 59µA
g=
1 1.5 ×115 ×10 −6 × 0.63 + 1.5 × 3.4 × 30 × 10−6 ×1.0 = −27.5 59 ×10 −6 0.06 + 0.1
VIL = 1.2V ;VIH = 1.3V ; NM L = NM H = 1.2V Inverter
Vout (V)
CMOS Inverter VTC from Simulation 0.25um, (W/L)p/(W/L)n = 3.4 (W/L)n = 1.5 (min size) VDD = 2.5V
2,5 2 1,5 1 0,5 0
VM ≈ 1.25V, g = -27.5
0
0,5
1
1,5
2
2,5
VIL = 1.2V, VIH = 1.3V NML = NMH = 1.2 (actual values are VIL= 1.03V, VIH = 1.45V NML = 1.03V & NMH = 1.05V) Output resistance low-output = 2.4kΩ high-output = 3.3kΩ
Vin (V)
Inverter
Inverter Gain : Example Simulation Gain is a strong function of the slopes of the currents in the saturation region, for Vin = VM
0 -2
VIL=1.03V
-4
gain
-6
(1+r) g ≈ ---------------------------------(VM-VTn-VDSATn/2)(λn - λp )
VIH=1.45V
-8 -10
NML=1.03V
-12
NMH=1.02V
Determined by technology parameters, especially channel length modulation (λ). Only designer influence through supply voltage and VM (transistor sizing).
-14 -16 -18 0
G=-17 0.5
VIL1
1.5
V (V) in
VIH
2
2.5
Inverter
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Electronique Numerique Integree
Gain As a Function of VDD 2.5
g≈
2
1+ r
(VM − VTn − VDSATn / 2)(λn − λ p )
V out (V)
1.5
VT=0.4V 1
0.5
0 0
0.5
1
1.5
2
2.5
V (V) in
Inverter
Gain As a Function of VDD 0.2
Very slow operation
V out (V)
0.15
EX: Watches
0.1
0.05
0 0
0.05
0.1 V (V)
0.15
0.2
in
Inverter
Vout (V)
Impact of Process Variation on VTC Curve 2,5 2 1,5 1 0,5 0
Good PMOS Bad NMOS
Nominal Bad PMOS Good NMOS
0
0,5
1 V (V)1,5 in
2
2,5
Process variations (mostly) cause a shift in the switching threshold Inverter
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Electronique Numerique Integree
Propagation Delay
Inverter
CMOS Inverter Propagation Delay Propagation
delay is proportional to the time-constant of the network formed by the pull-down resistor and the load capacitance
Vout = 0 Rn
Vin = V DD
CL
tpHL = ln(2) Reqn CL = 0.69 Reqn CL tpLH = ln(2) Reqp CL = 0.69 Reqp CL tp = (tpHL + tpLH)/2 = 0.69 CL(Reqn+Reqp)/2
To equalize rise and fall times make the on-resistance of the NMOS and PMOS approximately equal. Inverter
Equivalent Resistance REQ
Inverter
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Electronique Numerique Integree
Equivalent Resistance REQ Solving the integral:
with appropriately calculated Idsat I DSAT = k '
W L
V2 (VDD − VT )VDSAT − DSAT 2
Averaging resistances:
Inverter
Equivalent Resistance REQ
W/L=1, L=0.25µ
Inverter
Propagation Delay t pHL = ln(2) ReqnC L = 0.69 ReqnC L t pLH = ln(2) Reqp C L = 0.69 Reqp C L tp =
t pHL + t pLH 2
Reqn + Reqp = 0.69C L 2
Inverter
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Electronique Numerique Integree
Transient Response : Example 3 2.5
? CLHL=6.1fF CLLH=6.0fF
2
V
out
(V)
1.5 1
13kΩ t pHL = 0.69 × 6.1 fF = 36 ps 1 .5 31kΩ t pLH = 0.69 × 6.0 fF = 29 ps 4 .5
tpHL
tpLH
0.5 0 -0.5 0
0.5
1
1.5
2
2.5
t (sec)
-10
x 10
Inverter
Delay As a Function of VDD To see how a designer can optimize the delay of a gate have to expand the Req in the delay equation 5.5
t pHL = 0.69 ReqnC L
5 4.5
t pHL = 0.69
p
t (normalized)
4 3.5
t pHL ≈ 0.52
3
3 C LVDD 4 I DSATn CL
(W / L )n kn' VDSATn
VDD >> VTn + VDSATn / 2
2.5 2 1.5 1 0.8
1
1.2
1.4
1.6
V
DD
1.8
2
2.2
2.4
(V)
Inverter
Design for Performance
Reduce CL internal diffusion capacitance of the gate itself – keep the drain diffusion as small as possible interconnect capacitance fanout Increase W/L ratio of the transistor the most powerful and effective performance optimization tool in the hands of the designer watch out for self-loading! – when the intrinsic capacitance dominates the extrinsic load Increase VDD can trade-off energy for performance increasing VDD above a certain level yields only very minimal improvements reliability concerns enforce a firm upper bound on VDD Inverter
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Electronique Numerique Integree
NMOS/PMOS Ratio
So far have sized the PMOS and NMOS so that the Req’s match (ratio of 3 to 3.5) symmetrical VTC equal high-to-low and low-to-high propagation delays
Inverter
NMOS/PMOS Ratio
M2
Cdp1
Cgp2 M4
Vout
Vin
Vout2
Cw Cdn1
M1
M3
Cgn2 CL=(Cdp1+Cdn1)+(Cgp2+Cgn2)+CW Inverter
NMOS/PMOS Ratio β=
(W / L ) p (W / L )n
CL = (1 + β )(Cdn1 + C gn 2 ) + CW tp =
Reqp 0.69 ((1 + β )(Cdn1 + C gn 2 ) + CW ) Reqn + 2 β
r t p = 0.345((1 + β )(Cdn1 + C gn 2 ) + CW ) Reqn 1 + β ∂t β = β opt → p = 0 ∂β
C
W ≈ r β opt = r 1 + Cdn1 + C gn 2
Inverter
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Electronique Numerique Integree
NMOS/PMOS Ratio If speed is the only concern, reduce the width of the PMOS device!
widening the PMOS degrades the tpHL due to larger parasitic capacitance β = (W/Lp)/(W/Ln) r = Reqp/Reqn (resistance ratio of identically-sized PMOS and NMOS) βopt = √r when wiring capacitance is negligible
Inverter
NMOS/PMOS Ratio 5
x 10
-11
tpHL
tpLH
β of 2.4 (= 31 kΩ/13 kΩ) gives symmetrical response
tp 4
p
t (sec)
4.5
β of 1.9 gives optimal performance
3.5
3
1
1.5
2
2.5
3
3.5
4
4.5
5
β
β = Wp/Wn Inverter
Device Sizing for Performance Divide
capacitive load, CL, into
Cint : intrinsic - diffusion and Miller effect Cext : extrinsic - wiring and fanout
tp= 0.69 Req Cint (1 + Cext/Cint) = tp0 (1 + Cext/Cint) where tp0 = 0.69 Req Cint is the intrinsic (unloaded) delay of the gate Inverter
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Electronique Numerique Integree
Device Sizing for Performance
Widening both PMOS and NMOS by a factor S reduces Req by an identical factor (Req = Rref/S), but raises the intrinsic capacitance by the same factor (Cint = SCiref) tp = 0.69 Rref Ciref (1 + Cext/(SCiref)) = tp0(1 + Cext/(SCiref)) tp0 is independent of the sizing of the gate; with no load the drive of the gate is totally offset by the increased capacitance any S sufficiently larger than (Cext/Cint) yields the best performance gains with least area impact Inverter
Device Sizing 3.8
x 10
-11
(for fixed load)
3.6 3.4
p
t (sec)
3.2
The majority of the improvement is already obtained for S = 5. Sizing factors larger than 10 barely yield any extra gain (and cost significantly more area).
3 2.8
Self-loading effect: Intrinsic capacitances dominate
2.6 2.4 2.2 2
2
4
6
8 S
10
12
14
Inverter
Inverter Sizing
Inverter
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Electronique Numerique Integree
Impact of Fanout on Delay
Extrinsic capacitance, Cext, is a function of the fanout of the gate - the larger the fanout, the larger the external load.
First determine the input loading effect of the inverter. Both Cg and Cint are proportional to the gate sizing, so Cint = γCg is independent of gate sizing and tp = tp0 (1 + Cext/ γCg) = tp0 (1 + f/γ) i.e., the delay of an inverter is a function of the ratio between its external load capacitance and its input gate capacitance: the effective fan-out f f = Cext/Cg Inverter
Inverter Chain
Real goal is to minimize the delay through an inverter chain In
Out Cg,1
1
2
N
CL
the delay of the j-th inverter stage is tp,j = tp0 (1 + Cg,j+1/(γCg,j)) = tp0(1 + fj/ γ) and tp = tp1 + tp2 + . . . + tpN so tp = ∑tp,j = tp0 ∑ (1 + Cg,j+1/(γCg,j)) Inverter
Inverter Chain In
Out CL
If CL is given: - How many stages are needed to minimize the delay? - How to size the inverters? May need some additional constraints. Inverter
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Electronique Numerique Integree
Inverter Delay • Minimum length devices, L=0.25µm • Assume that for WP = 2WN =2W • same pull-up and pull-down currents • approx. equal resistances RN = RP • approx. equal rise tpLH and fall tpHL delays • Analyze as an RC network −1
2W
W
−1
W W RP = Runit P ≈ Runit N = RN = RW Wunit Wunit Delay (D): tpHL = (ln 2) RNCL
tpLH = (ln 2) RPCL
C gin = 3 ×
Load for the next stage:
W Cunit Wunit
Inverter
Inverter with Load Delay
RW
CL RW
Load (CL)
tp = 0.69 RWCL Assumptions: no load -> zero delay Wunit = 1
Inverter
Inverter with Load CP = 2Cunit
Delay
2W W
Cint
CL
CN = Cunit
Load
Delay = 0.69RW(Cint + CL) = 0.69RWCint + 0.69RWCL = 0.69RW Cint(1+ CL /Cint) = Delay (Internal) + Delay (Load) Inverter
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Electronique Numerique Integree
Delay Formula Delay ~ RW (C int + C L ) t p = 0 . 69 RW C int (1 + C L / C int ) = t p 0 (1 + f / γ
)
Cint = γCg with γ ≈ 1 f = CL/Cg - effective fanout R = Runit/W ; Cint =WCunit tp0 = 0.69RunitCunit
Inverter
Apply to Inverter Chain Out
In 1
2
N
CL
tp = tp1 + tp2 + …+ tpN
C t pj ~ Runit Cunit 1 + g , j +1 γC g, j N N C g , j +1 , C t p = ∑ t p , j = t p 0 ∑ 1 + = CL γC g , N +1 j =1 i =1 g, j
Inverter
Optimal Tapering for Given N Delay equation has N - 1 unknowns, Cg,2 – Cg,N Minimize the delay, find N - 1 partial derivatives
∂t p / ∂C g , j = 0
Result: Cg,j+1/Cg,j = Cg,j/Cg,j-1 Size of each stage is the geometric mean of two neighbors C g , j = C g , j −1C g , j +1
- each stage has the same effective fanout (Cout/Cin) - each stage has the same delay Inverter
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Electronique Numerique Integree
Optimum Delay & Number of Stages When each stage is sized by f and has same eff. fanout f:
f
N
= F = C L / C gin ,1
Effective fanout of each stage:
f =NF Minimum path delay
(
t p = Nt p 0 1 + N F / γ
)
The relationship between tp and F is linear for one inverter, square root for two, etc. Inverter
Example In C1
Out 1
f
CL= 8 C1
f2
CL/C1 has to be evenly distributed across N = 3 stages: CL/Cg,1 = 8/1 f =
3
8=2 Inverter
Optimum Number of Stages N
What is the optimal value for N given f
N
= F = C L / C gin ,1
(
t p = Nt p 0 1 + N F / γ
)
if the number of stages is too large, the intrinsic delay of the stages becomes dominate if the number of stages is too small, the effective fanout of each stage becomes dominate For a given load, CL and given input capacitance Cin Find optimal sizing f C L = F ⋅ Cin = f N Cin with N =
ln F ln f Inverter
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Electronique Numerique Integree
Optimum Number of Stages N
(
)
t p = Nt p 0 1 + F 1/ N / γ =
∂t p ∂f
=
t p 0 ln F f γ + γ ln f ln f
t p 0 ln F ln f − 1 − γ f ⋅ =0 γ ln 2 f
For γ = 0, f = e, N = lnF
f = exp(1 + γ f ) Inverter
Optimum Effective Fanout f 6
4,5
fopt = 3.6 for γ=1
4
Fopt
tp/tpopt
7
5
5 4 3
3,5
2 3
1
2,5
0 0
0,5
1
1,5
2
2,5
3
1
1,5
2
2,5
3
3,5
4
4,5
γ Choosing f larger than optimum has little effect on delay and reduces the number of stages (and area).
5
f
Common practice to use f = 4 (for γ = 1) But too many stages has a substantial negative impact on delay Inverter
Normalized delay function of F topt/tp0
F (γ = 1) Unbuffered 10
11
Two Stage Chain 8.3
100
101
22
16.5
1,000
1001
65
24.8
10,000
10,001
202
33.1
Opt. Inverter Chain 8.3
Impressive speed-ups with optimized cascaded inverter chain for very large capacitive loads.
Inverter
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Electronique Numerique Integree
Buffer Design 1
1
8
1
4
16
2.8
8
1
N
f
tp
1
64
65
2
8
18
64
3
4
15
64
4
2.8
15.3
64
64
22.6
Inverter
Input Signal Rise/ Rise/Fall Time In reality, the input signal changes gradually (and both PMOS and NMOS conduct for a brief time). This affects the current available for charging/discharging CL and impacts propagation delay. tp(sec)
tp increases linearly with increasing input slope, ts, once ts > tp ts is due to the limited driving capability of the preceding gate
5,4 5,2 5 4,8 4,6 4,4 4,2 4 3,8 3,6 0
2
4
ts(sec)
6
8
Inverter
Design Challenge
A gate is never designed in isolation: its performance is affected by both the fan-out and the driving strength of the gate(s) feeding its inputs. (η ≈ 0.25) tip = tistep + η ti-1step Keep signal rise times smaller than or equal to the gate propagation delays. good for performance good for power consumption
Keeping rise and fall times of the signals small and of approximately equal values is one of the major challenges in high-performance designs - slope engineering. Inverter
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Electronique Numerique Integree
Delay with Long Interconnects
When gates are farther apart, wire capacitance and resistance can no longer be ignored. (rw, cw, L)
Vin cint
Vout cfan
tp = 0.69RdrCint + (0.69Rdr+0.38Rw)Cw + 0.69(Rdr+Rw)Cfan where Rdr = (Reqn + Reqp)/2 = 0.69Rdr(Cint+Cfan) + 0.69(Rdrcw+rwCfan)L + 0.38rwcwL2
Wire delay rapidly becomes the dominate factor (due to the quadratic term) in the delay budget for longer wires. Inverter
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