New methodology to characterize packaging with acoustic microscopy EDMINA
Reliability about assembly, passive components and optoelectronics devices
Yves Ousten Bruno Levrier Laurent Bechou
[email protected]
CHALLENGES FOR THREE-DIMENSIONAL (3D)ICS AND SYSTEMS
Outline 30 mm QFP 900 mm² •
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Packaging evolution Acoustic evolution Discussion
20 mm
15 mm
TAB COB 225 mm²
11-12 mm
CSP, BGA
10 mm
Flip-Chip 100 mm²
Conclusion
2 CHALLENGES FOR THREE-DIMENSIONAL (3D)ICS AND SYSTEMS
Packaging evolution •
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Purchasers need only the right function and not “all the function” into a package! One level would be a specific function removable vs application. Plastic packages are more and more need for applications! Ceramic (LTCC) are also in the race but decreasing. Lot Problems are coming from the CTE mismatch ! Humidity is also a possible cause of defect.
25 mm²
3 CHALLENGES FOR THREE-DIMENSIONAL (3D)ICS AND SYSTEMS
Packaging evolution Categories of SiP (ITRS source)
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Packaging evolution Categories of SiP (ITRS source)
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Packaging evolution
Through silicon via (TSV) – source NXP interconex 2008
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Through silicon via – Wafer level package – Via close to 50µm • Problems : cross talk (frequency) and crack risk inside silicon (electro-migration). 6 CHALLENGES FOR THREE-DIMENSIONAL (3D)ICS AND SYSTEMS
Probably the best known of the more-than-Moore solutions is 3D chip stacking using through silicon vias (TSVs)
Size
Thickness close to 500µm Size via depth
