Modeling and Control of a Three-Phase Neutral-Point-Clamped Inverter by Means of a Direct Space Vector Control of Line to Line Voltages Bruno François*, Eric Semail** Laboratoire d’Electrotechnique et d’Electronique de Puissance de Lille (L2EP) *Ecole Centrale de Lille, Cité Scientifique, BP48, 59651 Villeneuve d’Ascq Cedex, France Corresponding author: E-mail :
[email protected]
**ENSAM, 8 Boulevard Louis XIV, 59046 Lille, France
Keywords Converter control, Modulation strategies, Vector control, Multilevel converters
Abstract This paper presents a modulation strategy that enables to copy directly modulated waveform onto output voltages of a three-phase N.P.C. inverter. A particular modeling of this converter is presented. The feasibility of a space vector scheme without using a Park transform is studied. All voltage vectors are drawn into the line to line voltage frame. Then three voltage vectors are selected for the modulation and simultaneously their durations are calculated. The effect of the modulation on the capacitor divider is studied and a balancing strategy is deduced.
I. Introduction The interest towards enhancing the performance of multilevel converters has increased, specially in the least decade. The main reason is their capabilitie for reducing the harmonic distortion in the generated multilevel waveform and for increasing the voltage ratings (and so the power ratings). For Neutral Point Clamped inverters (NPC), it is critical to balance the neutral point voltage in case of disturbed or even continuous load conditions. So far, several vector control schemes for NPC inverters have been proposed. High performance control strategies of N.P.C. inverters are based on the space vector approach (see [1] as example). The line-to-line output voltages are generated by switching PWM patterns among three vectors in triangular working areas. The vector selection is done in order to minimize the neutral point voltage variations but the complexity of involved calculations requires a very powerful microprocessor or DSP [2], [3]. Transformation of voltages into synchronously rotating reference coordinates has been explored in order to control direct and quadrate axis components by using hysteretic comparators [4], [5]. But, the obtained moving modula tion frequency is a strong constraint for power applications with high voltage semiconductors. The major limitation of N.P.C. converters is still the capacitive voltage unbalance and it restrains the industrial development of N.P.C. converters [6] [7]. In this paper, the principles of a neutral point voltage modulation system without Park transformation (in a d,q frame) are discussed. We first present the multilevel inverter operating principle and the converter modeling. A more appropriate average modeling for the control design is given. Then the proposed vector control scheme is presented. As usual, the plane is divided in triangular areas. The three vectors related with the area that includes the reference are used to create the PWM waveform. The innovation is that the space frame is not obtained through a mathematical transformation but is directly the line to line voltage space. 19 voltage vectors are used for the modulation. A few of these 19 vectors are redundant vectors: they are then used-for the dc bus balancing and the losses minimization. A practical implementation of this modulator is detailed. Then, experimental results on a 2.5 kVA prototype are given. EPE-PEMC 2002 Dubrovnik & Cavtat
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II. General Modeling of the Three Phase NPC Inverter A. Structure and operating principle The well-known topology of N.P.C. consists of three commutation circuits, which are fed with a capacitive divider (fig. 1). The dc voltage across these two capacitors comes from a voltage-controlled current-rectified generator and has a constant value. The two commutation circuits of four semiconductor switches enable to make reversible the modulated voltages (u m1 , um2 ). As the load current is alternative, required switches are made of four transistors with anti-parallel diodes. Additional steering diodes are required to clamp one terminal of each transistor to the capacitor midpoint. If voltages across capacitors are controlled to be equal to the half value of the full dc voltage, modulated phase to phase voltages may be modulated over five levels. In a such operating, each transistor in off state holds the half value of the full dc voltage, and, thus, it makes this converter suitable for high-voltage applications (U.P.S., traction, ...). As switches are switch-on and switch off controlled, their states are defined, at any time, by external gate signals. Therefore, the converter can operate in PWM mode to shape the modulated voltage in a multilevel waveform. The switching frequency must be chosen higher than the highest required load frequency and smaller than the permitted maximum transistor switching frequency. For our application, the maximum load frequency is 50Hz and we choose a switching frequency equal to 2 kHz. i m1 u s1
us
T11
T12
T13
T21
T22
T23
C1
im 2
dc current source (rectifier) =
u m1 u m2
L
i s1
L
is2
L
u s2
C2
T31
T 32
T33
T41
T42
T43
~
Fig. 1. Schematic diagram of the DC voltage-source N.P.C. inverter.
B. Fundamental principles of Neutral-Point-Clamped Converters In order to ensure a correct multilevel operating, the control system must maintain the same voltage value across capacitors: us1 =us2 = us = E .
2
(1)
2
Looking at the first clamped commutation circuit (fig. 2.a). The output voltage (um10 ) may be equal to the full level (us) by switching on the sets {T1c, D1c} and {T2c, D2c} or the half level ( us ) by
2
switching on the sets {T2c, D2c} and {T3c, D3c} or the zero level by switching on the sets {T3c, D3c} and {T4c, D4c}. Therefore, this clamped commutation circuit is equivalent to a commutation circuit whose one ideal switch among the three is at anytime switched on (fig. 2.b). The switch states are called switching functions (f rc). If f rc=1, the corresponding ideal switch (and so corresponding transistors) is closed. Otherwise, if f rc=0, it is open. The index r corresponds to a row and c to a commutation circuit. Thus, switching functions in the equivalent commutation circuit depend on transistor gate signals as : f1c=T1c, f3c =T4c, f2c =T2c.T3c (2) And, we can find the right gate signals of transistors inside the clamped commutation circuit in order to implement wished switching functions (f rc_ref) following this inverse relation:
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T1c = f1c _ref ,T2c = f1c _ref + f2c _ref ,T3c = f2c _ref + f3c _ref ,T4c = f3c_ref , Connection functions
Gate signals
us
us 1
T11 T21
D21
is
o
1
1
0
0
0
1
1
0
us us
0
0
1
1
0
2
um10
u s2 T31
f 1c
•
us
D31
T41
f1c f2c f3c 1 0 0
T 1c T 2c T 3c T 4c u m10
D11
f2c us2
D41
(2-1 )
•
f3 c
•
o
•
0
1
0
0
0
1
um 10
• •
2.b
2.a
Fig. 2. Equivalent commutation circuit.
C. Connection operating modeling The objective of this paragraph is to set a mathematical description of the voltage conversion. For an easier analysis of the discontinuous operation, we use the representation depicted fig. 3. This one is obtained from figure 1: - by replacing all reactive elements (which are connected to switches) by their equivalent electrical sources (a self by a current source and a capacitor by a voltage source), - by considering only two phase to phase voltage sources and modulated voltages (third one is linked to others and, so, is unnecessary for the modeling. We will show that this non-trivial choice will simplify greatly the design of the control algorithm), - by arranging all ideal switches in a matrix containing vertical equivalent commutation circuits as explained in the preceding section. As three ideal commutation circuits now chop voltage sources, we can write: vc0 =(vc -v0 )= f1 c.us+ f 2 c. us2 (3) And, phase to phase modulated voltages are expressed by: (4) u m 1 = v10 -v 30 = f11 − f13 . u s + f 21 − f 23 . u s 2 (5) u m 2 = v 20 -v 30 = f12 − f13 . u s + f 22 − f 23 . u s 2
( (
) )
( (
) )
Load
is1
im 1
f 11
um 1 O1
i s2 u m2 f 12
O2
O3
f 13
us i m2 u s2
f21
f22
f23
f31
f32
f33
0O
Fig. 3. Diagram of a matrix converter structure with three commutation cells of three switches.
D. Conversion modeling
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We may consider modulated voltages as the conversion of the full dc voltage (u s) and of one capacitor voltage. As voltage sources are supposed to have constant values, it appears that each phase to phase voltage is shaped through two modulated voltages as: (6) um = um + um 1
with
11
and
u m =u m 2
with
um
12
=m
12
21
(7)
u m11 = m11 . u s
12
um +um
=m
21
(8)
. u s2
(9)
22
(10)
.u s
21
(11)
u m 22 = m 22 .u s
In order to analyze the effect of conversions, we define conversion functions (mr ) as [8]: (12) and m 11 = f11 − f13 , m 21 = f 21 − f 23 (14) and m 12 = f12 − f13 , m 22 = f22 − f23 m rc = f rc − f r 3
(13) (15) (16)
E Analysis of multilevel operating The multilevel voltage is a consequence of the combination of two dc voltage sources, which are created from capacitor voltages. In balancing conditions (equ. (1) ), 5 voltage levels E/2 may be used to create modulated voltages. 27 (33 ) switching configurations exist and corresponding voltage levels have been reported into table 1. A simultaneous magnitude and width modulation is possible. By using levels 0 and E/2, we get an half level modulation. By using levels E/2 and E we obtain a full level modulation as depicted on fig.4. E
umc_ref us us
Full level modulation E 2
Half level 0 modulation
-E 2 Full level modulation -E
Fig. 4: Modulation operation regions and corresponding modulated voltage
F Average modeling The purpose of the control system is to regulate the equivalent mean value of modulated voltages (written ) inside each modulation period in order to get a constant value of the load current (is) [8]. The mean value of a modulated voltage during the modulation period (Te) is expressed as: (k +1 ).Te umc(t) = 1 . umc(t).dt Te k.Te Te −> 0
∫
(13)
with k ∈Ν . EPE-PEMC 2002 Dubrovnik & Cavtat
P. 4
This quantity is linked to modulation functions and voltage sources (equ. (8), (9), (11) and (12)), which are assumed to be nearly constant during the modulation period: (14) um = u m1c + u m2c c
(15)
u m1c = m1 c .u s
(16)
u m2 c = m 2c . us
The mean value of a modulation function is therefore defined as: (k +1).Te mrc(t) = 1 . mrc(t).dt Te k.Te Te−>0
∫
Switching functions
f11
f21
f31 f12 f 22 f32 f13
Modulation functions
f23
f33
m 11 m 21 m 12 m 22
(17) Voltages
Voltage vector
um 1
um 2
1
0
0
0
1
0
0
1
0
1
-1
0
0
E/2
0
c1
um u13
0
1
0
0
0
1
0
0
1
0
1
0
0
E/2
0
d1
u13
1
0
0
1
0
0
0
1
0
1
-1
1
-1
E/2
E/2
c2
u14
0
1
0
0
1
0
0
0
1
0
1
0
1
E/2
E/2
d2
u14
0
1
0
1
0
0
0
1
0
0
0
1
-1
0
E/2
c3
u15
0
0
1
0
1
0
0
0
1
0
0
0
1
0
E/2
d3
u15
0
0
1
0
1
0
0
1
0
0
-1
0
0
-E/2
0
c4
u16
0
1
0
1
0
0
1
0
0
-1
1
0
0
-E/2
0
d4
u16
0
0
1
0
0
1
0
1
0
0
-1
0
-1
-E/2
-E/2
c5
u17
0
1
0
0
1
0
1
0
0
-1
1
-1
1
-E/2
-E/2
d5
0
1
0
0
0
1
0
1
0
0
0
0
-1
0
-E/2
c6
1
0
0
0
1
0
1
0
0
0
0
-1
1
0
-E/2
d6
1
0
0
0
1
0
0
0
1
1
0
0
1
E
E/2
m1
u2
0
1
0
1
0
0
0
0
1
0
1
1
0
E/2
E
m2
u4
0
0
1
1
0
0
0
1
0
0
-1
1
-1
-E/2
E/2
m3
u6
0
0
1
0
1
0
1
0
0
-1
0
-1
1
-E
-E/2
m4
u8
0
1
0
0
0
1
1
0
0
-1
1
-1
0
-E/2
-E
m5
u10
1
0
0
0
0
1
0
1
0
1
-1
0
-1
E/2
-E/2
m6
u12
1
0
0
0
0
1
0
0
1
1
0
0
0
E
0
l1
u1
1
0
0
1
0
0
0
0
1
1
0
1
0
E
E
l2
u3
0
0
1
1
0
0
0
0
1
0
0
1
0
0
E
l3
u5
0
0
1
1
0
0
1
0
0
-1
0
0
0
-E
0
l4
u7
0
0
1
0
0
1
1
0
0
-1
0
-1
-1
-E
-E
l5
u9
1
0
0
0
0
1
1
0
0
0
0
-1
0
0
-E
l6
u11
1
0
0
1
0
0
1
0
0
0
0
0
0
0
0
z1
0 0
1 0
0 1
0 0
1 0
0 1
0 0
1 0
0 1
0 0
0 0
0 0
0 0
0 0
0 0
z2 z3
u0 u0
u17 u18 u18
u0
Table 1.
III Design of the control system A General control scheme All presented equations constitute a unified modeling, which can be used to describe control actions. The ordering of all implicated relations following the input output transfer and the causality respect gives the representation depicted fig. 5. In order to ensure a correct multilevel operating, the control system has two tasks. It must generate a correct multilevel waveform and it must maintain the same voltage value across capacitors ( equation (1) ). The control system is built around a connection controller and a space vector modulator. The connection controller processes corresponding gate signals in order to set voltage
EPE-PEMC 2002 Dubrovnik & Cavtat
P. 5
vector via an inverse mapping of table 1. This control function has been implemented into a CPLD circuit. The space vector modulator is now detailed. LEVEL CONVERSION
Trcrc
equ. (2)
AVERAGE M ODELLING
L EVEL CONVERSION
Tfrcrc
m rc
equ. (15)
equ. (19)
POWER CONVERSION
MULTILEVEL O PERATING
equ. (18)
u s1 us
equ. (17)
AVERAGE M ODELLING CONTROL SYSTEM SPACE VECTOR M ODULATION
CONNECTION CONTROLLER
Trc_ref
Fig. 5: Control architecture of the N.P.C. Inverter
B Space vector modulation for multilevel operation The 19 different configurations for the voltage space vector are represented in the frame
( ur m 1 , ur m 2 ) (fig. 6).
um1 E
r u11
r u1
r u2
r u3
r u12
r u13
r u14
r u4
r u18
r u0
r u15
r u5um2
-E
r u10
r u9
E
r u17
r u8
r u16
r u6
r -E u7
Fig. 6: Space vector location into the frame ( ur m 1 , ur m 2 ) We join two different vectors by a line if there is a way to join them by commutation in only one commutation circuit. The frame is consequently divided into 26 triangular areas The average value of both modulated voltages may be set by switching respectively the three vectors which define the sector where the wished voltage vector is located. The proposed vectorial approach, already used for multi-leg inverters ([9], [10]), allows to calculate explicitly the durations and is adapted for optimization. The duration of each vector is determined by the obtained projections onto frame vectors ( ur m 1 , ur m 2 ). As example, for a wished modulation vector located in the grayscale sector of fig. 7, the three selected vectors are vr1 =ur1 , vr2 =.ur2 , vr3 =. ur14 . Respective durations are t1 , t2 , t3 , according to: r t r t r t r Um= 1 .v1 + 2 .v2 + 3 . v3 Tm Tm Tm
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(18)
P. 6
um1 E
um1 r u1
r u2
E
um
r u14
r u2 um
r u13
r r u14 −u2
E 2
um2
r u0
r r u1 −u2
um2
r u0
2
2
Fig. 7: Expanded view of the studied sector In fact only two durations must be determined because all durations must be equal to the modulation period: (19) t1 +t2 +t3 =Tm r r In order to obtain parallel projections with vectors um1 et um2 , the duration of the vector which marks the corner of the triangle (pivot) will be always determined according to the others. For our example, we get: r t r Tm −t1 −t3 r t r Um= 1 .u1 + .u 2 + 3 .u14 (20) Tm Tm Tm r t r r r t r r Um= 1 . .u1 -.u2 + 3 . .u14 −.u 2 +.u2 (21) Tm Tm r r t r r r t Um= 1 . − E .u m1 + 3 .− E .u m2 + E .u m1 + E .u m2 (22) Tm 2 Tm 2 2
(
(
)
)
( )
(
)
( )
()
After identification of projections of this vector with coordinates of the wished modulator vector
r ( urm1 and um2 ), we get:
( ) ( )()
t1 .− E + E Tm 2 t = 3 . − E + E Tm 2 2 and so, durations are easily found : =
(
)
t1 = E− . 2.Tm E
(25)
(
)
(23) (24)
(
)
t3 = E − . 2.Tm 2 E
(26)
t2 = − E++ .2 .Tm E
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(27)
P. 7
The space vector modulator uses the nearest three vectors (node of the triangle containing the vector). So, the choice of the three selected vectors has to be modified according to the triangular area where the modulation vector is located. The determination of the three nearest vectors is graphically represented in fig.8. r r r r r r r r u2 u1 u1 u2 u1 u u1 u
r r u14 u13
r r u14 u13
r u13
r r u14 u13
r u14
Fig. 8: Three nearest vectors of a point in a grey square A lot of sectors has to be considered but durations of each selected vector are easily deduced from previous ones by a translation. r For the practical implementation each vector position ( u x ) has been coded by it 5-bit number x. The vector modulator has been designed with a multiplexer whose output selector is controlled by a timer (fig. 9). According to the wished references ( and ), the region is located, the three vectors are selected and corresponding values of x are applied to the multiplexer. Moreover the durations (t1 and t2 ) are sent to the timers. CS0
t1 Space Vector Modulator T imer
t2
CS1
r v1
D.S.P. t1 t1+ t2
Connection Controller
r r v2 v3 Data Bus
6
(Look-up table)
Adress Bus
Voltage Vector Selector ur
CS1 CS0
5
x 5
5
5
(CPLD) 5
r v1 r v2 r v3
Multiplexer 5
Comparators
us1 us2 is1 is2
Fig. 9: Practical implementation of the control system
IV Voltage capacitor balancing by voltage selection A Balancing capabilities The different positions of the voltage vector have been classified into different classes according to its magnitude: - L, large amplitude vectors, correspond to the application of a full level onto both modulated voltages. r They have only one switching states (l ). These vectors do not connect any of the phases to the common capacitor potential and so the capacitor voltage error remains unaffected. - M, medium amplitude vectors, simultaneously apply a full level and an half level. They have medium amplitudes and a single switching state ( mr ). They affect the capacitor voltage balancing.
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P. 8
- S, small amplitude vectors correspond to the application of the same half level onto both modulated voltages or the application of the half level onto a single modulated voltage. They have two different r switching states each ( cr and d ) and will be used to limit the voltage deviations across capacitors. - The last group of vectors correspond to zero vectors, Z. They have three different switching states ( zr ) which not affect the balancing of the DC-link capacitor voltages. The available voltage vectors must be chosen, not only to generate the modulated voltages, but also to minimize the capacitor voltage unbalance. As there are 6 redundancies in vector selection r (vectors cr or vectors d ), balancing capabilities are possible according to operating domains [11] as depicted on fig. 10. For a same value of modulated voltages, two equivalent switching configurations may exist and the selection of one will have a particular effect onto the capacitor balancing. This freedom degree will be used in our control structure to get the balancing condition: us1 =us2 = us = E .
2
2
For a given signed half level and a regenerative operation (negative currents), the use of a vector r r c will charge the capacitor C2 , the use of a vector d will decrease the voltage across it (table 2). These two switching states have complementary effects on the capacitor voltages. This possible choice is a freedom degree that will be exploited to regulate the balancing of capacitor voltages. um1 E
r l6
r l1
r m1
r l2
r m6
r r c1 ,d1
r r M c2 ,d2 M
r r c6 ,d 6
r r r z 0 ,z1 ,z2
r r c3 ,d3
-E
r m2 r l3um 2 E
r r c5 ,d5
r m5
r r c4 ,d4
r m3 One vector possibilities possibilities capacities Two vector possibilities
r l5
r -E r Fully possibilities m4 l4 Fig. 10: Representation of modulated voltage vectors
Vectors
Modulation functions m11 m 21 m12 m 22
Voltages u m1 um2
c1
1
-1
0
0
E/2
0
d1
0
1
0
0
E/2
0
c2
1
-1
1
-1
E/2
E/2
d2
0
1
0
1
E/2
E/2
c3
0
0
1
-1
0
E/2
d3
0
0
0
1
0
E/2
c4 d4
0 -1
-1 1
0 0
0 0
-E/2 -E/2
0 0
c5
0
-1
0
-1
-E/2
-E/2
d5
-1
1
-1
1
-E/2
-E/2
c6
0
0
0
-1
0
-E/2
d6
0
0
-1
1
0
-E/2
is1
