Mini-Control (MCL) : minimal processor control unit CCSI 00-3-1 MCL project TLD 2001 10 October 2001 © EIA-FR, Michel Bovet, application engineer, Louis Schmitt & Dominique Rhême, prof

TLD 2001

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TLD 2001 MCL Project

Contents… • • • • • • •

MCL Project overview Forth & virtual machine Stack processor & modeling style Spartan 2 technology HDL actual state HW actual state … the future 2

TLD 2001 MCL Project

Project Goals • Design of a very little control & command unit to swarm digital power deep in the field of a manufacturing process • Minimal size stack processor modeling and synthesis in a programmable device. • FORTH virtual machine implementation (ANSI X3.215 standard). 3

TLD 2001 MCL Project

Project Ressources • 12 man x months ressources : • CHFr 130'000.- by the CCSI (Centre de Compétence en Systèmes Intégrés, of the HESSO) • Technical & Scientific support by the EIA-FR and partners • Eval Board Prototype by the EIA-FR • January – december 2001 : NOT yet at the end! 4

TLD 2001 MCL Project

FORTH (1) • Charles H. MOORE write it in late'sixties. • Why Forth ? – FORTH is a compiler AND an interpreter – FORTH is an assembler language as good as an operating system – FORTH contains the principle of invariance – FORTH is the prototype of the virtual machine 5

TLD 2001 MCL Project

FORTH (2) • But Forth … – looks difficult at the first time – is a typical public domain product (support) – don't need sophisticated development systems and operating systems… => it’s not a money maker! • Little demo... 6

TLD 2001 MCL Project

Virtual Machine (1) Network Functions etc. Vector Functions (Applets) High level Functions : : PID Regulator 1

Extensions of the virtual machine looks like a DICTIONNARY. High level functions are build over the basic instruction's set.

; Virtual Machine's Basic Instruction Set (Processor's Specific Assembler Programm) Processor Instruction Set (Silicium-implemented)

All the basic instructions of the vitual machine (ie. DUP, SWAP, ROT etc.) are assembler-coded. This is the KERNEL of the virtual machine (between 4 and 16 ko).

Host processor, ( 68xxx, 80xxx, etc..)

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TLD 2001 MCL Project

Virtual Machine (2) Network Functions etc. Vector Functions (Applets) High level Functions : : PID Regulator 1 ; Virtual Machine's Basic Instruction Set (Processor's Specific Assembler Programm) Processor Instruction Set (Silicium-implemented)

MCL GOAL : the virtual machine will be directly implemented down in the silicium. The basic instruction's set of the virtual machine will be coincident closely with the processor's instruction set.

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TLD 2001 MCL Project

Stack Processor (1) • The Stack Principle :

• Strengths – Very powerful in interruptive systems. – Allows to have " light " hardware structures !

• Weakness – Must be correctly managed to avoid underflow or overflow situations

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TLD 2001 MCL Project

Stack Processor (2) • Canonical stack machine Vs Mini-Control stack machine Special registers … Address page register Address register

R page register +

Top of data stack Shl & Shr

Top of return stack

+

ALU Data stack

Return stack

(16x256)

(16x256)

Program counter

Instruction decoder

Memories Xmodem ROM 16x512 Flash 2 * 8x512K RAM 2 * 8x512K

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TLD 2001 MCL Project

VHDL Modeling • Data-Path modeling style for the stack processor |\ | \ | |-----alu_out------+ | | | | / | |/| | | | alu_sel---------+ | | |\ | S ----------- | \ | a ----------- | |---reg_out---+ | r ----------- | | | | stack_out --- | / | | |/| | | | | | reg_sel---------+ | | | | |\ +-------+ |\ | +-| \ | | data LSByte --| \ +------| |- t_in ----| |-data MSByte --| |---data_in----------| | tright --| T | data -------- | / +-| / tleft ---| | |/| | |/| clk -----| | | | | clr -----| | data_in_sel-----+ | | +-------+ | +---t_sel |\ | Crtl_status_reg -| \ | Page_reg_A ------| \ | Page_reg_R ------| |-reg_spec_out-+ DS_pointer ------| | RS_pointer ------| / ... | / |/| | r_content----------+ not t-------t xor S ----t and S ----t+S ---------

Data stack +-------+ | | t ------|n_stack|-- S npop ---| | npush --| | clk ----| | clr ----| | +-------+

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TLD 2001 MCL Project

Technology Spartan2

MINI -CONTROL

Xmodem ROM

Data stack

– Low cost! – RAM, DLLs, I/O Banking … – SoC methodology

Clk manag.

... Return stack

• FPGA Xilinx Spartan II

USB

UART 2

PWM

SCSI

(MCL : < 50% of an XC2S50) 12

TLD 2001 MCL Project

Spartan2 : CLB / Slice

• Before Virtex technology : – Just CLB definition

• After Virtex technology : – 1 Slice = 1 old CLB def. – 1 "new" CLB def. = 2 Slices

(MCL : < 500 Slices used for the logic) 13

TLD 2001 MCL Project

Spartan2 : Block SelectRAM+

• • • •

Synchronous RAM Dual ported RAM Size : 4096 bits Port independent configurable width : 1 / 2 / 4 / 8 /16 bits • Port independent clock (MCL : 3 Block RAM used for Data stack, Return stack and Xmodem) 14

TLD 2001 MCL Project

Spartan2 : Delay-Locked Loop • Frequency doubler • Programmable clock divider : 1.5, 2, 2.5, 3, 5, 8 or 16 • 3 phase-shifted version of CLKIN : 90°, 180° and 270° • Duty cycle correction possibility • fmin > 25 MHz (MCL : 1 DLL used for clock management) 15

TLD 2001 MCL Project

HDL actual state (1) • Mini-control VHDL modeling (~1k code lines) – – – – – – –

30 (31) defined opcodes (2 more free) Data bus : 16 bits / Address bus : 20 bits Data & Return stack in 2 on-chip BlockRAM 1 UART 1 Interrupt Handling Word or Byte access mode Xmodem mode (1 on-chip BlockRAM used as a ROM)

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TLD 2001 MCL Project

HDL actual state (2) • HDL Designer environment : mixed structural and dataphath modeling

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TLD 2001 MCL Project

HDL actual state (3) • Mini-Control 31-instructions set : – Jumps, calls : • jmp, jz, jnc, call, calla, ret, iret

– Memory / special register read / write • ftchrp, strp, ftcha, ftchap, sta, stap, fcw, stcw

– Logic & arithmetic opcodes • shl, shr, com, xorr, andd, addc, addd

– Stacks and A register operation opcodes • lit, pop, popa, push, pusha, dup, over, drop, nop 18

TLD 2001 MCL Project

Hardware actual state (1) • EVALUATION BOARD AVAILABLE :

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TLD 2001 MCL Project

Hardware actual state (2) • Mini-control EVALUATION BOARD description : – – – – – – –

1 FPGA Xilinx Spartan II XC2S50 (TQ144) JTAG & FPGA port access + EEPROM Memory : 2 Flash 512kx8 / 2 RAM 512kx8 1 RS232 driver connected on a double SUBD9 1 Interface RAM 512kx8 extension 1 CAN driver for extension (double SUBD9) ~ 40 free I/Os for future HW development 20

TLD 2001 MCL Project

The future... • Eval Board PCB prototype validation – Hardware & opcodes tests

• FORTH virtual machine writing – Ideally conforms to the ANSI X3.215 standard

• Address bus extension to 31 bits • Interface extensions (Hardware & VHDL) – USB port, RS422 port, CAN interface, PWM... – TouchScreen port, VGA output… – SCSI bus (ie. for a hard disk)… 21

TLD 2001 MCL Project

Contacts / resources • Dominique Rhême : project manager (EIA-FR) [email protected] and http://eif.ch/

• Louis Schmitt : Project co-applicant (EIA-FR) [email protected]

• Michel Bovet : Project engineer (EIA-FR) [email protected]

• JPB & Laurent Foube : www contacts http://jpb.forth.free.fr/ PCB prototyping & Realization by the BCE (EIA-FR) 22

TLD 2001 MCL Project

Internet references • FORTH references : – http://www.forth.org/ (FIG home page)

• “Stack Computers : The new wave” book in pdf : – http://www.cs.cmu.edu/~koopman/stack_computers/index.html

• P16 & F21 informations : – http://www.ultratechnology.com/dindex.htm

• Real-time FORTH kernel build around a MC68030 : – http://jpb.forth.free.fr/

• Xilinx FPGA technology : – http://www.xilinx.com 23

TLD 2001 MCL Project

Questions… • Thanks and see You next time for a demo of the power of MCL

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