Microcontrôleurs http://michel.deloizy.free.fr
Microprocesseur conventionnel + périphériques
Intégrés dans une puce
M. Deloizy
2
dsPIC30F2023
Intègrent : Mémoire (RAM,ROM) Circuits d’horloge Ports parallèles, timers, compteurs, ports série Convertisseurs analogiques AD / DA Périphériques spécialisés : I²C Contrôle moteur Bus CAN …
Constituent un système autonome à eux seuls M. Deloizy
3
dsPIC30F2023
Avantages : Système à faible coût Encombrement réduit Meilleure fiabilité Mise en œuvre facilitée
Adaptés : Aux grandes séries Aux systèmes embarqués
M. Deloizy
4
dsPIC30F2023
Inconvénients : Performance des périphériques réduite Inadaptés à la gestion de gros systèmes Utilisation simultanée de tous les périphériques impossible Complexité du système
M. Deloizy
5
dsPIC30F2023
Domaines d’utilisation : Systèmes embarqués Petits systèmes économiques Systèmes de commande à faible diffusion (prototypes…) Tout système ne nécessitant pas des ressources importantes
Applications plus importantes : PC industriel
M. Deloizy
6
dsPIC30F2023
Choix d’un microcontrôleur : Deux critères essentiels : Puissance du processeur Format des mots traités Fréquence d’horloge Architecture interne (optimisée ?) Jeu d’instructions et adressages, nombre de registres. Adaptation aux langages évolués. Périphériques intégrés Mémoire interne (RAM, ROM, EEPROM…) Nombre de lignes d’E/S Nombre de compteurs, précision, … Périphériques spécialisés Il est préférable de ne pas rajouter de périphériques autour du microcontrôleur ! M. Deloizy 7 dsPIC30F2023
Autres critères de choix : Le coût du composant Le coût du système de développement Consommation Langages disponibles et efficacité Ressources disponibles (Internet) Connaissance du système Première mise en œuvre difficile (système complexe)
M. Deloizy
8
dsPIC30F2023
MICROCHIP dsPIC30F2023 dsPIC30F1010/202X 28/44-Pin High-Performance Switch Mode Power Supply Digital Signal Controllers
M. Deloizy
9
dsPIC30F2023
Présentation
I
Présentation générale
M. Deloizy
Timers
Capture
Compare
UART
SPI
I 2 C™
PWM
ADCs
S&H
6K 6K 6K 12K 12K 12K 12K 12K
256 256 256 512 512 512 512 512
2 2 2 3 3 3 3 3
0 0 0 1 1 1 1 1
1 1 1 2 2 2 2 2
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
2x2 2x2 2x2 4x2 4x2 4x2 4x2 4x2
1 1 1 1 1 1 1 1
3 6 ch 3 6 ch 3 6 ch 5 8 ch 5 8 ch 5 8 ch 5 12 ch 5 12 ch
10
GPIO
Data SRAM (Bytes)
SDIP SOIC QFN-S SDIP SOIC QFN-S QFN TQFP
Analog Comparators
ProgramMemory (Bytes)
28 28 28 28 28 28 44 44
A/D Inputs
Packaging
Product dsPIC30F1010 dsPIC30F1010 dsPIC30F1010 dsPIC30F2020 dsPIC30F2020 dsPIC30F2020 dsPIC30F2023 dsPIC30F2023
Pins
I.1 dsPIC30F SWITCH MODE POWER SUPPLY FAMILY (dsPIC30F1010/202X)
2 2 2 4 4 4 4 4
21 21 21 21 21 21 35 35
dsPIC30F2023
Présentation
I.2 Boîtiers
44-Lead Plastic Quad Flat, No Lead Package (ML) - 8x8 mm Body (QFN) :
M. Deloizy
11
dsPIC30F2023
Présentation n
44-Lead Pllastic Th hin Quad d Flatpa ack (PT)) 10x10x x1 mm Body, B 1.0 0/0.10 mm m Lead Form F (T TQFP) :
M. M Deloizy
12
dsP PIC30F2 2023
Présentation
I.3 Caractéristiques générales I.3.a High-Performance Modified RISC CPU:
• • • • • • • •
• • • •
Modified Harvard architecture C compiler optimized instruction set architecture 83 base instructions with flexible addressing modes 24-bit wide instructions, 16-bit wide data path 12 Kbytes on-chip Flash program space 512 bytes on-chip data RAM 16 x 16-bit working register array Up to 30 MIPS operation: - Dual Internal RC - 9.7 and 14.55 MHz (±1%) Industrial Temp - 6.4 and 9.7 MHz (±1%) Extended Temp - 32X PLL with 480 MHz VCO - PLL inputs ±3% - External EC clock 6.0 to 14.55 MHz - HS Crystal mode 6.0 to 14.55 MHz 32 interrupt sources Three external interrupt sources 8 user-selectable priority levels for each interrupt 4 processor exceptions and software traps M. Deloizy
13
dsPIC30F2023
Présentation
I.3.b
• • • • • •
DSP Engine Features:
Modulo and Bit-Reversed modes Two 40-bit wide accumulators with optional saturation logic 17-bit x 17-bit single-cycle hardware fractional/integer multiplier Single-cycle Multiply-Accumulate (MAC) operation 40-stage Barrel Shifter Dual data fetch
M. Deloizy
14
dsPIC30F2023
Présentation
I.3.c Peripheral Features:
• High-current sink/source I/O pins: 25 mA/25 mA • Three 16-bit timers/counters; optionally pair up 16-bit timers into 32bit timer modules • One 16-bit Capture input functions • Two 16-bit Compare/PWM output functions - Dual Compare mode available • 3-wire SPI modules (supports 4 Frame modes) • I2CTM module supports o Multi-Master/Slave mode o 7-bit/10-bit addressing • UART Module: - Supports RS-232, RS-485 and LIN 1.2 - Supports IrDA® with on-chip hardware endec - Auto wake-up on Start bit - Auto-Baud Detect - 4-level FIFO buffer
M. Deloizy
15
dsPIC30F2023
Présentation
I.3.d
• • • •
• • •
• • • •
Power Supply PWM Module Features:
Four PWM generators with 8 outputs Each PWM generator has independent time base and duty cycle Duty cycle resolution of 1.1 ns at 30 MIPS Individual dead time for each PWM generator: - Dead-time resolution 4.2 ns at 30 MIPS - Dead time for rising and falling edges Phase-shift resolution of 4.2 ns @ 30 MIPS Frequency resolution of 8.4 ns @ 30 MIPS PWM modes supported: - Complementary - Push-Pull - Multi-Phase - Variable Phase - Current Reset - Current-Limit Independent Current-Limit and Fault Inputs Output Override Control Special Event Trigger PWM generated ADC Trigger M. Deloizy
16
dsPIC30F2023
Présentation
I.3.e Analog Features:
ADC • 10-bit resolution • 2000 Ksps conversion rate • Up to 12 input channels • “Conversion pairing” allows simultaneous conversion of two inputs (i.e., current and voltage) with a single trigger • PWM control loop: - Up to six conversion pairs available - Each conversion pair has up to four PWM and seven other selectable trigger sources • Interrupt hardware supports up to 1M interrupts per second
M. Deloizy
17
dsPIC30F2023
Présentation
COMPARATOR • Four Analog Comparators: - 20 ns response time - 10-bit DAC reference generator - Programmable output polarity - Selectable input source - ADC sample and convert capable • PWM module interface - PWM Duty Cycle Control - PWM Period Control - PWM Fault Detect • Special Event Trigger • PWM-generated ADC Trigger
M. Deloizy
18
dsPIC30F2023
Présentation
I.3.f Special Microcontroller Features:
• Enhanced Flash program memory: - 10,000 erase/write cycle (min.) for industrial temperature range, 100k (typical) • Self-reprogrammable under software control • Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Startup Timer (OST) • Flexible Watchdog Timer (WDT) with on-chip low power RC oscillator for reliable operation • Fail-Safe clock monitor operation • Detects clock failure and switches to on-chip low power RC oscillator • Programmable code protection • In-Circuit Serial Programming™ (ICSP™) • Selectable Power Management modes - Sleep, Idle and Alternate Clock modes
M. Deloizy
19
dsPIC30F2023
Présentation
I.3.g
• • • •
CMOS Technology:
Low-power, high-speed Flash technology 3.3V and 5.0V operation (±10%) Industrial and Extended temperature ranges Low power consumption
M. Deloizy
20
dsPIC30F2023
Présentation n
I.4 Schéma S fonction nnel
M. M Deloizy
21
dsP PIC30F2 2023
Présentation n
I.5 Brochage B
M. M Deloizy
22
dsP PIC30F2 2023
CPU
II Architecture du CPU II.1 Le noyau Instructions sur 24 bits (en adresses paires). 4M adressable. Pré-décodage des instructions (pas de pipeline) Structures de boucles de programmes (instructions DO REPEAT) 16 registres de 16 bits pour données, adresses ou offsets (W15 = SP) Espace adressage données : 64 k octets (32 k mots) divisé en 2 blocs Chaque bloc est géré par son AGU (Address Generation Unit) Accès aux données contenues dans la mémoire programme : - Pagination utilisant PSVPAG (les 32 ko du haut de l’espace de données peuvent être mappés tous les 16kmots du bas de la mémoire de programme (user space) - Utilisation d’instructions de lecture/écriture de tables Moteur DSP intégré Gestion de buffers circulaires (adressage modulo) Adressage bit-reverse Instructions MAC (Multiply and Acumulate) 62 vecteurs d’interruption (8 traps) avec 7 niveaux de priorité
M. Deloizy
23
dsPIC30F2023
CPU
Reg gistres : - W0 à W15 W : 16 6 registr res de travaiil - ACCA A, ACCB : accum mulateur rs 40 bitts - SR : re egistre d d’état - TBLPA AG : reg gistre de e page de e donné ées - PSVPA gistre de e visibiliité AG : reg de pag ge de pr rogramm me - DOST TART, DO OEND, DCOUNT D T et RCOU UNT : reg gistres de d gestio on de DO O REPEA AT - PC : co ompteu ur de pro ogramm me 5 est résservé po our la ge estion de e la W15 pile e systèm me (SP). W14 4 est déd dié à la p pile utillisateur (av vec les in nstructio ons LNK K et ULN NK). M. M Deloizy
24
dsP PIC30F2 2023
CPU
II.1.a
Instruction LNK
LNK #lit14
lit14
LNK #0xA0
[0 ... 16382]
Avant
Opération: W14 → (W15) W15 + 2 → W15 W15 → W14 W15 + lit14 → W15
W14 W15 Data 2000 SR
II.1.b
ULNK
Instruction ULNK
2000 2000 0000 0000
Avant
ULNK Opération: W14 → W15 W15 – 2 → W15 (W15) → W14
M. Deloizy
Après
W14 W15 Data 2000 SR
25
2002 20A2 2000 0000
W14 W15 Data 2000 SR
2002 20A2 2000 0000
Après W14 W15 Data 2000 SR
2000 2000 0000 0000
dsPIC30F2023
CPU
II.2 Mémoire M e program mme Car ractéristtiques : • Adresse e sur 24 bits • Instruc ctions su ur 24 bitts. Insttruction ns toute es les adr resses pa aires (pour assu urer com mpatibillité avec c donnée es quand d lecture e de don nnées). Pro ogramme es situéss dans l’’espace mémoir m e utilisa ateur ave ec PC sur r 23 bitss (0x000 0000 à 0x x7FFFFE E). Bit b23 per rmet acc cès à : • Device ID I • User ID D • Bits de configu uration Les instruc ctions TB BLRD ett TBLWT T perme ettent l’a accès aux x donnée es conten nues en mémoir re progr ramme. Posssibilité de "rem mapper" une pag ge (16K mots) m de e la mém moire pr rogramm me danss la mém moire de donnée es.
M. M Deloizy
26
PIC30F2 2023 dsP
CPU
II.3 Mémoire M e de donn nées II.3.a a
• • • •
Cara actéristiqu ues :
Adresse e sur 16 bits Donnée es sur 16 6 bits. Accès possible p aux octe ets. Les motts doiven nt être en e adresse e paire
Esp pace de données d divisé en e 2 bloc cs (X et Y, pour r certain nes insttruction ns DSP) et peut être vu com mme un unique u e en usage e CPU stan ndard. Les blocs so ont géré és par de es AGU (Ad ddress Generati G ion Unitt). Leurss adr resses so ont contiigües.
M. M Deloizy
27
dsP PIC30F2 2023
CPU
II.3.b
Espace Near
Espace dans le bloc X compris entre 0x0000 et 0x1FFF. Accessible par une adresse 13 bits. II.3.c
Pile système
Gérée par W15 (=SP) W15 pointe sur l’espace disponible situé au sommet de la pile. La pile croît vers les adresses hautes. Empilement : Donnée stockée en [W15] puis post-incrémentation de W15. Dépilement : Pré-décrémentation de W15, puis récupération de la donnée pointée par W15. SPLIM doit contenir la valeur maximale que peut atteindre la pile. Une exception est déclenchée si W15=SPLIM et qu’une donnée est empilée. De même, si W15 atteint une valeur inférieure à 0x800, une exception est déclenchée (afin de protéger l’espace SFR). M. Deloizy
28
dsPIC30F2023
CPU
II.3.d
Registres du noyau
Voir fascicule
M. Deloizy
29
dsPIC30F2023
CPU
II.4 Interruptions 35 sources d’interruption 4 exceptions processeur (traps) Table de vecteurs (IVT) à partir de l’adresse 4. Table de vecteurs alternée (AIVT) utilisée si ALTIVT (INTCON2.15) = 1.
M. Deloizy
30
dsPIC30F2023
CPU
M. Deloizy
31
dsPIC30F2023
CPU
II.4.a
Interruptions gérées par :
• IFS0, IFS1, IFS2 : demandes d’interruptions. o mis à 1 par les périphériques o remis à 0 par programme. • IEC0, IEC1, IEC2 : autorisations des interruptions. • IPC0 à IPC11 : gestion des priorités pour chaque périphérique. • IPL : niveau de priorité courant du CPU. o IPL dans CORCON (CORCON) o IPL dans SR (SR). • INTCON1, INTCON2 : registres de contrôle et d’état des exceptions • INTTREG : numéro du vecteur d’interruption et niveau de priorité • DISI : interdiction temporaire des interruptions de niveau ≤ 6 o DISICNT : nombre de cycles restant
M. Deloizy
32
dsPIC30F2023
CPU
II.4.b
Table des vecteurs d’interruption et priorités
Voir fascicule Niveau de priorité : • 1 : moins prioritaire • 7 : priorité maximale • Niveau 0 : interruptions du périphérique non prises en compte • IPCx : fixent la priorité pour chaque source d’interruption. • Si deux sources d’interruption on le même niveau de priorité, celle dont le niveau "naturel" est le plus élevé sera prise en compte en premier. • Tous les champs IP sont initialisés à 1 au RESET.
M. Deloizy
33
dsPIC30F2023
CPU
II.4.c c
Séqu uence d’in nterruptio on
1) ) IFSx x évalué és entre deux instruc ctions. 2) ) Si IF FSx=1 ett IECx =1 : o requ uête d’in nterrup ption valiide. 3) ) Le cy ycle d’in nterrup ption est lanc cé pour lla requê ête de niveau maxima al (en pr renant en comp pte IPCx x et la pr riorité naturellle), si ce e niveau u est strictem ment sup périeur au niveau courantt du CPU U (défin ni dans SR). S 4) ) Le CPU C emp pile alor rs PC, SR RL et IPL L3 5) ) Le niveau n co orrespondant à l’interr ruption prise en n compte est chargé dans d SR R : interdict i tion de toute t in nter. de niveau n iinférieu ur ou égal.. 6) ) IPL3 3 est miss à 0 pou ur les in nterrupttions. Il est e mis à 1 pour r les trap ps. 7) ) PC est e charg gé à par rtir du vecteur v d d’interr ruption M. M Deloizy
34
dsP PIC30F2 2023
CPU
8) … La routine de gestion de l’interruption s’exécute. Elle doit se terminer par RETFIE. Le flag de ISFx doit être remis à 0 (procédure d’acquittement) avant de quitter l’interruption. 9) RETFIE dépile PC, SR et IPL3, ce qui a pour effet de remettre pour le CPU le niveau d’interruption initial et de poursuivre l’exécution du programme interrompu. Notes : • Une interruption est interruptible si une requête de niveau supérieur survient. • On peut interdire la prise en compte d’une autre interruption pendant l’exécution d’une interruption en mettant NSTDIS (INTCON1) à 1, ceci indépendamment des priorités. • Pour interdire toutes les interruptions, on peut mettre IPL à 7 (dans SR). Ceci n’aura cependant pas d’incidence sur la prise en compte des traps.
M. Deloizy
35
dsPIC30F2023
CPU
II.4.d
Traps
Interruptions non masquables → Défaillance matérielle ou logicielle. Les priorités sont fixées et sont comprises entre 8 et 15 (IPL3=1). Déclenchement des traps : • Erreur mathématique o Division par 0 o Overflow d’un accumulateur (A ou B) sur b31 ou b39 (peut être paramétré et autorisé) o Nombre de décalages trop grand • Erreur d’adresse o Accès d’un mot à une adresse impaire o Accès d’une donnée à une adresse (programme ou donnée) non implémentée o Exécution d’une instruction dans la table des vecteurs d’interruptions o Branchement (BRA ou GOTO) à une adresse non implémentée o Modification de PC correspondant à une adresse non implémentée. • Erreur de pile M. Deloizy
36
dsPIC30F2023
CPU
o Si SP est chargé par ne valeur inférieure à 0x800 o Si SP prend une valeur supérieure à SPLIM. • Erreur d’oscillateur o Si l’oscillateur externe devient défaillant (passage sur oscillateur interne).
M. Deloizy
37
dsPIC30F2023
CPU
II.4.e
Commutation de contexte rapide
Une sauvegarde rapide de contexte peut être réalisée en utilisant des registres caches. Cette sauvegarde ne peut se faire que sur un niveau en utilisant les instructions PUSH.S et POP.S (il n’y a alors pas utilisation de la pile) Les données enregistrées sont les flags DC, N, OV, Z et C de SR, et les registres W0 à W3.
M. Deloizy
38
dsPIC30F2023
CPU
II.4.f
Reset
Réinitialisation de tous les registres du CPU et des périphériques à un état prédéfini. PC est mis à 0. Le déclenchement d’un RESET est obtenu par : • Patte RESET externe • Power-On RESET (croissance de VDD au-delà d’un certain seuil (1.85V nom.) • Instruction RESET • Un débordement du watchdog • Utilisation d’un registre W non initialisé • Code instruction illégal • Plusieurs traps matériels déclenchés simultanément
M. Deloizy
39
dsPIC30F2023
CPU
II.4.g
Réveil du processeur
Le processeur peut être sorti des modes SLEEP et IDLE à partir d’une interruption, si elle est active et autorisée. En mode Sleep le CPU, la source d’horloge et tous les périphériques dépendant de l’horloge système sont arrêtés. Il s’agit du mode de consommation minimale. En mode Idle, le CPU est arrêté mais l’horloge continue de fonctionner pour les périphériques. Ces modes sont activés grâce aux instructions suivantes : • PWRSAV #SLEEP_MODE ; Put the device into SLEEP mode • PWRSAV #IDLE_MODE ; Put the device into IDLE mode
M. Deloizy
40
dsPIC30F2023
CPU
II.4.h
Registres associés aux interruptions
♦ INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NSTDIS OVAERR OVBERR COVAERR
b15
R/W-0
R/W-0
SFTACERR DIV0ERR
b7
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
U-0 —
R/W-0
R/W-0 R/W-0
COVBERR OVATE OVBTE COVTE
R/W-0
b8
R/W-0
R/W-0
R/W-0
MATHERR ADDRERR STKERR OSCFAIL
U-0 —
b0
NSTDIS: Interrupt Nesting Disable bit 1 = Interrupt nesting is disabled 0 = Interrupt nesting is enabled OVAERR: Accumulator A Overflow Trap Flag bit 1 = Trap was caused by overflow of Accumulator A 0 = Trap was not caused by overflow of Accumulator A OVBERR: Accumulator B Overflow Trap Flag bit 1 = Trap was caused by overflow of Accumulator B 0 = Trap was not caused by overflow of Accumulator B COVAERR: Accumulator A Catastrophic Overflow Trap Enable bit 1 = Trap was caused by catastrophic overflow of Accumulator A 0 = Trap was not caused by catastrophic overflow of Accumulator A COVBERR: Accumulator B Catastrophic Overflow Trap Enable bit 1 = Trap was caused by catastrophic overflow of Accumulator B 0 = Trap was not caused by catastrophic overflow of Accumulator B OVATE: Accumulator A Overflow Trap Enable bit 1 = Trap overflow of Accumulator A 0 = Trap disabled OVBTE: Accumulator B Overflow Trap Enable bit 1 = Trap overflow of Accumulator B 0 = Trap disabled COVTE: Catastrophic Overflow Trap Enable bit 1 = Trap on catastrophic overflow of Accumulator A or B enabled 0 = Trap disabled
M. Deloizy
41
dsPIC30F2023
CPU bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SFTACERR: Shift Accumulator Error Status bit 1 = Math error trap was caused by an invalid accumulator shift 0 = Math error trap was not caused by an invalid accumulator shift DIV0ERR: Arithmetic Error Status bit 1 = Math error trap was caused by a divided by zero 0 = Math error trap was not caused by an invalid accumulator shift Unimplemented: Read as ‘0’ MATHERR: Arithmetic Error Status bit 1 = Overflow trap has occurred 0 = Overflow trap has not occurred ADDRERR: Address Error Trap Status bit 1 = Address error trap has occurred 0 = Address error trap has not occurred STKERR: Stack Error Trap Status bit 1 = Stack error trap has occurred 0 = Stack error trap has not occurred OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred Unimplemented: Read as ‘0’
M. Deloizy
42
dsPIC30F2023
CPU
♦ INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-0 ALTIVT
b15
U-0 —
U-0 —
b7
bit 15 bit 14 bit 13-3 bit 2 bit 1 bit 0
R-0 DISI U-0 —
U-0 —
U-0 —
U-0 —
U-0 —
R/W-0 INT2EP
U-0 —
U-0 — R/W-0 INT1EP
U-0 —
U-0 —
R/W-0 INT0EP
b8
b0
ALTIVT: Enable Alternate Interrupt Vector Table bit 1 = Use alternate vector table 0 = Use standard (default) vector table DISI: DISI Instruction Status bit 1 = DISI instruction is active 0 = DISI instruction is not active Unimplemented: Read as ‘0’ INT2EP: External Interrupt 2 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge
M. Deloizy
43
dsPIC30F2023
CPU
♦ IFS0: INTERRUPT FLAG STATUS REGISTER 0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — MI2CIF SI2CIF NVMIF ADIF
R/W-0 R/W-0 U1TXIF U1RXIF
b15
R/W-0 T3IF
b7
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R/W-0 T2IF
R/W-0 OC2IF
U-0 —
R/W-0 T1IF
Unimplemented: Read as ‘0’ MI2CIF: I2C Master Events Interrupt Flag Status bit SI2CIF: I2C Slave Events Interrupt Flag Status bit NVMIF: Nonvolatile Memory Interrupt Flag Status bit ADIF: ADC Conversion Complete Interrupt Flag Status bit U1TXIF: UART1 Transmitter Interrupt Flag Status bit U1RXIF: UART1 Receiver Interrupt Flag Status bit SPI1IF: SPI1 Event Interrupt Flag Status bit T3IF: Timer3 Interrupt Flag Status bit T2IF: Timer2 Interrupt Flag Status bit OC2IF: Output Compare Channel 2 Interrupt Flag Status bit Unimplemented: Read as ‘0’ T1IF: Timer1 Interrupt Flag Status bit OC1IF: Output Compare Channel 1 Interrupt Flag Status bit IC1IF: Input Capture Channel 1 Interrupt Flag Status bit INT0IF: External Interrupt 0 Flag Status bit
M. Deloizy
44
R/W-0 OC1IF
R/W-0 IC1IF
R/W-0 SPI1IF
b8
R/W-0 INT0IF
b0
dsPIC30F2023
CPU
♦ IFS1: INTERRUPT FLAG STATUS REGISTER 1 R/W-0 AC3IF
b15
b7
U-0 —
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10-7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R/W-0 AC2IF
R/W-0 AC1IF
U-0 —
R/W-0 CNIF
U-0 —
U-0 —
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PWM4IF PWM3IF PWM2IF PWM1IF PSEMIF INT2IF
U-0 —
b8
R/W-0 INT1IF
b0
AC3IF: Analog Comparator #3 Interrupt Flag Status bit AC2IF: Analog Comparator #2 Interrupt Flag Status bit AC1IF: Analog Comparator #1 Interrupt Flag Status bit Unimplemented: Read as ‘0’ CNIF: Input Change Notification Interrupt Flag Status bit Unimplemented: Read as ‘0’ PWM4IF: Pulse Width Modulation Generator #4 Interrupt Flag Status bit PWM3IF: Pulse Width Modulation Generator #3 Interrupt Flag Status bit PWM2IF: Pulse Width Modulation Generator #2 Interrupt Flag Status bit PWM1IF: Pulse Width Modulation Generator #1 Interrupt Flag Status bit PSEMIF: PWM Special Event Match Interrupt Flag Status bit INT2IF: External Interrupt 2 Flag Status bit INT1IF: External Interrupt 1 Flag Status bit
M. Deloizy
45
dsPIC30F2023
CPU
♦ IFS2: INTERRUPT FLAG STATUS REGISTER 2 U-0 —
U-0 —
b15
U-0 —
R/W-0 R/W-0 R/W-0 ADCP2IF ADCP1IF ADCP0IF b7
bit 15-11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4-1 bit 0
U-0 —
U-0 —
U-0 —
U-0 —
R/W-0 R/W-00 R/W-0 ADCP5IF ADCP4IF ADCP3IF b8
U-0 —
U-0 —
R/W-0 AC4IF
b0
Unimplemented: Read as ‘0’ ADCP5IF: ADC Pair 5 Conversion Done Interrupt Flag Status bit ADCP4IF: ADC Pair 4 Conversion Done Interrupt Flag Status bit ADCP3IF: ADC Pair 3 Conversion Done Interrupt Flag Status bit ADCP2IF: ADC Pair 2 Conversion Done Interrupt Flag Status bit ADCP1IF: ADC Pair 1 Conversion Done Interrupt Flag Status bit ADCP0IF: ADC Pair 0 Conversion Done Interrupt Flag Status bit Unimplemented: Read as ‘0’ AC4IF: Analog Comparator #4 Interrupt Flag Status bit
M. Deloizy
46
dsPIC30F2023
CPU
♦ IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — MI2CIE SI2CIE NVMIE ADIE U1TXIE U1RXIE
b15
R/W-0 T3IE
b7
R/W-0 T2IE
R/W-0 OC2IE
U-0 —
R/W-0 T1IE
R/W-0 OC1IE
♦ IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 AC3IE AC2IE AC1IE — CNIE — b15
b7
U-0 —
R/W-0 SPI1IE
b8
R/W-0 IC1IE
R/W-0 INT0IE
U-0 —
U-0 —
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PWM4IE PWM3IE PWM2IE PWM1IE PSEMIE INT2IE
b0
b8
R/W-0 INT1IE
b0
♦ IEC2: INTERRUPT ENABLE CONTROL REGISTER 2 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — ADCP5IE ADCP4IE ADCP3IE b15
b8
R/W-0 R/W-0 R/W-0 ADCP2IE ADCP1IE ADCP0IE b7
M. Deloizy
U-0 —
U-0 — 47
U-0 —
U-0 —
R/W-0 AC4IE
b0
dsPIC30F2023
CPU
♦ IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 bit 14-12 bit 10-8 bit 6-4 bit 2-0
T1IP: Timer1 Interrupt Priority bits OC1IP: Output Compare Channel 1 Interrupt Priority bits IC1IP: Input Capture Channel 1 Interrupt Priority bits INT0IP: External Interrupt 0 Priority bits
♦ IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 bit 14-12 bit 10-8 bit 6-4
T3IP: Timer3 Interrupt Priority bits T2IP: Timer2 Interrupt Priority bits OC2IP: Output Compare Channel 2 Interrupt Priority bits
♦ IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 bit 14-12 bit 10-8 bit 6-4 bit 2-0
ADIP: ADC Conversion Complete Interrupt Priority bit U1TXIP: UART1 Transmitter Interrupt Priority bits U1RXIP: UART1 Receiver Interrupt Priority bits SPI1IP: SPI1 Event Interrupt Priority bits
♦ IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 bit 10-8 bit 6-4 bit 2-0
MI2CIP: I2C Master Events Interrupt Priority bits SI2CIP: I2C Slave Events Interrupt Priority bits NVMIP: Nonvolatile Memory Interrupt Priority bits
♦ IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 bit 15 bit 14-12 bit 11 bit 10-8 bit 7 bit 6-4 bit 3 bit 2-0
Unimplemented: Read as ‘0’ PWM1IP: PWM Generator #1 Interrupt Priority bits Unimplemented: Read as ‘0’ PSEMIP: PWM Special Event Match Priority bits Unimplemented: Read as ‘0’ INT2IP: External Interrupt 2 Priority bits Unimplemented: Read as ‘0’ INT1IP: External Interrupt 1 Priority bits
M. Deloizy
48
dsPIC30F2023
CPU
♦ IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 bit 10-8 bit 6-4 bit 2-0
PWM4IP: PWM Generator #4 Interrupt Priority bits PWM3IP: PWM Generator #3 Interrupt Priority bits PWM2IP: PWM Generator #2 Interrupt Priority bits
♦ IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6 bit 14-12
CNIP: Change Notification Interrupt Priority bits
♦ IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 bit 14-12 bit 10-8 bit 6-4
AC3IP: Analog Comparator 3 Interrupt Priority bits AC2IP: Analog Comparator 2 Interrupt Priority bits AC1IP: Analog Comparator 1 Interrupt Priority bits
♦ IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8 bit 2-0
AC4IP: Analog Comparator 4 Interrupt Priority bits
♦ IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9 bit 14-12 bit 10-8 bit 6-4
ADCP2IP: ADC Pair 2 Conversion Done Interrupt Priority bits ADCP1IP: ADC Pair 1 Conversion Done Interrupt Priority bits ADCP0IP: ADC Pair 0 Conversion Done Interrupt Priority bits
♦ IPC10: INTERRUPT PRIORITY CONTROL REGISTER 10 bit 10 - 8 bit 6-4 bit 2-0
ADCP5IP: ADC Pair 5 Conversion Done Interrupt Priority bits ADCP4IP: ADC Pair 4 Conversion Done Interrupt Priority bits ADCP3IP: ADC Pair 3 Conversion Done Interrupt Priority bits
M. Deloizy
49
dsPIC30F2023
CPU
♦ INTTREG: INTERRUPT CONTROL AND STATUS REGISTER U-0 U-0 U-0 U-0 R-0 R-0 R-0 — — — — ILR
R-0
b15
b7
U-0 —
bit 15-12 bit 11-8
bit 7 bit 6-0
R-0
R-0
R-0
R-0 R-0 VECNUM
Unimplemented: Read as ‘0’ ILR: New CPU Interrupt Priority Level bits 1111 = CPU Interrupt Priority Level is 15 • • 0001 = CPU Interrupt Priority Level is 1 0000 = CPU Interrupt Priority Level is 0 Unimplemented: Read as ‘0’ VECNUM: Vector Number of Pending Interrupt bits 0111111 = Interrupt Vector pending is number 135 • • 0000001 = Interrupt Vector pending is number 9 0000000 = Interrupt Vector pending is number 8
M. Deloizy
50
R-0
b8
R-0 b0
dsPIC30F2023
CPU
II.5 Horloge II.5.a
• • • • • •
Caractéristiques
Horloge interne ou externe PLL intégrée Mécanisme de commutation d’horloges Post diviseur programmable (économie d’énergie) Détection des défaillances Mode programmé dans les bits de configuration (peut être modifié ensuite)
M. Deloizy
51
dsPIC30F2023
CPU
II.5.b b
Sourrces d’horloge
♦ Oscillateu O ur primaiire Mod de HS : quartz q 1 10 MHz-2 25 MHz.
♦ Horloge H e externe
C OSCILL LATOR EC CONFIGUR RATION N
M. M Deloizy
ECIO OS SCILLAT TOR CONFIG GURATIION
52
dsP PIC30F2 2023
CPU
♦ Oscillateur interne - INTERNAL FAST RC OSCILLATOR (FRC) • Rapide (6.4/9.7/14.55 MHz) • Précis (< 2% erreur) • Réglable à ±3% FRC sélectionné quand : • Oscillateurs EC ou HS non sélectionnés • Détection d’une défaillance d’horloge Sélection de gamme de fréquences : • Haute : 14.55 MHz (industrielle) / 9.7 MHz (étendue) • Basse : 9.7 MHz (industrielle) / 6.4 MHz (étendue) Mode réduction du bruit CEM pour la PWM par variation (faible) de la fréquence d’horloge • Mode séquence de fréquences • Mode glissement pseudo aléatoire
M. Deloizy
53
dsPIC30F2023
CPU
II.5.c
Schéma fonctionnel
X32
M. Deloizy
54
dsPIC30F2023
CPU
M. M Deloizy
55
dsP PIC30F2 2023
CPU
II.5.d
Registres de contrôle
♦ OSCCON: OSCILLATOR CONTROL REGISTER U-0 R-y R-y R-y U-0 HS,HC HS,HC HS,HC — COSC — b15
R/W-0
U-0
CLKLOCK
—
b7
bit 15 bit 14-12
bit 11 bit 10-8
R/W-y
R/W-y
R/W-y
NOSC
R/W-0 R/C-0 R/W-0 R-0 HS,HC HS,HC LOCK PRCDEN CF TSEQEN
U-0 —
b8
R/W-0 HC OSWEN
b0
Unimplemented: Read as ‘0’ COSC: Current Oscillator Group Selection bits (read-only) 000 = Fast RC Oscillator (FRC) 001 = Fast RC Oscillator (FRC) with PLL Module 010 = Primary Oscillator (HS, EC) 011 = Primary Oscillator (HS, EC) with PLL Module 100 = Reserved 101 = Reserved 110 = Reserved 111 = Reserved This bit is Reset upon: Set to FRC value (‘000’) on POR Loaded with NOSC at the completion of a successful clock switch Set to FRC value (‘000’) when FSCM detects a failure and switches clock to FRC Unimplemented: Read as ‘0’ NOSC: New Oscillator Group Selection bits 000 = Fast RC Oscillator (FRC) 001 = Fast RC Oscillator (FRC) with PLL Module 010 = Primary Oscillator (HS, EC) 011 = Primary Oscillator (HS, EC) with PLL Module 100 = Reserved
M. Deloizy
56
dsPIC30F2023
CPU
bit 7
bit 6 bit 5
bit 4 bit 3
bit 2
bit 1 bit 0
101 = Reserved 110 = Reserved 111 = Reserved CLKLOCK: Clock Lock Enabled bit 1 = If (FCKSM1 = 1), then clock and PLL configurations are locked. If (FCKSM1 = 0), then clock and PLL configurations may be modified 0 = Clock and PLL selection are not locked, configurations may be modified Note: Once set, this bit can only be cleared via a Reset. Unimplemented: Read as ‘0’ LOCK: PLL Lock Status bit (read-only) 1 = Indicates that PLL is in lock 0 = Indicates that PLL is out of lock (or disabled) This bit is : - Reset on POR - Reset when a valid clock switching sequence is initiated by the clock switch state machine - Set when PLL lock is achieved after a PLL start - Reset when lock is lost - Read zero when PLL is not selected as a Group 1 system clock PRCDEN: Pseudo Random Clock Dither Enable bit 1 = Pseudo random clock dither is enabled 0 = Pseudo random clock dither is disabled CF: Clock Fail Detect bit (read/clearable by application) 1 = FSCM has detected clock failure 0 = FSCM has NOT detected clock failure This bit is : - Reset on POR - Reset when a valid clock switching sequence is initiated by the clock switch state machine - Set when clock fail detected TSEQEN: FRC Tune Sequencer Enable bit 1 = The TUN, TSEQ1, ... , TSEQ7 bits in the OSCTUN and the OSCTUN2 registers sequentially tune the FRC oscillator. Each field being sequentially selected via the ROLL signals from the PWM module. 0 = The TUN bits in OSCTUN register tunes the FRC oscillator Unimplemented: Read as ‘0’ OSWEN: Oscillator Switch Enable bit 1 = Request oscillator switch to selection specified by NOSC bits 0 = Oscillator switch is complete This bit is Reset upon: - Reset on POR - Reset after a successful clock switch - Reset after a redundant clock switch - Reset after FSCM switches the oscillator to (Group 3) FRC
M. Deloizy
57
dsPIC30F2023
CPU
♦ OSCTUN: OSCILLATOR TUNING REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TSEQ3
b15
R/W-0 b7
bit 15-12 bit 11-8 bit 7-4 bit 3-0
R/W-0 R/W-0 TSEQ1
R/W-0
R/W-0
R/W-0 R/W-0 TSEQ2
R/W-0
R/W-0 R/W-0 TUN
R/W-0
b8
b0
TSEQ3: Tune Sequence Value #3 bits When PWM ROLL = 011, this field is used to tune the FRC instead of TUN TSEQ2: Tune Sequence Value #2 bits When PWM ROLL = 010, this field is used to tune the FRC instead of TUN TSEQ1: Tune Sequence Value #1 bits When PWM ROLL = 001, this field is used to tune the FRC instead of TUN TUN: Specifies the user tuning capability for the internal fast RC oscillator . If the TSEQEN bit in the OSCCON register is set, this field, along with bits TSEQ1-TSEQ7, will sequentially tune the FRC oscillator. 0111 = Maximum frequency 0110= 0101= 0100= 0011= 0010= 0001= 0000 = Center frequency, oscillator is running at calibrated frequency 1111= 1110= 1101= 1100= 1011= 1010= 1001= 1000 = Minimum frequency
M. Deloizy
58
dsPIC30F2023
CPU
♦ OSCTUN2: OSCILLATOR TUNING REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TSEQ7
b15
R/W-0 b7
bit 15-12 bit 11-8 bit 7-4 bit 3-0
R/W-0 R/W-0 TSEQ5
R/W-0
R/W-0
R/W-0 R/W-0 TSEQ6
R/W-0
R/W-0 R/W-0 TSEQ4
R/W-0
TSEQ7: Tune Sequence value #7 bits When PWM ROLL = 111, this field is used to tune the FRC instead of TUN TSEQ6: Tune Sequence value #6 bits When PWM ROLL = 110, this field is used to tune the FRC instead of TUN TSEQ5: Tune Sequence value #5 bits When PWM ROLL = 101, this field is used to tune the FRC instead of TUN TSEQ4: Tune Sequence value #4 bits When PWM ROLL = 100, this field is used to tune the FRC instead of TUN
M. Deloizy
59
b8
b0
dsPIC30F2023
CPU
♦ LFSR: LINEAR FEEDBACK SHIFT REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — LFSR
R/W-0
b15
R/W-0 b7
bit 15 bit 14-8 bit 7-0
R/W-0
R/W-0
R/W-0 R/W-0 LFSR
Unimplemented: Read as ‘0’ When PWM ROLL = 111, this field is used to tune the FRC instead of TUN LFSR : Most Significant 7 bits of the pseudo random FRC trim value bits LFSR : Least Significant 8 bits of the pseudo random FRC trim value bits
M. Deloizy
60
R/W-0
R/W-0 b8
R/W-0
R/W-0 b0
dsPIC30F2023
CPU
II.6 Watchdog (Chien de garde) Prévient les dysfonctionnements logiciels en réinitialisant (RESET) le CPU. Composé d’un timer et d’une horloge indépendants. Activé ou désactivé par FWDTEN dans FWDT (registre de configuration). Quand activé, le compteur s’incrémente. Quand un overflow apparaît, RESET est déclenché (sauf en mode SLEEP). Pour éviter le RESET, l’instruction CLRWDT permet de remettre à 0 le compteur. Si FWDTEN=0, SWDTEN (RCON) permet d’activer le Watchdog par programme.
M. Deloizy
61
dsPIC30F2023
CPU
II.7 Mots de configuration Les mots de configuration sont chargés lors de la programmation du composant.
M. Deloizy
62
dsPIC30F2023
CPU
♦ FOSCSEL (0xF80006): OSCILLATOR SELECTION CONFIGURATION BITS
b23
b15
b7
U-0 —
U-0 —
U-0 —
U-0 —
U-0 —
U-0 —
U-0 —
U-0 —
U-0 —
U-0 —
U-0 —
U-0 —
U-0 —
U-0 —
U-0 —
U-0 —
U-0 —
U-0 —
U-0 —
U-0 —
U-0 —
U-0 —
bit 23-2 bit 1-0
b16
b8
R/P R/P FNOSC1 FNOSC0
b0
Unimplemented: Read as ‘0’ FNOSC: Initial Oscillator Group Selection on POR bits 00 = Fast RC Oscillator (FRC) 01 = Fast RC Oscillator (FRC) divided by N, with PLL module 10 = Primary Oscillator (HS,EC) 11 = Primary Oscillator (HS,EC) with PLL module
M. Deloizy
63
dsPIC30F2023
CPU
♦ FOSC (0xF80008) : OSCILLATOR SELECTION CONFIGURATION BITS U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — —
b23
b15
b7
U-0 —
U-0 —
R/P R/P FCKSM
bit 23-8 bit
bit 5
U-0 — R/P FRANGE
0= Low Range
bit 1-0
U-0 —
U-0 —
U-0 —
U-0 — R/P OSCIOFNC
U-0 —
U-0 —
R/P R/P POSCMD
Unimplemented: Read as ‘0’ 7-6 FCKSM: Clock Switching and Monitor Selection Configuration bits 1x = Clock switching is disabled, fail-safe clock monitor is disabled 01 = Clock switching is enabled, fail-safe clock monitor is disabled 00 = Clock switching is enabled, fail-safe clock monitor is enabled FRANGE: Frequency Range Select for FRC and PLL bit Acts like a “Gear Shift” feature that enables the dsPIC DSC device to operate at reduced MIPS at a reduced supply voltage (3.3V) FRANGE Bit Value 1= High Range
bit 4-3 bit 2
U-0 —
b16
Temperature Rating Industrial Extended Industrial Extended
FRC Frequency (Nominal) 14.55 MHz 9.7 MHz 9.7 MHz 6.4 MHz
b8
b0
PLL VCO (Nominal) 466 MHz (480 MHz max.) 310 MHz (320 MHz max.) 310 MHz (320 MHz max.) 205 MHz (211 MHz max.)
Unimplemented: Read as ‘0’ OSCIOFNC: OSC2 Pin I/O Enable bit 1= CLKO output signal active on the OSCO pin 0= CLKO output disabled POSCMD: Primary Oscillator Mode 11 = Primary Oscillator Disabled 10 = HS oscillator mode selected 01 = Reserved 00 = External clock mode selected
M. Deloizy
64
dsPIC30F2023
CPU
♦ FBS (0xF80000): Boot Code Segment Configuration Register BWRP
BSS
Boot Segment Program Flash Write Protection 1 = Boot segment may be written 0 = Boot segment is write-protected Boot Segment Program Flash Code Protection Size x11= No boot program Flash segment x00= No boot program Flash segment 110= Standard security; small boot segment; boot program Flash segment starts at the end of the Interrupt Vector Segment and ends at 0003FFH 010 = High security; small boot segment; boot program Flash segment starts at the end of the Interrupt Vector Segment and ends at 0003FFH 101= Standard security; medium boot segment; boot program Flash segment starts at the end of the Interrupt Vector Segment and ends at 000FFFH 001= High security; medium boot segment; boot program Flash segment starts at the end of the Interrupt Vector Segment and ends at 000FFFH
M. Deloizy
65
dsPIC30F2023
CPU
♦ FGS (0xF80004): General Code Segment Configuration Register GWRP
GSS
General Segment Program Flash Write Protection 1 = General segment may be written 0 = General segment is write-protected General Segment Program Flash Code Protection 11 = No Protection 10 = Standard security; general program Flash segment starts at the end of the Boot Segment and ends at the end of program Flash 0x = Reserved
♦ FWDT (0xF8000A): Watchdog Timer Configuration Register
FWDTEN Watchdog Timer Enable bit 1 = Watchdog Timer always enabled. (LPRC oscillator cannot be dis-abled. Clearing the SWDTEN bit in the RCON register will have no effect.) 0 = Watchdog Timer enabled/disabled by user software (LPRC can be disabled by clearing the SWDTEN bit in the RCON register) WWDTEN Watchdog Timer Window Enable bit 1 = Watchdog Timer in Non-Window mode 0 = Watchdog Timer in Window mode WDTPRE Watchdog Timer Prescaler bit 1 = 1:128 0 = 1:32 WDTPOST Watchdog Timer Postscaler bits 1111= 1:32, 768 1110= 1:16, 384 . . 0001 = 1:2 0000 = 1:1
M. Deloizy
66
dsPIC30F2023
CPU
♦ FPOR (0xF8000C): Power-On Reset Configuration Register FPWRT Power-on Reset Timer Value Select bits 111= PWRT = 128 ms 110= PWRT = 64 ms 101= PWRT = 32 ms 100= PWRT = 16 ms 011= PWRT = 8 ms 010= PWRT = 4 ms 001= PWRT = 2 ms 000= PWRT = Disabled
M. Deloizy
67
dsPIC30F2023
Les ports d’E/S
III Ports d’Entrées / Sorties
III.1 Caractéristiques • 5 ports (A, B, D, E, F) • Toutes les pattes sont partagées entre E/S et périphériques (sauf alimentations, MCLR et OSC1/CLKI) • Toutes les entrées disposent d’un trigger de Schmitt
M. Deloizy
68
dsPIC30F2023
Les ports d’E E/S
• Étage de conne exion :
M. M Deloizy
69
dsP PIC30F2 2023
Les ports d’E/S
III.2 Fonctionnement III.2.a
Ports non multiplexés avec une entrée analogique
♦ Programmation du mode Entrée ou Sortie TRISA, TRISB, TRISD, TRISE ou TRISF : • Bit à 1 ⇒ patte en entrée. • Bit à 0 ⇒ patte en sortie. ♦ Écriture en sortie Écriture dans PORTA, PORTB, PORTD, PORTE ou PORTF : • Bit à 1 ⇒ niveau logique patte =1. • Bit à 0 ⇒ niveau logique patte =0. LATA, LATB, LATD, LATE ou LATF : Mémorisent la valeur écrite dans PORTx. Les contenus de LATx et PORTx peuvent être différents : • Si une sortie a un niveau imposé par un circuit extérieur (Ex. : court-circuit) • Si un bit est mis en entrée • Si un bit est utilisé par un périphérique
Les bits orientés en entrée ne sont pas affectés par une écriture dans PORTx. M. Deloizy
70
dsPIC30F2023
Les ports d’E/S
♦ Lecture d’une entrée Lecture de PORTx : lecture du niveau logique présent sur les pattes. III.2.b
Ports multiplexés avec une entrée analogique
Le port B est multiplexé avec les entrées du convertisseur analogique numérique. Les E/S multiplexées avec une entrée analogique sont en mode analogique par défaut. Les registres ADPCFG (voir p 99) et TRISx contrôlent le mode de fonctionnement de ces E/S. En mode analogique, les ports doivent être mis en entrée (bits de TRISx = 1) Les bits de ADPCFG doivent être à 1 pour utiliser le port en numérique.
M. Deloizy
71
dsPIC30F2023
Les ports d’E/S
III.3 Notification de changement (Input Change Notification) • CN0 à CN7 peuvent déclencher une interruption quand un changement d’état est détecté. • Fonctionne en mode SLEEP. CN0 CN1 CN2 CN3 CN4 CN5 CN6 CN7 RE6 RE7 RB0 RB1 RB2 RB3 RB4 RB5 Les registres CNEN1 & CNPU1 contrôlent les CNx : • CNEN1 active (bit=1) ou désactive (bit=0) les entrées CNx • CNPU1 active (bit=1) ou désactive (bit=0) les pull-ups Si une patte CNx est mise en sortie, le tirage doit être désactivé.
M. Deloizy
72
dsPIC30F2023
Les ports d’E/S
III.4 Registres associés Bits SFR Name-Addr Reset State TRISA-02C0 0000 1111 0000 0000 PORTA-02C2 0000 0000 0000 0000 LATA-02C4 0000 0000 0000 0000 TRISB-02C6 0000 1111 1111 1111 PORTB-02C8 0000 0000 0000 0000 LATB-02CA 0000 0000 0000 0000 TRISD-02D2 0000 0000 0000 0011 PORTD-02D4 0000 0000 0000 0000 LATD-02D6 0000 0000 0000 0000 TRISE02D8 0000 0000 1111 1111 PORTE-02DA 0000 0000 0000 0000 LATE-02DC 0000 0000 0000 0000 TRISF-02DE 1100 0001 1100 1100 PORTF-02E0 0000 0000 0000 0000 LATF02E2 0000 0000 0000 0000 TRISG-02E4 0000 0000 0000 1100 PORTG-02E6 0000 0000 0000 0000 LATG-02E8 0000 0000 0000 0000 ADPCFG-0302 0000 0000 0000 0000 CNEN1-0060 0000 0000 0000 0000 CNPU1-0064 0000 0000 0000 0000
M. Deloizy
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
TRISA11
TRISA10
TRIS9
TRISA8
—
—
—
—
—
—
—
—
—
—
—
—
RA11
RA10
RA9
RA8
—
—
—
—
—
—
—
—
—
—
—
—
LATA11
LATA10
LATA9
LATA8
—
—
—
—
—
—
—
—
—
—
—
—
TRISB11
TRISB10
TRISB9
TRISB8
TRISB7
TRIS6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
—
—
—
—
RB11
RB10
RB9
RB8
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
—
—
—
—
LATB11
LATB10
LATB9
LATB8
LATB7
LATB6
LATB5
LATB4
LATB3
LATB2
LATB1
LATB0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISD1
TRISD0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RD1
RD0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LATD1
LATD0
—
—
—
—
—
—
—
—
TRSE7
TRSE6
TRISE5
TRISE4
TRISE3
TRISE2
TRISE1
TRISE0
—
—
—
—
—
—
—
—
RE7
RE6
RE5
RE4
RE3
RE2
RE1
RE0
—
—
—
—
—
—
—
—
LATE7
LATE6
LATE5
LATE4
LATE3
LATE2
LATE1
LATE0
TRISF15
TRISF14
—
—
—
—
—
TRISF8
TRISF7
TRISF6
—
—
TRISF3
TRISF2
—
—
RF15
RF14
—
—
—
—
—
RF8
RF7
RF6
—
—
RF3
RF2
—
—
LATF15
LATF14
—
—
—
—
—
LATF8
LATF7
LATF6
—
—
LATF3
LATF2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISG3
TRISG2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RG3
RG2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LATG3
LATG2
—
—
—
—
—
—
PCFG11
PCFG10
PCFG9
PCFG8
PCFG7
PCFG6
PCFG5
PCFG4
PCFG3
PCFG2
PCFG1
PCFG0
—
—
—
—
—
—
—
—
CN7IE
CN6IE
CN5IE
CN4IE
CN3IE
CN2IE
CN1IE
CN0IE
—
—
—
—
—
—
—
—
CN7PUE
CN6PUE
CN5PUE
CN4PUE
CN3PUE
CN2PUE
CN1PUE
CN0PUE
73
dsPIC30F2023
Les ports d’E/S
♦ Application 1 : Simulateur logique A 0 0 1 1
B NAND NOR XOR 0 1 1 0 1 1 0 1 0 1 0 1 1 0 0 0
J 0 0 1 1
K Qn+1 0 Qn 1 0 0 1 1 /Qn
M. Deloizy
74
dsPIC30F2023
Les ports d’E E/S
♦ Applicatio A on 2 Dan ns le sch héma ci-c contre, MODE M représen nte un sé électeur à cavaliier : Cav valier su ur : 1-2 : mo ode 1 2-3 : mo ode 2 cavalier r retiré : mode 3 Écr rire la fo onction m mode : int t mode(v void) ;
M. M Deloizy
75
dsP PIC30F2 2023
Les ports d’E/S
♦ Application 3 : Serrure codée Code de 3 à 6 chiffres ‘C’ : Recommencer ‘V’ : Valider LED indique : Code Ok (allumage 1s) Début saisie (2 clign.) Activation gâche : 1 sec On dispose de : void delay(unsigned ms)
M. Deloizy
76
dsPIC30F2023
Timers
IV Timers 3 timers 16 bits : • TIMER1 : Timer de type A • TIMER2 et TIMER3 constituent un Timer 32 bits, mais peuvent fonctionner séparément • TIMER2 : Timer de type B • TIMER3 : Timer de type C
M. Deloizy
77
dsPIC30F2023
Timers
TIMER1 IV.1.a
Caractéristiques :
• Peut fonctionner en : o Timer o Compteur synchrone o Compteur asynchrone. • Peut être validé par une entrée (Gate) • Prédiviseur programmable • Peut fonctionner en mode SLEEP ou IDLE • Effectue des cycles 0…(PR1), 0…(PR1), … où PR1 est le registre de période (Period Register 1) • Déclenche une interruption quand : o TMR1 est remis à 0 (suite au passage par PR1). o Front descendant de Gate (en mode Gate)
M. Deloizy
78
dsPIC30F2023
Timers
IV.1..b
Sché éma foncttionnel
M. M Deloizy
79
dsP PIC30F2 2023
Timers
IV.1.c
Modes
♦ Mode Timer Le timer s’incrémente au rythme de FCY (à chaque instruction). Quand le timer atteint la valeur contenue dans PR1, le timer est remis à 0 et le cycle se poursuit. En mode SLEEP, le timer s’arrête (plus d’horloge système). En mode Idle, le timer continue de fonctionner si TSIDL (T1CON) = 0. Il s’arrête si TSIDL=1. ♦ Mode compteur synchrone Le compteur s’incrémente à chaque front montant du signal appliqué sur T1CK. Ce signal est synchronisé sur l’horloge système. Quand le compteur atteint la valeur contenue dans PR1, le compteur est remis à 0 et le cycle se poursuit. En mode SLEEP, le compteur s’arrête (plus d’horloge système). En mode Idle, le compteur continue de fonctionner si TSIDL (T1CON) = 0. Il s’arrête si TSIDL=1. ♦ Mode compteur asynchrone Le compteur s’incrémente à chaque front montant du signal appliqué sur T1CK. M. Deloizy
80
dsPIC30F2023
Timers
Quand le compteur atteint la valeur contenue dans PR1, le compteur est remis à 0 et le cycle se poursuit. En mode SLEEP, le compteur continue de fonctionner, car il fonctionne indépendamment de l’horloge système. En mode Idle, le compteur continue de fonctionner si TSIDL (T1CON) = 0. Il s’arrête si TSIDL=1. ♦ Mode Gate Dans ce mode, l’entrée T1CK fonctionne en Gate et permet d’autoriser (T1CK=1) le comptage ou de l’arrêter (T1CK=0). IV.1.d
Registres
♦ TMR1 : Timer 1 Register Reset State : uuuu uuuu uuuu uuuu ♦ PR1 : Period Register 1 Reset State : 1111 1111 1111 1111
M. Deloizy
81
dsPIC30F2023
Timers
♦ T1CON : Type A Time Base Register R/W-0 TON
U-0 —
U-0 —
R/W-0 TGATE
b15
b7
bit 15 bit 14 bit 13 bit 12-7 bit 6
bit 5-4
bit 3 bit 2
bit 1 bit 0
R/W-0 TSIDL
U-0 —
R/W-0 R/W-0 TCKPS
U-0 —
U-0 —
U-0 —
U-0 —
U-0 —
R/W-0 TSYNC
R/W-0 TCS
U-0 —
TON: Timer On Control bit 1= Starts the timer 0= Stops the timer Unimplemented: Read as ‘0’ TSIDL: Stop in Idle Mode bit 1= Discontinue timer operation when device enters Idle mode 0= Continue timer operation in Idle mode Unimplemented: Read as ‘0’ TGATE: Timer Gated Time Accumulation Enable bit 1= Gated time accumulation enabled 0= Gated time accumulation disabled (TCS must be set to ‘0’ when TGATE = 1. Reads as ‘0’ if TCS = 1) TCKPS: Timer Input Clock Prescale Select bits 11 = 1:256 prescale value 10 = 1:64 prescale value 01 = 1:8 prescale value 00 = 1:1 prescale value Unimplemented: Read as ‘0’ TSYNC: Timer External Clock Input Synchronization Select bit When TCS = 1: 1= Synchronize external clock input 0= Do not synchronize external clock input When TCS = 0: This bit is ignored. Read as ‘0’. Timer1 uses the internal clock when TCS = 0. TCS: Timer Clock Source Select bit 1= External clock from pin T1CK 0= Internal clock (FOSC/4) Unimplemented: Read as ‘0’
M. Deloizy
82
b8
b0
dsPIC30F2023
Timers
IV.2
TIMER2 et TIMER3
IV.2.a
Caractéristiques du Timer 32 bits
• • • • • • • •
TMR2 : LSW, TMR3 : MSW Mode Timer Mode compteur synchrone Déclenchement événement convertisseur analogique numérique Mode Gate Prédiviseur programmable Fonctionnement possible pendant le mode IDLE Déclenche une interruption quand : o [TMR3 :TMR2] est remis à 0 (suite au passage par [PR3 :PR2]). o Front descendant de Gate (en mode Gate) • T3CON ignoré. Seuls T2CON et T2CK (entrée gate) sont utilisés. L’interruption est contrôlée par TIMER3 (T3IE, T3IF).
M. Deloizy
83
dsPIC30F2023
Timers
IV.2..b
Sché éma foncttionnel du u Timer 32 bits
M. M Deloizy
84
dsP PIC30F2 2023
Timers
♦ Mode Timer Le timer 32 bits s’incrémente au rythme de FCY (à chaque instruction). Quand le timer atteint la valeur contenue dans [PR3 :PR2], le timer est remis à 0 et le cycle se poursuit. Pour lire la valeur courante du timer, il faut lire d’abord TMR2 : Ceci a pour effet de transférer simultanément la valeur de TMR3 dans le registre TMR3HLD qui peut être lu ensuite. Pour écrire dans le timer 32 bits, on écrit d’abord dans TMR3HLD, puis dans TMR2. Cette dernière écriture transfert simultanément TMR3HLD dans TMR3. En mode SLEEP, le timer s’arrête (plus d’horloge système). En mode Idle, le timer continue de fonctionner si TSIDL (T2CON) = 0. Il s’arrête si TSIDL=1. ♦ Mode compteur (synchrone) Le compteur 32 bits s’incrémente à chaque front montant du signal appliqué sur T2CK. Ce signal est synchronisé sur l’horloge système. Quand le compteur atteint la valeur contenue dans [PR3 :PR2], le compteur est remis à 0 et le cycle se poursuit. En mode SLEEP, le compteur s’arrête (plus d’horloge système). En mode Idle, le compteur continue de fonctionner si TSIDL (T2CON) = 0. Il s’arrête si TSIDL=1. M. Deloizy 85 dsPIC30F2023
Timers
♦ Mode Gate Dans ce mode, l’entrée T2CK fonctionne en Gate et permet d’autoriser (T2CK=1) le comptage ou de l’arrêter (T2CK=0). ♦ Déclenchement événement convertisseur analogique Quand [TMR3 :TMR2]=[PR3 :PR2], un événement convertisseur analogique est déclenché par le timer 3. IV.2.c
TIMER 2 et TIMER 3 en modes 16 bits
Les Timers 2 et 3 fonctionnent comme le timer 1, sans le mode compteur asynchrone. Ils ne peuvent pas fonctionner en mode SLEEP. Le timer 2 dispose d’une synchronisation d’horloge en sortie du prédiviseur. Le timer 3 ne possède pas d’entrée externe (modes compteur et gate impossibles).
M. Deloizy
86
dsPIC30F2023
Timers
♦ Schéma S fonctionn nel du tim mer 2
M. M Deloizy
87
dsP PIC30F2 2023
Timers
♦ Schéma S fonctionn nel du tim mer 3
M. M Deloizy
88
dsP PIC30F2 2023
Timers
♦ TMR2 : Timer 2 Register Reset State : uuuu uuuu uuuu uuuu ♦ PR2 : Period Register 2 Reset State : 1111 1111 1111 1111 ♦ TMR3 : Timer 3 Register Reset State : uuuu uuuu uuuu uuuu ♦ TMR3HLD : Timer3 Holding Register
(For 32-bit timer operations only)
Reset State : uuuu uuuu uuuu uuuu ♦ PR3 : Period Register 3 Reset State : 1111 1111 1111 1111
M. Deloizy
89
dsPIC30F2023
Timers
♦ T2CON : Type B Time Base Register R/W-0 U-0 R/W-0 U-0 TON — TSIDL —
U-0 —
U-0 —
U-0 —
U-0 —
R/W-0 T32
U-0 —
R/W-0 TCS
U-0 —
b15
b7
U-0 —
bit 15
bit 14 bit 13 bit 12-7 bit 6
bit 5-4
bit 3 bit 2 bit 1 bit 0
R/W-0 TGATE
R/W-0 R/W-0 TCKPS
TON: Timer On bit When T32 = 1 (in 32-bit Timer mode): 1= Starts 32-bit TMR3:TMR2 timer pair 0= Stops 32-bit TMR3:TMR2 timer pair When T32 = 0 (in 16-bit Timer mode): 1= Starts 16-bit timer 0= Stops 16-bit timer Unimplemented: Read as ‘0’ TSIDL: Stop in Idle Mode bit 1= Discontinue timer operation when device enters Idle mode 0= Continue timer operation in Idle mode Unimplemented: Read as ‘0’ TGATE: Timer Gated Time Accumulation Enable bit 1= Timer gated time accumulation enabled 0= Timer gated time accumulation disabled (TCS must be set to logic ‘0’ when TGATE = 1) TCKPS: Timer Input Clock Prescale Select bits 11 = 1:256 prescale value 10 = 1:64 prescale value 01 = 1:8 prescale value 00 = 1:1 prescale value T32: 32-bit Timer Mode Select bits 1= TMR2 and TMR3 form a 32-bit timer 0= TMR2 and TMR3 form separate 16-bit timer Unimplemented: Read as ‘0’ TCS: Timer Clock Source Select bit 1= External clock from pin T2CK 0= Internal clock (FOSC/4) Unimplemented: Read as ‘0’
M. Deloizy
90
b8
b0
dsPIC30F2023
Timers
♦ T3CON: Type C Time Base Register R/W-0 TON
U-0 —
U-0 —
R/W-0 TGATE
b15
b7
bit 15 bit 14 bit 13 bit 12-7 bit 6
bit 5-4
bit 3-2 bit 1 bit 0
R/W-0 TSIDL
U-0 —
R/W-0 R/W-0 TCKPS
TON: Timer On bit 1= Starts 16-bit TMR3 0= Stops 16-bit TMR3 Unimplemented: Read as ‘0’ TSIDL: Stop in Idle Mode bit 1= Discontinue module operation when device enters Idle mode 0= Continue module operation in Idle mode Unimplemented: Read as ‘0’ TGATE: Timer Gated Time Accumulation Enable bit 1= This mode should not be used 0= Timer gated time accumulation disabled (Read as ‘0’ if TCS = 1) (TCS must be set to logic ‘0’ when TGATE = 1) TCKPS: Timer Input Clock Prescale Select bits 11 = 1:256 prescale value 10 = 1:64 prescale value 01 = 1:8 prescale value 00 = 1:1 prescale value Unimplemented: Read as ‘0’ TCS: Timer Clock Source Select bit 1= This mode should not be used 0= Internal clock (FOSC/4) Unimplemented: Read as ‘0’
M. Deloizy
91
U-0 —
U-0 —
U-0 —
U-0 —
U-0 —
U-0 —
R/W-0 TCS
U-0 —
b8
b0
dsPIC30F2023
Timers
♦ Applications
On suppose que le dsPIC fonctionne à 30 MIPS. Temporisations Programmer le timer 1 pour déclencher des interruptions toutes les ms Quelle est la durée maximale de comptage sans utiliser le prédiviseur ? En utilisant l’interruption précédente, écrire la fonction Delay : void Delay(unsigned ms). Peut-on créer une fonction de temporisation avec une résolution de 1 s ? Exemple : void Sleep(unsigned sec) Clavier Utiliser une interruption Timer pour gérer le clavier : • Mettre les caractères dans une FIFO lue par le programme principal Fonctions : int Getch(void) int KbHit(void) M. Deloizy
92
dsPIC30F2023
Convertisseur AN
V Convertisseur Numérique Analogique V.1 Caractéristiques • 12 entrées analogiques • 1 convertisseur 10 bits • Entrées unipolaires • 2000 k-échantillons/seconde (en 5V) (2 conversions/μs) • 4 échantillonneurs bloqueurs dédiés, 1 échantillonneur commun • Ne fonctionne pas en mode SLEEP • Nécessite le fonctionnement de la PLL • Plusieurs conversions peuvent être demandées simultanément : Séquentiellement en commençant par les canaux d’ordre inférieur. • Conversions par paires de canaux. • Conversion d’une paire en 24 cycles. • 16 sources de déclenchement pour chaque paire. • Buffer résultat (ADCBUFx) pour chaque canal, avec 2 formats. • Système d’indexation permettant la reconnaissance rapide de la source d’interruption.
M. Deloizy
93
dsPIC30F2023
Convertisseur AN
V.2 Schéma fonctionnel
M. Deloizy
94
dsPIC30F2023
Convertisseur AN
V.3 Registres de contrôle ♦ ADCON : A/D CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 ADON — ADSIDL —
U-0 —
b15
R/W-0 EIE
b7
bit 15 bit 14 bit 13 bit 12-11 bit 10 bit 9 bit 8 bit 7
bit 6
R/W-0 R/W-0 ORDER SEQSAMP
U-0 —
U-0 —
R/W-0 GSWTRG R/W-0
U-0 —
95
b8
R/W-1 R/W-1 ADCS
ADON: A/D Operating Mode bit 1 = A/D converter module is operating 0 = A/D converter is off Unimplemented: Read as ‘0’ ADSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode Unimplemented: Read as ‘0’ GSWTRG: Global Software Trigger bit When this bit is set by the user, it will trigger conversions if selected by the TRGSRC bits in the ADCPCx registers. This bit must be cleared by the user prior to initiating another global trigger (i.e., this bit is not auto-clearing). Unimplemented: Read as ‘0’ FORM: Data Output Format bit 1 = Fractional (DOUT = dddd dddd dd00 0000) 0 = Integer (DOUT = 0000 00dd dddd dddd) EIE: Early Interrupt Enable bit 1 = Interrupt is generated after first conversion is completed 0 = Interrupt is generated after second conversion is completed Note: This control bit can only be changed while ADC is disabled (ADON = 0). ORDER: Conversion Order bit 1 = Odd numbered analog input is converted first, followed by conversion of even numbered input 0 = Even numbered analog input is converted first, followed by conversion of odd numbered input Note: This control bit can only be changed while ADC is disabled (ADON = 0).
M. Deloizy
R/W-0 FORM
b0
dsPIC30F2023
Convertisseur AN bit 5
bit 4-3 bit 2-0
SEQSAMP: Sequential Sample Enable. 1 = Shared S&H is sampled at the start of the second conversion if ORDER = 0. If ORDER = 1, then the shared S&H is sampled at the start of the first conversion. 0 = Shared S&H is sampled at the same time the dedicated S&H is sampled if the shared S&H is not currently busy with an existing conversion process. If the shared S&H is busy at the time the dedicated S&H is sampled, then the shared S&H will sample at the start of the new conversion cycle Unimplemented: Read as ‘0’ ADCS: A/D Conversion Clock Divider Select bits If PLL is enabled (assume 15 MHz external clock as clock source): 111 = FADC/18 = 13.3 MHz @ 30 MIPS 110 = FADC/16 = 15.0 MHz @ 30 MIPS 101 = FADC/14 = 17.1 MHz @ 30 MIPS 100 = FADC/12 = 20.0 MHz @ 30 MIPS 011 = FADC/10 = 24.0 MHz @ 30 MIPS 010 = FADC/8 = 30.0 MHz @ 30 MIPS 001 = FADC/6 = Reserved, defaults to 30 MHz @ 30 MIPS 000 = FADC/4 = Reserved, defaults to 30 MHz @ 30 MIPS If PLL is disabled (assume 15 MHz external clock as clock source): 111 = FADC/18 = 0.83 MHz @ 7.5 MIPS 110 = FADC/16 = 0.93 MHz @ 7.5 MIPS 101 = FADC/14 = 1.07 MHz @ 7.5 MIPS 100 = FADC/12 = 1.25 MHz @ 7.5 MIPS 011 = FADC/10 = 1.5 MHz @ 7.5 MIPS 010 = FADC/8 = 1.87 MHz @ 7.5 MIPS 001 = FADC/6 = 2.5 MHz @ 7.5 MIPS 000 = FADC/4 = 3.75 MHz @ 7.5 MIPS
M. Deloizy
96
dsPIC30F2023
Convertisseur AN
♦ ADSTAT : A/D STATUS REGISTER U-0 U-0 U-0 U-0 — — — —
U-0 —
U-0 —
U-0 —
U-0 —
R/C-0 H-S P3RDY
R/C-0 H-S P2RDY
R/C-0 H-S P1RDY
R/C-0 H-S P0RDY
b15
b7
U-0
U-0
—
—
R/C-0 H-S P5RDY
R/C-0 H-S P4RDY
C = Clear in software H-S = Set by hardware bit 15-6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
b8
b0
Unimplemented: Read as ‘0’ P5RDY: Conversion Data for Pair #5 Ready bit Bit set when data is ready in buffer, cleared when a ‘0’ is written to this bit. P4RDY: Conversion Data for Pair #4 Ready bit Bit set when data is ready in buffer, cleared when a ‘0’ is written to this bit. P3RDY: Conversion Data for Pair #3 Ready bit Bit set when data is ready in buffer, cleared when a ‘0’ is written to this bit. P2RDY: Conversion Data for Pair #2 Ready bit Bit set when data is ready in buffer, cleared when a ‘0’ is written to this bit. P1RDY: Conversion Data for Pair #1 Ready bit Bit set when data is ready in buffer, cleared when a ‘0’ is written to this bit. P0RDY: Conversion Data for Pair #0 Ready bit Bit set when data is ready in buffer, cleared when a ‘0’ is written to this bit.
M. Deloizy
97
dsPIC30F2023
Convertisseur AN
♦ ADBASE : A/D BASE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADBASE
R/W-0
R/W-0
R/W-0
b15
R/W-0 b7
bit 15-1
bit 0
R/W-0
R/W-0 R/W-0 R/W-0 ADBASE
b8
R/W-0
R/W-0
U-0 —
b0
ADC Base Register: This register contains the base address of the user’s ADC Interrupt Service Routine jump table. This register, when read, contains the sum of the ADBASE register contents and the encoded value of the PxRDY Status bits. The encoder logic provides the bit number of the highest priority PxRDY bits where P0RDY is the highest priority, and P5RDY is lowest priority. Note: The encoding results are shifted left two bits so bits 1-0 of the result are always zero. Unimplemented: Read as ‘0’
M. Deloizy
98
dsPIC30F2023
Convertisseur AN
♦ ADPCFG : A/D PORT CONFIGURATION REGISTER U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — PCFG11 PCFG10
b15
R/W-0 PCFG7
b7
bit 15-12 bit 11-0
R/W-0 PCFG6
R/W-0 PCFG5
R/W-0 PCFG4
R/W-0 PCFG3
R/W-0 PCFG2
Unimplemented: Read as ‘0’ PCFG: A/D Port Configuration Control bits 1 = Port pin in Digital mode, port read input enabled, A/D input multiplexor connected to AVSS 0 = Port pin in Analog mode, port read input disabled, A/D samples pin voltage
M. Deloizy
99
R/W-0 PCFG9
R/W-0 PCFG8
R/W-0 PCFG1
R/W-0 PCFG0
b8
b0
dsPIC30F2023
Convertisseur AN
♦ ADCPCn : A/D CONVERT PAIR CONTROL REGISTER #n ADCPC0 : contrôle de la conversion des paires (AN0, AN1) et (AN2, AN3)
n=0 x=0
y=1
c=0
ADCPC1 : contrôle de la conversion des paires (AN4, AN5) et (AN6, AN7)
n=1 x=2
y=3
c=4
ADCPC2 : contrôle de la conversion des paires (AN8, AN9) et (AN10, AN11)
n=2
M. Deloizy
100
x=4
y=5
c=8
dsPIC30F2023
Convertisseur AN
R/W-0 R/W-0 R/W-0 R/W-0 IRQENy PENDy SWTRGy
R/W-0 R/W-0 R/W-0 TRGSRCy
R/W-0
R/W-0 R/W-0 R/W-0 R/W-0 IRQENx PENDx SWTRGx
R/W-0 R/W-0 R/W-0 TRGSRCx
R/W-0
b15
b7
bit 15 bit 14 bit 13 bit 12-8
b8
b0
IRQENy: Interrupt Request Enable y bit 1 = Enable IRQ generation when requested conversion of channels AN(c+3) and AN(c+2) is completed 0 = IRQ is not generated PENDy: Pending Conversion Status y bit 1 = Conversion of channels AN(c+3) and AN(c+2) is pending. Set when selected trigger is asserted 0 = Conversion is complete SWTRGy: Software Trigger y bit 1 = Start conversion of AN(c+3) and AN(c+2) (if selected in TRGSRC bits). If other conversions are in progress, then conversion will be performed when the conversion resources are available. This bit will be reset when the PEND bit is set. TRGSRy: Trigger y Source Selection bits Selects trigger source for conversion of analog channels AN(c+3) and AN(c+2). 00000 = No conversion enabled 00001 = Individual software trigger selected 00010 = Global software trigger selected (voir GSWTRG, ADCON) 00011 = PWM Special Event Trigger selected 00100 = PWM generator #1 trigger selected 00101 = PWM generator #2 trigger selected 00110 = PWM generator #3 trigger selected 00111 = PWM generator #4 trigger selected 01100 = Timer #1 period match 01101 = Timer #2 period match 01110 = PWM GEN #1 current-limit ADC trigger 01111 = PWM GEN #2 current-limit ADC trigger 10000 = PWM GEN #3 current-limit ADC trigger 10001 = PWM GEN #4 current-limit ADC trigger 10110 = PWM GEN #1 fault ADC trigger 10111 = PWM GEN #2 fault ADC trigger 11000 = PWM GEN #3 fault ADC trigger 11001 = PWM GEN #4 fault ADC trigger
M. Deloizy
101
dsPIC30F2023
Convertisseur AN
bit 7 bit 6 bit 5 bit 4-0
IRQENx: Interrupt Request Enable x bit 1 = Enable IRQ generation when requested conversion of channels AN(c+1) and AN(c+0) is completed 0 = IRQ is not generated PENDx: Pending Conversion Status x bit 1 = Conversion of channels AN(c+1) and AN(c+0) is pending. Set when selected trigger is asserted. 0 = Conversion is complete SWTRGx: Software Trigger x bit 1 = Start conversion of AN(c+1) and AN(c+0) (if selected by TRGSRC bits). If other conversions are in progress, then conversion will be performed when the conversion resources are available. This bit will be reset when the PEND bit is set TRGSRCx: Trigger x Source Selection bits Selects trigger source for conversion of analog channels AN(c+1) and AN(c+0). 00000 = No conversion enabled 00001 = Individual software trigger selected 00010 = Global software trigger selected 00011 = PWM Special Event Trigger selected 00100 = PWM generator #1 trigger selected 00101 = PWM generator #2 trigger selected 00110 = PWM generator #3 trigger selected 00111 = PWM generator #4 trigger selected 01100 = Timer #1 period match 01101 = Timer #2 period match 01110 = PWM GEN #1 current-limit ADC trigger 01111 = PWM GEN #2 current-limit ADC trigger 10000 = PWM GEN #3 current-limit ADC trigger 10001 = PWM GEN #4 current-limit ADC trigger 10110 = PWM GEN #1 fault ADC trigger 10111 = PWM GEN #2 fault ADC trigger 11000 = PWM GEN #3 fault ADC trigger 11001 = PWM GEN #4 fault ADC trigger
M. Deloizy
102
dsPIC30F2023
C Convertisseur AN
V.4 Séquenc ce de co onversion n (SE EQSAMP P = 0)
M. M Deloizy
103
dsP PIC30F2 2023
Convertisseur AN
V.5 Interruptions V.5.a
Interruption par groupe
• Interruption unique pour le module de conversion analogique. • On autorise les interruptions de chaque paire dans les registres ADCPCn.
• L’interruption est déclenchée quand la conversion est terminée : o Le bit PxRDY (dans ADSTAT) est mis à 1 (mis à 0 par programme) o ADIF (IFS0) est mis à 1 (mis à 0 avant PxRDY par programme) V.5.b
Interruption individuelle (par paire)
• Ces interruptions sont toujours autorisées par le module de conversion analogique • Autorisations par les flags ADCPxIE dans le registre IEC2 V.5.c
Interruption anticipée
• Une interruption peut être déclenchée dès la fin de conversion du premier canal de la paire grâce à EIE (ADCON). • Le bit PENDx des registres ADCPCn restent à 1 tant que les deux canaux ne sont pas convertis. • Quand la conversion de la paire est terminée, PENDx = 0 et PxRDY (dans ADSTAT) passe à 1.
M. Deloizy
104
dsPIC30F2023
Convertisseur AN
♦ Application Lire la tension analogique présente sur AN3. Quelle est la valeur numérique obtenue si la tension vaut : - 1 volt ? - 2,5 volts ? - 3 volts ? - 5 volts ? - 5,5 volts ? Quelle est la résolution obtenue ? On souhaite mesurer le courant circulant dans une résistance avec le montage suivant : • On mémorise 256 échantillons à 10 KHz • On utilise le timer 2. • R=100Ω. I exprimé en μA (1u/μA)
M. Deloizy
105
I
V0
AN0
R V1
AN1
dsPIC30F2023
Capture Compare
VI Modules Capture Compare
M. Deloizy
106
dsPIC30F2023
Capture Compare
VI.1
Module Capture
VI.1.a
Caractéristiques
• Détection de l’instant d’un événement • 1 entrée capture (IC1, multiplexée avec RD0. Doit être configurée en entrée.)
• Utilisation du Timer 2 ou du Timer 3 • Événement sur IC1 : o Front descendant o Front montant o Tous les 4 fronts montants o Tous les 16 fronts montants o Chaque front (montant ou descendant) • FIFO à 4 niveaux • Détection d’un overflow • Déclenchement d’interruptions • Possibilités de fonctionnement en modes IDLE ou SLEEP
M. Deloizy
107
dsPIC30F2023
Capture Comp pare
VI.1..b
Sché éma foncttionnel
M. M Deloizy
108
dsP PIC30F2 2023
Capture Compare
VI.1.c
Registres associés
♦ IC1BUF : Input 1 Capture Register Reset State : uuuu uuuu uuuu uuuu
M. Deloizy
109
dsPIC30F2023
Capture Compare
♦ IC1CON: Input Capture 1 Control Register U-0 U-0 R/W-0 U-0 U-0 — — ICSIDL — —
b15
R/W-0 ICTMR
b7
bit 15-14 bit 13 bit 12-8 bit 7
bit 6-5
bit 4 bit 3 bit 2-0
R/W-0 R/W-0 ICI
R-0, HC ICOV
R-0, HC ICBNE
U-0 — R/W-0
U-0 —
U-0 —
b8
R/W-0 R/W-0 ICM
b0
Unimplemented: Read as ‘0’ ICSIDL: Input Capture Module Stop in Idle Control bit 1= Input capture module will halt in CPU Idle mode 0= Input capture module will continue to operate in CPU Idle mode Unimplemented: Read as ‘0’ ICTMR: Input Capture Timer Select bits 1= TMR2 contents are captured on capture event 0= TMR3 contents are captured on capture event Note: Timer selections may vary. Refer to the device data sheet for details. ICI: Select Number of Captures per Interrupt bits 11= Interrupt on every fourth capture event 10= Interrupt on every third capture event 01= Interrupt on every second capture event 00= Interrupt on every capture event ICOV: Input Capture Overflow Status Flag (Read Only) bit 1= Input capture overflow occurred 0= No input capture overflow occurred ICBNE: Input Capture Buffer Empty Status (Read Only) bit 1= Input capture buffer is not empty, at least one more capture value can be read 0= Input capture buffer is empty ICM: Input Capture Mode Select bits 111 = Input Capture functions as interrupt pin only, when device is in Sleep or Idle mode (Rising edge detect only, all other control bits are not applicable.) 110 = Unused (module disabled) 101 = Capture mode, every 16th rising edge 100 = Capture mode, every 4th rising edge 011 = Capture mode, every rising edge 010 = Capture mode, every falling edge 001 = Capture mode, every edge (rising and falling) (ICI does not control interrupt generation for this mode.) 000 = Input capture module turned off
M. Deloizy
110
dsPIC30F2023
Capture Compare
VI.2
Module Compare
VI.2.a
Caractéristiques
• • • •
2 sorties Compare (OC1 et OC2, doivent être configurées en sortie) Déclenchement d’un événement à un instant prédéterminé. Utilisation de Timer 2 ou Timer 3 Fonctions possibles : o OCx mis à 0 o OCx mis à 1 o OCx inversé (toggle) o Génération PWM (avec possibilité entrée défaut OCFLTA) o Génération d’impulsions simples ou continues • Déclenchement possible d’interruptions
M. Deloizy
111
dsPIC30F2023
Capture Comp pare
VI.2..b
Sché éma foncttionnel
M. M Deloizy
112
dsP PIC30F2 2023
Capture Compare
VI.2.c
Mode comparaison simple
• Mise à 0, 1 ou inversion de la sortie quand la valeur du timer atteint celle contenue dans le registre OCxR • Si le timer effectue repasse par 0 avant d’atteindre OCxR, la sortie n’est pas modifiée • Le niveau de la sortie est initialisé à l'état 1 pour une mise à 0, et à l’état 0 pour une mise à 1, lors de la programmation de ces modes. • Une interruption est déclenchée à la suite de la comparaison.
M. Deloizy
113
dsPIC30F2023
Capture Compare
VI.2.d
Mode comparaison double
Permet de générer une impulsion ou des impulsions continues. • L’impulsion débute à la valeur contenue dans OCxR. Elle se termine à la valeur contenue dans OCxRS. Le registre de période du timer doit avoir une valeur supérieure à OCxRS. • Le niveau initial de la sortie est 0, dès la programmation du mode (OCM = 100 ou 101) • En mode impulsion simple (OCM = 100), une nouvelle impulsion peut être générée en reprogrammant le mode (OCM = 100). • En mode impulsion continue, l’impulsion est générée à chaque période définie par le timer. • Une interruption est déclenchée à la fin de l’impulsion.
M. Deloizy
114
dsPIC30F2023
C Capture Comp pare
VI.2..e
Mode e PWM
• La pério ode de la a PWM (fréquen ( nce portteuse) esst fixée par le re egistre de d période e du timer. port cycllique estt conten nu dans OCxRS • Le rapp • OCxR devient d e en lectur re seule e • Fonctio onnemen nt :
c Timerr is clearred and new n duty y cycle va alue is loa aded from m OCxRS S into OC CxR. d Timerr value eequals vallue in the OCxR register, r OCx Pin is driven n low. e Timerr overfloow, valuee from OC CxRS is loaded l in nto OCxR R, OCx pin n driven high. nterrupt flag is assserted. TyIF in
M. M Deloizy
115
dsP PIC30F2 2023
Capture Compare
• En mode PWM avec entrée défaut (fault), la patte OCFLTA (RA9) est utilisée. Si cette patte passe au niveau 0, la sortie PWM (OC1 ou OC2) passe en haute impédance o Tant que le défaut subsiste o Tant que le mode n’est pas reprogrammé
M. Deloizy
116
dsPIC30F2023
Capture Compare
VI.2.f
Registres
♦ OCxCON: Output Compare x Control Register (OC1CON, OC2CON) U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 — — OCSIDL — — — — b15
b7
U-0 —
bit 15-14 bit 13 bit 12-5 bit 4
bit 3
bit 2-0
U-0 —
U-0 —
R-0, HC R/W-0 OCFLT OCTSEL
R/W-0
117
b8
R/W-0 R/W-0 OCM
Unimplemented: Read as ‘0’ OCSIDL: Stop Output Compare in Idle Mode Control bit 1= Output compare x will halt in CPU Idle mode 0= Output compare x will continue to operate in CPU Idle mode Unimplemented: Read as ‘0’ OCFLT: PWM Fault Condition Status bit 1= PWM Fault condition has occurred (cleared in HW only) 0= No PWM Fault condition has occurred (This bit is only used when OCM = 111.) OCTSEL: Output Compare Timer Select bit 1= Timer3 is the clock source for compare x 0= Timer2 is the clock source for compare x Note: Refer to the device data sheet for specific time bases available to the output compare module. OCM: Output Compare Mode Select bits 111 = PWM mode on OCx, Fault pin enabled 110 = PWM mode on OCx, Fault pin disabled 101 = Initialize OCx pin low, generate continuous output pulses on OCx pin 100 = Initialize OCx pin low, generate single output pulse on OCx pin 011 = Compare event toggles OCx pin 010 = Initialize OCx pin high, compare event forces OCx pin low 001 = Initialize OCx pin low, compare event forces OCx pin high 000 = Output compare channel is disabled
M. Deloizy
U-0 —
b0
dsPIC30F2023
Capture Compare
♦ OCxRS : Output Compare x Slave Register (OC1RS, OC2RS) Reset State : 0000 0000 0000 0000 ♦ OCxR : Output Compare x Master Register (OC1R, OC2R) Reset State : 0000 0000 0000 0000
M. Deloizy
118
dsPIC30F2023
Capture Compare
♦ Application Faire la mesure de la période d’un signal rectangulaire pour un signal dont la fréquence peut varier : • Entre 10 et 20 KHz. • Entre 10 Hz et 2 KHz
T
Mesurer (en %) le rapport cyclique défini par : Générer une impulsion de 100μs toutes les ms Utiliser la sortie PWM pour générer une tension continue de : • 1 volt • 3 volts R On utilise le filtre suivant : R=10kΩ - C=10μF C
M. Deloizy
119
dsPIC30F2023
PWM
VII Module PWM VII.1
Caractéristiques
La PLL doit être active (voir FNOSC dans FOSCSEL) pour que le module PWM fonctionne. • • • • • •
4 Générateurs PWM (MLI) avec 8 entrées/sorties 4 bases de temps indépendantes Résolution du rapport cyclique de 1.1 ns @ 30 MIPS Résolution des temps morts de 4.2 ns @ 30 MIPS Résolution de phase de 4.2 ns @ 30 MIPS Résolution de fréquence de 8.4 ns @ 30 MIPS
M. Deloizy
120
dsPIC30F2023
PWM
• Modes PWM supportés : o PWM standard alignée sur fronts o PWM complémentaire o PWM Push-Pull o PWM Multi-Phase o PWM à phase variable o PWM à temps d’allumage ou d’extinction constants (réinitialisation par courant) o PWM à limitation de courant o PWM à bases de temps indépendantes • Changement dynamique de la fréquence, du rapport cyclique et de la phase • Contrôle forcé des sorties • Entrées défaut et limitation de courant indépendantes • Comparateur d’événement spécial pour commander d’autres périphériques • Chaque générateur PWM a un comparateur pour déclencher des conversions analogiques.
M. Deloizy
121
dsPIC30F2023
PWM
VII.2 2
Sché éma fonc ctionnel
M. M Deloizy
122
dsP PIC30F2 2023
PWM
VII.3
Fonctionnalités
VII.3.a
PWM alignée sur fronts
• PWM standard • Un compteur compte de 0 à la valeur de la période Quand le compteur a une valeur inférieure à celle contenue dans le registre contenant le rapport cyclique, la sortie PWM vaut 1, et 0 sinon.
M. Deloizy
123
dsPIC30F2023
PWM
VII.3.b PWM complémentaire
• Fonctionnement identique à la PWM alignée sur fronts
• Génération des commandes de bras : o Commande du transistor du haut (PWMH) o Commande du transistor du bas (PWML) • Insertion des temps morts • Exemple d’utilisation :
M. Deloizy
124
dsPIC30F2023
PWM
VII.3.c
PWM push-pull
• Fonctionnement identique à la PWM alignée sur fronts adapté à la commande par transformateurs : o Évite composante continue dans les bobinages • Le signal PWM est généré alternativement sur PWMH et PWML, avec le même rapport cyclique. • Exemple d’utilisation :
M. Deloizy
125
dsPIC30F2023
PWM
VII.3.d PWM multiphase
• Utilise les valeurs de déphasage contenue dans les registres de phases (PHASEx) • Exemple d’utilisation :
M. Deloizy
126
dsPIC30F2023
PWM
VII.3.e
PWM à phase variable
• Contrôle de la différence de phase entre 2 signaux PWM • Rapport cyclique constant (souvent ½) • Mise à jour du déphasage quand les sorties sont à0 • Possibilité de générer les sorties complémentaires
M. Deloizy
127
dsPIC30F2023
PWM
VII.3.f
PWM à limitation de courant
• PWM à fréquence constante • La sortie PWM est forcée à la valeur indiquée dans FLTDAT de IOCONx jusqu’à la fin de la période.
M. Deloizy
128
dsPIC30F2023
PWM
VII.3.g PWM à Reset par courant
• PWM à fréquence variable • La base de temps du signal PWM est remise à 0 par un signal extérieur avant la période programmée ♦ PWM à temps d’extinction constant • Utilisation de la sortie complémentaire (PWML)
M. Deloizy
129
dsPIC30F2023
PWM
♦ PWM à temps d’allumage constant • Utilisation de la sortie haute (PWMH) • Exemple d’utilisation :
M. Deloizy
130
dsPIC30F2023
PWM
VII.3.h PWM à bases de temps indépendantes
• Permet le contrôle de dispositifs différents, fonctionnant à des fréquences de hachage différentes • Les signaux PWM sont indépendants
M. Deloizy
131
dsPIC30F2023
PWM
VII.4 Base de temps primaire • Base de temps (PTMR) pour la totalité du module PWM • Non accessible par programme • Cadencé à 120 MHz @ 30 MIPS. • Indique quand il y a égalité entre PTMR et PTPER. La fréquence correspondante est donnée par : 4· 15: 3 1 • Chaque générateur PWM dispose de sa base de temps propre • Gère o la mise à jour des registres de rapport cyclique et de phase o les déclenchements d’événements spéciaux o les interruptions liées au timer • Peut être remis à 0 par un signal externe défini par les bits SYNCSRC dans PTCON, si autorisé par SYNCEN (PTCON). • Possibilité de synchronisation sur la base de temps d’un autre dsPIC de même type.
M. Deloizy
132
dsPIC30F2023
PWM
VII.5 Compteur de cycles (Roll counter) du compteur primaire • Compteur 6 bits non accessible par programme • Compte les cycles du timer primaire • Permet d’indiquer l’instant du déclenchement de l’événement à destination du convertisseur analogique, à partir des bits TRGSTRT dans les registres TRGCONx.
M. Deloizy
133
dsPIC30F2023
PWM
VII.6 Bases de temps individuelles Le bit ITB des registres PWMCONx permet de fonctionner à la fréquence donnée par le compteur primaire (PTPER) ou à partir du registre de phase. Dans ce cas, la fréquence de la PWM est donnée par : 4· 1 VII.7 Rapport cyclique • Chaque générateur PWM possède un registre de rapport cyclique (PDCx) ou peut utiliser le registre de rapport cyclique commun (MDC). • La sortie est active quand la valeur du compteur est inférieure ou égale aux 13 bits de poids fort du registre de rapport cyclique. • La durée du niveau actif est donnée par : ·
• La résolution de la PWM est de 8.4 ns @30MIPS • Le rapport cyclique (PDCx ou MDC) doit être compris entre 0x0008 et 0xFFEF : o 0x0000 mettra 0 en sortie o 0xFFFF mettra 1 en sortie M. Deloizy
134
dsPIC30F2023
PWM
VII.8 Temps morts • Des temps morts peuvent être insérés entre les sorties PWM complémentaires. • Les temps morts peuvent être négatifs. • La génération des temps morts est activée par les bits DTC des registres PWMCONx. • DTRx spécifie le temps mort appliqué au signal PWMH et ALTDTRx celui appliqué au signal PWML. • La durée du temps mort est donnée par : ·
VII.9 Déclenchement d’événement spécial Synchronisation de conversions analogiques sur la PWM VII.9.a
Commun
• Basé sur la base de temps primaire • L’événement spécial est toujours généré, mais pas forcément utilisé par le module analogique. • Géré par les bits SEVTPS de PTCON et le registre SEVTCMP • Quand PTRM atteint SEVTCMP, un événement spécial est déclenché. • Un post-diviseur d’événement spécial peut être programmé par SEVTPS de PTCON M. Deloizy 135 dsPIC30F2023
PWM
VII.9.b Individuel
• Déclenché tant que la valeur de TRIGx est inférieure à la base de temps locale • Génère une interruption si le bit TRGIEN de PWMCONx est à 1. • Un post-diviseur est programmable par TRGDIV de TRGCONx
M. Deloizy
136
dsPIC30F2023
PWM
VII.10 Défauts et sur-courants • Les registres IOCONx et FCLCONx permettent de gérer les défauts. • Chaque générateur PWM peut sélectionner une des 12 pattes de défaut ou sur-courants, selon les bits FLTSRC de PWMCONx. • Les bits FLTPOL des registres FCLCONx permettent de fixer la polarité des défauts. • Lorsqu’un défaut est détecté, on peut forcer l’état de la sortie PWM selon les bits FLTDAT de IOCONx. • Deux modes de fonctionnement existent lors de l’apparition du défaut : o Mode verrouillé : La sortie PWM est figée dans l’état indiqué par FLTDAT tant que le défaut subsiste et que les flags d’interruption ne sont pas remis à 0. o Mode cycle par cycle : PWMH est mis à 0, PWML est mis à 1 tant que le défaut subsiste.
M. Deloizy
137
dsPIC30F2023
PWM
VII.11 Interruptions Les interruptions peuvent être déclenchées à partir des bases de temps ou des lignes de défaut ou de sur-courants : • Base de temps primaire, lors du déclenchement de l’événement spécial, si autorisé par le bit SEIEN de PTCON. • Bases de temps individuelles, lors du déclenchement de l’événement spécial, si autorisé par le bit TRGIEN de PWMCONx. • Les lignes FLTx (quand=1) peuvent déclencher des interruptions si autorisé par les bits FLTIENx de PWMCONx • Les sur-courants peuvent être détectés avec le module comparateur et peuvent déclencher des interruptions si autorisé par les bits CLIEN de PWMCONx
M. Deloizy
138
dsPIC30F2023
PWM
VII.12 Registres ♦ PTCON: PWM TIME BASE CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTEN — PTSIDL SESTAT SEIEN EIPU SYNCPOL SYNCOEN
b15
b8
R/W-0 R/W-0 R/W-0 R/W-0 SYNCEN SYNCSRC b7
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7
R/W-0
PTEN: PWM Module Enable bit 1 = PWM module is enabled 0 = PWM module is disabled Unimplemented: Read as ‘0’ PTSIDL: PWM Time Base Stop in Idle Mode bit 1 = PWM time base halts in CPU Idle mode 0 = PWM time base runs in CPU Idle mode SESTAT: Special Event Interrupt Status bit 1 = Special Event Interrupt is pending 0 = Special Event Interrupt is not pending SEIEN: Special Event Interrupt Enable bit 1 = Special Event Interrupt is enabled 0 = Special Event Interrupt is disabled EIPU: Enable Immediate Period Updates bit 1 = Active Period register is updated immediately 0 = Active Period register updates occur on PWM cycle boundaries SYNCPOL: Synchronize Input Polarity bit 1 = SYNCIN polarity is inverted (low active) 0 = SYNCIN is high active SYNCOEN: Primary Time Base Sync Enable bit 1 = SYNCO output is enabled 0 = SYNCO output is disabled SYNCEN: External Time Base Synchronization Enable bit 1 = External synchronization of primary time base is enabled 0 = External synchronization of primary time base is disabled
M. Deloizy
139
R/W-0 R/W-0 SEVTPS
R/W-0 b0
dsPIC30F2023
PWM bit 6-4
bit 3-0
SYNCSRC: Sync Source Selection bits 000 = SYNCI 001 = Reserved . . 111 = Reserved SEVTPS: PWM Special Event Trigger Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale | | | | 1111 = 1:16 Postscale
M. Deloizy
140
dsPIC30F2023
PWM
♦ PTPER: PRIMARY TIME BASE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
R/W-0
R/W-0
R/W-0
b15
R/W-0 b7
bit 15-3 bit 2-0
R/W-0
R/W-0
R/W-0
R/W-0
Primary Time Base (PTMR) Period Value bits Unimplemented: Read as ‘0’
M. Deloizy
141
b8
U-0 —
U-0 —
U-0 —
b0
dsPIC30F2023
PWM
♦ SEVTCMP: PWM SPECIAL EVENT COMPARE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SEVTCMP
R/W-0
R/W-0
b15
R/W-0 R/W-0 SEVTCMP b7
bit 15-3 bit 2-0
R/W-0 R/W-0
Special Event Compare Count Value bit Unimplemented: Read as ‘0’
M. Deloizy
142
R/W-0
U-0 —
b8
U-0 —
U-0 —
b0
dsPIC30F2023
PWM
♦ MDC: PWM MASTER DUTY CYCLE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MDC
R/W-0
R/W-0
b15
R/W-0 b15
bit 15-0
R/W-0
R/W-0
R/W-0 R/W-0 MDC
Master PWM Duty Cycle Value bits The minimum value for this register is 0x0008 and the maximum value is 0xFFEF.
M. Deloizy
143
R/W-0 b8
R/W-0
R/W-0
R/W-0 b8
dsPIC30F2023
PWM
♦ PWMCONx: PWM CONTROL REGISTER HS/HC-0 HS/HC- HS/HC-0 R/W-0 R/W-0 R/W-0 R/W-0 0 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN ITB b15
R/W-0 R/W-0 DTC
b7
bit 15
bit 14
bit 13
bit 12 bit 11 bit 10 bit 9
U-0 —
U-0 —
U-0 —
U-0 —
R/W-0 XPRES
FLTSTAT: Fault Interrupt Status 1 = Fault Interrupt is pending 0 = No Fault Interrupt is pending This bit is cleared by setting FLTIEN = 0. Note: Software must clear the interrupt status here, and the corresponding IFS bit in Interrupt Controller. CLSTAT: Current-Limit Interrupt Status bit 1 = Current-limit interrupt is pending 0 = No current-limit interrupt is pending This bit is cleared by setting CLIEN = 0. Note: Software must clear the interrupt status here, and the corresponding IFS bit in Interrupt Controller. TRGSTAT: Trigger Interrupt Status bit 1 = Trigger interrupt is pending 0 = No trigger interrupt is pending This bit is cleared by setting TRGIEN = 0. FLTIEN: Fault Interrupt Enable bit 1 = Fault interrupt enabled 0 = Fault interrupt disabled and FLTSTAT bit is cleared CLIEN: Current-Limit Interrupt Enable bit 1 = Current-limit interrupt enabled 0 = Current-limit interrupt disabled and CLSTAT bit is cleared TRGIEN: Trigger Interrupt Enable bit 1 = A trigger event generates an interrupt request 0 = Trigger event interrupts are disabled and TRGSTAT bit is cleared ITB: Independent Time Base Mode bit 1 = Phasex register provides time base period for this PWM generator 0 = Primary time base provides timing for this PWM generator
M. Deloizy
144
R/W-0 MDCS
b8
R/W-0 IUE
b0
dsPIC30F2023
PWM bit 8 bit 7-6
bit 5-2 bit 1 bit 0
MDCS: Master Duty Cycle Register Select bit 1 = MDC register provides duty cycle information for this PWM generator 0 = PDCx register provides duty cycle information for this PWM generator DTC: Dead-time Control bits 00 = Positive dead time actively applied for all output modes 01 = Negative dead time actively applied for all output modes 10 = Dead-time function is disabled 11 = Reserved Unimplemented: Read as ‘0’ XPRES: External PWM Reset Control bit 1 = Current-limit source resets time base for this PWM generator if it is in independent time base mode 0 = External pins do not affect PWM time base IUE: Immediate Update Enable bit 1 = Updates to the active PDC registers are immediate 0 = Updates to the active PDC registers are synchronized to the PWM time base
M. Deloizy
145
dsPIC30F2023
PWM
♦ PDCx: PWM GENERATOR DUTY CYCLE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PDCx
R/W-0
b15
R/W-0 b7
bit 15-0
R/W-0
R/W-0
R/W-0 R/W-0 PDCx
PWM Generator #x Duty Cycle Value bits The minimum value for this register is 0x0008 and the maximum value is 0xFFEF.
M. Deloizy
146
R/W-0
R/W-0 b8
R/W-0
R/W-0 b0
dsPIC30F2023
PWM
♦ PHASEx: PWM PHASE-SHIFT REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PHASEx
R/W-0
R/W-0
R/W-0
b15
R/W-0 b7
bit 15-2 bit 1-0
R/W-0
R/W-0 R/W-0 PHASEx
R/W-0
b8
R/W-0
PHASEx: PWM Phase-Shift Value or Independent Time Base Period for this PWM Generator bits Note: If used as an independent time base, bits are not used. Unimplemented: Read as ‘0’
M. Deloizy
147
U-0 —
U-0 —
b0
dsPIC30F2023
PWM
♦ DTRx: PWM DEAD-TIME REGISTER U-0 U-0 R/W-0 R/W-0 — —
b15
R/W-0 b7
bit 15-14 bit 13-2 bit 1-0
R/W-0
R/W-0 R/W-0 DTRx
R/W-0 R/W-0 DTRx R/W-0
Unimplemented: Read as ‘0’ DTRx: Unsigned 12-bit Dead-Time Value bits for PWMx Dead-Time Unit bits Unimplemented: Read as ‘0’
M. Deloizy
148
R/W-0
R/W-0
R/W-0 b8
U-0 —
U-0 —
b0
dsPIC30F2023
PWM
♦ ALTDTRx: PWM ALTERNATE DEAD-TIME REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — ALTDTRx
R/W-0
R/W-0
b15
R/W-0 b7
bit 15-14 bit 13-2 bit 1-0
R/W-0
R/W-0 R/W-0 ALTDTRx
R/W-0
R/W-0
Unimplemented: Read as ‘0’ ALTDTRx: Unsigned 12-bit Dead-Time Value bits for PWMx Dead-Time Unit bits Unimplemented: Read as ‘0’
M. Deloizy
149
b8
U-0 —
U-0 —
b0
dsPIC30F2023
PWM
♦ TRGCONx: PWM TRIGGER CONTROL REGISTER R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 TRGDIV — — —
b15
b7
U-0 —
bit 15-13
bit 12-6 bit 5-0
U-0 —
R/W-0
R/W-0
R/W-0 R/W-0 TRGSTRT
TRGDIV: Trigger Output Divider bits 000 = Trigger output for every trigger event 001 = Trigger output for every 2nd trigger event 010 = Trigger output for every 3rd trigger event 011 = Trigger output for every 4th trigger event 100 = Trigger output for every 5th trigger event 101 = Trigger output for every 6th trigger event 110 = Trigger output for every 7th trigger event 111 = Trigger output for every 8th trigger event Unimplemented: Read as ‘0’ TRGSTRT: Trigger Postscaler Start Enable Select bits This value specifies the ROLL counter value needed for a match that will then enable the trigger postscaler logic to begin counting trigger events.
M. Deloizy
150
U-0 —
U-0 —
R/W-0
R/W-0
b8
b0
dsPIC30F2023
PWM
♦ IOCONx: PWM I/O CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PENH PENL POLH POLL PMOD OVRENH OVRENL
b15
b8
R/W-0 R/W-0 OVRDAT
b7
bit 15 bit 14 bit 13 bit 12 bit 11-10
bit 9 bit 8 bit 7-6
R/W-0 R/W-0 FLTDAT
R/W-0 R/W-0 CLDAT
PENH: PWMH Output Pin Ownership bit 1 = PWM module controls PWMxH pin 0 = GPIO module controls PWMxH pin PENL: PWML Output Pin Ownership bit 1 = PWM module controls PWMxL pin 0 = GPIO module controls PWMxL pin POLH: PWMH Output Pin Polarity bit 1 = PWMxH pin is low active 0 = PWMxH pin is high active POLL: PWML Output Pin Polarity bit 1 = PWMxL pin is low active 0 = PWMxL pin is high active PMOD: PWM #x I/O Pin Mode bits 00 = PWM I/O pin pair is in the Complementary Output mode 01 = PWM I/O pin pair is in the Independent Output mode 10 = PWM I/O pin pair is in the Push-Pull Output mode 11 = Reserved OVRENH: Override Enable for PWMxH Pin bit 1 = OVRDAT provides data for output on PWMxH pin 0 = PWM generator provides data for PWMxH pin OVRENL: Override Enable for PWMxL Pin bit 1 = OVRDAT provides data for output on PWMxL pin 0 = PWM generator provides data for PWMxL pin OVRDAT: Data for PWMxH,L Pins if Override is Enabled bits If OVERENH = 1 then OVRDAT provides data for PWMxH If OVERENL = 1 then OVRDAT provides data for PWMxL
M. Deloizy
151
U-0 —
R/W-0 OSYNC
b0
dsPIC30F2023
PWM bit 5-4 bit 3-2 bit 1 bit 0
FLTDAT: Data for PWMxH,L Pins if FLTMODE is Enabled bits If Fault active, then FLTDAT provides data for PWMxH If Fault active, then FLTDAT provides data for PWMxL CLDAT: Data for PWMxH,L Pins if CLMODE is Enabled bits If current limit active, then CLDAT provides data for PWMxH If current limit active, then CLDAT provides data for PWMxL Unimplemented: Read as ‘0’ OSYNC: Output Override Synchronization bit 1 = Output overrides via the OVRDAT bits are synchronized to the PWM time bas 0 = Output overrides via the OVDDAT bits occur on next clock boundary
M. Deloizy
152
dsPIC30F2023
PWM
♦ FCLCONx: PWM FAULT CURRENT-LIMIT CONTROL REGISTER U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — CLSRC
b15
R/W-0 R/W-0 CLMODE b7
bit 15-13 bit 12-9
bit 8 bit 7 bit 6-3
R/W-0 R/W-0 FLTSRC
R/W-0
R/W-0 FLTPOL
Unimplemented: Read as ‘0’ CLSRC: Current-Limit Control Signal Source Select for PWM #X Generator bits 0000 = Analog Comparator #1 0001 = Analog Comparator #2 0010 = Analog Comparator #3 0011 = Analog Comparator #4 0100 = Reserved 0101 = Reserved 0110 = Reserved 0111 = Reserved 1000 = Shared Fault #1 (SFLT1) 1001 = Shared Fault #2 (SFLT2) 1020 = Shared Fault #3 (SFLT3) 1011 = Shared Fault #4 (SFLT4) 1100 = Reserved 1101 = Independent Fault #2 (IFLT2) 1110 = Reserved 1111 = Independent Fault #4 (IFLT4) CLPOL: Current-Limit Polarity for PWM Generator #X bit 1 = The selected current-limit source is low active 0 = The selected current-limit source is high active CLMODE: Current-Limit Mode Enable for PWM Generator #X bit 1= Current-limit function is enabled 0= Current-limit function is disabled FLTSRC: Fault Control Signal Source Select for PWM Generator #X bits 0000 = Analog Comparator #1 0001 = Analog Comparator #2 0010 = Analog Comparator #3
M. Deloizy
153
R/W-0 CLPOL
b8
R/W-0 R/W-0 FLTMOD
b0
dsPIC30F2023
PWM
bit 2 bit 1-0
0011 = Analog Comparator #4 0100 = Reserved 0101 = Reserved 0110 = Reserved 0111 = Reserved 1000 = Shared Fault #1 (SFLT1) 1001 = Shared Fault #2 (SFLT2) 1020 = Shared Fault #3 (SFLT3) 1011 = Shared Fault #4 (SFLT4) 1100 = Reserved 1101 = Independent Fault #2 (IFLT2) 1110 = Reserved 1111 = Independent Fault #4 (IFLT4) FLTPOL: Fault Polarity for PWM Generator #X bit 1 = The selected Fault source is low active 0 = The selected Fault source is high active FLTMOD: Fault Mode for PWM Generator #x bits 00 = The selected Fault source forces PWMxH, PWMxL pins to FLTDAT values (latched condition) 01 = The selected Fault source forces PWMxH, PWMxL pins to FLTDAT values (cycle) 10 = Reserved 11 = Fault input is disabled
M. Deloizy
154
dsPIC30F2023
PWM
♦ TRIGx: PWM TRIGGER COMPARE VALUE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TRGCMP
R/W-0
R/W-0
b15
R/W-0 b7
bit 15-3 bit 2-0
R/W-0 R/W-0 R/W-0 TRGCMP
R/W-0
U-0 —
b8
U-0 —
U-0 —
TRGCMP: Trigger Control Value bits Register contains the compare value for PWMx time base for generating a trigger to the ADC modu for initiating a sample and conversion process, or generating a trigger interrupt. Unimplemented: Read as ‘0’ The minimum usable value for this register is 0x0008 A value of 0x0000 does not produce a trigger. If the TRIGx value is being calculated based on duty cycle value, you must ensure that a minimum TRIGx value is written into the register at all times.
M. Deloizy
155
b0
dsPIC30F2023
PWM
♦ LEBCONx: LEADING EDGE BLANKING CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PHR PHF PLR PLF FLTLEBEN CLLEBEN LEB
b15
b8
R/W-0 b7
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9-3 bit 2-0
R/W-0
R/W-0 R/W-0 LEB
R/W-0
U-0 —
PHR: PWMH Rising Edge Trigger Enable bit 1 = Rising edge of PWMH will trigger LEB counter 0 = LEB ignores rising edge of PWMH PHL: PWMH Falling Edge Trigger Enable bit 1 = Falling edge of PWMH will trigger LEB counter 0 = LEB ignores falling edge of PWMH PLR: PWML Rising Edge Trigger Enable bit 1 = Rising edge of PWML will trigger LEB counter 0 = LEB ignores rising edge of PWML PLF: PWML Falling Edge Trigger Enable bit 1 = Falling edge of PWML will trigger LEB counter 0 = LEB ignores falling edge of PWML FLTLEBEN: Fault Input Leading Edge Blanking Enable bit 1 = Leading Edge Blanking is applied to selected Fault Input 0 = Leading Edge Blanking is not applied to selected Fault Input CLLEBEN: Current-Limit Leading Edge Blanking Enable bit 1 = Leading Edge Blanking is applied to selected Current-Limit Input 0 = Leading Edge Blanking is not applied to selected Current-Limit Input LEB: Leading Edge Blanking for Current-Limit and Fault Inputs bits Value is 8 nsec increments Unimplemented: Read as ‘0’
M. Deloizy
156
U-0 —
U-0 —
b0
dsPIC30F2023
I²C
VIII Module I²C VIII.1
Registres
♦ I2CCON: I2C™ Control Register R/W-0 U-0 R/W-0 R/W-1 R/W-0 HC I2CEN — I2CSIDL SCLREL IPMIEN b15
R/W-0
R/W-0
GCEN
STREN
b7
bit 15 bit 14 bit 13 bit 12
bit 11
R/W-0
R/W-0 HC ACKDT ACKEN
R/W-0 HC RCEN
R/W-0
R/W-0
R/W-0
A10M
DISSLW
SMEN
R/W-0 HC PEN
R/W-0 HC RSEN
R/W-0 HC SEN
I2CEN: I2C Enable bit 1 = Enables the I2C module and configures the SDA and SCL pins as serial port pins 0 = Disables I2C module. All I2C pins are controlled by port functions. Unimplemented: Read as ‘0’ I2CSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters an Idle mode 0 = Continue module operation in Idle mode SCLREL: SCL Release Control bit (when operating as I2C Slave) 1 = Release SCL clock 0 = Hold SCL clock low (clock stretch) If STREN = 1: Bit is R/W (i.e., software may write ‘0’ to initiate stretch and write ‘1’ to release clock) Hardware clear at beginning of slave transmission. Hardware clear at end of slave reception. If STREN = 0: Bit is R/S (i.e., software may only write ‘1’ to release clock) Hardware clear at beginning of slave transmission. IPMIEN: Intelligent Peripheral Management Interface (IPMI) Enable bit 1 = Enable IPMI Support mode. All addresses Acknowledged.
M. Deloizy
157
b8
b0
dsPIC30F2023
I²C bit 10 bit 9 bit 8 bit 7 bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0 = IPMI mode not enabled A10M: 10-bit Slave Address bit 1 = I2CADD is a 10-bit slave address 0 = I2CADD is a 7-bit slave address DISSLW: Disable Slew Rate Control bit 1 = Slew rate control disabled 0 = Slew rate control enabled SMEN: SMBus Input Levels bit 1 = Enable I/O pin thresholds compliant with SMBus specification 0 = Disable SMBus input thresholds GCEN: General Call Enable bit (when operating as I2C slave) 1 = Enable interrupt when a general call address is received in the I2CRSR (module is enabled for reception) 0 = General call address disabled STREN: SCL Clock Stretch Enable bit (when operating as I2C slave) Used in conjunction with SCLREL bit. 1 = Enable software or receive clock stretching 0 = Disable software or receive clock stretching ACKDT: Acknowledge Data bit (When operating as I2C Master. Applicable during master receive.) Value that will be transmitted when the software initiates an Acknowledge sequence. 1 = Send NACK during acknowledge 0 = Send ACK during acknowledge ACKEN: Acknowledge Sequence Enable bit (When operating as I2C master. Applicable during master receive.) 1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit Hardware clear at end of master Acknowledge sequence. 0 = Acknowledge sequence not in progress RCEN: Receive Enable bit (when operating as I2C master) 1 = Enables Receive mode for I2C Hardware clear at end eighth bit of master receive data byte. 0 = Receive sequence not in progress PEN: Stop Condition Enable bit (when operating as I2C master) 1 = Initiate Stop condition on SDA and SCL pins Hardware clear at end of master Stop sequence. 0 = Stop condition not in progress RSEN: Repeated Start Condition Enabled bit (when operating as I2C master) 1 = Initiate Repeated Start condition on SDA and SCL pins Hardware clear at end of master Repeated Start sequence. 0 = Repeated Start condition not in progress SEN: Start Condition Enabled bit (when operating as I2C master) 1 = Initiate Start condition on SDA and SCL pins Hardware clear at end of master Start sequence. 0 = Start condition not in progress
M. Deloizy
158
dsPIC30F2023
I²C
♦ I2CSTAT: I2C™ Status Register R-0 R-0 U-0 U-0 HS, HC HS, HC ACKSTAT TRSTAT — —
U-0 —
b15
R/C-0 HS IWCOL
b7
bit 15
bit 14
bit 13-11 bit 10
bit 9
bit 8
R/W-0 HS I2COV
R-0 HS, HC D_A
R/C-0 HS, HC P
R/C-0 HS, HC S
R/C-0 HS BCL R-0 HS, HC R_W
R-0 R-0 HS, HC HS, HC GCSTAT ADD10
b8
R-0 HS, HC RBF
ACKSTAT: Acknowledge Status bit (When operating as I2C master. Applicable to master transmit operation.) 1= NACK received from slave 0= ACK received from slave Hardware set or clear at end of slave Acknowledge. TRSTAT: Transmit Status bit (When operating as I2C master. Applicable to master transmit operation.) 1= Master transmit is in progress (8 bits + ACK) 0= Master transmit is not in progress Hardware set at beginning of master transmission. Hardware clear at end of slave Acknowledge. Unimplemented: Read as ‘0’ BCL: Master Bus Collision Detect bit 1= A bus collision has been detected during a master operation 0= No collision Hardware set at detection of bus collision. GCSTAT: General Call Status bit 1= General call address was received 0= General call address was not received Hardware set when address matches general call address. Hardware clear at Stop detection. ADD10: 10-bit Address Status bit 1 = 10-bit address was matched 0 = 10-bit address was not matched Hardware set at match of 2nd byte of matched 10-bit address.
M. Deloizy
159
R-0 HS, HC TBF
b0
dsPIC30F2023
I²C bit 7
bit 6
bit 5
bit 4
bit 3
bit 2 bit 1
bit 0
Hardware clear at Stop detection. IWCOL: Write Collision Detect bit 1= An attempt to write the I2CTRN register failed because the I2C module is busy 0= No collision Hardware set at occurrence of write to I2CTRN while busy (cleared by software). I2COV: Receive Overflow Flag bit 1= A byte was received while the I2CRCV register is still holding the previous byte 0= No overflow Hardware set at attempt to transfer I2CRSR to I2CRCV (cleared by software). D_A: Data/Address bit (when operating as I2C slave) 1= Indicates that the last byte received was data 0= Indicates that the last byte received was device address Hardware clear at device address match. Hardware set by write to I2CTRN or by reception of slave byte. P: Stop bit 1= Indicates that a Stop bit has been detected last 0= Stop bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. S: Start bit 1= Indicates that a Start (or Repeated Start) bit has been detected last 0= Start bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. R_W: Read/Write bit Information (when operating as I2C slave) 1= Read - indicates data transfer is output from slave 0= Write - indicates data transfer is input to slave Hardware set or clear after reception of I2C device address byte. RBF: Receive Buffer Full Status bit 1 = Receive complete, I2CRCV is full 0= Receive not complete, I2CRCV is empty Hardware set when I2CRCV written with received byte. Hardware clear when software reads I2CRCV. TBF: Transmit Buffer Full Status bit 1= Transmit in progress, I2CTRN is full 0 = Transmit complete, I2CTRN is empty Hardware set when software writes I2CTRN. Hardware clear at completion of data transmission.
M. Deloizy
160
dsPIC30F2023
I²C
♦ I2CRCV : Receive Register Reset State : 0000 0000 0000 0000 ♦ I2CTRN : Transmit Register Reset State : 0000 0000 1111 1111 ♦ I2CBRG : Baud Rate Generator Reset State : 0000 0000 0000 0000 ♦ I2CADD : Address Register Reset State : 0000 0000 0000 0000
M. Deloizy
161
dsPIC30F2023
I²C
Exemple de gestion (mode maître) #define FREQI2C 1E5
// Fréquence bus I²C
#define TRIS_SCL _TRISG2 #define TRIS_SDA _TRISG3
// Gestion I2C #define ACK 0 #define NACK 1 #define WRITE 0 #define READ 1 #define I2CAD 0x40
// Adresse du périphérique I²C
static void I2cMasterInit(void) { TRIS_SCL=1; TRIS_SDA=1; I2CBRG=(unsigned)(FCY/FREQI2C-FCY/1111111.-1+0.5); I2CCON=0x9040; // 1001 0000 0100 0000 }
M. Deloizy
162
dsPIC30F2023
I²C
static void I2cStart(void) { _SEN=1; while(_SEN); } static void I2cRStart(void) { _RSEN=1; while(_RSEN); } static void I2cStop(void) { _PEN=1; while(_PEN); }
M. Deloizy
163
dsPIC30F2023
I²C
static unsigned char I2cMasterWrite(unsigned char b) { I2CTRN=b; while(_TRSTAT); return _ACKSTAT; } static unsigned char I2cMasterRead(unsigned char ack) { unsigned char x; _RCEN=1; while(_RCEN); x=I2CRCV; _ACKDT=ack; _ACKEN=1; while(_ACKEN); return x; }
Exemple d’utilisation : I2cStart(); while(I2cMasterWrite(I2CAD|WRITE)!=ACK) I2cRStart(); I2cMasterWrite(0); // accès au registre d’adresse 0 I2cRStart(); I2cMasterWrite(I2CAD|READ); nb=I2cMasterRead(NACK); I2cStop();
M. Deloizy
164
dsPIC30F2023
SPI
IX Interface SPI IX.1
Registres
♦ SPIxSTAT: SPIx STATUS AND CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 SPIEN — SPISIDL — — — b15
b7
U-0 —
bit 15 bit 14 bit 13 bit 12-7 bit 6 bit 5-2 bit 1
bit 0
R/C-0 SPIROV
U-0 —
U-0 —
U-0 —
U-0 —
U-0 —
U-0 —
b8
R-0 R-0 SPITBF SPIRBF
b0
SPIEN: SPIx Enable bit 1 = Enables module and configures SCKx, SDOx, SDIx and SSx as serial port pins 0 = Disables module Unimplemented: Read as ‘0’ SPISIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode Unimplemented: Read as ‘0’ SPIROV: Receive Overflow Flag bit 1 = A new byte/word is completely received and discarded. The user software has not read the previous data in the SPIxBUF register. 0 = No overflow has occurred Unimplemented: Read as ‘0’ SPITBF: SPIx Transmit Buffer Full Status bit 1 = Transmit not yet started, SPIxTXB is full 0 = Transmit started, SPIxTXB is empty Automatically set in hardware when CPU writes SPIxBUF location, loading SPIxTXB. Automatically cleared in hardware when SPIx module transfers data from SPIxTXB to SPIxSR. SPIRBF: SPIx Receive Buffer Full Status bit 1 = Receive complete, SPIxRXB is full 0 = Receive is not complete, SPIxRXB is empty Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB. Automatically cleared in hardware when core reads SPIxBUF location, reading SPIxRXB.
M. Deloizy
165
dsPIC30F2023
SPI
SPIXCON1: SPIx CONTROL REGISTER 1 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — DISSCK DISSDO MODE16
b15
R/W-0 SSEN
b7
bit 15-13 bit 12 bit 11 bit 10 bit 9
bit 8 bit 7 bit 6 bit 5
R/W-0 CKP
R/W-0 MSTEN
R/W-0
R/W-0 R/W-0 SPRE
Unimplemented: Read as ‘0’ DISSCK: Disable SCKx pin bit (SPI Master modes only) 1 = Internal SPI clock is disabled, pin functions as I/O 0 = Internal SPI clock is enabled DISSDO: Disable SDOx pin bit 1 = SDOx pin is not used by module; pin functions as I/O 0 = SDOx pin is controlled by the module MODE16: Word/Byte Communication Select bit 1 = Communication is word-wide (16 bits) 0 = Communication is byte-wide (8 bits) SMP: SPIx Data Input Sample Phase bit Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time Slave mode: SMP must be cleared when SPIx is used in Slave mode. CKE: SPIx Clock Edge Select bit(1) 1 = Serial output data changes on transition from active clock state to Idle clock state (see bit 6) 0 = Serial output data changes on transition from Idle clock state to active clock state (see bit 6) SSEN: Slave Select Enable bit (Slave mode) 1 = SSx pin used for Slave mode 0 = SSx pin not used by module. Pin controlled by port function. CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level; active state is a low level 0 = Idle state for clock is a low level; active state is a high level MSTEN: Master Mode Enable bit 1 = Master mode 0 = Slave mode
M. Deloizy
166
R/W-0 SMP
R/W-0 CKE(1)
b8
R/W-0 R/W-0 PPRE
b0
dsPIC30F2023
SPI bit 4-2
bit 1-0
Note 1:
SPRE: Secondary Prescale bits (Master mode) 111 = Secondary prescale 1:1 110 = Secondary prescale 2:1 ... 000 = Secondary prescale 8:1 PPRE: Primary Prescale bits (Master mode) 11 = Primary prescale 1:1 10 = Primary prescale 4:1 01 = Primary prescale 16:1 00 = Primary prescale 64:1 The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1).
♦ SPIxCON2: SPIx CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 U-0 U-0 FRMEN SPIFSD FRMPOL — — b15
b7
U-0 —
bit 15 bit 14 bit 13 bit 12-2 bit 1 bit 0
U-0 —
U-0 —
U-0 —
U-0 —
FRMEN: Framed SPIx Support bit 1 = Framed SPIx support enabled (SSx pin used as frame sync pulse input/output) 0 = Framed SPIx support disabled SPIFSD: Frame Sync Pulse Direction Control bit 1 = Frame sync pulse input (slave) 0 = Frame sync pulse output (master) FRMPOL: Frame Sync Pulse Polarity bit 1 = Frame sync pulse is active-high 0 = Frame sync pulse is active-low Unimplemented: Read as ‘0’ FRMDLY: Frame Sync Pulse Edge Select bit 1 = Frame sync pulse coincides with first bit clock 0 = Frame sync pulse precedes first bit clock Unimplemented: This bit must not be set to ‘1’ by the user application.
M. Deloizy
167
U-0 —
U-0 —
U-0 —
U-0 —
R/W-0 FRMDLY
U-0 —
b8
b0
dsPIC30F2023
SPI
♦ SPI1BUF : Transmit and Receive Buffer
M. Deloizy
168
dsPIC30F2023
UART
X UART X.1 Registres ♦ U1MODE: UART1 MODE REGISTER R/W-0 U-0 R/W-0 R/W-0 UARTEN — USIDL IREN
U-0 —
R/W-0 ALTIO
U-0 —
U-0 —
R/W-0
R/W-0
R/W-0
R/W-0
b15
R/W-0 R/W-0 R/W-0 R/W-0 HC HC WAKE LPBACK ABAUD RXINV
b7
bit 15 bit 14 bit 13 bit 12
bit 11 bit 10 bit 9-8 bit 7
BRGH
PDSEL1 PDSEL0
b8
STSEL
b0
UARTEN: UART1 Enable bit 1 = UART1 enabled; all UART1 pins are controlled by UART1 as defined by UEN 0 = UART1 disabled; all UART1 pins are controlled by PORT latches; UART1 power consumption minimal Unimplemented: Read as ‘0’ USIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode IREN: IrDA Encoder and Decoder Enable bit 1 = IrDA encoder and decoder enabled 0 = IrDA encoder and decoder disabled Note: This feature is only available for the 16x BRG mode (BRGH = 0). Unimplemented: Read as ‘0’ ALTIO: UART Alternate I/O Selection bit 1 = UART communicates using U1ATX and U1ARX I/O pins 0 = UART communicates using U1TX and U1RX I/O pins. Unimplemented: Read as ‘0’ WAKE: Wake-up on Start bit Detect During Sleep Mode Enable bit 1 = UART1 will continue to sample the U1RX pin; interrupt generated on falling edge, bit cleared in hardware on following rising edge 0 = No wake-up enabled
M. Deloizy
169
dsPIC30F2023
UART bit 6 bit 5
bit 4 bit 3 bit 2-1
bit 0
LPBACK: UART1 Loopback Mode Select bit 1 = Enable Loopback mode 0 = Loopback mode is disabled ABAUD: Auto-Baud Enable bit 1 = Enable baud rate measurement on the next character – requires reception of a Sync field (55h); cleared in hardware upon completion 0 = Baud rate measurement disabled or completed RXINV: Receive Polarity Inversion bit 1 = U1RX Idle state is ‘0’ 0 = U1RX Idle state is ‘1’ BRGH: High Baud Rate Enable bit 1 = BRG generates 4 clocks per bit period (4x Baud Clock, High-Speed mode) 0 = BRG generates 16 clocks per bit period (16x Baud Clock, Standard mode) PDSEL1:PDSEL0: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity STSEL: Stop Bit Selection bit 1 = Two Stop bits 0 = One Stop bit
♦ U1STA: UART1 STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 UTXISEL1 UTXINV(1) UTXISEL0 — UTXBRK UTXEN UTXBF TRMT b15
b8
R/W-0 R/W-0 R/W-0 R/W-0 URXISEL1 URXISEL0 ADDEN RIDLE b7
bit 15, 13
R/W-0 PERR
R/W-0 FERR
R/W-0 R/W-0 OERR URXDA
UTXISEL1:UTXISEL0: Transmission Interrupt Mode Selection bits 11 =Reserved; do not use 10 =Interrupt when a character is transferred to the Transmit Shift Register and as a result, the transmit buffer becomes empty 01 =Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit operations are completed 00 =Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at least one character open in the transmit buffer)
M. Deloizy
170
b0
dsPIC30F2023
UART bit 14
bit 12 bit 11
bit 10 bit 9 bit 8 bit 7-6
bit 5 bit 4 bit 3 bit 2 bit 1
bit 0
UTXINV: IrDA Encoder Transmit Polarity Inversion bit(1) 1 = IrDA encoded U1TX idle state is ‘1’ 0 = IrDA encoded U1TX idle state is ‘0’ Note 1: Value of bit only affects the transmit properties of the module when the IrDA encoder is enabled (IREN = 1). Unimplemented: Read as ‘0’ UTXBRK: Transmit Break bit 1 = Send Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit; cleared by hardware upon completion 0 = Sync Break transmission disabled or completed UTXEN: Transmit Enable bit 1 = Transmit enabled, U1TX pin controlled by UART1 0 = Transmit disabled, any pending transmission is aborted and buffer is reset. U1TX pin controlled by PORT. UTXBF: Transmit Buffer Full Status bit (Read-Only) 1 = Transmit buffer is full 0 = Transmit buffer is not full, at least one more character can be written TRMT: Transmit Shift Register Empty bit (Read-Only) 1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed) 0 = Transmit Shift Register is not empty, a transmission is in progress or queued URXISEL1:URXISEL0: Receive Interrupt Mode Selection bits 11 =Interrupt is set on RSR transfer, making the receive buffer full (i.e., has 4 data characters) 10 =Interrupt is set on RSR transfer, making the receive buffer 3/4 full (i.e., has 3 data characters) 0x =Interrupt is set when any character is received and transferred from the RSR to the receive buffer. Receive buffer has one or more characters. ADDEN: Address Character Detect bit (bit 8 of received data = 1) 1 = Address Detect mode enabled. If 9-bit mode is not selected, this does not take effect. 0 = Address Detect mode disabled RIDLE: Receiver Idle bit (Read-Only) 1 = Receiver is Idle 0 = Receiver is active PERR: Parity Error Status bit (Read-Only) 1 = Parity error has been detected for the current character (character at the top of the receive FIFO) 0 = Parity error has not been detected FERR: Framing Error Status bit (Read-Only) 1 = Framing error has been detected for the current character (character at the top of the receive FIFO) 0 = Framing error has not been detected OERR: Receive Buffer Overrun Error Status bit (Read/Clear-Only) 1 = Receive buffer has overflowed 0 = Receive buffer has not overflowed (clearing a previously set OERR bit (1 0transition) will reset the receiver buffer and the RSR to the empty state) URXDA: Receive Buffer Data Available bit (Read-Only) 1 = Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty
M. Deloizy
171
dsPIC30F2023
UART
♦ U1TXREG : UART Transmit Register ♦ U1RXREG : UART Receive Register ♦ U1BRG : Baud Rate Generator Prescaler
M. Deloizy
172
dsPIC30F2023
Comparateur
XI Module Comparateur XI.1
Schéma fonctionnel
XI.2
Registres
♦ CMPCONx : COMPARATOR CONTROL REGISTERx (x=1,…4) R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 CMPON — CMPSIDL — — — — b15
U-0 —
b8
U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INSEL EXTREF — CMPSTAT — CMPPOL RANGE b7
b0
M. Deloizy
173
dsPIC30F2023
Comparateur bit 15 bit 14 bit 13
bit 12-8 bit 7-6
bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
CMPON: A/D Operating Mode bit 1 = Comparator module is enabled 0 = Comparator module is disabled (reduces power consumption) Unimplemented: Read as ‘0’ CMPSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode. 0 = Continue module operation in Idle mode. If a device has multiple comparators, any CMPSIDL bit set to ‘1’ disables ALL comparators while in Idle mode. Reserved: Read as ‘0’ INSEL: Input Source Select for Comparator bits 00 = Select CMPxA input pin 01 = Select CMPxB input pin 10 = Select CMPxC input pin 11 = Select CMPxD input pin EXTREF: Enable External Reference bit 1 = External source provides reference to DAC 0 = Internal reference sources provide source to DAC Reserved: Read as ‘0’ CMPSTAT: Current State of Comparator Output Including CMPPOL Selection bit Reserved: Read as ‘0’ CMPPOL: Comparator Output Polarity Control bit 1 = Output is inverted 0 = Output is non inverted RANGE: Selects DAC Output Voltage Range bit 1 = High Range: Max DAC value = AVDD / 2, 2.5V @ 5 volt VDD 0 = Low Range: Max DAC value = INTREF, 1.2V ±1%
♦ CMPDACx : COMPARATOR DAC CONTROL REGISTERx (x=1,…4) U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — CMREF b15
b8
R/W-0 b7
bit 15-10
R/W-0
R/W-0
R/W-0 R/W-0 CMREF
Reserved: Read as ‘0’
M. Deloizy
174
R/W-0
R/W-0
R/W-0 b0
dsPIC30F2023
Comparateur bit 9-0
These bits are reserved for possible future expansion of the DAC from 10 bits to more bits. CMREF: Comparator Reference Voltage Select bits 1111111111 = (CMREF * INTREF/1024) or (CMREF * (AVDD/2)/1024) volts depending on Range bit ····· 0000000000 = 0.0 volts
M. Deloizy
175
dsPIC30F2023
Compilateur C
XII Compilateur C • MPLAB C30 • ANSI x3.159-1989-compliant • GCC (Free Software Foundation) • Intégré dans MPLAB (version limitée, sans optimisation) • Extensions du langage pour le dsPIC • Bibliothèques pour le contrôle des périphériques • Inclure XII.1 Types de données Utilisation du format “little endian” (poids faible en adresse basse) XII.1.a
Types entiers
Type char, signed char unsigned char short, signed short unsigned short int, signed int unsigned int long, signed long M. Deloizy
Bits 8 8 16 16 16 16 32 176
Min -128 0 -32768 0 -32768 0 -231
Max 127 255 32767 65535 32767 65535 231 - 1 dsPIC30F2023
Compilateur C
unsigned long 32 long long**, signed long long** 64 unsigned long long** 64
0 -263 0
232 - 1 263 - 1 264 - 1
XII.1.b Virgule flottante
Type float double* long double
Bits 32 32 64
E Min -126 -126 -1022
E Max 127 127 1023
N Min 2-126 2-126 2-1022
N Max 2128 2128 21024
* double is equivalent to long double if -fno-short-double is used. XII.2
Extensions du langage
XII.2.a
Constantes binaires
• Préfixe 0b ou 0B Exemple : x = 0b00001111 ;
// x = 0x0F
XII.2.b Fonctions inline
Permet de définir une fonction en ligne (évite la transmission des paramètres et l’appel de la fonction) Nécessite optimisation active ou option -finline Exemple : __inline__ int inc(int *a) { (*a)++; } M. Deloizy
177
dsPIC30F2023
Compilateur C
XII.2.c
Interruptions
• • • •
Écriture de la fonction de gestion de l’interruption Écriture du vecteur d’interruption Fonctions « void » Ne pas les appeler (exécutées automatiquement lors des requêtes d’interruption) • Doivent être « rapides ». Éviter l’appel d’autres fonctions • Sauvegarde automatique des registres utilisés et RCOUNT o Si appel de fonction : sauvegarde de tous les registres • Les interruptions sont interruptibles par défaut (voir le bit NSTDIS dans INTCON1, p 41) ♦ Syntaxe : __attribute__((__interrupt__ [( [ __save__(symbol-list)] liste de variables à sauvegarder et restituer [, irq(irqid)] spécification d’un vecteur d’interruption [, altirq(altirqid)] spécification d’un vecteur d’interruption alterné [, preprologue(asm)] insertion d’instr. ass. avant prologue routine interruption )] ))
Exemple : void __attribute__((__interrupt__(__save__(var1,var2)))) _INT0Interrupt(void); void __attribute__((__interrupt__(__irq__(52)))) MyIRQ(void); void __attribute__((__interrupt__(__preprologue__("inc _semaphore")))) isr0(void); M. Deloizy
178
dsPIC30F2023
Compilateur C
♦ Utilisation de macros #define _ISR __attribute__((interrupt)) #define _ISRFAST __attribute__((interrupt, shadow))
Utilisation de push.s, pop.s
Exemple : void _ISR _INT0Interrupt(void);
♦ Vecteurs d’interruption IRQ# N/A N/A N/A N/A N/A N/A N/A N/A 0 1 2 3 4 5 6 7 8
Primary Name _ReservedTrap0 _OscillatorFail _AddressError _StackError _MathError _ReservedTrap5 _ReservedTrap6 _ReservedTrap7 _INT0Interrupt _IC1Interrupt _OC1Interrupt _T1Interrupt _Interrupt4 _OC2Interrupt _T2Interrupt _T3Interrupt _SPI1Interrupt
Alternate Name _AltReservedTrap0 _AltOscillatorFail _AltAddressError _AltStackError _AltMathError _AltReservedTrap5 _AltReservedTrap6 _AltReservedTrap7 _AltINT0Interrupt _AltIC1Interrupt _AltOC1Interrupt _AltT1Interrupt _AltInterrupt4 _AltOC2Interrupt _AltT2Interrupt _AltT3Interrupt _AltSPI1Interrupt
9 10
_U1RXInterrupt _U1TXInterrupt
_AltU1RXInterrupt _AltU1TXInterrupt
M. Deloizy
179
Vector Function Reserved Oscillator fail trap Address error trap Stack error trap Math error trap Reserved Reserved Reserved INT0 External interrupt 0 IC1 Input capture 1 OC1 Output compare 1 TMR1 Timer 1 expired Reserved OC2 Output compare 2 TMR2 Timer 2 expired TMR3 Timer 3 expired SPI1 Serial peripheral interface 1 UART1RX Uart 1 Receiver UART1TX Uart 1 Transmitter
dsPIC30F2023
Compilateur C
11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
_ADCInterrupt _NVMInterrupt _SI2CInterrupt _MI2CInterrupt _Interrupt15 _INT1Interrupt _INT2Interrupt _PWMSpEventMatchInterrupt _PWM1Interrupt _PWM2Interrupt _PWM3Interrupt _PWM4Interrupt _Interrupt23 _Interrupt24 _Interrupt25 _Interrupt26 _CNInterrupt _Interrupt28 _CMP1Interrupt _CMP2Interrupt _CMP3Interrupt _CMP4Interrupt _Interrupt33 _Interrupt34 _Interrupt35 _Interrupt36 _ADCP0Interrupt _ADCP1Interrupt _ADCP2Interrupt _ADCP3Interrupt M. Deloizy
_AltADCInterrupt _AltNVMInterrupt _AltSI2CInterrupt _AltMI2CInterrupt _AltInterrupt15 _AltINT1Interrupt _AltINT2Interrupt _AltPWMSpEventMatchInterrupt _AltPWM1Interrupt _AltPWM2Interrupt _AltPWM3Interrupt _AltPWM4Interrupt _AltInterrupt23 _AltInterrupt24 _AltInterrupt25 _AltInterrupt26 _AltCNInterrupt _AltInterrupt28 _AltCMP1Interrupt _AltCMP2Interrupt _AltCMP3Interrupt _AltCMP4Interrupt _AltInterrupt33 _AltInterrupt34 _AltInterrupt35 _AltInterrupt36 _AltADCP0Interrupt _AltADCP1Interrupt _AltADCP2Interrupt _AltADCP3Interrupt
180
ADC Convert completed NVM write completed Slave I2C™ interrupt Master I2C™ interrupt Reserved INT1 External interrupt 1 INT2 External interrupt 2 PWM special event interrupt PWM period match 1 PWM period match 2 PWM period match 3 PWM period match 4 Reserved Reserved Reserved Reserved Input Change Notification Reserved Analog comparator interrupt 1 Analog comparator interrupt 2 Analog comparator interrupt 3 Analog comparator interrupt 4 Reserved Reserved Reserved Reserved ADC Pair 0 conversion complete ADC Pair 1 conversion complete ADC Pair 2 conversion complete ADC Pair 3 conversion complete
dsPIC30F2023
Compilateur C
41 42 43 44 45 46 47 48 49 50 51 52 53
_ADCP4Interrupt _ADCP5Interrupt _Interrupt43 _Interrupt44 _Interrupt45 _Interrupt46 _Interrupt47 _Interrupt48 _Interrupt49 _Interrupt50 _Interrupt51 _Interrupt52 _Interrupt53
_AltADCP4Interrupt _AltADCP5Interrupt _AltInterrupt43 _AltInterrupt44 _AltInterrupt45 _AltInterrupt46 _AltInterrupt47 _AltInterrupt48 _AltInterrupt49 _AltInterrupt50 _AltInterrupt51 _AltInterrupt52 _AltInterrupt53
ADC Pair 4 conversion complete ADC Pair 5 conversion complete Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
♦ Routines par défaut Par défaut, si aucune routine d’interruption n’est déclarée, le compilateur installe un vecteur d’interruption sur une instruction RESET. On peut définir un gestionnaire par défaut en nommant une routine d’interruption : _DefaultInterrupt ♦ Protection de zones On peut interdire les interruptions momentanément en utilisant les macros suivantes : SET_CPU_IPL(ipl) SET_AND_SAVE_CPU_IPL(save_to, ipl) RESTORE_CPU_IPL(saved_to) M. Deloizy
181
dsPIC30F2023
Compilateur C
Exemple : int current_cpu_ipl; SET_AND_SAVE_CPU_IPL(current_cpu_ipl, 7); /* disable interrupts */ /* protected code here */ RESTORE_CPU_IPL(current_cpu_ipl);
XII.2.d Fonctions intrinsèques
Permettent d’utiliser des instructions assembleur sans recourir à l’assembleur en ligne. __builtin_addab __builtin_add __builtin_btg __builtin_clr __builtin_clr_prefetch __builtin_divmodsd __builtin_divmodud __builtin_divsd __builtin_divud __builtin_dmaoffset __builtin_ed
__builtin_edac __builtin_fbcl __builtin_lac __builtin_mac __builtin_modsd __builtin_modud __builtin_movsac __builtin_mpy __builtin_mpyn __builtin_msc __builtin_mulss
__builtin_mulsu __builtin_mulus __builtin_muluu __builtin_nop __builtin_psvpage __builtin_psvoffset __builtin_readsfr __builtin_return_address __builtin_sac __builtin_sacr __builtin_sftac
__builtin_subab __builtin_tblpage __builtin_tbloffset __builtin_tblrdh __builtin_tblrdl __builtin_tblwth __builtin_tblwtl __builtin_write_NVM __builtin_write_OSCCONL __builtin_write_OSCCON
Exemple : unsigned MulDiv(unsigned a, unsigned b, unsigned c) { unsigned long u; u=__builtin_muluu(a,b); return __builtin_divud(u,c); } M. Deloizy
182
dsPIC30F2023
Compilateur C
XII.3
Exemple d’en-tête :
#include //--------------------------Device Configuration-----------------------_FOSC(CSW_FSCM_OFF&OSC2_IO&FRC_HI_RANGE); _FOSCSEL(FRC_PLL); _FWDT(FWDTEN_OFF); _FPOR(PWRT_OFF); _FGS(CODE_PROT_OFF); _FICD( ICS_PGD2 ); //Utilise ICD2 sur EMUC1/EMUD1 #define PLL 32 #define FCY ((unsigned long)(14.55E6*PLL/16)) // FRC = 14.55 Mhz; PLLx16 -> 29.1 MIPS
XII.4
Définition des bits
/* SR */ #define #define #define #define #define #define #define #define #define #define #define #define #define #define
_C _Z _OV _N _RA _IPL _DC _DA _SAB _OAB _SB _SA _OB _OA
/* CORCON */ #define #define #define #define #define #define #define #define #define #define #define
_IF CORCONbits.IF _RND CORCONbits.RND _PSV CORCONbits.PSV _IPL3 CORCONbits.IPL3 _ACCSAT CORCONbits.ACCSAT _SATDW CORCONbits.SATDW _SATB CORCONbits.SATB _SATA CORCONbits.SATA _DL CORCONbits.DL _EDT CORCONbits.EDT _US CORCONbits.US
/* MODCON */ #define #define
_YMODEN _XMODEN
/* XBREV */ #define
_XB
M. Deloizy
SRbits.C SRbits.Z SRbits.OV SRbits.N SRbits.RA SRbits.IPL SRbits.DC SRbits.DA SRbits.SAB SRbits.OAB SRbits.SB SRbits.SA SRbits.OB SRbits.OA
MODCONbits.YMODEN MODCONbits.XMODEN
XBREVbits.XB
#define
_BREN
XBREVbits.BREN
_CN0IE _CN1IE _CN2IE _CN3IE _CN4IE _CN5IE _CN6IE _CN7IE
CNEN1bits.CN0IE CNEN1bits.CN1IE CNEN1bits.CN2IE CNEN1bits.CN3IE CNEN1bits.CN4IE CNEN1bits.CN5IE CNEN1bits.CN6IE CNEN1bits.CN7IE
/* CNEN1 */ #define #define #define #define #define #define #define #define /* CNPU1 */ #define #define #define #define #define #define #define #define
_CN0PUE CNPU1bits.CN0PUE _CN1PUE CNPU1bits.CN1PUE _CN2PUE CNPU1bits.CN2PUE _CN3PUE CNPU1bits.CN3PUE _CN4PUE CNPU1bits.CN4PUE _CN5PUE CNPU1bits.CN5PUE _CN6PUE CNPU1bits.CN6PUE _CN7PUE CNPU1bits.CN7PUE
/* INTCON1 */ #define #define #define #define #define #define #define #define #define #define
_OSCFAIL INTCON1bits.OSCFAIL _STKERR INTCON1bits.STKERR _ADDRERR INTCON1bits.ADDRERR _MATHERR INTCON1bits.MATHERR _DIV0ERR INTCON1bits.DIV0ERR _SFTACERR INTCON1bits.SFTACERR _COVTE INTCON1bits.COVTE _OVBTE INTCON1bits.OVBTE _OVATE INTCON1bits.OVATE _COVBERR INTCON1bits.COVBERR
183
#define #define #define #define
_COVAERR INTCON1bits.COVAERR _OVBERRINTCON1bits.OVBERR _OVAERR INTCON1bits.OVAERR _NSTDIS INTCON1bits.NSTDIS
/* INTCON2 */ #define #define #define #define #define
_INT0EP _INT1EP _INT2EP _DISI _ALTIVT
INTCON2bits.INT0EP INTCON2bits.INT1EP INTCON2bits.INT2EP INTCON2bits.DISI INTCON2bits.ALTIVT
/* IFS0 */ #define #define #define #define #define #define #define #define #define #define #define #define #define #define
_INT0IF _IC1IF _OC1IF _T1IF _OC2IF _T2IF _T3IF _SPI1IF _U1RXIF _U1TXIF _ADIF _NVMIF _SI2CIF _MI2CIF
IFS0bits.INT0IF IFS0bits.IC1IF IFS0bits.OC1IF IFS0bits.T1IF IFS0bits.OC2IF IFS0bits.T2IF IFS0bits.T3IF IFS0bits.SPI1IF IFS0bits.U1RXIF IFS0bits.U1TXIF IFS0bits.ADIF IFS0bits.NVMIF IFS0bits.SI2CIF IFS0bits.MI2CIF
/* IFS1 */ #define #define #define #define #define #define
_INT1IF IFS1bits.INT1IF _INT2IF IFS1bits.INT2IF _PSEMIF IFS1bits.PSEMIF _PWM1IF IFS1bits.PWM1IF _PWM2IF IFS1bits.PWM2IF _PWM3IF IFS1bits.PWM3IF
dsPIC30F2023
Compilateur C #define #define #define #define #define
_PWM4IF IFS1bits.PWM4IF _CNIF IFS1bits.CNIF _AC1IF IFS1bits.AC1IF _AC2IF IFS1bits.AC2IF _AC3IF IFS1bits.AC3IF
/* IFS2 */ #define #define #define #define #define #define #define
_AC4IF IFS2bits.AC4IF _ADCP0IF IFS2bits.ADCP0IF _ADCP1IF IFS2bits.ADCP1IF _ADCP2IF IFS2bits.ADCP2IF _ADCP3IF IFS2bits.ADCP3IF _ADCP4IF IFS2bits.ADCP4IF _ADCP5IF IFS2bits.ADCP5IF
/* IEC0 */ #define #define #define #define #define #define #define #define #define #define #define #define #define #define
_INT0IE _IC1IE _OC1IE _T1IE _OC2IE _T2IE _T3IE _SPI1IE _U1RXIE _U1TXIE _ADIE _NVMIE _SI2CIE _MI2CIE
/* IEC1 */ #define #define #define #define #define #define #define #define #define #define #define
#define
_T3IP
IPC1bits.T3IP
/* IPC2 */ #define #define #define #define
_SPI1IP _U1RXIP _U1TXIP _ADIP
IPC2bits.SPI1IP IPC2bits.U1RXIP IPC2bits.U1TXIP IPC2bits.ADIP
/* IPC3 */ #define #define #define
_NVMIP IPC3bits.NVMIP _SI2CIP IPC3bits.SI2CIP _MI2CIP IPC3bits.MI2CIP
/* IPC4 */ #define #define #define #define
_INT1IP IPC4bits.INT1IP _INT2IP IPC4bits.INT2IP _PSEMIP IPC4bits.PSEMIP _PWM1IP IPC4bits.PWM1IP
/* IPC5 */ #define #define #define
_PWM2IP IPC5bits.PWM2IP _PWM3IP IPC5bits.PWM3IP _PWM4IP IPC5bits.PWM4IP
/* IPC6 */ #define
_CNIP
IPC6bits.CNIP
/* IPC7 */ #define #define #define
_AC1IP _AC2IP _AC3IP
IPC7bits.AC1IP IPC7bits.AC2IP IPC7bits.AC3IP
_INT1IE IEC1bits.INT1IE _INT2IE IEC1bits.INT2IE _PSEMIE IEC1bits.PSEMIE _PWM1IE IEC1bits.PWM1IE _PWM2IE IEC1bits.PWM2IE _PWM3IE IEC1bits.PWM3IE _PWM4IE IEC1bits.PWM4IE _CNIE IEC1bits.CNIE _AC1IE IEC1bits.AC1IE _AC2IE IEC1bits.AC2IE _AC3IE IEC1bits.AC3IE
/* IPC8 */ #define
_AC4IP
IPC8bits.AC4IP
/* IPC9 */ #define #define #define
_ADCP0IP _ADCP1IP _ADCP2IP
IPC9bits.ADCP0IP IPC9bits.ADCP1IP IPC9bits.ADCP2IP
/* IEC2 */ #define #define #define #define #define #define #define
/* IPC10 */ #define #define #define
_ADCP3IP _ADCP4IP _ADCP5IP
IPC10bits.ADCP3IP IPC10bits.ADCP4IP IPC10bits.ADCP5IP
_AC4IE IEC2bits.AC4IE _ADCP0IE IEC2bits.ADCP0IE _ADCP1IE IEC2bits.ADCP1IE _ADCP2IE IEC2bits.ADCP2IE _ADCP3IE IEC2bits.ADCP3IE _ADCP4IE IEC2bits.ADCP4IE _ADCP5IE IEC2bits.ADCP5IE
/* INTTREG */ #define #define
_VECNUM INTTREGbits.VECNUM _ILR INTTREGbits.ILR
/* IPC0 */ #define #define #define #define
_INT0IP _IC1IP _OC1IP _T1IP
IPC0bits.INT0IP IPC0bits.IC1IP IPC0bits.OC1IP IPC0bits.T1IP
/* IPC1 */ #define #define
_OC2IP _T2IP
IPC1bits.OC2IP IPC1bits.T2IP
M. Deloizy
IEC0bits.INT0IE IEC0bits.IC1IE IEC0bits.OC1IE IEC0bits.T1IE IEC0bits.OC2IE IEC0bits.T2IE IEC0bits.T3IE IEC0bits.SPI1IE IEC0bits.U1RXIE IEC0bits.U1TXIE IEC0bits.ADIE IEC0bits.NVMIE IEC0bits.SI2CIE IEC0bits.MI2CIE
/* No unique SFR bit names for Timer Register Map */ /*IC1CON */ #define #define #define #define
_ICBNE _ICOV _ICTMR _ICSIDL
IC1CONbits.ICBNE IC1CONbits.ICOV IC1CONbits.ICTMR IC1CONbits.ICSIDL
/* No unique SFR bit names for Output Compare Register Map */ /* I2CCON: I2C Control Register */ #define _SEN I2CCONbits.SEN #define _RSEN I2CCONbits.RSEN
184
#define #define #define #define #define #define #define #define #define #define #define #define
_PEN _RCEN _ACKEN _ACKDT _STREN _GCEN _SMEN _DISSLW _IPMIEN _SCLREL _I2CSIDL _I2CEN
I2CCONbits.PEN I2CCONbits.RCEN I2CCONbits.ACKEN I2CCONbits.ACKDT I2CCONbits.STREN I2CCONbits.GCEN I2CCONbits.SMEN I2CCONbits.DISSLW I2CCONbits.IPMIEN I2CCONbits.SCLREL I2CCONbits.I2CSIDL I2CCONbits.I2CEN
/* I2CSTAT Register*/ #define _TBF I2CSTATbits.TBF #define _RBF I2CSTATbits.RBF #define _R_W I2CSTATbits.R_W #define _S I2CSTATbits.S #define _P I2CSTATbits.P #define _D_A I2CSTATbits.D_A #define _I2COV I2CSTATbits.I2COV #define _IWCOL I2CSTATbits.IWCOL #define _ADD10 I2CSTATbits.ADD10 #define _GCSTAT I2CSTATbits.GCSTAT #define _TRSTAT I2CSTATbits.TRSTAT #define _ACKSTAT I2CSTATbits.ACKSTAT /* No unique SFR bit names for UART1 Register Map */ /* SPI1 Register */ #define #define #define #define #define
_SPIRBF SPI1STAT.SPIRBF _SPITBF SPISTAT.SPITBF _SPIROV SPI1STAT.SPIROV _SPISIDL SPI1STAT.SPISIDL _SPIEN SPI1STAT.SPIEN
/* TRISA */ #define #define #define #define
_TRISA8 TRISAbits.TRISA8 _TRISA9 TRISAbits.TRISA9 _TRISA10 TRISAbits.TRISA10 _TRISA11 TRISAbits.TRISA11
/* PORTA */ #define #define #define #define
_RA8 _RA9 _RA10 _RA11
PORTAbits.RA8 PORTAbits.RA9 PORTAbits.RA10 PORTAbits.RA11
/* LATA */ #define #define #define #define
_LATA8 _LATA9 _LATA10 _LATA11
LATAbits.LATA8 LATAbits.LATA9 LATAbits.LATA10 LATAbits.LATA11
/* TRISB */ #define #define #define #define #define #define #define
_TRISB0 _TRISB1 _TRISB2 _TRISB3 _TRISB4 _TRISB5 _TRISB6
TRISBbits.TRISB0 TRISBbits.TRISB1 TRISBbits.TRISB2 TRISBbits.TRISB3 TRISBbits.TRISB4 TRISBbits.TRISB5 TRISBbits.TRISB6
dsPIC30F2023
Compilateur C #define #define #define #define #define
_TRISB7 TRISBbits.TRISB7 _TRISB8 TRISBbits.TRISB8 _TRISB9 TRISBbits.TRISB9 _TRISB10 TRISBbits.TRISB10 _TRISB11 TRISBbits.TRISB11
/* PORTB */ #define #define #define #define #define #define #define #define #define #define #define #define
_RB0 _RB1 _RB2 _RB3 _RB4 _RB5 _RB6 _RB7 _RB8 _RB9 _RB10 _RB11
PORTBbits.RB0 PORTBbits.RB1 PORTBbits.RB2 PORTBbits.RB3 PORTBbits.RB4 PORTBbits.RB5 PORTBbits.RB6 PORTBbits.RB7 PORTBbits.RB8 PORTBbits.RB9 PORTBbits.RB10 PORTBbits.RB11
/* LATB */ #define #define #define #define #define #define #define #define #define #define #define #define
_LATB0 _LATB1 _LATB2 _LATB3 _LATB4 _LATB5 _LATB6 _LATB7 _LATB8 _LATB9 _LATB10 _LATB11
LATBbits.LATB0 LATBbits.LATB1 LATBbits.LATB2 LATBbits.LATB3 LATBbits.LATB4 LATBbits.LATB5 LATBbits.LATB6 LATBbits.LATB7 LATBbits.LATB8 LATBbits.LATB9 LATBbits.LATB10 LATBbits.LATB11
/* TRISD */ #define #define
_TRISD0 TRISDbits.TRISD0 _TRISD1 TRISDbits.TRISD1
/* PORTD */ #define #define
_RD0 _RD1
/* LATD */ #define #define
_LATD0 LATDbits.LATD0 _LATD1 LATDbits.LATD1
/* TRISE */ #define #define #define #define #define #define #define #define
_TRISE0 _TRISE1 _TRISE2 _TRISE3 _TRISE4 _TRISE5 _TRISE6 _TRISE7
TRISEbits.TRISE0 TRISEbits.TRISE1 TRISEbits.TRISE2 TRISEbits.TRISE3 TRISEbits.TRISE4 TRISEbits.TRISE5 TRISEbits.TRISE6 TRISEbits.TRISE7
/* PORTE */ #define #define #define #define #define
_RE0 _RE1 _RE2 _RE3 _RE4
PORTEbits.RE0 PORTEbits.RE1 PORTEbits.RE2 PORTEbits.RE3 PORTEbits.RE4
M. Deloizy
PORTDbits.RD0 PORTDbits.RD1
#define #define #define
_RE5 _RE6 _RE7
PORTEbits.RE5 PORTEbits.RE6 PORTEbits.RE7
/* LATE */ #define #define #define #define #define #define #define #define
_LATE0 _LATE1 _LATE2 _LATE3 _LATE4 _LATE5 _LATE6 _LATE7
LATEbits.LATE0 LATEbits.LATE1 LATEbits.LATE2 LATEbits.LATE3 LATEbits.LATE4 LATEbits.LATE5 LATEbits.LATE6 LATEbits.LATE7
/* TRISF */ #define #define #define #define #define #define #define
_TRISF2 TRISFbits.TRISF2 _TRISF3 TRISFbits.TRISF3 _TRISF6 TRISFbits.TRISF6 _TRISF7 TRISFbits.TRISF7 _TRISF8 TRISFbits.TRISF8 _TRISF14 TRISFbits.TRISF14 _TRISF15 TRISFbits.TRISF15
/* PORTF */ #define #define #define #define #define #define #define
_RF2 _RF3 _RF6 _RF7 _RF8 _RF14 _RF15
PORTFbits.RF2 PORTFbits.RF3 PORTFbits.RF6 PORTFbits.RF7 PORTFbits.RF8 PORTFbits.RF14 PORTFbits.RF15
/* LATF */ #define #define #define #define #define #define #define
_LATF2 _LATF3 _LATF6 _LATF7 _LATF8 _LATF14 _LATF15
LATFbits.LATF2 LATFbits.LATF3 LATFbits.LATF6 LATFbits.LATF7 LATFbits.LATF8 LATFbits.LATF14 LATFbits.LATF15
/* TRISG */ #define #define
_TRISG2 TRISGbits.TRISG2 _TRISG3 TRISGbits.TRISG3
/* PORTG */ #define #define
_RG2 _RG3
/* LATG */ #define #define
_LATG2 LATGbits.LATG2 _LATG3 LATGbits.LATG3
/* ADCON */ #define #define
_ADCS ADCONbits.ADCS _SEQSAMP ADCONbits.SEQSAMP
#define #define #define #define #define
_ORDER ADCONbits.ORDER _EIE ADCONbits.EIE _FORM ADCONbits.FORM _GSWTRG ADCONbits.GSWTRG _ADSIDL ADCONbits.ADSIDL
PORTGbits.RG2 PORTGbits.RG3
185
#define
_ADON
ADCONbits.ADON
/* ADPCFG */ #define #define #define #define #define #define #define #define #define #define #define #define
_PCFG0 _PCFG1 _PCFG2 _PCFG3 _PCFG4 _PCFG5 _PCFG6 _PCFG7 _PCFG8 _PCFG9 _PCFG10 _PCFG11
ADPCFGbits.PCFG0 ADPCFGbits.PCFG1 ADPCFGbits.PCFG2 ADPCFGbits.PCFG3 ADPCFGbits.PCFG4 ADPCFGbits.PCFG5 ADPCFGbits.PCFG6 ADPCFGbits.PCFG7 ADPCFGbits.PCFG8 ADPCFGbits.PCFG9 ADPCFGbits.PCFG10 ADPCFGbits.PCFG11
/* PTCON */ #define #define #define #define #define #define #define #define #define #define
_SEVTPS PTCONbits.SEVTPS _SYNCSRC PTCONbits.SYNCSRC _SYNCEN PTCONbits.SYNCEN _SYNCOEN PTCONbits.SYNCOEN _SEIEN PTCONbits.SEIEN _PTSIDL PTCONbits.PTSIDL _PTEN PTCONbits.PTEN _SESTAT PTCONbits.SESTAT _SYNCPOL PTCONbits.SYNCPOL _EIPU PTCONbits.EIPU
/* No unique SFR bit names for Analog Comparator Register Map */ /* RCON */ #define #define #define #define #define #define #define #define #define #define
_POR RCONbits.POR _IDLE RCONbits.IDLE _SLEEP RCONbits.SLEEP _WDTO RCONbits.WDTO _SWDTEN RCONbits.SWDTEN _SWR RCONbits.SWR _EXTR RCONbits.EXTR _BGST RCONbits.BGST _IOPUWRRCONbits.IOPUWR _TRAPR RCONbits.TRAPR
/* OSCCON */ #define #define #define #define #define #define #define #define
_OSWEN OSCCONbits.OSWEN _TSEQEN OSCCONbits.TSEQEN _CF OSCCONbits.CF _PRCDENOSCCONbits.PRCDEN _LOCK OSCCONbits.LOCK _CLKLOCK OSCCONbits.CLKLOCK _NOSC OSCCONbits.NOSC _COSC OSCCONbits.COSC
/* CLKDIV #define #define #define
_DOZEN CLKDIV.DOZEN _DOZE CLKDIV.DOZE _ROI CLKDIV.ROI
/* NVMCON */ #define #define #define
_SIZSEL NVMCONbits.SIZSEL _MEMSEL NVMCONbits.MEMSEL _SEGSEL NVMCONbits.SEGSEL
*/
dsPIC30F2023
Compilateur C #define #define #define #define #define
_ERASE _TWRI _WRERR _WREN _WR
NVMCONbits.ERASE NVMCONbits.TWRI NVMCONbits.WRERR NVMCONbits.WREN NVMCONbits.WR
/* PMD1 */ #define #define
_ADCMD PMD1bits.ADCMD _SPI1MD PMD1bits.SPI1MD
XII.5
Code généré
XII.5.a
Registres utilisés
#define #define #define #define #define #define
_U1MD PMD1bits.U1MD _I2CMD PMD1bits.I2CMD _PWMMD PMD1bits.PWMMD _T1MD PMD1bits.T1MD _T2MD PMD1bits.T2MD _T3MD PMD1bits.T3MD
/* PMD2 */ #define
_OC1MD PMD2bits.OC1MD
#define #define
_OC2MD PMD2bits.OC2MD _IC1MD PMD2bits.IC1MD
/* PMD3 */ #define
_CMP_PSMD
PMD3bits.CMP_PSMD
• W0 … W13 : données • W14 : frame pointer • W15 : SP XII.5.b Appel de fonction
• Registers W0-W7 are caller saved. The calling function must push these values onto the stack for the register values to be preserved. • Registers W8-W14 are callee saved. The function being called must save any of these registers it will modify. • Registers W0-W4 are used for function return values. • The first eight working registers (W0-W7) are used for function parameters. Data Type char int short M. Deloizy
Number of Registers Required 1 1 1 186
dsPIC30F2023
Compilateur C
pointer 1 long 2 (contiguous – aligned to even numbered register) float 2 (contiguous – aligned to even numbered register) double* 2 (contiguous – aligned to even numbered register) long double 4 (contiguous – aligned to quad numbered register) structure 1 register per 2 bytes in structure • Return Value o W0 for 8- or 16-bit scalars o W1:W0 for 32-bit scalars o W3:W2:W1:W0 for 64-bit scalars. o Aggregates are returned indirectly through W0, which is set up by the function caller to contain the address of the aggregate value. XII.5.c
Données constantes
• Rangées dans section .const mappée dans la fenêtre définie par PSVPAG (p 23) • PSVPAG est initialisé par le compilateur
M. Deloizy
187
dsPIC30F2023
Compilateur C
XII.5.d Exemples
♦ Observation du code int Add(int a, int b) { return a+b; } volatile int X; void main(void) { X=Add(3,4); if(X Vk-1 + DVmax Vk = Vk-1 + DVmax extraction de v'k à partir de Vk ⇒ application de la nouvelle commande Rem. : Vk-1 : valeur précédente de Vk → utilisation d'une variable statique.
M. Deloizy
218
dsPIC30F2023
ANNEXES
XV ANNEXE : BUS I²C XV.1 Description • Développé initialement par Philips • Bus de type série synchrone o Bidirectionnel o Multi maîtres o Multi points o Chaque point a une adresse • 2 fils (+ GND) : o SDA : données o SCL : horloge • Lignes bidirectionnelles o Collecteur ouvert (nécessite une résistance de tirage) o Au repos : état haut
M. Deloizy
219
dsPIC30F2023
ANNEXES •
•
Vitesse : o standard : 100 kbits/s o rapide (fast) : 400 kbits/s o très rapide (high speed) : 3,4 Mbits/s Versions : o 1.0 (1992) : suppression de la possibilité de programmer l’adresse d’un point mode fast ajouté format d’adresse sur 10 bits ajouté o 2.0 (1998) : mode high speed (Hs-mode) ajouté adaptation pour dispositifs alimentés en 2 volts o 2.1 (2000) : modification des timings du mode Hs
M. Deloizy
220
dsPIC30F2023
ANNEXES
XV.2 Spécifications • SDA doit être stable quand SCL=1 SDA peut changer quand SCL=0
M. Deloizy
221
dsPIC30F2023
ANNEXES •
•
Début de message : START (S) o Front descendant sur SDA quand SCL=1 Fin de message : STOP (P) o Front montant de SDA quand SCL=1
START et STOP sont générés par le maître o START ⇒ bus occupé o STOP ⇒ bus devient libre (après un délai) XV.3 Transfert des données • Par octet • 8 bits transmis (b7 en tête), puis bit acknowledge (ACK) • ACK : o L’émetteur met la ligne SDA à 1 o Le récepteur met la ligne SDA à 0 o Le maître génère l’impulsion d’horloge o Si un esclave souhaite marquer une pause (gestion interne), il peut forcer SCL à 0 pour forcer le maître à attendre •
M. Deloizy
222
dsPIC30F2023
ANNEXES
o Si un esclave ne génère pas ACK sur son adresse (par ex. s’il est occupé), ACK doit rester à 1. Le maître peut alors générer : Un STOP (fin du transfert) Un START (nouveau transfert) o Si un esclave génère un ACK sur son adresse, puis sur les données suivantes et qu’à un instant donné il cesse de générer ACK : le maître doit cesser le transfert • possibilité transmission plusieurs octets (bit ACK toujours présent) Transfert de données sur le bus
ACK sur le bus
M. Deloizy
223
dsPIC30F2023
ANNEXES
Transfert de données complet
XV.4 Format avec adresse sur 7 bits • Chaque point a une adresse propre sur 7 bits • Le maître envoie : o START o L’adresse de l’esclave sur 7 bits (b6 en tête) o Le sens du transfert sur 1 bit (R/W) • L’esclave doit générer ACK M. Deloizy
224
dsPIC30F2023
ANNEXES
• Les données sont transférées (terminées par ACK, sauf éventuellement la dernière) • Le maître envoie STOP Émission de données du maître vers un esclave
Réception de données de l’esclave vers le maître
Format combiné (Lectures / écritures successives)
M. Deloizy
225
dsPIC30F2023
ANNEXES
XV.5
Chronogrammes
PARAMETER
SYMBOL
STANDARD-MODE MIN.
FAST-MODE
MAX.
MIN.
UNIT
MAX.
SCL clock frequency
fSCL
0
100
0
400
kHz
Hold time (repeated) START condition. After this period, the first clock pulse is generated
tHD;STA
4.0
–
0.6
-
ms
LOW period of the SCL clock
tLOW
4.7
–
1.3
–
ms
tHIGH
4.0
–
0.6
–
ms
tSU;STA
4.7
–
0.6
–
ms
5.0 0(2)
– 3.45(3)
– 0.9(3)
ms ms
–
ns
HIGH period of the SCL clock Set-up time for a repeated START condition Data hold time:
tHD;DAT for CBUS compatible masters for I2C-bus devices
Data set-up time
tSU;DAT
250
-
– 0(2) 100(4)
Rise time of both SDA and SCL signals
tr
–
1000
20 + 0.1Cb(5)
300
ns
Fall time of both SDA and SCL signals
tf
–
300
20 + 0.1Cb(5)
300
ns
Set-up time for STOP condition Bus free time between a STOP and START condition Capacitive load for each bus line Noise margin at the LOW level for each connected device (including hysteresis)
M. Deloizy
tSU;STO
4.0
–
0.6
–
ms
tBUF
4.7
–
1.3
–
ms
Cb
–
400
–
400
pF
VnL
0.1VDD
–
0.1VDD
–
V
226
dsPIC30F2023
ANNEXES Noise margin at the HIGH level for each connected device (including hysteresis)
VnH
0.2VDD
–
0.2VDD
–
V
1. All values referred to VIHmin and VILmax levels (see Table 4). 2. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL. 3. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal. 4. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSU;DAT ³ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCL line is released. 5. Cb = total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall-times according to Table 6 are allowed.
M. Deloizy
227
dsPIC30F2023
ANNEXES
XV.6
Mise en œuvre
unsigned char I2cInit(void); • Initialisation du bus I²C void I2cStart(void); • Génère START sur le bus I²C unsigned char I2cMasterWrite(unsigned char x); • Émission de x sur le bus I²C • Renvoie 1 si ACK reçu, 0 sinon unsigned char I2cMasterRead(unsigned char ack) ; • Réception d’un octet sur le bus I²C • ack : état de ACK à générer après la réception de l’octet (0 : ACK, 1 : NOACK) • Renvoie l’octet reçu M. Deloizy
228
dsPIC30F2023
ANNEXES
unsigned char I2cStop(void); • Génère STOP sur le bus I²C • Renvoie 0 si Ok, 1 sinon (SCL maintenue à 0 par ???) XV.7
Documentations
XV.7.a RTC PCF8563
The PCF8563 contains sixteen 8-bit registers with an auto-incrementing address register, an on-chip 32.768 kHz oscillator with one integrated capacitor, a frequency divider which provides the source clock for the M. Deloizy
229
dsPIC30F2023
ANNEXES
Real Time Clock/calender (RTC), a programmable clock output, a timer, an alarm, a voltage-low detector and a 400 kHz I2C-bus interface. All 16 registers are designed as addressable 8-bit parallel registers although not all bits are implemented. The first two registers (memory address 00H and 01H) are used as control and/or status registers. The memory addresses 02H through 08H are used as counters for the clock function (seconds up to years counters). Address locations 09H through 0CH contain alarm registers which define the conditions for an alarm. Address 0DH controls the CLKOUT output frequency. 0EH and 0FH are the timer control and timer registers, respectively. The seconds, minutes, hours, days, weekdays, months, years as well as the minute alarm, hour alarm, day alarm and weekday alarm registers are all coded in BCD format. When one of the RTC registers is read the contents of all counters are frozen. Therefore, faulty reading of the clock/calendar during a carry condition is prevented.
M. Deloizy
230
dsPIC30F2023
ANNEXES
M. Deloizy
231
dsPIC30F2023
ANNEXES
M. Deloizy
232
dsPIC30F2023
ANNEXES
M. Deloizy
233
dsPIC30F2023
ANNEXES
M. Deloizy
234
dsPIC30F2023
ANNEXES
♦ Master transmits to slave receiver (write mode) :
M. Deloizy
235
dsPIC30F2023
ANNEXES
♦ Master reads after setting word address (write word address; read data).
XV.7.b 24C65 64K 5.0V I2C™Smart Serial™ EEPROM
♦ Device Addressing A control byte is the following the start master device. The a four bit control code, as 1010 binary for read The next three bits of the device select bits used by the master M. Deloizy
first byte received condition from the control byte consists of for the 24C65 this is set and write operations. the control byte are (A2, A1, A0). They are device to select which 236
dsPIC30F2023
ANNEXES
of the eight devices are to be accessed. These bits are in effect the three most significant bits of the word address. The last bit of the control byte (R/W) defines the operation to be performed. When set to a one a read operation is selected, when set to a zero a write operation is selected. The next two bytes received define the address of the first data byte (Figure 4-1). Because only A12..A0 are used, the upper three address bits must be zeros. The most significant bit of the most significant byte is transferred first. Following the start condition, the 24C65 monitors the SDA bus checking the device type identifier being transmitted. Upon receiving a 1010 code and appropriate device select bits, the slave device (24C65) outputs an acknowledge signal on the SDA line. Depending upon the state of the R/W bit, the 24C65 will select a read or write operation. ♦ Byte Write Following the start condition from the master, the control code (four bits), the device select (three bits), and the R/W bit which is a logic low is placed onto the bus by the master transmitter. This indicates to the addressed slave receiver (24C65) that a byte with a word address will follow after it has generated an acknowledge bit during the ninth clock cycle. Therefore the next byte transmitted by the master is the high-order M. Deloizy
237
dsPIC30F2023
ANNEXES
byte of the word address and will be written into the address pointer of the 24C65. The next byte is the least significant address byte. After receiving another acknowledge signal from the 24C65 the master device will transmit the data word to be written into the addressed memory location. The 24C65 acknowledges again and the master generates a stop condition. This initiates the internal write cycle, and during this time the 24C65 will not generate acknowledge signals. BYTE WRITE :
♦ Random Read Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, first the word address must be set. This is done by sending the word address to the 24C65 as part of a write operation (R/W bit set to 0). After the word address is sent, the master generates a start condition following the acknowledge. This terminates the write operation, but not before the internal address pointer is set. Then the master issues the M. Deloizy 238 dsPIC30F2023
ANNEXES
control byte again but with the R/W bit set to a one. The 24C65 will then issue an acknowledge and transmit the eight bit data word. The master will not acknowledge the transfer but does generate a stop condition which causes the 24C65 to discontinue transmission. RANDOM READ
XV.7.c DAC5571 8-BIT DIGITAL-TO-ANALOG CONVERTER
The DAC5571 contains four separate modes of operation. These modes are programmable via two bits (PD1 and PD0). When both bits are set to zero, the device works normally with normal power consumption of 150 μA at 5 V. However, for the three power-down modes, the supply current falls to 200 nA at 5 V (50 nA at 3 V). Not only does the supply current fall but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. This has the advantage that the output M. Deloizy
239
dsPIC30F2023
ANNEXES
impedance of the device is known while in power-down mode. There are three different options: The output is connected internally to AGND through a 1-kΩ resistor, a 100-kΩ resistor, or it is left open-circuited (high impedance).
M. Deloizy
240
dsPIC30F2023
Table des matières
M. Deloizy
241
dsPIC30F2023
