Study of Fin Profiles and MuGFETs built on SOI Wafers with a Nitride-Oxide Buried Layer (NOx-BL) as the Buried Insulator Layer Paul Patruno1, Marek Kostrzewa2, Weize Xiong3, C. Rinn Cleavelin3, Che-Hua Hsu 4, Mike Ma4, Jean-Pierre Colinge 5 1. SOITEC S.A., Parc Technologique des Fontaines – 38190 Bernin, France 2. CEA LETI-MINATEC, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France 3. Texas Instruments Inc, SiTD, 13121 TI Boulevard, Dallas, TX USA 4. Central R&D Division, United Microelectronics Corporation (UMC), No. 3, Li-Hsin Rd. II, Hsin-Chu City, Taiwan 5. Tyndall National Institute, Cork, Ireland Email: [email protected], Tel :1-512-891-0974 ABSTRACT Chemical Vapor Deposition at 780°C on the donor Multiple-Gate-MOSFETs (MuGFET) have better wafers. The donor wafers were then subjected to H2 ion short-channel effects (SCE) control than planar implantation with a dose and energy in the typical range MOSFET and MuGFETs are good candidates to replace used for standard SOI. The base wafer was prepared by planar bulk MOSFET for Low Power Applications [1]. thermal growth of 70 nm thick silicon dioxide layers. A key feature in the MuGFETs is the recess and Both donor and base wafers were cleaned and then undercut of the fins in the buried oxide. Undercut bonded. After the SmartCutTM splitting and layer improves gate control of the channel at fin and BOx transfer, the additional steps (polishing and annealing) interface [2,3], but also undermines the fin stability, and achieved a very smooth silicon surface of required increases susceptibility to gate etch defects. This paper thickness. No dislocations or stacking faults are observed introduces SOI wafers with nitride buried dielectric that in the silicon upper layer. Fig 3 and Fig. 4 eliminates the undercut, while maintaining good gate III. Device Characterization control of the channel through higher buried insulator NOx-BL wafers and standard SOI control wafers dielectric constant. were used in this study. All SOI wafers have 70nm Si I. Introduction top layer. Standard SOI wafers have 145nm SiO2 BOx. Omega-Gate and Pi-Gate MOSFETs take advantage The three NOx-BL wafers are a split for Si3N4 thickness. of the undercut in the buried oxide to improve electrode The split consists of 10, 20, 30nm Si3N4 on top of 70 nm static control of the channel at the fin and buried oxide SiO2. All wafers went through MuGFET processing interface [2,3]. The undercut in the buried oxide is an similar to [1], including HF-last pre-gate clean. inherent by-product of pre-gate clean (HF based As expected, the standard SiO2 BOx shows 21nm isotropic wet etch). Such under-cut undermines the fin recess (Fig. 5a), while NOx-BL yielded negligible recess stability (Fig. 1). Furthermore during gate etching, the (Fig. 5b and Fig. 5c) gate material hiding in the under-cut region is difficult to Both MuGFET and planar FD-SOI MOSFETs were remove and is a source of gate to gate electrical short if characterized. Fig. 6 shows similar Vt roll-off behavior not etched completely. for NOx-BL MuGFET and for the control SOI MuGFET In this paper we present an alternative SOI substrate, with 21nm BOx recess. Despite the lack of recess, NOxNOx-BL, with a high-k (NOx) insulating Buried Layer, BL tri-gate devices have similar SCE as the control. which eliminates undercut while maintaining a good gate We found a large shift (>100mV) in NMOS Vt for electrode static control of the channel bottom interface. NOx-BL MuGFET, while PMOS Vt shift was small The capacitive coupling between the gate and the bottom (Fig. 6). The lowered Vtn is the result of a secondary of the fin increases with the dielectric constant of the back channel conduction, which can be eliminated with a buried insulator. Fig. 2 shows the potential distribution large back gate bias (Fig. 7). NMOS Vt shift is larger for of a tri-gate MOSFET with different bottom insulators at Planar FDSOI than it is for MuGFET (Fig. 8). The threshold. The gate exerts a better control of the fin observations above indicate a large positive charge exists bottom through a higher K value insulator than oxide, in the buried nitride layer. This charge cause secondary thus, retaining the advantage of the Pi-Gate structure back channel conduction for NMOS at the Si and buried without any recess in the insulator. nitride interface, therefore shift Vt. Planar FDSOI Vt II. NOx-BL Substrate Fabrication by SmartCutTM shift is almost 1V larger than the MuGFET, since the Si3N4 has a K value of 7.5, and is resistant to HF MuGFET has much smaller body effect factor [7] and chemical used in pre-gate dielectric clean. If Si3N4 were larger relative parasitic transistor width. used as the buried insulator, we would have no under IV. CONCLUSION cut. We have reported the successful fabrication of Silicon on Nitride was at first realized by implanting MuGFET on an advanced SOI with NOx-BL substrate. nitrogen into the silicon, referred as SIMON process The nitride film in the NOx-BL acts as an etch-stop layer [4,5], Silicon on Insulating Nitride-Oxide Multilayer to prevent BOx recess and fin undercut. Current nitride substrates were recently fabricated using the SmartCutTM and Si interface still have large positive charge that technology [6] and called NOx-BL SOI. The silicon degrades NMOS performance. nitride (Si3N4) layer was deposited by Low Pressure

Fig. 1: TEM cross-section of Pi-Gate MOSFET fin. Large undercut in the Box.

Fig.3: TEM cross section of a processed SOI wafer with NOx-BL stack: Poly+ Metal top layer on Si3N4 30 nm / SiO2 70 nm / Si bulk substrate

Fig. 4: Optical view (incident light) of assplit Si top layer / Si3N4 30 nm / SiO2 70 nm / Si bulk substrate (200 mm of diameter)

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Fig. 2: Potential Distribution of Tri-Gate MOSFET at threshold. High-K buried insulator improves the gate control of the channel at the fin-BOx interface: Fins are 40x40nm. Gate dielectric is 2nm SiO2.

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Fig. 7: IdVg curves NMOS NOx-BL Tri-Gate. Positive charges at the silicon and buried insulator interface induced a back channel conduction (Humps), which is eliminated with negative back bias.

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Fig. 5: Fin under-cut profiles (a) standard buried SiO2 recess is 21nm (b) recess on 10nm Si3N4 on top of SiO2 and c) 30nm Si3N4 is less than 3nm

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Lg (um) Fig. 6: Linear Vt roll off as a function of Lg. NOx-BL Tri-Gate has similar SCE as 21nm recessed SiO2 BOx Pi-Gate MOSFET

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Reference W. Xiong et al, ECS Spring 2007 Conference Proceedings J.T. Park et al, IEEE Electron Device Letters, pp. 405-406, Aug., 2001 F.-L. Yang et al, IEDM, pp. 255-258, 2002 W. Skorupa et al, Nucl. Instr. and Meth. in Phys. Research, Vol B32, p. 440, 1988 L. Nesbit et al, J. Electrochemical Soc., Vol. 133 p. 1186, 1986 M. Kostrzewa, private communication, 2006 and O. Rayssac et al, SOI Technology and Devices, ECS Proc., PV01-03, 39, 2001 J. Frei et al, IEEE Electron Device Letter p. 813, Dec., 2004