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PRINCIPLES AND TECHNIQUES Section 1. Information, Communication, Noise, and Interference

1.3

Section 2. Systems Engineering and Systems Management

2.1

Section 3. Reliability

3.1

Section 4. Computer-Assisted Digital System Design

4.1

On the CD-ROM Basic Phenomena Mathematics, Formulas, Definitions, and Theorems Circuit Principles

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PRINCIPLES AND TECHNIQUES

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Source: STANDARD HANDBOOK OF ELECTRONIC ENGINEERING

SECTION 1

INFORMATION, COMMUNICATION, NOISE, AND INTERFERENCE The telephone profoundly changed our methods of communication, thanks to Alexander Graham Bell and other pioneers (Bell, incidentally, declined to have a telephone in his home!). Communication has been at the heart of the information age. Electronic communication deals with transmitters and receivers of electromagnetic waves. Even digital communications systems rely on this phenomenon. This section of the handbook covers information sources, codes and coding, communication channels, error correction, continuous and band-limited channels, digital data transmission and pulse modulation, and noise and interference. C.A.

In This Section: CHAPTER 1.1 COMMUNICATION SYSTEMS CONCEPTS SELF-INFORMATION AND ENTROPY ENTROPY OF DISCRETE RANDOM VARIABLES MUTUAL INFORMATION AND JOINT ENTROPY CHAPTER 1.2 INFORMATION SOURCES, CODES, AND CHANNELS MESSAGE SOURCES MARKOV INFORMATION SOURCE NOISELESS CODING NOISELESS-CODING THEOREM CONSTRUCTION OF NOISELESS CODES CHANNEL CAPACITY DECISION SCHEMES THE NOISY-CODING THEOREM ERROR-CORRECTING CODES PARITY-CHECK CODES OTHER ERROR-DETECTING AND ERROR-CORRECTING CODES CONTINUOUS-AMPLITUDE CHANNELS MAXIMIZATION OF ENTROPY OF CONTINUOUS DISTRIBUTIONS GAUSSIAN SIGNALS AND CHANNELS BAND-LIMITED TRANSMISSION AND THE SAMPLING THEOREM

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1.7 1.7 1.7 1.8 1.9 1.12 1.12 1.13 1.14 1.15 1.16 1.17 1.19 1.20 1.21 1.23 1.25 1.25 1.26 1.27 1.29

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INFORMATION, COMMUNICATION, NOISE, AND INTERFERENCE

CHAPTER 1.3 MODULATION MODULATION THEORY ELEMENTS OF SIGNAL THEORY DURATION AND BANDWIDTH–UNCERTAINTY RELATIONSHIPS CONTINUOUS MODULATION LINEAR, OR AMPLITUDE, MODULATION DOUBLE-SIDEBAND AMPLITUDE MODULATION (DSBAM) DOUBLE-SIDEBAND AMPLITUDE MODULATION, SUPPRESSED CARRIER VESTIGIAL-SIDEBAND AMPLITUDE MODULATION (VSBAM) SINGLE-SIDEBAND AMPLITUDE MODULATION (SSBAM) BANDWIDTH AND POWER RELATIONSHIPS FOR AM ANGLE (FREQUENCY AND PHASE) MODULATION

1.32 1.32 1.33 1.36 1.37 1.38 1.39 1.40 1.41 1.41 1.41 1.42

CHAPTER 1.4 DIGITAL DATA TRANSMISSION AND PULSE MODULATION DIGITAL TRANSMISSION PULSE-AMPLITUDE MODULATION (PAM) QUANTIZING AND QUANTIZING ERROR SIGNAL ENCODING BASEBAND DIGITAL-DATA TRANSMISSIONS PULSE-CODE MODULATION (PCM) SPREAD-SPECTRUM SYSTEMS

1.44 1.44 1.44 1.45 1.46 1.48 1.50 1.51

CHAPTER 1.5 NOISE AND INTERFERENCE GENERAL RANDOM PROCESSES CLASSIFICATION OF RANDOM PROCESSES ARTIFICIAL NOISE

1.52 1.52 1.52 1.54 1.55

Section Bibliography: Of Historical Significance Davenport, W. B., Jr., and W. L. Root, “An Introduction to the Theory of Random Signals and Noise,” McGraw-Hill, 1958. (Reprint edition published by IEEE Press, 1987.) Middleton, D., “Introduction to Statistical Communication Theory,” McGraw-Hill, 1960. (Reprint edition published by IEEE Press, 1996.) Sloane, N. J. A., and A. D. Wyner (eds.), “Claude Elwood Shannon: Collected Papers,” IEEE Press, 1993. General Carlson, A. B., et al., “Communications Systems,” 4th ed., McGraw-Hill, 2001. Gibson, J. D., “Principles of Digital and Analog Communications,” 2nd ed., Macmillan, 1993. Haykin, S., “Communication Systems,” 4th ed., Wiley, 2000. Papoulis, A., and S. U. Pillai, “Probability, Random Variables, and Stochastic Processes,” 4th ed., McGraw-Hill, 2002. Thomas, J. B., “An Introduction to Communication Theory and Systems,” Springer-Verlag, 1987. Ziemer, R. E., and W. H. Tranter, “Principles of Communications: Systems, Modulation, and Noise,” 5th ed., Wiley, 2001. Information Theory Blahut, R. E., “Principles and Practice of Information Theory,” Addison-Wesley, 1987. Cover, T. M., and J. A. Thomas, “Elements of Information Theory,” Wiley, 1991. Gallagher, R., “Information Theory and Reliable Communication,” Wiley, 1968.

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Coding Theory Blahut, R. E., “Theory and Practice of Error Control Codes,” Addison-Wesley, 1983. Clark, G. C., Jr., and J. B. Cain, “Error-correction Coding for Digital Communications,” Plenum Press, 1981. Lin, S., and D. J. Costello, “Error Control Coding,” Prentice-Hall, 1983. Digital Data Transmission Barry, J. R., D. G. Messerschmitt, and E. A. Lee, “Digital Communications,” 3rd ed., Kluwer, 2003. Proakis, J. G., “Digital Communications,” 4th ed., McGraw-Hill, 2000.

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CHAPTER 1.1

COMMUNICATION SYSTEMS Geoffrey C. Orsak, H. Vincent Poor, John B. Thomas

CONCEPTS The principal problem in most communication systems is the transmission of information in the form of messages or data from an originating information source S to a destination or receiver D. The method of transmission is frequently by means of electric signals under the control of the sender. These signals are transmitted via a channel C, as shown in Fig. 1.1.1. The set of messages sent by the source will be denoted by {U}. If the channel were such that each member of U were received exactly, there would be no communication problem. However, because of channel limitations and noise, a corrupted version {U*} of {U} is received at the information destination. It is generally desired that the distorting effects of channel imperfections and noise be minimized and that the number of messages sent over the channel in a given time be maximized. These two requirements are interacting, since, in general, increasing the rate of message transmission increases the distortion or error. However, some forms of message are better suited for transmission over a given channel than others, in that they can be transmitted faster or with less error. Thus it may be desirable to modify the message set {U} by a suitable encoder E to produce a new message set {A} more suitable for a given channel. Then a decoder E −1 will be required at the destination to recover {U*} from the distorted set {A*}. A typical block diagram of the resulting system is shown in Fig. 1.1.2.

SELF-INFORMATION AND ENTROPY Information theory is concerned with the quantification of the communications process. It is based on probabilistic modeling of the objects involved. In the model communication system given in Fig. 1.1.1, we assume that each member of the message set {U} is expressible by means of some combination of a finite set of symbols called an alphabet. Let this source alphabet be denoted by the set {X} with elements x1, x2, . . . , xM, where M is the size of the alphabet. The notation p(xi), i = 1, 2, . . . , M, will be used for the probability of occurrence of the ith symbol xi. In general the set of numbers {p(xi)} can be assigned arbitrarily provided that p(xi) ≥ 0

i = 1, 2, . . . , M

(1)

and M

∑=1 p( xi ) = 1

(2)

i

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FIGURE 1.1.1

Basic communication system.

A measure of the amount of information contained in the ith symbol xi can be defined based solely on the probability p(xi). In particular, the self-information I(xi) of the ith symbol xi is defined as I(xi) = log 1/p(xi) = −log p(xi)

(3)

This quantity is a decreasing function of p(xi) with the endpoint values of infinity for the impossible event and zero for the certain event. It follows directly from Eq. (3) that I(xi) is a discrete random variable, i.e., a real-valued function defined on the elements xi of a probability space. Of the various statistical properties of this random variable I(xi), the most important is the expected value, or mean, given by M

M

i =1

i =1

E{I ( xi )} = H ( X ) = ∑ p( xi ) I ( xi ) = − ∑ p( xi ) log p( xi )

(4)

This quantity H(X) is called the entropy of the distribution p(xi). If p(xi) is interpreted as the probability of the ith state of a system in phase space, then this expression is identical to the entropy of statistical mechanics and thermodynamics. Furthermore, the relationship is more than a mathematical similarity. In statistical mechanics, entropy is a measure of the disorder of a system; in information theory, it is a measure of the uncertainty associated with a message source. In the definitions of self-information and entropy, the choice of the base for the logarithm is arbitrary, but of course each choice results in a different system of units for the information measures. The most common bases used are base 2, base e (the natural logarithm), and base 10. When base 2 is used, the unit of I(⋅) is called the binary digit or bit, which is a very familiar unit of information content. When base e is used, the unit is the nat; this base is often used because of its convenient analytical properties in integration, differentiation, and the like. The base 10 is encountered only rarely; the unit is the Hartley.

ENTROPY OF DISCRETE RANDOM VARIABLES The more elementary properties of the entropy of a discrete random variable can be illustrated with a simple example. Consider the binary case, where M = 2, so that the alphabet consists of the symbols 0 and 1 with probabilities p and 1 − p, respectively. It follows from Eq. (4) that H1(X) = −[p log2 p + (1 − p) log2 (1 − p)] (bits)

FIGURE 1.1.2

Communication system with encoding and decoding.

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Equation (5) can be plotted as a function of p, as shown in Fig. 1.1.3, and has the following interesting properties: 1. H1(X) ≥ 0. 2. H1(X) is zero only for p = 0 and p = 1. 3. H1(X) is a maximum at p = 1 − p = 1/2. More generally, it can be shown that the entropy H(X) has the following properties for the general case of an alphabet of size M: 1. H(X) ≥ 0. (6) 2. H(X) = 0 if and only if all of the probabilities are zero FIGURE 1.1.3 Entropy in the binary case. except for one, which must be unity. (7) 3. H(X) ≤ logb M. (8) 4. H(X) = logb M if and only if all the probabilities are equal so that p(xi) = 1/M for all i. (9)

MUTUAL INFORMATION AND JOINT ENTROPY The usual communication problem concerns the transfer of information from a source S through a channel C to a destination D, as shown in Fig. 1.1.1. The source has available for forming messages an alphabet X of size M. A particular symbol x1 is selected from the M possible symbols and is sent over the channel C. It is the limitations of the channel that produce the need for a study of information theory. The information destination has available an alphabet Y of size N. For each symbol xi sent from the source, a symbol yj is selected at the destination. Two probabilities serve to describe the “state of knowledge” at the destination. Prior to the reception of a communication, the state of knowledge of the destination about the symbol xj is the a priori probability p(xi) that xi would be selected for transmission. After reception and selection of the symbol yj, the state of knowledge concerning xi is the conditional probability p(xi yj), which will be called the a posteriori probability of xi. It is the probability that xi was sent given that yj was received. Ideally this a posteriori probability for each given yj should be unity for one xi and zero for all other xi. In this case an observer at the destination is able to determine exactly which symbol xi has been sent after the reception of each symbol yj. Thus the uncertainty that existed previously and which was expressed by the a priori probability distribution of xi has been removed completely by reception. In the general case it is not possible to remove all the uncertainty, and the best that can be hoped for is that it has been decreased. Thus the a posteriori probability p(xi yj) is distributed over a number of xi but should be different from p(xi). If the two probabilities are the same, then no uncertainty has been removed by transmission or no information has been transferred. Based on this discussion and on other considerations that will become clearer later, the quantity I(xi; yj) is defined as the information gained about xi by the reception of yj, where I(xi; yj) = logb [p(xi yj)/p(xi)]

(10)

This measure has a number of reasonable and desirable properties. Property 1.

The information measure I(xi; yj) is symmetric in xi and yj; that is, I(xi; yj) = I(yj; xi)

(11)

The mutual information I(xi; yj) is a maximum when p(xi yj) = 1, that is, when the reception of yj completely removes the uncertainty concerning xi: Property 2.

I(xi; yj) ≤ − log p(xi) = (xi)

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INFORMATION, COMMUNICATION, NOISE, AND INTERFERENCE

If two communications yj and zk concerning the same message xi are received successively, and if the observer at the destination takes the a posteriori probability of the first as the a priori probability of the second, then the total information gained about xi is the sum of the gains from both communications:

Property 3.

I(xi; yj, zk) = I(xi; yj) + I(xi; zk yj)

(13)

Property 4. If two communications yj and yk concerning two independent messages xi and xm are received, the total information gain is the sum of the two information gains considered separately:

I(xi, xm; yj, yk) = I(xi; yj) + I(xm; yk)

(14)

These four properties of mutual information are intuitively satisfying and desirable. Moreover, if one begins by requiring these properties, it is easily shown that the logarithmic definition of Eq. (10) is the simplest form that can be obtained. The definition of mutual information given by Eq. (10) suffers from one major disadvantage. When errors are present, an observer will not be able to calculate the information gain even after the reception of all the symbols relating to a given source symbol, since the same series of received symbols may represent several different source symbols. Thus, the observer is unable to say which source symbol has been sent and at best can only compute the information gain with respect to each possible source symbol. In many cases it would be more desirable to have a quantity that is independent of the particular symbols. A number of quantities of this nature will be obtained in the remainder of this section. The mutual information I(xi; yj) is a random variable just as was the self-information I(xi); however, two probability spaces X and Y are involved now, and several ensemble averages are possible. The average mutual information I(X; Y ) is defined as a statistical average of I(xi; yj) with respect to the joint probability p(xi; yj); that is, I ( X ; Y ) = E XY {I ( xi ; y j )} = ∑ ∑ p( xi , y j ) log[ p( xi y j ) /p( xi )] i

(15)

j

This new function I(X; Y ) is the first information measure defined that does not depend on the individual symbols xi or yj.. Thus, it is a property of the whole communication system and will turn out to be only the first in a series of similar quantities used as a basis for the characterization of communication systems. This quantity I(X; Y ) has a number of useful properties. It is nonnegative; it is zero if and only if the ensembles X and Y are statistically independent; and it is symmetric in X and Y so that I(X; Y) = I(Y; X). A source entropy H(X) was given by Eq. (4). It is obvious that a similar quantity, the destination entropy H(Y), can be defined analogously by N

H (Y ) = − ∑ p( y j ) log p( y j )

(16)

j =1

This quantity will, of course, have all the properties developed for H(X). In the same way the joint or system entropy H(X, Y ) can be defined by M

N

H ( X , Y ) = − ∑ ∑ p( xi , y j ) log p( xi , y j ) i =1 j =1

(17)

If X and Y are statistically independent so that p(xi, yj) = p(xi)p( yj) for all i and j, then Eq. (17) can be written as H(X, Y ) = H(X ) + H(Y )

(18)

On the other hand, if X and Y are not independent, Eq. (17) becomes H(X, Y ) = H(X ) + H(Y X ) = H(Y ) + H(XY)

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where H(Y X ) and H(X Y ) are conditional entropies given by M

N

H (Y X ) = − ∑ ∑ p( xi , y j ) log p( y j xi )

(20)

i =1 j =1

and by M

N

H ( X Y ) = − ∑ ∑ p( xi , y j ) log p( xi y j ) i =1 j =1

(21)

These conditional entropies each satisfies an important inequality 0 ≤ H(Y H) ≤ H(Y )

(22)

0 ≤ H(X Y) ≤ H(X)

(23)

and

It follows from these last two expressions that Eq. (15) can be expanded to yield I(X; Y) = −H(X, Y) + H(X) + H(Y) ≥ 0

(24)

This equation can be rewritten in the two equivalent forms I(X; Y ) = H(Y) − H(Y X) ≥ 0

(25)

I(X Y) = H(X ) − H(X Y) ≥ 0

(26)

or

It is also clear, say from Eq. (24), that H(X, Y) satisfies the inequality H(X, Y) ≤ H(X ) + H(Y)

(27)

Thus, the joint entropy of two ensembles X and Y is a maximum when the ensembles are independent. At this point it may be appropriate to comment on the meaning of the two conditional entropies H(Y X) and H(X Y). Let us refer first to Eq. (26). This equation expresses the fact that the average information gained about a message, when a communication is completed, is equal to the average source information less the average uncertainty that still remains about the message. From another point of view, the quantity H(X Y) is the average additional information needed at the destination after reception to completely specify the message sent. Thus, H(X Y) represents the information lost in the channel. It is frequently called the equivocation. Let us now consider Eq. (25). This equation indicates that the information transmitted consists of the difference between the destination entropy and that part of the destination entropy that is not information about the source; thus the term H(Y X) can be considered a noise entropy added in the channel.

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Source: STANDARD HANDBOOK OF ELECTRONIC ENGINEERING

CHAPTER 1.2

INFORMATION SOURCES, CODES, AND CHANNELS Geoffrey C. Orsak, H. Vincent Poor, John B. Thomas

MESSAGE SOURCES As shown in Fig. 1.1.1, an information source can be considered as emitting a given message ui from the set {U} of possible messages. In general, each message ui will be represented by a sequence of symbols xj from the source alphabet {X}, since the number of possible messages will usually exceed the size M of the source alphabet. Thus sequences of symbols replace the original messages ui, which need not be considered further. When the source alphabet {X} is of finite size M, the source will be called a finite discrete source. The problems of concern now are the interrelationships existing between symbols in the generated sequences and the classification of sources according to these interrelationships. A random or stochastic process xi, t  T, can be defined as an indexed set of random variables where T is the parameter set of the process. If the set T is a sequence, then xt is a stochastic process with discrete parameter (also called a random sequence or series). One way to look at the output of a finite discrete source is that it is a discrete-parameter stochastic process with each possible given sequence one of the ensemble members or realizations of the process. Thus the study of information sources can be reduced to a study of random processes. The simplest case to consider is the memoryless source, where the successive symbols obey the same fixed probability law so that the one distribution p(xi) determines the appearance of each indexed symbol. Such a source is called stationary. Let us consider sequences of length n, each member of the sequence being a realization of the random variable xi with fixed probability distribution p(xi). Since there are M possible realizations of the random variable and n terms in the sequence, there must be Mn distinct sequences possible of length n. Let the random variable Xi in the jth position be denoted by Xij so that the sequence set (the message set) can be represented by {U} = Xn = {Xi1, Xi2, . . . , Xin}

i = 1, 2, . . . , M

(1)

The symbol Xn is sometimes used to represent this sequence set and is called the nth extension of the memoryless source X. The probability of occurrence of a given message ui is just the product of the probabilities of occurrence of the individual terms in the sequence so that p{ui} = p(xi1)p(xi2) . . . p{xin}

(2)

Now the entropy for the extended source Xn is H ( X n ) = − ∑ p{ui }log p{ui } = nH ( X ) xn

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1.13

as expected. Note that, if base 2 logarithms are used, then H(X) has units of bits per symbol, n is symbols per sequence, and H(Xn) is in units of bits per sequence. For a memoryless source, all sequence averages of information measures are obtained by multiplying the corresponding symbol by the number of symbols in the sequence.

MARKOV INFORMATION SOURCE The memoryless source is not a general enough model in most cases. A constructive way to generalize this model is to assume that the occurrences of a given symbol depends on some number m of immediately preceeding symbols. Thus the information source can be considered to produce an mth-order Markov chain and is called an mth-order Markov source. For an mth-order Markov source, the m symbols preceding a given symbol position are called the state sj of the source at that symbol position. If there are M possible symbols xi, then the mth-order Markov source will have Mm = q possible states sj making up the state set S = {s1, s2, … , sq}

q = Mm

(4)

At a given time corresponding to one symbol position the source will be in a given state sj. There will exist a probability p(sk sj) = pjk that the source will move into another state sk with the emission of the next symbol. The set of all such conditional probabilities is expressed by the transition matrix T, where  p11 p12   p21 p22 T = [ p jk ] =   ... ...   pq1 pq 2

... ... ... ...

p1q   p2 q   ...   pqq  

(5)

A Markov matrix or stochastic matrix is any square matrix with nonnegative elements such that the row sums are unity. It is clear that T is such a matrix since q

q

j =1

j =1

∑ pij = ∑ p(s j si ) = 1

i = 1, 2, . . . , q

(6)

Conversely, any stochastic matrix is a possible transition matrix for a Markov source of order m, where q = Mm is equal to the number of rows or columns of the matrix. A Markov chain is completely specified by its transition matrix T and by an initial distribution vector p giving the probability distribution for the first state occurring. For the memoryless source, the transition matrix reduces to a stochastic matrix where all the rows are identical and are each equal to the initial distribution vector p, which is in turn equal to the vector giving the source alphabet a priori probabilities. Thus, in this case, we have p jk = p(sk s j ) = p(sk ) = p( x k )

k = 1, 2, . . . , M

(7)

For each state si of the source an entropy H(si) can be defined by q

M

j =1

k =1

H (si ) = − ∑ p(s j si ) log p(s j si ) = − ∑ p( x k si ) log p( x k si )

(8)

The source entropy H(S) in information units per symbol is the expected value of H(si); that is, q

q

q

M

H (S ) = − ∑ ∑ p(si ) p(s j si ) log p(s j si ) = − ∑ ∑ p(si ) p( x k si ) log p( x k si ) i =1 j =1

i =1 k =1

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where p(si) = pi is the stationary state probability and is the ith element of the vector P defined by P = [p1 p2 · · · pq]

(10)

It is easy to show, as in Eq. (8), that the source entropy cannot exceed log M, where M is the size of the source alphabet {X}. For a given source, the ratio of the actual entropy H(S) to the maximum value it can have with the same alphabet is called the relative entropy of the source. The redundancy h of the source is defined as the positive difference between unity and this relative entropy:

η =1 −

H (S ) log M

(11)

The quantity log M is sometimes called the capacity of the alphabet.

NOISELESS CODING The preceding discussion has emphasized the information source and its properties. We now begin to consider the properties of the communication channel of Fig. 1.1.1. In general, an arbitrary channel will not accept and transmit the sequence of xi’s emitted from an arbitrary source. Instead the channel will accept a sequence of some other elements ai chosen from a code alphabet A of size D, where A = {a1, a2, . . . , aD}

(12)

with D generally smaller than M. The elements ai of the code alphabet are frequently called code elements or code characters, while a given sequence of ai’s may be called a code word. The situation is now describable in terms of Fig. 1.1.2, where an encoder E has been added between the source and channel. The process of coding, or encoding, the source consists of associating with each source symbol xi a given code word, which is just a given sequence of ai’s. Thus the source emits a sequence of ai’s chosen from the source alphabet A, and the encoder emits a sequence of ai’s chosen from the code alphabet A. It will be assumed in all subsequent discussions that the code words are distinct, i.e., that each code word corresponds to only one source symbol. Even though each code word is required to be distinct, sequences of code words may not have this property. An example is code A of Table 1.2.1, where a source of size 4 has been encoded in binary code with characters 0 and 1. In code A the code words are distinct, but sequences of code words are not. It is clear that such a code is not uniquely decipherable. On the other hand, a given sequence of code words taken from code B will correspond to a distinct sequence of source symbols. An examination of code B shows that in no case is a code word formed by adding characters to another word. In other words, no code word is a prefix of another. It is clear that this is a sufficient (but not necessary) condition for a code to be uniquely decipherable. That it is not necessary can be seen from an examination of codes C and D of Table 1.2.1. These codes are uniquely decipherable even though many of the code words are prefixes of other words. In these cases any sequence of code words can be decoded by subdividing the sequence of 0s and 1s to the left of every 0 for code C and to the right of every 0 for code D. The character 0 is the first (or last) character of every code word and acts as a comma; therefore this type of code is called a comma code. TABLE 1.2.1 Four Binary Coding Schemes Source symbol

Code A

Code B

Code C

Code D

x1 x2 x3 x4

0 1 00 11

0 10 110 111

0 01 011 0111

0 10 110 1110

Note: Code A is not uniquely decipherable; codes B, C, and D are uniquely decipherable; codes B and D are instantaneous codes; and codes C and D are comma codes.

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1.15

In general the channel will require a finite amount of time to transmit each code character. The code words should be as short as possible in order to maximize information transfer per unit time. The average length L of a code is given by M

L = ∑ ni p( xi )

(13)

i =1

where ni is the length (number of code characters) of the code word for the source symbol xi and p(xi) is the probability of occurrence of xi. Although the average code length cannot be computed unless the set {p(xi)} is given, it is obvious that codes C and D of Table 1.2.1 will have a greater average length than code B unless p(x4) = 0. Comma codes are not optimal with respect to minimum average length. Let us encode the sequence x3x1x3x2 into codes B, C, and D of Table 1.2.1 as shown below: Code B: Code C: Code D:

110011010 011001101 110011010

Codes B and D are fundamentally different from code C in that codes B and D can be decoded word by word without examining subsequent code characters while code C cannot be so treated. Codes B and D are called instantaneous codes while code C is noninstantaneous. The instantaneous codes have the property (previously maintained) that no code word is a prefix of another code word. The aim of noiseless coding is to produce codes with the two properties of (1) unique decipherability and (2) minimum average length L for a given source S with alphabet X and probability set {p(xi)}. Codes which have both these properties will be called optimal. It can be shown that if, for a given source S, a code is optimal among instantaneous codes, then it is optimal among all uniquely decipherable codes. Thus it is sufficient to consider instantaneous codes. A necessary property of optimal codes is that source symbols with higher probabilities have shorter code words; i.e., p( xi ) > p( x j ) ⇒ ni ≤ n j

(14)

The encoding procedure consists of the assignment of a code word to each of the M source symbols. The code word for the source symbol xi will be of length ni; that is, it will consist of ni code elements chosen from the code alphabet of size D. It can be shown that a necessary and sufficient condition for the construction of a uniquely decipherable code is the Kraft inequality M

∑ D− n

i

≤1

(15)

i =1

NOISELESS-CODING THEOREM It follows from Eq. (15) that the average code length L, given by Eq. (13), satisfies the inequality L ≥ H(X)/log D

(16)

Equality (and minimum code length) occurs if and only if the source-symbol probabilities obey p(xi) = D−ni

i = 1, 2, . . . , M

(17)

A code where this equality applies is called absolutely optimal. Since an integer number of code elements must be used for each code word, the equality in Eq. (16) does not usually hold; however, by using one more code element, the average code length L can be bounded from above to give H(X)/log D ≤ L ≤ H(X)/log D + 1 This last relationship is frequently called the noiseless-coding theorem.

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INFORMATION SOURCES, CODES, AND CHANNELS 1.16

INFORMATION, COMMUNICATION, NOISE, AND INTERFERENCE

CONSTRUCTION OF NOISELESS CODES The easiest case to consider occurs when an absolutely optimal code exists; i.e., when the source-symbol probabilities satisfy Eq. (17). Note that code B of Table 1.2.1 is absolutely optimal if p(x1) = 1/2, p(x2) = 1/4, and p(x3) = p(x4) = 1/8. In such cases, a procedure for realizing the code for arbitrary code-alphabet size (D ≥ 2) is easily constructed as follows: 1. Arrange the M source symbols in order of decreasing probability. 2. Arrange the D code elements in an arbitrary but fixed order, i.e., a1, a2, . . . , aD. 3. Divide the set of symbols xi into D groups with equal probabilities of 1/D each. This division is always possible if Eq. (17) is satisfied. 4. Assign the element a1 as the first digit for symbols in the first group, a2 for the second, and ai for the ith group. 5. After the first division each of the resulting groups contains a number of symbols equal to D raised to some integral power if Eq. (17) is satisfied. Thus, a typical group, say group i, contains Dki symbols, where ki is an integer (which may be zero). This group of symbols can be further subdivided ki times into D parts of equal probabilities. Each division decides one additional code digit in the sequence. A typical symbol xi is isolated after q divisions. If it belongs to the i1 group after the first division, the i2 group after the second division, and so forth, then the code word for xi will be ai1 ai2 . . . aiq. An illustration of the construction of an absolutely optimal code for the case where D = 3 is given in Table 1.2.2. This procedure ensures that source symbols with high probabilities will have short code words and vice versa, since a symbol with probability D−ni will be isolated after ni divisions and thus will have ni elements in its code word, as required by Eq. (17).

TABLE 1.2.2 Construction of an Optimal Code; D = 3 Source symbols xi

A priori probabilities p(xi)

Step 1

2

3

Final code

x1

1/3

1

1

x2

1/9

0

1

0

x3

1/9

0

0

0

0

x4

1/9

0

–1

0

–1

x5

1/27

–1

1

1

–1

1

x6

1/27

–1

1

0

–1

1

0

x7

1/27

–1

1

–1

–1

1

–1

x8

1/27

–1

0

1

–1

0

1

x9

1/27

–1

0

0

–1

0

0

x10

1/27

–1

0

–1

–1

0

–1

x11

1/27

–1

–1

1

–1

–1

1

x12

1/27

–1

–1

0

–1

–1

0

x13

1/27

–1

–1

–1

–1

–1

–1

1

1

Note: Average code length L = 2 code elements per symbol: source entropy H(X) = 2 log2 3 bits per symbol. L=

H (X ) log2 3

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1.17

TABLE 1.2.3 Construction of Huffman Code; D = 2

The code resulting from the process just discussed is sometimes called the Shannon-Fano code. It is apparent that the same encoding procedure can be followed whether or not the source probabilities satisfy Eq. (17). The set of symbols xi is simply divided into D groups with probabilities as nearly equal as possible. The procedure is sometimes ambiguous, however, and more than one Shannon-Fano code may be possible. The ambiguity arises, of course, in the choice of approximately equiprobable subgroups. For the general case where Eq. (17) is not satisfied, a procedure owing to Huffman guarantees an optimal code, i.e., one with minimum average length. This procedure for code alphabet of arbitrary size D is as follows: 1. As before, arrange the M source symbols in order of decreasing probability. 2. As before, arrange the code elements in an arbitrary but fixed order, that is, a1, a2, . . . , aD. 3. Combine (sum) the probabilities of the D least likely symbols and reorder the resulting M − (D − 1) probabilities; this step will be called reduction 1. Repeat as often as necessary until there are D ordered probabilities remaining. Note: For the binary case (D = 2), it will always be possible to accomplish this reduction in M − 2 steps. When the size of the code alphabet is arbitrary, the last reduction will result in exactly D ordered probabilities if and only if M = D + n(D − 1) where n is an integer. If this relationship is not satisfied, dummy source symbols with zero probability should be added. The entire encoding procedure is followed as before, and at the end the dummy symbols are thrown away. 4. Start the encoding with the last reduction which consists of exactly D ordered probabilities; assign the element a1 as the first digit in the code words for all the source symbols associated with the first probability; assign a2 to the second probability; and ai to the ith probability. 5. Proceed to the next to the last reduction; this reduction consists of D + (D − 1) ordered probabilities for a net gain of D − 1 probabilities. For the D new probabilities, the first code digit has already been assigned and is the same for all of these D probabilities; assign a1 as the second digit for all source symbols associated with the first of these D new probabilities; assign a2 as the second digit for the second of these D new probabilities, etc. 6. The encoding procedure terminates after 1 + n(D − 1) steps, which is one more than the number of reductions. As an illustration of the Huffman coding procedure, a binary code is constructed in Table 1.2.3.

CHANNEL CAPACITY The average mutual information I(X; Y) between an information source and a destination was given by Eqs. (25) and (26) as I(X; Y) = H(Y) − H(Y X) = H(X) − H(X Y ) ≥ 0

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INFORMATION SOURCES, CODES, AND CHANNELS 1.18

INFORMATION, COMMUNICATION, NOISE, AND INTERFERENCE

The average mutual information depends not only on the statistical characteristics of the channel but also on the distribution p(xi) of the input alphabet X. If the input distribution is varied until Eq. (19) is a maximum for a given channel, the resulting value of I(X; Y) is called the channel capacity C of that channel; i.e., C = max I (X; Y ) p ( xi )

(20)

In general, H(X), H(Y ), H(X Y ), and H(Y X) all depend on the input distribution p(xi). Hence, in the general case, it is not a simple matter to maximize Eq. (19) with respect to p(xi). All the measures of information that have been considered in this treatment have involved only probability distributions on X and Y. Thus, for the model of Fig. 1.1.1, the joint distribution p(xi, yj) is sufficient. Suppose the source [and hence the input distribution p(xi)] is known; then it follows from the usual conditional-probability relationship p(xi, yj) = p(xi)p(yj xi)

(21)

that only the distribution p(yj xi) is needed for p(xi yj) to be determined. This conditional probability p(yj xi) can then be taken as a description of the information channel connecting the source X and the destination Y. Thus, a discrete memoryless channel can be defined as the probability distribution xi  X and yj  Y

p(yj xi)

(22)

or, equivalently, by the channel matrix D, where  p( y1 x1 ) p( y2 x 2 ) . . . p( yN x1 )     p( y1 x 2 ) p( y2 x 2 ) . . . p( yN x 2 )  D = [ p( y j | xi )] =       p( y1 x M ) ... . . . p( yN x M ) 

(23)

A number of special types of channels are readily distinguished. Some of the simplest and/or most interesting are listed as follows: (a) Lossless Channel. Here H(X Y) = 0 for all input distribution p(xi), and Eq. (20) becomes C = max H ( X ) = log M p( xi )

(24)

This maximum is obtained when the xi are equally likely, so that p(xi) = 1/M for all i. The channel capacity is equal to the source entropy, and no source information is lost in transmission. (b) Deterministic Channel. Here H(Y X) = 0 for all input distributions p(xi), and Eq. (20) becomes C = max H (Y ) = log N p ( xi )

(25)

This maximum is obtained when the yj are equally likely, so that p(yj) = 1/N for all j. Each member of the X set is uniquely associated with one, and only one, member of the destination alphabet Y. (c) Symmetric Channel. Here the rows of the channel matrix D are identical except for permutations, and the columns are identical except for permutations. If D is square, rows and columns are identical except for permutations. In the symmetric channel, the conditional entropy H(Y X) is independent of the input distribution p(xi) and depends only on the channel matrix D. As a consequence, the determination of channel capacity is greatly simplified and can be written N

C = log N + ∑ p( y j xi ) log p( y j xi ) j =1

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1.19

This capacity is obtained when the yi are equally likely, so that p(yj) = 1/N for all j. (d) Binary Symmetric Channel (BSC). This is the special case of a symmetric channel where M = N = 2. Here the channel matrix can be written  p 1 − p D=  p  1 − p

(27)

and the channel capacity is C = log 2 − G(p)

(28)

where the function G(p) is defined as G(p) = −[p log p + (1 − p) log (1 − p)]

(29)

This expression is mathematically identical to the entropy of a binary source as given in Eq. (5) and is plotFIGURE 1.2.1 Capacity of the binary symmetric channel. ted in Fig. 1.1.3 using base 2 logarithms. For the same base, Eq. (28) is shown as a function of p in Fig. 1.2.1. As expected, the channel capacity is large if p, the probability of correct transmission, is either close to unity or to zero. If p = 1/2, there is no statistical evidence which symbol was sent and the channel capacity is zero.

DECISION SCHEMES A decision scheme or decoding scheme B is a partitioning of the Y set into M disjoint and exhaustive sets B1, B2, … , BM such that when a destination symbol yk falls into set Bi, it is decided that symbol xi was sent. Implicit in this definition is a decision rule d(yj), which is a function specifying uniquely a source symbol for each destination symbol. Let p(e yj) be the probability of error when it is decided that yj has been received. Then the total error probability p(e) is N

p(e) = ∑ p( y j ) p(e y j ) j =1

(30)

For a given decision scheme b, the conditional error probability p(e yj) can be written p(e yj) = 1 − p[d(yj) yj]

(31)

where p[d(yj) yj] is the conditional probability p(xi yj) with xi assigned by the decision rule; i.e., for a given decision scheme d(yj) = xi. The probability p(yj) is determined only by the source a priori probability p(xi) and by the channel matrix = D [p(yj xi)]. Hence, only the term p(e yj) in Eq. (30) is a function of the decision scheme. Since Eq. (30) is a sum of nonnegative terms, the error probability is a minimum when each summand is a minimum. Thus, the term p(e yj) should be a minimum for each yj. It follows from Eq. (31) that the minimumerror scheme is that scheme which assigns a decision rule d(yj) = x*

j = 1, 2, . . . , N

(32)

where x* is defined by p(x* yj) ≥ p(xi yj)

i = 1, 2, . . . , M

(33)

In other words, each yj is decoded as the a posteriori most likely xi. This scheme, which minimizes the probability of error p(e), is usually called the ideal observer.

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INFORMATION SOURCES, CODES, AND CHANNELS 1.20

INFORMATION, COMMUNICATION, NOISE, AND INTERFERENCE

The ideal observer is not always a completely satisfactory decision scheme. It suffers from two major disadvantages: (1) For a given channel D, the scheme is defined only for a given input distribution p(xi). It might be preferable to have a scheme that was insensitive to input distributions. (2) The scheme minimizes average error but does not bound certain errors. For example, some symbols may always be received incorrectly. Despite these disadvantages, the ideal observer is a straightforward scheme which does minimize average error. It is also widely used as a standard with which other decision schemes may be compared. Consider the special case where the input distribution is p(xi) = 1/M for all i, so that all xi are equally likely. Now the conditional likelihood p(xi yj) is p( xi | y j ) =

p( xi ) p( y j xi ) p( y j )

=

p( y j xi ) Mp( y j )

(34)

For a given yj, that input xi is chosen which makes p(yj xi) a maximum, and the decision rule is d(yj) = x†

j = 1, 2, . . . , N

(35)

where x† is defined by p(yj x†) ≥ p(yj xi)

i = 1, 2, . . . , M

(36)

The probability of error becomes N  p( y j x † )  p(e) = ∑ p( y j ) 1 −  Mp( y j )   j =1

(37)

This decoder is sometimes called the maximum-likelihood decoder or decision scheme. It would appear that a relationship should exist between the error probability p(e) and the channel capacity C. One such relationship is the Fano bound, given by H(X Y) ≤ G[p(e)] + p(e) log (M − 1)

(38)

and relating error probability to channel capacity through Eq. (20). Here G(⋅) is the function already defined by Eq. (29). The three terms in Eq. (38) can be interpreted as follows: H(X Y) is the equivocation. It is the average additional information needed at the destination after reception to completely determine the symbol that was sent. G[p(e)] is the entropy of the binary system with probabilities p(e) and 1 − p(e). In other words, it is the average amount of information needed to determine whether the decision rule resulted in an error. log (M − 1) is the maximum amount of information needed to determine which among the remaining M − 1 symbols was sent if the decision rule was incorrect; this information is needed with probability p(e).

THE NOISY-CODING THEOREM The concept of channel capacity was discussed earlier. Capacity is a fundamental property of an information channel in the sense that it is possible to transmit information through the channel at any rate less than the channel capacity with arbitrarily small probability of error. This result is called the noisy-coding theorem or Shannon’s fundamental theorem for a noisy channel. The noisy-coding theorem can be stated more precisely as follows: Consider a discrete memoryless channel with nonzero capacity C; fix two numbers H and  such that 0 binary representation of decimal value -input valid only between 0-9 but can handle -15-0 but anything above 9 will default to zero -- Output : LS7seg -> seven segment display decimal representation of -Least Significant Digit of counter -MS7seg -> seven segment display decimal representation of -Most Significant Digit of Counter -- Chip : 10K70RC240-4 -- Board : Altera University Program Development Board UP2 --- NOTE : Must Compile These Files and have them -in the same folder -1) counter.vhd -2) clkdivider.vhd -3) sevensegdisplay.vhd --This program creates a program that joins all -of the subprograms compiled before --I/O pin numbers are can be predefined in the -.acf file -I/O pin number verification be seen in the -.rpt file --- ****************************************************************** -- Include Libraries LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; -- ****************************************************************** -- Declaration of INPUT & OUTPUT variables -- ENTITY must have a reference which is the same as the file name ENTITY completesystem IS PORT( clk : IN std_logic; LSreg : IN std_logic_vector(3 MSreg : IN std_logic_vector(3 Reset_Switch : IN std_logic; LS7seg : OUT std_logic_vector(6 MS7seg : OUT std_logic_vector(6 DP7seg : OUT std_logic_vector(1 Buzer : OUT std_logic); END completesystem; -- ******************************************************************

DOWNTO 0); DOWNTO 0); DOWNTO 0); DOWNTO 0); DOWNTO 0);

FIGURE 4.1.10 VHDL code for the complete system component that links all the other components together.

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-- ****************************************************************** -- The actual body of the program -ARCHITECTURE arch OF completesystem IS -- component declaration -- files which are interconnected to make up the entire file -- include: -file name -inputs -outputs COMPONENT clkdivider PORT( clk_high : IN STD_LOGIC; clk_low : OUT STD_LOGIC); END COMPONENT; COMPONENT counter PORT( clk update LSDigit MSDigit Reset_Flag LSDigit_out MSDigit_out Buzer END COMPONENT; COMPONENT sevensegdisplay PORT( LSinput MSinput LSdisplay MSdisplay DPdisplay END COMPONENT;

: : : : : : : :

IN IN IN IN IN OUT OUT OUT

STD_LOGIC; STD_LOGIC; STD_LOGIC_VECTOR(3 STD_LOGIC_VECTOR(3 STD_LOGIC; STD_LOGIC_VECTOR(3 STD_LOGIC_VECTOR(3 STD_LOGIC);

: : : : :

IN IN OUT OUT OUT

STD_LOGIC_VECTOR(3 STD_LOGIC_VECTOR(3 STD_LOGIC_VECTOR(6 STD_LOGIC_VECTOR(6 STD_LOGIC_VECTOR(1

DOWNTO 0); DOWNTO 0); DOWNTO 0); DOWNTO 0);

DOWNTO DOWNTO DOWNTO DOWNTO DOWNTO

0); 0); 0); 0); 0));

-- interconnection signals -- signals that connect outputs to inputs within the system SIGNAL pulse : STD_LOGIC; SIGNAL BCD_low : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL BCD_high : STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN -- mapping the inputs and outputs to and from each subsystem clkdivider_unit: clkdivider PORT MAP(clk_high=>clk, clk_low=>pulse); counter_unit: counter PORT MAP(clk=>clk, update=>pulse, Reset_Flag=>Reset_Switch, LSDigit=>LSreg, MSDigit=>MSreg, LSDigit_out=>BCD_low, MSDigit_out=>BCD_high, Buzer=>Buzer); sevensegdisplay_unit: sevensegdisplay PORT MAP(LSinput=>BCD_low, MSinput=>BCD_high, LSdisplay=>LS7seg, MSdisplay=>MS7seg, DPdisplay=>DP7seg); END arch; -- ****************************************************************** FIGURE 4.1.10 (Continued) VHDL code for the complete system component that links all the other components together.

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DESIGN OF DIGITAL SYSTEMS USING CAD TOOLS 4.12

COMPUTER-ASSISTED DIGITAL SYSTEM DESIGN

EXAMPLE DESIGN A complete example design will be shown in this section. The example will be the remaining components of the kitchen timer problem. The complete system code has already been shown in Fig. 4.1.10. The remainder of the components shall be shown in Figs. 4.1.11 to 4.1.13. -- ****************************************************************** -- Program Name : clkdivider.vhd -- File Name : desktop\new folder\altera\kitchen timer -- Programed By : Brian Fast -- Date : April 2, 2004 -- Purpose : Clock Divider -take a high frequency clock and output a -lower frequency cycle -- Input : currently configured for system clock (25.175 MHz) -can be changed by changing the constant values -freq_in = input frequency/(2*desired output frequency) -freq_in_switch = (input frequency/(2*desired output frequency))/2 -- Ouput : currently configured for clock signal at (60 Hz) -- Chip : 10K70RC240-4 -- Board : Altera University Program Development Board UP2 -- Software : Altera Max+Plus v10.22 --- NOTE : This file will be used as a black box within -another file so the I/O pins will not be -set within this file. The I/O signals will -be interconnections set within the main program -which is where the I/O pins will be set --Num Description By Date ---------------------------------------------------------------------------------------------------------------------------------------------------- Status : 1.0 Began Initial Program BRF 4/2/2004 -The program is working correctly -The program takes an input frequency -and outputs a lower frequency -which is dependent on the values set -in the constants -freq_in & freq_in_switch -these constants are dependent on the -input frequency and the desired -output frequency -the input output frequency is not -determined but is dependent on the -input frequency output frequency -size of the registers and the -internal speed of the code --------------| freq | -high frequency ---->| divider |---> lower frequency -system clock | | new desire frequency -[clk_high] -----------[clk_low] ---- ****************************************************************** FIGURE 4.1.11 VHDL code for the clock divider component.

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DESIGN OF DIGITAL SYSTEMS USING CAD TOOLS DESIGN OF DIGITAL SYSTEMS USING CAD TOOLS

4.13

-- Include Libraries LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; USE ieee.std_logic_unsigned.ALL; -- ****************************************************************** -- Declaration of INPUT & OUTPUT variables -- ENTITY must have a reference which is the same as the file name ENTITY clkdivider IS PORT( clk_high : IN STD_LOGIC; clk_low : OUT STD_LOGIC); END clkdivider; -- ****************************************************************** -- ****************************************************************** -- The actual body of the program -- This routine is the meat of the frequency divider ARCHITECTURE arch OF clkdivider IS -- Set constant by the equation below -- freq_in = (the input frequency/(2*desired frequency)) -- the max freq_in is dependent on the output frequency CONSTANT freq_in : integer := 12587500; -- Set constant by the equation below -- freq_in_switch = (the input frequency/desired frequency)/2 CONSTANT freq_in_switch : integer := 6293750; -- used for testing --CONSTANT freq_in : integer := 34215; --CONSTANT freq_in_switch : integer := 17107; -- temporary registers used to keep track of how many input signals -- have been input to the system SIGNAL count_now: std_logic_vector(27 DOWNTO 0); SIGNAL count_next: std_logic_vector(27 DOWNTO 0); BEGIN PROCESS(clk_high) BEGIN -- increments count_next each time the input signal -- goes high -- keeps tracked of the number of cycles input by the system clock -- via clk_high if(clk_high ='1' AND clk_high'EVENT) THEN count_next | counter | -[MSDigit] (4 bits) ---->| 0|---> [Buzer] (1 bit) -[Reset_Flag] (1 bit) ---->| | --------------Currently this program is decrementing a 2 seg -BCD counter from the value loaded down to -zero. The program begins when the Reset_Flag -is pulled high and then low. The program -continues to decrement the value until it -reaches zero zero. Then the value remains -zero zero until a new value is loaded. --- ****************************************************************** -- Include Libraries LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; USE ieee.std_logic_unsigned.ALL; -- ****************************************************************** -- Declaration of INPUT & OUTPUT variables -- ENTITY must have a reference which is the same as the file name ENTITY counter IS PORT(

clk update LSDigit MSDigit Reset_Flag LSDigit_out MSDigit_out Buzer

: : : : : : : :

IN IN IN IN IN OUT OUT OUT

STD_LOGIC; STD_LOGIC; STD_LOGIC_VECTOR(3 STD_LOGIC_VECTOR(3 STD_LOGIC; STD_LOGIC_VECTOR(3 STD_LOGIC_VECTOR(3 STD_LOGIC);

DOWNTO 0); DOWNTO 0); DOWNTO 0); DOWNTO 0);

END counter; -- ****************************************************************** -- ****************************************************************** -- The actual body of the program -- This routine is the meat of the frequency divider ARCHITECTURE arch OF counter IS SIGNAL LSDreg_now : std_logic_vector(3 DOWNTO 0); SIGNAL LSDreg_next : std_logic_vector(3 DOWNTO 0); SIGNAL MSDreg_now : std_logic_vector(3 DOWNTO 0); SIGNAL MSDreg_next : std_logic_vector(3 DOWNTO 0); SIGNAL Done_Flag : std_logic; BEGIN ----------------------------------------------------------------- Counter Routine -- counts down the Least Significant Digit until it gets to zero -- then decrements the Most Significant Digit -- then decrements resets Least Significant Digit back to nine -- until it gets to zero zero FIGURE 4.1.12 (Continued ) VHDL code for the counter component.

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DESIGN OF DIGITAL SYSTEMS USING CAD TOOLS 4.16

COMPUTER-ASSISTED DIGITAL SYSTEM DESIGN

-- then the buzzer goes off -- if the initial value set for the input is greater then 9 -- then the initial value will be set to 9 PROCESS(clk) BEGIN IF(clk = '1' AND clk'EVENT) THEN -- checks to see if the value is greater then IF(MSDreg_now > 9 OR LSDreg_now > 9) THEN IF(MSDreg_now > 9) THEN MSDreg_next 9) THEN LSDreg_next 0) THEN LSDreg_next G0G2. These circuits have the property of low sensitivity at the expense of two amplifiers.

SALLEN AND KEY NETWORKS The circuits of Figs. 10.3.12, 10.3.13, and 10.3.14 are low-pass, high-pass, and bandpass circuits, respectively, having a positive gain K. Design of any of these circuits requires choice of suitable linear and quadratic denominator factors, transformation and frequency scaling, and coefficient matching. Since there are more elements

FIGURE 10.3.12 A low-pass active filter network with gain K greater than 0.

FIGURE 10.3.13 A high-pass active filter network with gain K greater than 0.

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10.51

FIGURE 10.3.14 A bandpass active filter network with gain K greater than 0.

to be specified than there are constraints, two elements may be chosen arbitrarily. Often, K = 1 or K = 2 leads to a good network. For Fig. 10.3.12, V2 (s ) = V1

K /( R1R2C1C2 )  1 1 1 1  + + s + (1 − K ) s + C R R R C R C R 2 2 1 1 2 1 1 2C1C2 

(29)

2

For Fig. 10.3.13, V2 (s ) = V1

Ks 2

(30)

 1 1 1  1 + + s2 + (1 − K ) s+ R1C1 R2C2 R2C1  R1R2C1C2 

For Fig. 10.3.14,

V2 (s ) = V1

Ks R1C2  (1 − K ) 1 1 1 1  1  1  1 + + + + s2 +  s +  R + R  R C R C R C R C R C R C C 3 2 1 1 2 1 1 2  1 2  2 2 3 1 2

(31)

CHAIN NETWORK Figure 10.3.15 shows a chain network that realizes low-pass functions and is easily designed. For this circuit,

ω1ω 2ω 3  ω n V2 (s ) = n V1 s + ω1s n−1 + ω1ω 2 s n− 2 +  + ω1ω 2ω 3  ω n

(32)

wi = 1/RiCi

(33)

where

As an example, consider a third-order Bessel filter, for which V2 15 (s ) = 3 2 V1 s + 6s + 15s + 15

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(34)

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FILTERS AND ATTENUATORS

FIGURE 10.3.15 An RC-unity-gain amplifier realization of an active low-pass filter.

Choose 1/R1C1 = 6, 6(1/R2C2) = 15, and 15(1/R3C3) = 15. If all C’s are set to 1.0, then R1 = 1/6, R2 = 2/5, and R3 = 1. Use frequency and impedance scaling as required.

LEAPFROG FILTERS Also called active ladders or multiple feedback filters, these circuits use the tabulated element values from Table 10.1.10 to develop a set of active networks that have the sensitivity characteristics of passive ladders. The process may be extended from low-pass to bandpass networks using the transformation from prototype to bandpass filter disc under “Bandpass Filter” and techniques that will be discussed in this paragraph. The term “leapfrog” was suggested by Girling and Good,28 the inventors, because of the topology. Figure 10.3.16a shows a conventional fourth-order low-pass prototype network, and Fig. 10.3.16b shows a block diagram of a simulation with the same equations, which follow, using Laplace notation. In writing these equations and preparing the block diagram, current terms have been multiplied by an arbitrary constant R so that all variables appear to have the dimensions of voltage. This simplifies the block diagram and later examples. I1 = (V1 – V3)[R/(R1 + sL1)] V3 = (RI1 – RI3)(1/sC2R)

FIGURE 10.3.16 (a) Low-pass prototype ladder filter; (b) block-diagram simulation.

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ACTIVE FILTERS ACTIVE FILTERS

RI3 = (V3 – V2)(R/sL3) V2 = RI 3

10.53

(35)

1 R (1/R4 + sC4 )

Though shown for a specific case, the technique is general and may be extended for any order of ladder network. In the simulation it should be noted that the algebraic signs of the blocks alternate. This variation is important in the realization. In Fig. 10.3.16b, the currents are simulated by voltages, and this suggests the use of operational amplifiers as realization elements. The blocks in simulation require integrations, which the readily achieved with operational amplifiers, resistors, and capacitors. Figure 10.3.17 shows suitable combinations that will realize integrators, both inverting and noninverting, and also lossy integrators, which have a pole in the left half plane, rather than at the origin. Bruton25 shows that, for integration, the circuit of Fig. 10.3.17b has superior performance compared with Fig. 10.3.17a when the imperfections of nonideal operational amplifiers are considered.

FIGURE 10.3.17 Building blocks for leapfrog filters: (a) noninverting integrator, for which V2 /V1 = R4/sC2R1R3; (b) noninverting integrator, for which V2/V1 = R4/sC2R1R3; (c) lossy, summing integrator to realize (V1 – V3)R/(R1 + sL1) = −RI1; (d) lossy, noninverting integrator to realize V2/RI4 = 1/R(1/R4 + sC4).

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FILTERS AND ATTENUATORS

FIGURE 10.3.18 Two arrangements of a leapfrog low-pass circuit: (a) block-diagram arrangement; (b) ladder arrangement.

In Fig. 10.3.18, the combination of these blocks into a circuit is shown. In the preparation of this drawing, the integrator of Fig. 10.3.16b has been used, and the drawing is given in two forms. Figure 10.3.18a follows from the simulation, while Fig. 10.3.18b is a rearrangement that emphasizes the ladder structure. The design of a low-pass leapfrog ladder may be summarized in these steps. 1. Select a normalized low-pass filter from Table 10.1.10 2. Identify the integrations represented by inductors, capacitors, and series resistor-inductor or parallel resistorcapacitor combinations. For each, determine an appropriate block diagram. 3. Connect together, using inverters, summers, and gain adjustment as needed. 4. Apply techniques of frequency and magnitude scaling to achieve a practical circuit.

BANDPASS LEAPFROG CIRCUITS The technique of the previous section may be extended to bandpass circuits. The basic idea follows from the low-pass to bandpass transformation introduced in “Bandpass Filters” and from the recognition that it is possible to build second-order resonators from operational amplifiers, capacitors, and resistors. When the transformation is applied to an inductor, the circuit of Fig. 10.3.19a results. The resistor is added to allow for losses or source/load resistors that may be present. Similarly, the transformation applied to a

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10.55

capacitor yields Fig. 10.3.19b. It is to be noted that the forms of the equations are identical, and since the leapfrog technique makes use of simulation, the realizations will be similar. The necessary equations are given by Eq. (36). Figure 10.3.20 shows an active simulation of a resonant circuit. This circuit is similar to that of Fig. 10.3.8, though the first two stages are interchanged. The new circuit has the advantage that both inverted and noninverted resonant outputs are available. Further, the input allows for summing operations, which may be needed in the leapfrog realization. Appropriate equations are given by Eq. (37). Ys (s) =

FIGURE 10.3.19 Passive resonant circuits: (a) series resonator; (b) parallel resonator.

Vo 2 (s) = −Vo1 (s) =

Z p (s ) =

(1 /Ls )s s + (Rs /Ls ) s + 1 /LsCs 2

(1 /C p )s

(36)

s 2 + (1 /R pC p )s + 1 /L pC p

(1 / R3C1 )s s 2 + (1 / R1C1 )s + 1 / R2 R4C1C2

(V11 + V12 )(s)

(37)

The implementation of this circuit is substantially the same as that of Fig. 10.3.18, with the resonators being used as the blocks of the simulation. Since both inverted and noninverted signals are available, the one needed is chosen. Table 10.3.2 gives the parameters of the active resonators in terms of the transformed series or parallel resonant circuits. Frequency and magnitude scaling may be done either before or after the elements of the active resonator are determined, but it generally is more convenient to do it afterward. An example is given to show this technique. It begins with a third-order Butterworth normalized low-pass filter, Fig. 10.3.21a, which has been taken from Table 10.1.10. The circuit is transformed to a bandpass network

FIGURE 10.3.20 Active resonator.

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FILTERS AND ATTENUATORS

TABLE 10.3.2 Resonator Design Relationships* Circuit parameters from Fig. 10.3.20 R2 = R4 = R R1 R3 R5

Series circuit prototype values from Fig. 10.3.19a

Parallel circuit prototype values from Fig. 10.3.19b

(1 /C ) Ls Cs

(1 /C ) L pC p

R

R C p /L p

R

Ls /C s

R C p /L p

Ls /C s

Choose any convenient value

*In this table it is presumed that C = C = C and that this is chosen to be some convenient value. It is further presumed 1 2 that R2 = R4.

for which the center frequency w0 is 1.0 rad/s and the bandwidth b′ is 0.45 rad/s, corresponding to upper and lower half-power frequencies of 1.25 and 0.80 rad/s. This result is shown as Fig. 10.3.21b. For the first and third stages of the circuit, application of the equations from Table 10.3.2 shows that R1 = R3 = 20/9 Ω, and that all other components have unit value. For the second stage, R1 is infinite, as indicated by the table, and R3 = 9/40 Ω. Other components have unit value. The complete circuit is shown as Fig. 10.3.21c. This circuit has been left in normalized form. Impedance and frequency denormalization techniques must be used to achieve reasonable values.

FIGURE 10.3.21 Leapfrog active resonator realization: (a) low-pass prototype; (b) bandpass transformation, w¢0 = 1.0b′ = 0.45; (c) complete circuit.

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Source: STANDARD HANDBOOK OF ELECTRONIC ENGINEERING

CHAPTER 10.4

SWITCHED CAPACITOR FILTERS Edwin C. Jones, Jr., Harry W. Hale

Switched capacitor filters, also known as analog sampled data filters, result from a new technology that builds on the passive network theory of Darlington and implements the circuits in active-network integrated-circuit forms. Essentially, the switched capacitor replaces the resistor in operational-amplifier circuits, including the resonator. Early work was reported by Allstot, Broderson, Fried, Gray, Hosticka, Jacobs, Kuntz, and others. Huelsman12 and Van Valkenburg16 give additional information. Consider the circuit of Fig. 10.4.1a and the two-phase clock signal of Fig. 10.4.1b. The circuit has two MOS switches and a capacitor C. The clock cycles the MOS switches between their low- and high-resistance states. In the analysis that follows, it is assumed that the clock speed is sufficiently high that a simplified analysis is valid. It is also assumed that the Nyquist sampling theorem is satisfied. It is possible to use discrete circuit analysis and z transforms if some of the approximations are not met. Let the clock be such that switch A is closed and B is open. This may be modeled by Fig. 10.4.1c. The source will charge the capacitor to V1. When the clock cycles so that B is closed and A is open, the capacitor will discharge toward V2, transferring a charge qC = C(V1 – V2) This will require a time TC = 1/fC, yielding an average current iav = C(V1 – V2)/TC corresponding to a resistor Req = (V1 – V2)/iav, or Req = TC /C = 1/(CfC)

(1)

Figure 10.4.2 shows a conventional integrator, a damped integrator, and several sum and difference integrators, along with realizations and transfer functions of circuits implemented with switched capacitors. It is noted that the transfer functions are functions of the ratios of two capacitors, and this fact makes them useful. It is possible in integrated-circuit design to realize the ratio of two capacitors with high precision, leading to accurate designs of filters. With similar techniques it is possible to realize many of the second-order circuits given in earlier sections. Possibly the most important application is in the realization of leapfrog filters. As discussed in the previous section, leapfrog filters use integrators to realize the resonators that are the basic building blocks. In this technology, the resistors of the resonators are replaced by switched capacitors. In essence, the technique is to realize the circuit with resonators, as was done in Fig. 10.3.21, and then to replace the resistors with switched capacitors. Though slightly less complex, the technique for low-pass filters is similar. Consider the low-pass prototype filter of Fig. 10.4.3a. A simulation is shown in Fig. 10.4.3b. This simulation has equations that are identical with those of the prototype. While the simulation is similar to that of Fig. 10.3.16; two important differences may be noted. The first is that the termination resistors are separate,

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SWITCHED CAPACITOR FILTERS 10.58

FILTERS AND ATTENUATORS

FIGURE 10.4.1 Integrators with switched capacitor realizations: (a) conventional integrator; (b) damped or lossy integrator; (c) summing integrator; (d) difference integrator.

rather than being incorporated with the input and output elements. The second is that all the elements have positive signs, and the amplifiers used are different types. This is more convenient. Figure 10.4.3c shows a switched capacitor equivalent for the low-pass filter. The equations for the simulation and for the development of the switched capacitor version follow. RI3 = (V1 – V4)(R/R1) V4 = I5(1/sC3) = (I3 – I6)(R)(1/sC3R) RI6 = (V4 – V6)(R/sL4) V2 = R(I6 – I8)(1/sC5R) RI8 = V2(R/R2)

(2)

As was done previously, the current equations have been nominally multiplied by R so that all terms appear to be voltages. In practice, R may be set to 1.0 as scaling will take care of it.

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SWITCHED CAPACITOR FILTERS

FIGURE 10.4.2 Development of equivalent circuit for a switched capacitor: (a) double MOS switch; (b) two-phase clock; (c) switch A closed; (d) switch B closed; (e) representation; ( f ) double-pole double-throw switch; and (g) representation.

FIGURE 10.4.3 Low-pass switched capacitor filter development; (a) low-pass prototype and definition of equation symbols; C3, L4, and C5 would be obtained from Table 10.1.10; (b) simulation of low-pass prototype; R may be set to 1.0; (c) switched capacitor equivalent network.

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SWITCHED CAPACITOR FILTERS 10.60

FILTERS AND ATTENUATORS

The next step is to determine the capacitor ratios in the final simulation. From Fig. 10.4.2d it may be seen that a typical integrator term is given by fC V2 (s) = c 1 V1 (s) − V0 (s) sC2 Similar results are obtained for the remaining integrators. The prototype values were obtained from Table 10.1.10, including C3, L4, and C5 for this circuit. The similarity of terms then suggests that C3 = (1/fC)(C23/C13) C5 = (1/fC)(C25/C15)

(3)

L4 = (1/fC)(C24/C14)

(4)

Extension to the inductors shows that

As used here, C3, L4, and C5 are prototype values, but they may be magnitude- and frequency-scaled as desired to achieve realistic values. In Eqs. (3) and (4), the ratios C2/C1 are computed after the clock speed is known, and the second subscripts on both numerator and denominator denote which prototype the ratio has been derived from. In general they will differ for each element. In design, it is likely that one of these would be fixed and have a common value for all integrators, thus allowing the other capacitor to vary in each case. Figure 10.4.3c shows the circuit that results. It uses the difference-type integrator of Fig. 10.4.1d. It also shows a method for handling the terminations. It should be noted that the clock phases are adjusted so that alternate integrators have open and closed resistors at a given instant. This is necessary to avoid delay problems. The extension of this technique to bandpass filters is a matter of combining the principles of leapfrog filters and switched capacitor implementation of resistors. From the specifications, a transformation to equivalent low-pass requirements is made, and the low-pass prototype is chosen. This prototype is transformed to a bandpass network, an appropriate simulation is developed, and the network is developed using integrators. Finally, scaling in frequency and magnitude is needed. It is desirable to test these simulations using computer programs designed for analysis of sampled data networks.

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Source: STANDARD HANDBOOK OF ELECTRONIC ENGINEERING

CHAPTER 10.5

CRYSTAL, MECHANICAL, AND ACOUSTIC COUPLED-RESONATOR FILTERS Edwin C. Jones, Jr., Harry W. Hale

In applications such as single-sideband communications it is often necessary to have a bandpass filter with a bandwidth that is a fractional percentage of the center frequency and in which one or both transition regions are very short. Meeting such requirements usually requires a filter in which the resonators are not electrical. Two types of resonator are quartz crystals and mechanical elements, such as disks or rods. Transducers from the electric signal to the mechanical device, output transducers, and resonator-coupling elements are needed. Crystal filters include resonators made from piezoelectric quartz crystals. The transducers are plates of a conductor deposited on the appropriate surfaces of the crystal, and coupling from one crystal to the next is electrical. The center frequency depends on the size of the crystal, its manner of cutting, and the choice of frequency determining modes of oscillation. It can vary from about 1.0 kHz to 100 MHz. If extreme care is taken, equivalent quality factors (Q’s) can be greater than 100,000. These filters can also be very stable with regard to temperature and age. Mechanical filters use rods or disks as resonating elements, which are coupled together mechanically, usually with wires welded to the resonators. The transducers are magnetostrictive. The frequency range varies from as low as 100 Hz to above 500 kHz. Quality factors above 20,000 are possible and, with proper choice of alloys, temperature coefficients of as low as 1.0 ppm/°C are possible. Acoustic filters use a combination of crystal and mechanical filter principles. The resonators are monolithic quartz crystals; the transducers are similar to those of crystal filters, but the coupling is mechanical (referred to as acoustic coupling). These filters have many of the properties of crystal filters, but the design techniques have much in common with those of mechanical filters. Coupled-resonator filters are usually described in terms of an electric equivalent circuit. The direct or mobility analogy (mass to capacitance, friction to conductance, and springs to inductance) is more useful, because the “across” variables of velocity and voltage are analogous, as are the “through” variables of force and current. Equivalent capacitances or inductances and center frequencies are among the common parameters specified for filter elements. The following paragraphs discuss, in general terms, the design procedure used for coupled-resonator filters, the equivalent circuits used, and some network transformations that enable the designer to implement the design procedure. References 6, 8, and 27 give much additional information, and in particular, Ref. 27 contains an extensive discussion and bibliography. Manufacturer’s catalogs are a good source of current data.

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CRYSTAL, MECHANICAL, AND ACOUSTIC COUPLED-RESONATOR FILTERS 10.62

FILTERS AND ATTENUATORS

COUPLED-RESONATOR DESIGN PROCEDURE The insertion-loss low-pass prototype filters can be used to design coupled-resonator bandpass filters. Five steps can be identified in the process, though in some cases the dividing lines become indistinct. 1. Transform the bandpass specifications to a low-pass prototype, using Eq. (8). This will take the center frequency to w = 0 and, usually, the band edge to w = 1. 2. Choose the appropriate low-pass response, e.g., Chebyshev, elliptic, or Butterworth, that meets the transformed specifications. Zeros of transmission are fixed at this time. From this characteristic function determine the transfer function that is needed. The tables presented earlier may be useful. 3. Determine the short-circuit y or open-circuit z parameters from the transfer function. 4. If possible, look up or synthesize the appropriate ladder or lattice network needed. At this point, it is still a low-pass prototype. The technique chosen may depend on the expected form of the final network. 5. Use Fig. 10.2.7 to transform the network into a bandpass network and then use network theorems to adjust the network to a configuration and a set of element values that is practical, i.e., one that matches the resonators. This process is not one in which success is assured. It may require a variety of attempts before a suitable design is achieved. Equivalent circuits and network theorems are summarized in the following paragraphs.

EQUIVALENT CIRCUITS The most common equivalent circuit for a piezoelectric crystal shows a series-resonant RLC circuit in parallel with a second capacitor, as shown in Fig. 10.5.1. The parallel capacitor CP is composed of the mounting hardware and electric plates on the crystal. In practice, the ratio CP /C cannot be reduced below about 125, but it may be increased if needed. When a filter contains more than one crystal, the coupling is electrical, usually with capacitors. Mechanical filters have an equivalent circuit, as indicated in Fig. 10.5.2. The resonant circuits L0, CR represent the transducer magnetostrictive coils and their tuning capacitances. (In cases of small RL, it may be more accurate to place CR in series with L0.) The resonant circuit L1, C1, R1 and Ln, Cn, Rn include the motional parameters of the transducers. Elements L2, C2, R2, . . . , Ln–1, Cn–1, Rn–1 represent the motional parameters of the resonant eleFIGURE 10.5.1 Equivalent circuit for piezoelectric ments, and L12, . . . , Ln–1,n represent the compliances of the crystal. Because coupling is electrical, a one-port reprecoupling wires. sentation is sufficient.

FIGURE 10.5.2 Equivalent circuit for a mechanical filter. A two-port representation allows an electric equivalent circuit for the entire filter.

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10.63

FIGURE 10.5.3 Equivalent circuit for a monolithic crystal or acoustic filter. The one-to-one ideal transformer models the 180° phase shift observed in these filters.

The acoustic filter is represented, after substantial development, by the circuit shown in Fig. 10.5.3. The development has made the circuit easy to use, but the association between the electrical elements and the filter elements is less apparent than in the previous circuits. The ideal transformer at the output accounts for the 180° phase shift observed in these filters. In some analyses, it may be omitted.

NETWORK TRANSFORMATIONS In the process of changing a bandpass circuit to meet the configuration of the equivalent circuit of a coupled resonator a variety of equivalent networks may be useful. At one step negative elements may appear. These can be absorbed later in series or parallel with positive elements so that the overall result is positive. The impedance inverters of Fig. 10.5.4 can be used to invert an impedance, as indicated. Over a very narrow frequency range they can often be approximated with three capacitors, two of which are negative. An inverter can be used to convert an inductance into a capacitance provided the negative elements can then be absorbed. Other similar reactive configurations can also be used. Lattice networks (Fig. 10.5.5) are often used in crystal filters. If the condition prevailing in Fig. 10.5.6 exists, the equivalent can be used in either direction to affect a change. In particular, the ladder can be transformed into a lattice, which then has the crystal equivalent circuit. Two Norton transformations and networks derived from them are shown in Figs. 10.5.7 and 10.5.8. They lead to negative elements, and it is expected that they will later be absorbed into positive elements. Humpherys8 gives another derived Norton transformation that can be used to reduce inductance values. It changes the impedance level on one side of the network. When this is applied to a symmetrical network, the new impedance levels will eventually become directly connected, so that no transformer is needed.

FIGURE 10.5.4 Reactive impedance inverters: (a) T inverter; (b) T inverter with load Z; Zin = X2/Z; (c) p inverter.

FIGURE 10.5.5 Symmetrical lattice. The dotted diagonal line indicates a second Zb; the dotted horizontal line, a second Za.

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FILTERS AND ATTENUATORS

FIGURE 10.5.6 Lattice and ladder: (a) general lattice and equivalent circuit; (b) application to crystal filters.

n −1 Z n Z/n

Z

( 1n− n )

1:n

Z

Z

2

1:n

Z /n

1 Z 1−n 1 Z n(n −1)

(

( a)

Za /n Za

(a)

)

Za /n 1:n

Za Zb /n

Zb

Zb

1:n

Zb /n

n =1 +

Za Zb

( b)

FIGURE 10.5.7 Norton’s first transformation and a derived network.

n=

Zb Za + Z b (b)

FIGURE 10.5.8 Norton’s second transformation and a derived network.

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Source: STANDARD HANDBOOK OF ELECTRONIC ENGINEERING

CHAPTER 10.6

DIGITAL FILTERS* Arthur B. Williams, Fred J. Taylor

RELATION TO ANALOG FILTERS Digital filters provide many of the same frequency selective services (low, high, bandpass) expected of analog filters. In some cases, digital filters are defined in terms of equivalent analog filters. Other digital filters are designed using rules unique to this technology. The hardware required to fabricate a digital filter are basic digital devices such as memory and arithmetic logic units (ALUs). Many of these hardware building blocks provide both high performance and low cost. Coefficients and data are stored as digital computer words and, as a result, provide a precise and noise free (in an analog sense) signal processing medium. Compared to analog filters, digital filters generally enjoy the following advantages: 1. They can be fabricated in high-performance general-purpose digital hardware or with application-specific integrated circuits (ASIC). 2. The stability of certain classes of digital filters can be guaranteed. 3. There are no input or output impedance matching problems. 4. Coefficients can be easily programmed and altered. 5. Digital filters can operate over a wide range of frequencies. 6. Digital filters can operate over a wide dynamic range and with high precision. 7. Some digital filters provide excellent phase linearity. 8. Digital filters do not require periodic alignment and do not drift or degrade because of aging.

DATA REPRESENTATION In an analog filter, all signals and coefficients are considered to be real or complex numbers. As such, they are defined over an infinite range with infinite precision. In the analog case, filter coefficients are implemented with lumped R, L, C, and amplifier components of assumed absolute precision. Along similar lines, the designs of digital filters typically begin with the manipulation of idealized equations. However, the implementation of a digital filter is accomplished using digital computational elements of finite precision (measured in bits). Therefore, the analysis of a digital filter is not complete until the effects of finite precision arithmetic has been

*This

section is based on the author’s Electronic Filter Design Handbook, 3rd ed., McGraw-Hill, 1995.

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FILTERS AND ATTENUATORS

determined. As a result, even though there has been a significant sharing of techniques in the area of filter synthesis between analog and digital filters, the analyses of these two classes of filters have developed separate tools and techniques. Data, in a digital system, are represented as a set of binary-valued digits. The process by which a real signal or number is converted into a digital word is called analog-to-digital conversion (ADC). The most common formats used to represent data are called fixed and floating point (FXP and FLP). Within the fixed-point family of codes, the most popular are binary-coded decimal sign magnitude (SM) and diminished radix (DR) codes. Any integer X such that |X| < 2n–1 has a unique sign-magnitude representation, given by X = Xn – 1: (2n – 2 Xn – 2 + … + 2X1 + X0)

(1)

where Xi is the ith bit and X0 is referred to as the least significant bit (LSB). Similarly Xn – 2 is called the most significant bit (MSB) and Xn – 1 is the sign bit. The LSB often corresponds to a physically measurable electrical unit. For example, if a signed 12-bit ADC is used to digitize a signal whose range is ±15 V, the LSB represents a quantization step size of Q = 30 V (range)/212 – bits = 7.32 mV/bit. Fractional numbers are also possible simply by scaling X by a power of 2. The value of X' = X/2m has the same binary representation of X except that the m LSBs are considered to be fractional bits.

SIGNAL REPRESENTATION An analog filter manipulates real signals of assumed infinite precision. In a discrete system, analog signals of assumed infinite precision are periodically sampled at a rate of f samples per second. The same period is therefore given by ts = 1/fs second(s). A string of contiguous samples is called a time series. If the samples are further processed by an ADC, a digital time series results. A digital filter can be used to manipulate this time series using digital technology. The hardware required to implement such a filter is the product of the microelectronics revolution.

SPECTRAL REPRESENTATION Besides representing signals in the continuous or discrete time domain, signals can also be modeled in the frequency domain. This condition is called spectral representation. The principal tools used to describe a signal in the frequency domain are: (1) Fourier transforms, (2) Fourier series, and (3) discrete Fourier transforms (DFT). A Fourier transform will map an arbitrary transformable signal into a continuous frequency spectrum consisting of all frequency components from –∞ to +∞. The Fourier transform is defined by an indefinite integral equation whose limits range from –∞ to +∞. The Fourier series will map a continuous but periodic signal of period T [i.e., x(t) = x(t + kT) for all integer values of k] into a discrete but infinite spectrum consisting of frequency harmonics located at multiples of the fundamental frequency 1/T. The Fourier series is defined by a definite integral equation whose limits are [0, T]. The discrete Fourier transform differs from the first two transforms in that it does not accept data continuously but rather from a time series of finite length. Also, unlike the first two transforms, which produce spectra ranging out to ±∞ Hz, the DFT spectrum consists of a finite number of harmonics. The DFT is an important and useful tool in the study of digital filters. The DFT can be used to both analyze and design digital filters. One of its principal applications is the analysis of a filter’s impulse response. An impulse response database can be directly generated by presenting a one-sample unit pulse to a digital filter that is initially at a zero state (i.e., zero initial conditions). The output is the filter’s impulse response, which is observed for N contiguous samples. The N-sample database is then presented to an N-point DFT, transformed, and analyzed. The spectrum produced by the DFT should be a reasonable facsimile of the frequency response of the digital filter under test.

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FILTER REPRESENTATION A transfer function is defined by the ratio of output and input transforms. For digital filters, it is given by H(z) = Y(z)/U(z) where U(z) is the z transform of the input signal u(n) and Y(z) is for the output signal y(n). The frequency response of a filter H(z) can be computed using a DFT of the filter’s impulse response. Another transform tool that also is extensively used to study digital filters is the bilinear z transform. While the standard z transform can be related to the simple sample and hold circuit, the bilinear z transform is analogous to a first-order hold. The bilinear z transform is related to the familiar Laplace transform through s=

2( z − 1) ts ( z + 1)

z=

(2/ts ) + s (2/ts ) − s

(2)

Once an analog filter H(s) is defined, it can be converted into a discrete filter H(z) by using the variable substitution rule.

FINITE IMPULSE-RESPONSE (FIR) FILTERS Linear constant coefficient filters can be categorized into two broad classes known as finite impulse-response (FIR) or infinite impulse-response (IIR) filters. An FIR filter can be expressed in terms of a simple discrete equation: y(n) = c0x(n) + c1x(n – 1) + … + cN – 1x(n – N + 1)

(3)

where the coefficients {Ci} are called filter tap weights. In terms of a transfer function, Eq. (3) can be restated as n −1

H ( z ) = ∑ Ci z −1 i=0

(4)

As an example, a typical N = 111th-order FIR is shown in Fig. 10.6.1. The FIR exhibits several interesting features: 1. The filter’s impulse response exists for only N = 111 (finite) contiguous samples. 2. The filter’s transform function consists of zeros only (i.e., no poles). As a result, an FIR is sometimes referred to as an all-zero, or transversal, filter. 3. The filter has a very simple design consisting of a set of word-wide shift registers, tap-weight multipliers, and adders (accumulators). 4. If the input is bounded by united (i.e., |x(i)| ≤ 1 for all i), the maximum value of the output y(i) is Σ|Ci|. If all the tap weights Ci are bounded, the filter’s output is likewise bounded and, as a result, stability is guaranteed. 5. The phase, when plotted with respect to frequency (plot shown over the principal angles ± π/2), is linear with constant slope.

LINEAR PHASE BEHAVIOR The FIR is basically a shift-register network. Since digital shift registers are precise and easily controlled, the FIR can offer the designer several phase domain attributes that are difficult to achieve with analog filters. The most important of these are: (1) Potential for linear phase versus frequency behavior and (2) potential for constant

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FIGURE 10.6.1 Typical FIR architecture, impulse response, and frequency response.

DIGITAL FILTERS*

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group-delay behavior. These properties are fundamentally important in the fields of digital communications systems, phase synchronization systems (e.g., phase-locked loops), speech processing, image processing, spectral analysis (e.g., Fourier analysis), and other areas where nonlinear phase distortion cannot be tolerated.

FIR DESIGN METHODS The design of an FIR entails specifying the filter’s impulse response, tap weights {Ci}. As a result, the design of an FIR can be as simple as prespecifying the desired impulse response. Other acceptable analytical techniques used to synthesize a desired impulse response are the inverse Fourier transform of a given frequency domain filter specification or the use of polynomial approximation techniques. These methods are summarized below. A simple procedure for designing an FIR is to specify an acceptable frequency domain model, invert the filter’s spectral representation using the inverse Fourier transform, and use the resulting time series to represent the filter’s impulse response. In general, the inverse Fourier transform of a desired spectral waveshape would produce an infinitely long time domain record. However, from a hardware cost or throughput standpoint, it is unreasonable to consider the implementing of an infinitely or extremely long FIR. Therefore, a realizable FIR would be defined in terms of a truncated Fourier series. For example, the Fourier transform of the “nearly ideal” N = 101 order low-pass filter has a sin (x)/x type impulse-response envelope. For a large value of N, the difference between the response of an infinitely long impulse response and its N-sample approximation is small; however, when N is small, large approximation errors can occur.

Optimal Modeling Techniques Weighted Chebyshev polynomials have been successfully used to design FIRs. In this application, Chebyshev polynomials are combined so that their combined sum minimizes the maximum difference between an ideal and the realized frequency response (i.e., mini-max principle). Because of the nature of these polynomials, they produce a “rippled” magnitude frequency-response envelope of equal minima and maxima in the pass- and stopbands. As a result, this class of filters is often called an equiripple filter. Much is known about the synthesis process, which can be traced back to McClellan et al.48 Based on these techniques, a number of software-based CAD tools have been developed to support FIR design.

WINDOWS Digital filters usually are expected to operate over long, constantly changing data records. An FIR, while being capable of offering this service, can only work with a limited number of samples at a time. A similar situation presents itself in the context of a discrete Fourier transform. The quality of the produced spectrum is a function of the number of transformed samples. Ideally, an infinitely long impulse response would be defined by an ideal filter. A uniform window of length T will pass N contiguous samples of data. The windowing effect may be modeled as a multiplicative switch that multiplies the presented signal by zero (open) for all time exclusive of the interval [0, T]. Over [0, T], the signal is multiplied by unity (closed). In a sampled system, the interval [0, T] is replaced by N samples taken at a sample rate fs where T = N/fs. When the observation interval (i.e., N) becomes small, the quality of the spectral estimate begins to deteriorate. This consequence is called the finite aperture effect. Windowing is a technique that tends to improve the quality of a spectrum obtained from a limited number of samples. Some of the more popular windows found in contemporary use are the rectangular or uniform window, the Hamming window, the Hann window, the Blackman window, and the Kaiser window. Windows can be directly applied to FIRs. To window an N-point FIR, simply multiply the tap weight coefficients Ci with the corresponding window weights wi. Note that all of the standard window functions have even symmetry about the midsample. As a result, the application of such a window will not disturb the linear phase behavior of the original FIR.

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FILTERS AND ATTENUATORS

MULTIRATE SIGNAL PROCESSING Digital signal processing systems accept an input time series and produce an output time series. In between, a signal can be modified in terms of its time and/or frequency domain attributes. One of the important functions that a digital signal processing system can serve is that of sample rate conversion. As the name implies, a sample rate converter changes a system’s sample rate from a value of fin samples per second to a rate of fout samples per second. Such devices are also called multirate systems since they are defined in terms of two or more sample rates. If fin > fout then the system is said to perform decimation and is said to be decimated by an integer M if M=

fout fin

(5)

In this case, the decimated time series xd[n] = x[Mn], or every Mth sample of the original time series is retained. Furthermore, the effective sample rate is reduced from fin to fdec = fin/M samples per second. Applications of decimation include audio and image signal processing involving two or more subsystems having dissimilar sample rates. Other applications occur when a high data rate ADC is placed at the front end of a system and the output is to be processed parameters that are sampled at a very low rate by a general-purpose digital computer. At other times, multirate systems are used simply to reduce the Nyquist rate to facilitate computational intensive algorithms, such as a digital Fourier analyzer, to be performed at a slower arithmetic rate. Another class of applications involves processing signals, sampled at a high data rate, through a limited bandwidth channel.

QUADRATURE MIRROR FILTERS (QMF) We have stated that multirate systems are often used to reduce the sample rate to a value that can be passed through a band-limited communication channel. Supposedly, the signal can be reconstructed on the receiver side. The amount of allowable decimation has been established by the Nyquist sampling theorem. When the bandwidth of the signal establishes a Nyquist frequency that exceeds the bandwidth of a communication channel, the signal must be decomposed into subbands that can be individually transmitted across band-limited channels. This technique uses a bank of band-limited filters to break the signal down into a collection of subbands that fit within the available channel bandwidths. Quadrature mirror filters (QMF) are often used in the subband application described in Fig. 10.6.2. The basic architecture shown in that figure defines a QMF system and establishes two input-output paths that have a bandwidth requirement that is half the input or output requirements. Using this technique, the channels can be subdivided over and over, reducing the bandwidth by a factor of 2 each time. The top path consists of lowpass filters and the bottom path is formed by high-pass filters.

FIGURE 10.6.2 Quadrature mirror filter (QMF).

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Designing QMF is, unfortunately, not a trivial process. No meaningful flat response linear phase QMF filter exists. Most QMF designs represent some compromise.

INFINITE IMPULSE-RESPONSE FILTER The FIR filter exhibits superb linear phase behavior; however, in order to achieve a high-quality (steep-skirt) magnitude frequency response, a high-order FIR is required. Compared to the FIR, the IIR filter 1. Generally satisfies a given magnitude frequency-response design objective with a lower-order filter. 2. Does not generally exhibit linear phase or constant group-delay behavior. If the principal objective of the digital filter design is to satisfy the prespecified magnitude frequency response, an IIR is usually the design of choice. Since the order of an IIR is usually significantly less than that of an FIR, the IIR would require fewer coefficients. This translates into a reduced multiplication budget and an attendant saving in hardware and cost. Since multiplication is time consuming, a reduced multiplication budget also translates into potentially higher sample rates. From a practical viewpoint, a realizable filter must produce bounded outputs if stimulated by bounded inputs. The magnitude is bounded on an IIR’s impulse response, namely, ∞

∑ | h(n) | < M n=0

(6)

If M is finite (bounded), the filter is stable, and if it is infinite (unbounded), the filter is unstable. This condition can also be more conveniently related to the pole locations of the filter under study. It is well known that a causal discrete system with a rational transfer function H(z) is stable (i.e., bounded inputs produce bounded outputs) if and only if its poles are interior to the unit circle in the z domain. This is often referred to as the circle criterion and it can be tested using general-purpose computer root-finding methods. Other algebraic tests—Schur-Cohen, Routh-Hurwitz, and Nyquist—may also be used. The stability condition is implicit to the FIR as long as all N coefficients are finite. Here the finite sum of real bounded coefficients will always be bounded.

DESIGN OBJECTIVES The design of an IIR begins with a magnitude frequency-response specification of the target filter. The filter’s magnitude frequency response is specified as it would be for an analog filter design. In particular, assume that a filter with a magnitude-squared frequency response given by |H(w)|2, having passband, transition band, and stopband behavior as suggested by Fig. 10.6.3, is to be synthesized. The frequency response of the desired filter is specified in terms of a cutoff critical frequency wp a stopband critical frequency ws and stop- and passband delimiters  and A. The critical frequencies wp and wa represent the end of the passband and the start of the stopband, respectively, for the low-pass example. In decibels, the gains at these critical frequencies are given by (passband ripple constraint) and –Aa = –10 log (A2) (stopband attenuation). For the case where  = 1, the common 3-dB passband filter is realized.

FIR AND IIR FILTERS COMPARED The principal attributes of FIR are its simplicity, phase linearity, and ability to decimate a signal. The strength of the IIR is its ability to achieve high-quality (steep-skirt) filtering with a limited number order design. Those positive characteristics of the FIR are absent in the IIR and vice versa.

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FIGURE 10.6.3 Typical design objective for low-pass, high-pass, and bandstop IIR filters.

The estimated order of an FIR, required to achieve an IIR design specification, was empirically determined by Rabiner. It was found that the approximate order n of an FIR required to meet a design objective 1 δ1 (passband-ripple) 1+ ε2 1 δ 22 = 2 δ 2 (stopband bound) A ∆f (transition frequency range/fs )

(7)

−10 log((1 − δ1 )δ 2 ) − 15 +1 14 ∆f

(8)

(1 − δ1 )2 =

is given by n∼

STANDARD FILTER FORMS The standard filter forms found in common use are: (1) Direct II, (2) Standard, (3) Cascade, and (4) Parallel. These basic filter cases are graphically interpreted in Ref. 52. The direct II and standard architectures are somewhat similar in their structure. Both strategies possess information feedback paths ranging from one

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delay to n delays. The transfer function denominator is an nth-order polynomial. The cascade and parallel models are constructed using a system of low-order subsections or subfilters. In the cascade design, the loworder subsections are serially interconnected. In the parallel filter, these sections are simply connected in parallel. The low-order subfilters, in both cases, are the result of factoring the nth-order transfer function polynomial into lower-order polynomials. The design and analysis of all four classes of filters can be performed using manually manipulated equations or a digital computer. The most efficient method of formulating the filter design problem, whether using tables, calculators, or a computer, is called the state-variable technique. A state variable is a parameter that represents the information stored in a system. The set of state variables is called a state vector. For an analog system, information is stored on capacitors or in inductors. In earlier chapters, state variables were used to specify and facilitate the manipulation of the R, L, and C components of an analog filter. In these cases, capacitive voltage and inductive current were valid state variables. Since resistors have no memory, they would not be the source of a state variable. In digital filters, the memory element, which stores the state information, is simply a delay (shift) register. The realization of digital filters is described in Ref. 52.

FIXED-POINT DESIGN An IIR, once designed and architected, often needs to be implemented in hardware. The choices are fixed- or floating-point. Of the two, fixed-point solutions generally provide the highest real-time bandwidth at the lowest cost. Unfortunately, fixed-point designs also introduce errors that are not found in more expensive floatingpoint IIR designs. The fixed-point error sources are either low-order inaccuracies, because of finite precision arithmetic and data (coefficient) roundoff effects or potentially large errors because of run-time dynamic range overflow (saturation). Additional precision can be gained by increasing the number of fractional bits assigned to the data and coefficients fields with an attendant decrease in dynamic range and an increased potential for runtime overflow. On the other hand, the overflow saturation problem can be reduced by enlarging the dynamic range of the system by increasing the integer bit field with an accompanying loss of precision. The problem facing the fixed-point filter design, therefore, is achieving a balance between the competing desire to maximize precision and to simultaneously eliminate (or reduce) run-time overflow errors. This is called the binary-point assignment problem.

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Source: STANDARD HANDBOOK OF ELECTRONIC ENGINEERING

CHAPTER 10.7

ATTENUATORS Arthur B. Williams, Fred, J. Taylor

ATTENUATOR NETWORK DESIGN Attenuators are passive circuits that introduce a fixed power loss between a source and load while matching impedances. The power loss is independent of the direction of power flow. Figure 10.7.1 shows T, Π, and bridged-T networks. The first two are unbalanced and unsymmetrical, unless ZL = ZS. In this case, Z1 = Z2, and the network is symmetrical. To build an unbalanced network, divide Z1 and Z2 by 2, and put half of each element in each series arm. The bridged-T shown is only for symmetrical networks. These design equations are valid for resistive and complex impedances. ZS = source impedance ZL = load impedance A = ratio of available power to desired load power (dB) = 10B/10 B = 10 log A

(1)

q = 1/2 ln A = 1/2 ln 10B/10 As an example, design an attenuator to match a 75-Ω source to a 300-Ω load and to introduce a 14.0-dB loss. Use a T section. In terms of Eq. (1), Zs = 75 Ω q = 1.612

ZL = 300 Ω Z3 = 62.34 Ω

B = 14.0 dB Z1 = 18.88 Ω

A = 25.12 Z2 = 262.54 Ω

Figure 10.7.2 shows the network.

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ATTENUATORS

ATTENUATORS

FIGURE 10.7.1 Attenuator networks and equations.

FIGURE 10.7.2 A 14.0-dB attenuator between a 75-Ω source and a 300-Ω load.

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Source: STANDARD HANDBOOK OF ELECTRONIC ENGINEERING

SECTION 11

AMPLIFIERS AND OSCILLATORS Amplifiers serve a number of purposes from allowing us to hear beautiful music to accurately positioning elements of complicated systems using control technologies. Oscillators are found in a number of applications from the watch on your wrist to the transmitter and receiver in your cell phone. We look at audio-frequency amplifiers and oscillators and radio-frequency amplifiers and oscillators. The most versatile amplifier has to be the operational amplifier (op amp). The key to its success is that it is perhaps the most ideal device in analog electronics. Because of this it is found in a number of amplifier designs. High-power amplifiers are necessary where significant amounts of power need to be used to accomplish activities such as radio and television broadcasts. Just imagine what a rock concert might sound like without power amplifiers. Microwave amplifiers and oscillators represent a special part of the high-power amplifier and oscillator field. C.A.

In This Section: CHAPTER 11.1 AMPLIFIER AND OSCILLATOR PRINCIPLES OF OPERATION AMPLIFIERS: PRINCIPLES OF OPERATION OSCILLATORS: PRINCIPLES OF OPERATION

11.5 11.5 11.14

CHAPTER 11.2 AUDIO-FREQUENCY AMPLIFIERS AND OSCILLATORS AUDIO-FREQUENCY AMPLIFIERS AUDIO OSCILLATORS

11.18 11.18 11.25

CHAPTER 11.3 RADIO-FREQUENCY AMPLIFIERS AND OSCILLATORS RADIO-FREQUENCY AMPLIFIERS RADIO-FREQUENCY OSCILLATORS BROADBAND AMPLIFIERS TUNNEL-DIODE AMPLIFIERS PARAMETRIC AMPLIFIERS MASER AMPLIFIERS ACOUSTIC AMPLIFIERS MAGNETIC AMPLIFIERS

11.35 11.35 11.43 11.47 11.60 11.64 11.66 11.70 11.79

CHAPTER 11.4 OPERATIONAL AMPLIFIERS DIRECT-COUPLED AMPLIFIERS OPERATIONAL AMPLIFIERS FOR ANALOG ARITHMETIC LOW-NOISE OPERATIONAL AMPLIFIERS POWER OPERATIONAL AMPLIFIERS

11.87 11.87 11.93 11.97 11.99

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AMPLIFIERS AND OSCILLATORS

CHAPTER 11.5 HIGH-POWER AMPLIFIERS THERMAL CONSIDERATIONS HIGH-POWER BROADCAST-SERVICE AMPLIFIERS CLASS B LINEAR RF AMPLIFIERS HIGH-EFFICIENCY POWER AMPLIFIERS INDUCTION HEATING CIRCUITS DIELECTRIC HEATING TRANSISTORS IN HIGH-POWER AMPLIFIERS MOSFET AUDIO AMPLIFIERS AND SWITCHING APPLICATIONS

11.102 11.102 11.102 11.102 11.103 11.103 11.103 11.104 11.105

CHAPTER 11.6 MICROWAVE AMPLIFIERS AND OSCILLATORS MICROWAVE SOLID-STATE DEVICES IMPATT DIODE CIRCUITS TRAPATT DIODE CIRCUITS BARITT AND DOVETT DIODES TRANSFERRED ELECTRON EFFECT DEVICE (TED) CIRCUITS TRANSISTOR AMPLIFIER AND OSCILLATOR MICROWAVE CIRCUITS NOISE PERFORMANCE OF MICROWAVE BIPOLAR TRANSISTOR CIRCUITS HIGH-POWER MICROWAVE TRANSISTOR AMPLIFIERS (USING BIPOLAR TRANSISTORS) GaAs FIELD-EFFECT TRANSISTOR CIRCUITS NOISE PERFORMANCE OF MICROWAVE FET CIRCUITS HIGH ELECTRON MOBILITY TRANSISTORS HIGH-POWER MICROWAVE FET AMPLIFIERS MONOLITHIC MICROWAVE INTEGRATED CIRCUITS TRANSISTOR OSCILLATORS TRAVELING-WAVE-TUBE CIRCUITS KLYSTRON OSCILLATORS AND AMPLIFIERS CROSSED-FIELD-TUBE CIRCUITS GYROTRON CIRCUITS

11.107 11.107 11.107 11.110 11.112 11.113 11.115 11.118 11.119 11.122 11.122 11.122 11.122 11.123 11.123 11.124 11.126 11.127 11.128

Section Bibliography: Classic General References Bode, H. W., “Network Analysis and Feedback Amplifier Design,” Van Nostrand, 1959. (Reprinted 1975 by R. E. Krieger). Ghausi, M. S., and D. O. Pederson, “A new approach to feedback amplifiers,” IRE Trans. Circuit Theory, Vol. CT-4, September 1957. Ginzton, E. L., W. R. Hewlett, J. H. Jasberg, and J. D. Noe, “Distributed amplification,” Proc. IRE, Vol. 20, August 1948. Glasford, G. M., “Fundamentals of Television Engineering,” McGraw-Hill, 1955. Hines, M. E., “High-frequency negative-resistance circuit principles for Esaki diodes,” Bell Syst. Tech. J., Vol. 39, May 1960. Hutson, A. R., J. H. McFee, and D. L. White, “Ultrasonic amplification in CdS,” Phys. Rev. Lett., September 15, 1961. Kim, C. S., and A. Brandli, “High frequency high power operation of tunnel diodes,” IRE Trans. Circuit Theory, December 1962. Millman, J., “Vacuum Tube and Semiconductor Electronics,” McGraw-Hill, 1958. Read, W. T., “A proposal high-frequency negative resistance diode,” Bell Syst. Tech. J., Vol. 37, 1958. Reich, H. J., “Functional Circuits and Oscillators,” Van Nostrand, 1961. Seely, S., “Electron Tube Circuits,” McGraw-Hill, 1950. Shea, R. F. (ed.), “Amplifier Handbook,” McGraw-Hill, 1968. Singer, J. R., “Masers,” Wiley, 1959. Storm, H. F., “Magnetic Amplifiers,” Wiley, 1955. Truxal, J. C., “Automatic Feedback Control System Synthesis,” McGraw-Hill, 1955.

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Specific-Topic and Contemporary References Bahl, I. (ed.), “Microwave Solid State Circuit Design,” Wiley, 1988. Wilson, F. A., “An Introduction to Microwaves,” Babani, 1992. Blackwell, L. A., and K. L. Kotzebue, “Semiconductor-Diode Parametric Amplifiers,” Prentice Hall, 1961. Blotekjaer, K., and C. F. Quate, “The coupled modes of acoustic waves and drifting carriers in piezoelectric crystals,” Proc. IEEE, Vol. 52, No. 4, pp. 360–377, April 1965. Cate, T., “Modern techniques of analog multiplication,” Electron. Eng., pp. 75–79, April 1970. Chang, K. K. N., “Parametric and Tunnel Diodes,” Prentice Hall, 1964. Coldren, L. A., and G. S. Kino, “Monolithic acoustic surface-wave amplifier,” Appl. Phys. Lett., Vol. 18, No. 8, p. 317, 1971. Cunningham, D. R., and J. A. Stiller, “Basic Circuit Analysis,” Houghton Mifflin, 1991. Curtis, F. W., “High-Frequency Induction Heating,” McGraw-Hill, 1964. Datta, S., “Surface Acoustic Wave Devices,” Prentice Hall, Vol. 72, 1986. Duenas, J. A., and A. Serrano, “Directional coupler design graphs for parallel coupled lines and interdigitated 3 dB couplers,” RF Design, pp. 62–64, February 1986. Evaluating, Selecting, and Using Multiplier Circuit Modules for Signal Manipulation and Function Generation, Analog Devices, 1970. Garmand, P. A., “Complete small size 2 to 30 GHz hybrid distributed amplifier using a novel design technique,” IEEE MITT-S Digest, pp. 343–346, 1986. Hagt, W. H., Jr., and J. E. Kemmerly, “Engineering Circuit Analysis,” 5th ed., McGraw-Hill, 1993. Helms, H. L., “Contemporary Electronics Circuit Deskbook,” McGraw-Hill, 1986. Helszajn, J., “Microwave Planar Passive Circuits and Filters,” Wiley, 1994. Ingebritsen, K. A., “Linear and nonlinear attenuation of acoustic surface waves in a piezoelectric coated with a semiconducting film,” J. Appl. Phys., Vol. 41, p. 454, 1970. Inglis, A. F., “Video Engineering,” McGraw-Hill, 1993. Kino, G. S., and T. M. Reeder, “A normal mode theory for the Rayleigh wave amplifier,” IEEE Trans. Electron Devices, Vol. ED-18, p. 909, 1971. Kotelyanski, I. M., A. I. Kribunov, A. V. Edved, R. A. Mishkinis, and V. V. Panteleev, “Fabrication of LiNbO3-InSb layer structures and their use in amplification of surface acoustic waves,” Sov. Phys. Semicon, Vol. 12, No. 7, pp. 751–754, July 1978. Kouril, F., “Non-linear and Parametric Circuits: Principles, Theory, and Applications,” Chichester/Wiley, 1988. Ladbrooke, P. H., “MMIC Design: GaAs FETs and HEMTs,” Artech House, 1989. Lakin, K. M., and H. J. Shaw, “Surface wave delay line amplifiers, IEEE Trans. Microwave Theory Techniques, MTT-17, p. 912, 1969. Lange, L., “Interdigitated stripline quadrature hybrid,” IEEE Trans. MTT, December 1969. Liff, A. A., “Color and Black and White Television,” Regents/Prentice Hall, 1993. Lin, Y., “Ion Beam Sputtered InSb Thin Films and Their Application to Surface Acoustic Wave Amplifiers,” Ph.D. Dissertation, Polytechnic University of 1995. May, J. E., Jr., “Electronic signal amplification in the UHF range with the ultrasonic traveling wave amplifier,” Proc. IEEE, Vol. 53, No. 10, October 1965. McFee, J. H., “Transmission and amplification of acoustic waves,” in: Physical Acoustics, Vol. 4A, Academic Press, 1964. Middlebrook, R. D., “Differential Amplifiers,” Wiley, 1963. Mizuta, H., “The Physics and Applications of Resonant Tunnelling Diodes,” Cambridge University Press, 1995. Nelson, J. C. C., “Operational Amplifier Circuits: Analysis and Design,” Butterworth-Heinemann, 1995. Optical Pumping and Masers, Appl. Opt., Vol. 1, No. 1, January 1962. Pauley, R. G., P. G. Asher, J. M. Schellenberg, and H. Yamasaki, “A 2 to 40 GHz monolithic distributed amplifier,” GaAs IC Symp., pp. 15–17, November 1985. Penfield, P. Jr., and R. P. Rafuse, “Varactor Applications,” The MIT Press, 1962. Petruzzela, F. D., “Industrial Electronics,” Glencoe/McGraw-Hill, 1996. “Power Op-amp Handbook,” Apex Microtechnology, 85741, 1987. Pucel, R. A., “Monolithic Microwave Integrated Circuits,” IEEE Press, 1985.

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Robertson, I. D., “MMIC Design,” IEE, London, 1995. Rutkowski, G. B., “Operational Amplifiers: Integrated and Hybrid Circuits,” Wiley, 1993. Simpson, C. D., “Industrial Electronics,” Prentice Hall, 1996. Southgate, P. D., and H. N. Spector, “Effect of carrier trapping on the Weinreich relation in acoustic amplification,” J. Appl. Phys., vol. 36, pp. 3728–3730, December 1965. Tehon, S. W., “Acoustic wave amplifiers,” Chap. 30, Amplifier Handbook, McGraw-Hill, 1968. Tobey, G. E., L. P. Huelsman, and J. G. Graeme, “Operational Amplifiers,” McGraw-Hill, 1971. Traister, R. J., “Operational Amplifier Circuit Manual,” Academic Press, 1989. Vizmuller, P., “RF Design Guide: Systems, Circuits and Equations,” Artech House, 1995. Wang, W. C., “Strong electroacoustic effect in CdS,” Phys. Rev. Lett., Vol. 9, No. 11, pp. 443–445, December 1, 1962. Wang, W. C., and Y. Lin, “Acousto-electric Attenuation Determined by Transmission Line Technique,” International Workshop on Ultrasonic Application, September 1–3, 1996. Wanuga, S., “CW acoustic amplifier, Proc. IEEE (Corres.), Vol. 53, No. 5, p. 555, May 1965. White, D. L., Amplification of ultrasonic waves in piezoelectric semiconductors,” J. Appl. Phys., Vol. 33, No. 8, pp. 2547–2554, August 1962. White, R. M., “Surface elastic-wave propagation and amplification,” IEEE Trans. Electron Devices, ED-14, 181 (1967). Wilkinson, E. J., “An N-way hybrid power divider,” IRE MTT, January 1960. Wilson, T. G., “Series connected magnetic amplifier with inductive loading,” Trans. AIEE, Vol. 71, 1952.

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Source: STANDARD HANDBOOK OF ELECTRONIC ENGINEERING

CHAPTER 11.1

AMPLIFIER AND OSCILLATOR PRINCIPLES OF OPERATION G. Burton Harrold

AMPLIFIERS: PRINCIPLES OF OPERATION Gain In most amplifier applications the prime concern is gain. A generalized amplifier is shown in Fig. 11.1.1. The most widely applied definitions of gain using the quantities defined there are: Voltage gain Aυ = e22 / e11 Available power from source Pavs = Output load power PL =

|e22 |2 Re Z L

Available power at output Pavo =

|es |2 4 Re Z s

where Re = real part of complex impedance

Input power PI = | e22 |2 4 Re Z out

Available power gain G A = Pavo / Pavs Insertion power gain GI =

Current gain Ai = i2 / i1

|e11 |2 Re Z in

Transducer gain GT = PL / Pavs

Power gain G = PL / PI

power into load with network inserted power into load with sourrce connected to load

Bandwidth and Gain-Bandwidth Product Bandwidth is a measure of the range of frequencies within which an amplifier will respond. The frequency range (passband) is usually measured between the half-power (3-dB) points on the output-responseversus-frequency curve, for constant input. In some cases it is defined at the quarter-power points (6 dB). See Fig. 11.1.2. The gain-bandwidth product of a device is a commonly used figure of merit. It is defined for a bandpass amplifier as Fa = Ar B 11.5 Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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AMPLIFIERS AND OSCILLATORS

where Fa = figure of merit (rad/s) Ar = reference gain, either the maximum gain or the gain at the frequency where the gain is purely real or purely imaginary B = 3-dB bandwidth (rad/s) For low-pass amplifiers FIGURE 11.1.1 Input and output quantities of generalized amplifier.

Fa = ArWH where Fa = figure of merit (rad/s) Ar = reference gain WH = upper cutoff frequency (rad/s)

In the case of vacuum tubes and certain other active devices this definition is reduced to Fa = gm / CT where Fa = figure of merit (rad/s) gm = transconductance of active device CT = total output capacitance, plus input capacitance of subsequent stage Noise The major types of noise are illustrated in Fig. 11.1.3. Important relations and definitions in noise computations are: Noise factor

F=

Si / N i So / N o

where Si = signal power available at input So = signal power available at output Ni = noise power available at input at T = 290 K No = noise power available at output Available noise power

Pn ,av =

en2 = KTB for thermal noise 4R

where the quantities are as defined in Fig. 11.1.3. Excess noise factor

F − 1 = Ne / Ni

FIGURE 11.1.2 Amplifier response and bandwidth.

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en2 = mean-square open-circuit noise voltage from a resistor R K = 1.38 × 10 −23 J/K T = temperature, K B = bandwith, Hz R = resistance, Ω

in2 = mean-square short-circuit noise current e = 1.6 × 10 −19 C I = dc current amps through R R = reesistance, Ω B = bandwith, Hz

inf2 = mean-square short-circuit flicker noisee current R = resistance, Ω I = dc current f = frequency, Hz ∆ f = frequency interval k ,α , n = empirical constants depending on device and mode off operation FIGURE 11.1.3 Noise-equivalent circuits.

where F − 1 = excess noise factor Ne = total equivalent device noise referred to input Ni = thermal noise of source at standard temperature Noise temperature

T = Pn ,av / KB

where Pn,av is the average noise power available. At a single input-output frequency in a two-port, Effective input noise temperature

Te = 290( F − 1)

Noise Factor of Transmission Lines and Attenuators. The noise factor of two ports composed entirely of resistive elements at room temperature (290 K) and an impedance matched loss of L = 1/GA is F = L. Cascaded noise factor

FT = F1 + ( F2 − 1)/ G A

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where FT = overall noise factor F1 = noise factor of first stage F2 = noise factor of second stage GA = available gain of first stage System Noise Temperature. Space probes and satellite communication systems using low-noise amplifiers and antennas directed toward outer space make use of system noise temperatures. When we define TA = antenna temperature, L = waveguide numeric loss (greater than 1), TE1 = amplifier noise temperature, GA = amplifier available gain, F = postamplifier noise factor, and B = postamplifier bandwidth, this temperature can be calculated as Tsys = TA + | L − 1| 290° + LTE1 +

( F − 1)(290 L ) G A1

The quantity of interest is the output signal-to-noise ratio where SA is available signal power at the antenna (assuming the antenna is matched to free space) S/N = S A / KTsys B K = 1.38 × 10 −23 Generalized Noise Factor. A general representation of noise performances can be expressed in terms of Fig. 11.1.4. This is the representation of a noisy two-port in terms of external voltage and current noise sources with a correlation admittance. In this case the noise factor becomes F = 1+

Gu RN − [(Gs + Gγ )2 + ( Bs + Bγ )2 ] Gs Gs

where F = noise factor Gs = real part of Ys Bs = imaginary part of Ys Gu = conductance owing to the uncorrelated part of the noise current Yg = correlation admittance between cross product of current and voltage noise sources Gg = real part of Yg Bg = imaginary part of Yg RN = equivalent noise resistance of the noise voltage The optimum source admittance is Yopt = Gopt + jBopt

Gopt

 G + R G2  u N γ  =   RN

1/ 2

FIGURE 11.1.4 Noise representation using correlation admittance.

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where Bopt = −Bgg and the value of the optimum noise factor Fopt is Fopt = 1 + 2 RN (Gγ + G0 ) The noise factor for an arbitrary source impedance is F = Fopt +

RN [(Gs − G0 )2 + ( Bs − B0 )2 ] Gs

The values of the parameters of Fig. 11.1.4 can be determined by measurement of (1) noise figure versus Bs with Gs constant and (2) noise figure versus Gs with Bs at its optimum value. Dynamic Characteristic, Load Lines, and Class of Operation Most active devices have two considerations involved in their operation. The first is the dc bias condition that establishes the operating point (the quiescent point). The choice of operating point is determined by such considerations as signal level, uniformity of the device, and temperature of operation. The second consideration is the ac operating performance, related to the slope of the dc characteristic and to the parasitic reactances of the device. These ac variations give rise to the small-signal parameters. The ac parameters may also influence the choice of dc bias point when basic constraints, such as gain and noise performance, are considered. For frequencies of operation where these parasites are not significant, the use of a load line is valuable. The class of amplifier operation is dependent on its quiescent point, its load line, and input signal level. The types of operation are shown in Fig. 11.1.5. Distortion Distortion takes many forms, most of them undesirable. The basic causes of distortion are nonlinearity in amplitude response and nonuniformity of phase response. The most commonly encountered types of distortion are as follows: Harmonic distortion is a result of nonlinearity in the amplitude transfer characteristics. The typical output contains not only the fundamental frequency but integer multiples of it. Crossover distortion is a result of the nonlinear characteristics of a device when changing operating modes (e.g., in a push-pull amplifier). It occurs when one device is cut off and the second turned on if the crossover is not smooth between the two modes. Intermodulation distortion is a spurious output resulting from the mixing of two or more signals of different frequencies. The spurious output occurs at the sum or difference of integer multiples of the original frequencies. Cross-modulation distortion occurs when two signals pass through an amplifier and the modulation of one is transferred to the other. Phase distortion results from the deviation from a constant slope of the output-phase–versus–frequency response of an amplifier. This deviation gives rise to echo responses in the output that precede and follow the main response, and a distortion of the output signal when an input signal having a large number of frequency components is applied. Feedback Amplifiers Feedback amplifiers fall into two categories: those having positive feedback (usually oscillators) and those having negative feedback. The positive-feedback case is discussed under oscillators. The following discussion is concerned with negative-feedback amplifiers.

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FIGURE 11.1.5 Classes of amplifier operation. Class S operation is a switching mode in which a squarewave output is produced by a sine-wave input.

Negative Feedback A simple representation of a feedback network is shown in Fig. 11.1.6. The closed-loop gain is given by e2 / e1 = A/(1 − BA) where A is the forward gain with feedback removed and B is the fraction of output returned to input. For negative feedback, A provides a 180° phase shift in midband, so that FIGURE 11.1.6 Amplifier with feedback loop.

1 − AB > 1

in this frequency range

The quantity 1 − AB is called the feedback factor, and if the circuit is cut at any X point in Fig. 11.1.6, the openloop gain is AB. It can be shown that for large loop gain AB the closed-loop transfer function reduces to e2 / e1 ≈ 1/ B The gain then becomes essentially independent of variations in A. In particular, if B is passive, the closed-loop gain is controlled only by passive components. Feedback has no beneficial effect in reducing unwanted signals

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at the input of the amplifier, e.g., input noise, but does reduce unwanted signals generated in the amplifier chain (e.g., output distortion). The return ratio can be found if the circuit is opened at any point X (Fig. 11.1.6) and a unit signal P is injected at that X point. The return signal P′ is equal to the return ratio, since the input P is unity. In this case the return ratio T is the same at any point X and is T = − AB The minus sign is chosen because the typical amplifier has an odd number of phase reversals and T is then a positive quantity. The return difference is by definition F =1+ T It has been shown by Bode that F = ∆ / ∆0 where ∆ is the network determinant with XX point connected and ∆0 is the network determinant of amplifier when gain of active device is set to zero. Stability The stability of the network can be analyzed by several techniques. Of prime interest are the Nyquist, Bode, Routh, and root-locus techniques of analyzing stability. Nyquist Method. The basic technique of Nyquist involves plotting T on a polar plot as shown in Fig. 11.1.7 for all values s = jw for w between minus and plus infinity. Stability is then determined by the following method: 1. Draw a vector from the −1 + j0 point to the plotted curve and observe the rotation of this vector as w varies from −∞ to +∞. Let R be the net number of counterclockwise revolutions of this vector. 2. Determine the number of roots of the denominator of T = −AB which have positive real parts. Call this number P. 3. The system is stable if and only if P = R. Note that in many systems A and B are stable by themselves, so that P becomes zero and the net counterclockwise revolution N becomes zero for stability. Bode’s Technique. A technique that has historically found wide use in determining stability and performance, especially in control systems, is the Bode diagram. The assumptions used here for this method are that T = –AB, where A and B are stable when the system is open-circuitFIGURE 11.1.7 Nyquist diagram for determining ed and consists of minimum-phase networks. It is also necstability. essary to define a phase margin g such that g = 180 + f, where f is the phase angle of T and is positive when measured counterclockwise from zero, and g, the phase margin, is positive when measured counterclockwise from the 180° line (Fig. 11.1.7). The stability criterion under these conditions reads: Systems having a positive phase margin when their return ratio equal to 20 log |T| goes through 0 dB (i.e., where |T| crosses the unit circle in the Nyquist plot) are stable; if a negative g exists at 0 dB, the system is unstable. Bode’s theorems show that the phase angle of a system is related to the attenuation or gain characteristic as a function of frequency. Bode’s technique relies heavily on straight-line approximation.

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FIGURE 11.1.8 Equivalent circuits of active devices: (a) vacuum tube; (b) bipolar transistor; (c) field-effect transistor (FET).

Routh’s Criterion for Stability. Routh’s method has also been used to test the characteristic equations or return difference F = 1 + T = 0, to determine whether it has any roots that are real and positive or complex with positive real parts that will give rise to growing exponential responses and hence instability. Root-Locus Method. The root-locus method of analysis is a means of finding the variations of the poles of a closed-loop response as some network parameter is varied. The most convenient and commonly used parameter is that of the gain K. The basic equation then used is F = 1 + KT (s) = 1 − K

( S − S2 )( S − S4 ) =0 ( S − S1 )( S − S3 )

This is a useful technique in feedback and control systems, but it has not found wide application in amplifier design. A detailed exposition of the technique is found in Truxal.

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FIGURE 11.1.9 Definitions of active-network parameters: (a) general network; (b) ratios ai and bi of incident and reflected waves (square root of power); (c) s parameters.

Active Devices Used in Amplifiers There are numerous ways of representing active devices and their properties. Several common equivalent circuits are shown in Fig. 11.1.8. Active devices are best analyzed in terms of the immittance or hybrid matrices. Figures 11.1.9 and 11.1.10 show the definition of the commonly used matrices, and their interconnections are shown in Fig. 11.1.11. The requirements at the bottom of Fig. 11.1.11 must be met before the interconnection of two matrices is allowed. The matrix that is becoming increasingly important at higher frequencies is the S matrix. Here the network is embedded in a transmission-line structure, and the incident and reflected powers are measured and reflected coefficients and transmission coefficients are defined.

Cascaded and Distributed Amplifiers Most amplifiers are cascaded (i.e., connected to a second amplifier). The two techniques commonly used are shown in Fig. 11.1.12. In the cascade structure the overall response is the product of the individual responses: in the distributed structure the response is one-half the sum of the individual responses, since each stage’s output is propagated in both directions. In cascaded amplifiers the frequency response and gain are determined by the active device as well as the interstage networks. In simple audio amplifiers these interstage networks may become simple RC combinations, while in rf amplifiers they may become critically coupled double-tuned circuits. Interstage coupling networks are discussed in subsequent sections.

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FIGURE 11.1.10 Network matrix terms.

In distributed structures (Fig. 11.1.12b), actual transmission lines are used for the input to the amplifier, while the output is taken at one end of the upper transmission line. The propagation time along the input line must be the same as that along the output line, or distortion will result. This type of amplifier, noted for its wide frequency response, is discussed later.

OSCILLATORS: PRINCIPLES OF OPERATION Introduction An oscillator can be considered as a circuit that converts a dc input to a time-varying output. This discussion deals with oscillators whose output is sinusoidal, as opposed to the relaxation oscillator whose output exhibits abrupt transitions (see Section 14). Oscillators often have a circuit element that can be varied to produce different frequencies. An oscillator’s frequency is sensitive to the stability of the frequency-determining elements as well as the variation in the active-device parameters (e.g., effects of temperature, bias point, and aging). In many instances

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FIGURE 11.1.11 Matrix equivalents of network interconnections.

the oscillator is followed by a second stage serving as a buffer, so that there is isolation between the oscillator and its load. The amplitude of the oscillation can be controlled by automatic gain control (AGC) circuits, but the nonlinearity of the active element usually determines the amplitude. Variations in bias, temperature, and component aging have a direct effect on amplitude stability. Requirements for Oscillation Oscillators can be considered from two viewpoints: as using positive feedback around an amplifier or as a one-port network in which the real component of the input immittance is negative. An oscillator must have frequency-determining elements (generally passive components), an amplitude-limiting mechanism, and sufficient closed-loop gain to make up for the losses in the circuit. It is possible to predict the operating frequency and conditions needed to produce oscillation from a Nyquist or Bode analysis. The prediction of output amplitude requires the use of nonlinear analysis. Oscillator Circuits Typical oscillator circuits applicable up to ultra high frequencies (UHF) are shown in Fig. 11.1.13. These are discussed in detail in the following subsections. Also of interest are crystal oscillators. In this case the crystal is used as the passive frequency-determining element. The frequency range of crystal oscillators extends from a few hundred hertz to over 200 MHz by use of overtone crystals. The analysis of crystal oscillators is best done using the equivalent circuit of the crystal.

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AMPLIFIER AND OSCILLATOR PRINCIPLES OF OPERATION

FIGURE 11.1.12 Multiamplifier structures: (a) cascade; (b) distributed.

FIGURE 11.1.13 Types of oscillators: (a) tuned-output; (b) Hartley; (c) phase-shift; (d) tuned-input; (e) Colpitts; ( f ) Wien bridge.

FIGURE 11.1.14 Phase-locked-loop oscillator.

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FIGURE 11.1.15 Injection-locked oscillator.

Synchronization Synchronization of oscillators is accomplished by using phase-locked loops or by direct low-level injection of a reference frequency into the main oscillator. The diagram of a phase-locked loop is shown in Fig. 11.1.14 and that of an injection-locked oscillator in Fig. 11.1.15.

Harmonic Content The harmonic content of the oscillator output is related to the amount of oscillator output power at frequencies other than the fundamental. From the viewpoint of a negative-conductance (resistance) oscillator, better results are obtained if the curve of the negative conductance (or resistance) versus amplitude of oscillation is smooth and without an inflection point over the operating range. Harmonic content is also reduced if the oscillator’s operating point Q is chosen so that the range of negative conductance is symmetrical about Q on the negative conductance-versus-amplitude curve. This can be done by adjusting the oscillator’s bias point within the requirement of |GC| = |GD| for sustained oscillation (see Fig. 11.1.16).

Stability The stability of the oscillator’s output amplitude and frequency from a negative-conductance viewpoint depends on the variation of its negative conductance with operating point and the amount of fixed positive conductance in the oscillator’s associated circuit. In particular, if the change of bias results in vertical translation of the conductance-(resistance)-versus-amplitude curve, the oscillator’s stability is related to the change of slope at the point where the circuit’s fixed conductance intersects this curve (point Q in Fig. 11.1.16). If the |GD| curve is of the shape of |GD|2, the oscillation can stop when a large enough change in bias point occurs for |GD| to be less than |GC| for all amplitudes of oscillation. Stabilization of the amplitude of oscillation may occur in the form of modifying GC, GD , or both to compensate for bias changes. Particular types of oscillators and their parameters are discussed later in this section.

FIGURE 11.1.16 Device conductance vs. amplitude of oscillation.

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Source: STANDARD HANDBOOK OF ELECTRONIC ENGINEERING

CHAPTER 11.2

AUDIO-FREQUENCY AMPLIFIERS AND OSCILLATORS Samuel M. Korzekwa, Robert J. McFadyen

AUDIO-FREQUENCY AMPLIFIERS Samuel M. Korzekwa Preamplifiers General Considerations. The function of a preamplifier is to amplify a low-level signal to a higher level before further processing or transmission to another location. The required amplification is achieved by increased signal voltage and/or impedance reduction. The amount of power amplification required varies with the particular application. A general guideline is to provide sufficient preamplification to ensure that further signal handling adds minimal (or acceptable) signal-to-noise degradation. Signal-to-Noise Considerations. The design of a preamplifier must consider all potential signal degradation from sources of noise, whether generated externally or within the preamplifier itself. Examples of externally generated noise are hum and pickup, which may be introduced by the input-signal lines or the power-supply lines. Shielding of the input-signal lines often proves to be an acceptable solution. The preamplifier should be located close to the transmitting source, and the preamplifier power gain must be sufficient to override interference that remains after these steps are taken. A second major source of noise is that internally generated in the amplifier itself. The noise figure specified in decibels for a preamplifier, which serves as a figure of merit, is defined as the ratio of the available input-to-output signal-to-noise power ratios: F=

Si / N i So / N o

where F = noise figure of preamplifier Si = available signal input power Ni = available noise input power So = available signal output power No = available noise output power Design precautions to realize the lowest possible noise figure include the proper selection of the active device, optimum input and output impedance, correct voltage and current biasing conditions, and pertinent design parameters of devices.

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Low-Level Amplifiers The low-level designation applies to amplifiers operated below maximum permissible power-dissipation, current, and voltage limits. Thus many low-level amplifiers are purposely designed to realize specific attributes other than delivering the maximum attainable power to the load, such as gain stability, bandwidth, optimum noise figure, and low cost. In an amplifier designed to be operated with a 24-V power supply and a specified load termination, for example, the operating conditions may be such that the active devices are just within their allowable limits. If operated at these maximum limits, this is not a low-level amplifier; however, if this amplifier also fulfills its performance requirements at a reduced power-supply voltage of 6 V, with resulting much lower internal dissipation levels, it becomes a low-level amplifier. Medium-Level and Power Amplifiers The medium-power designation for an amplifier implies that some active devices are operated near their maximum dissipation limits, and precautions must be taken to protect these devices. If power-handling capability is taken as the criterion, the 5- to 100-W power range is a current demarcation line. As higher-power-handling devices come into use, this range will tend to shift to higher power levels. The amount of power that can safely be handled by an amplifier is usually dictated by the dissipation limits of the active devices in the output stages, the efficiency of the circuit, and the means used to extract heat to maintain devices within their maximum permissible temperature limits. The classes of operation (A, B, AB, C) are discussed relative to Fig. 11.1.5. When single active devices do not suffice, multiple series or parallel configurations can be used to achieve higher voltage or power operation. Multistage Amplifiers An amplifier may take the form of a single stage or a complex single stage, or it may employ an interconnection of several steps. Various biasing, coupling, feedback, and other design alternatives influence the topology of the amplifier. For a multistage amplifier, the individual stages may be essentially identical or radically different. Feedback techniques may be used at the individual stage level, at the amplifier functional level, or both, to realize bias stabilization, gain stabilization, output-impedance reduction, and so forth. Typical Electron-Tube Amplifier Figure 11.2.1 shows a typical electron-tube amplifier stage. For clarity the signal-source and load sections are shown partitioned. For a multistage amplifier the source represents the equivalent signal generator of the preceding stage. Similarly, the load indicated includes the loading effect of the subsequent stage, if any. The voltage gain from the grid of the tube to the output can be calculated to be Aυ1 = −

µ R1 rp + Rl

Similarly, the voltage gain from the source to the tube grid is Aυ 2 =

R1 ( R1 + Rg ) + 1/ jωC

Combining the above equations gives the composite amplifier voltage gain Aυ =

µ R1Rl (rp + Rl )[( R1 + Rg ) + 1/ jωC ]

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AMPLIFIERS AND OSCILLATORS

FIGURE 11.2.1 Typical triode electron-tube amplifier stage (biasing not shown).

This example illustrates the fundamentals of an electron-tube amplifier stage. Many excellent references treat this subject in detail.

Typical Transistor Amplifier The analysis techniques used for electron-tube amplifier stages generally apply to transistorized amplifier stages. The principal difference is that different active-device models are used. The typical transistor stage shown in Fig. 11.2.2 illustrates a possible form of biasing and coupling. The source section is partitioned and includes the preceding-stage equivalent generator, and the load includes subsequent stage-loading effects. Figure 11.2.3 shows the generalized h-equivalent circuit representation for transistors. Table 11.2.1 lists the h-parameter transformations for the common-base, common-emitter, and common-collector configurations.

FIGURE 11.2.2 Typical bipolar transistor-amplifier stage.

FIGURE 11.2.3 Equivalent circuit of transistor, based on h parameters.

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TABLE 11.2.1 h Parameters of the Three Transistor Circuit Configurations Common-base h11 h12 h21 h22

hib hrb hf b hob

Common-emitter

Common-collector

hib(hfe + 1) hibhob(hfe + 1) − hrb hfe hob(hfe + 1)

hib(hfe + 1) 1 – (hfe + 1) hob(hfe + 1)

While these parameters are complex and frequencydependent, it is often feasible to use simplifications. Most transistors have their parameters specified by their manufacturers, but it may be necessary to determine additional parameters by test. Figure 11.2.4 illustrates a simplified model of the transistor amplifier stage of Fig. 11.2.2. The common-emitter h parameters are used to represent the equivalent transistor. The voltage gain for this stage is Aυ =

h fe Rl Vo =− Vi Rg + hie

FIGURE 11.2.4 Simplified equivalent circuit of transistor amplifier stage.

The complexity of analysis depends on the accuracy needed. Currently, most of the more complex analysis is performed with the aid of computers. Several transistor-amplifier-analysis references treat this subject in detail.

Typical Multistage Transistor Amplifier Figure 11.2.5 is an example of a capacitively coupled three-stage transistor amplifier. It has a broad frequency response, illustrating the fact that an audio amplifier can be useful in other applications. The component values are R1 = 16, 000 Ω

R2 = 6200 Ω

R3 = 1600 Ω

R4 = 1000 Ω

RL = 560 Ω Q1 , Q2 , Q3 = 2 N1565 C1 = 10 µ F C2 = 100 µ F

FIGURE 11.2.5 Typical three-stage transistor amplifier.

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AMPLIFIERS AND OSCILLATORS

This amplifier is designed to operate over a range of −55 to +125°C, with an output voltage swing of 2 V peak to peak and frequency response down 3 dB at approximately 200 Hz and 2 MHz. The overall gain at 1000 Hz is nominally 88 dB at 25°C.

Biasing Methods The biasing scheme used in an amplifier determines the ultimate performance that can be realized. Conversely, an amplifier with poorly implemented biasing may suffer in performance, and be susceptible to catastrophic circuit failure owing to high stresses within the active devices. In view of the variation of parameters within the active devices, it is important that the amplifier function properly even when the initial and/or end-of-life parameters of the devices vary.

Electron-Tube Biasing Biasing is intended to maintain the quiescent currents and voltages of the electron tube at the prescribed levels. The tube-plate characteristics represent the biasing relations between the tube parameters. The principal bias parameters (steady-state plate and grid voltages) can be readily identified by the construction of a load line on the plate characteristic. The operating point Q is located at the intersection of the selected plate characteristic with the load line.

Transistor Biasing Although the methods of biasing a transistor-amplifier stage are in many respects similar to those of an electrontube amplifier, there are many different types of transistors, each characterized by different curves. Bipolar transistors are generally characterized by their collector and emitter families, while field-effect transistors have different characterizations. The npn transistor requires a positive base bias voltage and current (with respect to its emitter) for proper operation; the converse is true for a pnp transistor. Figure 11.2.6 illustrates a common biasing technique. A single power supply is used, and the transistor is self-biased with the unbypassed emitter resistor Re. Although a graphical solution of the value of Re could be found by referring to the collector-emitter curves, an iterative solution, described below, is also commonly used. Because the performance of the transistors depends on the collector current and collector-to-emitter voltage, they are often selected as starting conditions for biasing design. The unbypassed emitter resistor Re and collector resistor Rc, the primary voltage-gain-determining components, are determined next, taking into account other considerations such as the anticipated maximum signal level and available power supply Vcc. FIGURE 11.2.6 Capacitively coupled The last step is to determine the R1 and R2 values. npn transistor-amplifier stage.

Coupling Methods Transformer coupling and capacitance coupling are commonly used in transistor and electron-tube audio amplifiers. Direct coupling is also used in transistor stages and particularly in integrated transistor amplifiers. Capacitance coupling, referred to as RC coupling, is the most common method of coupling stages of an audio amplifier. The discrete-component transistorized amplifier stage shown in Fig. 11.2.6 serves as an example of RC coupling, where Ci and Co are the input and output coupling capacitors, respectively.

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FIGURE 11.2.7 Transformer-coupled pnp transistoramplifier stage.

11.23

FIGURE 11.2.8 Classes of amplifier operation, based on transistor characteristics.

Transformer coupling is commonly used to match the input and output impedances of electron-tube amplifier stages. Since the input impedance of an electron tube is very high at audio frequencies, the design of an electron-tube stage depends primarily on the transformer parameters. The much lower input impedances of transistors demand that many other factors be taken into account, and the design becomes more complex. The output-stage transformer coupling to a specific load is often the optimum method of realizing the best power match. Figure 11.2.7 illustrates a typical transformer-coupled transistor audio-amplifier stage. The direct-coupling approach is now also used for discrete-component transistorized amplifiers, and particularly in integrated amplifier versions. The level-shifting requirement is realized by selection from the host of available components, such as npn and pnp transistors and zener diodes. Since it is difficult to realize largesize capacitors via integrated-circuit techniques, special methods have been developed to direct-couple integrated amplifiers.

Classes A, B, AB, and C Operation The output or power stage of an amplifier is usually classified as operating class A, B, AB, or C, depending on the conduction characteristics of the active devices (see Fig. 11.1.5). These definitions can also apply to any intermediate amplifier stage. Figure 11.2.8 illustrates relations between the class of operation and conduction using transistor parameters. This figure would be essentially the same for an electron-tube amplifier with the tube plate current and grid voltage as the equivalent device parameters. Subscripts may be used to denote additional conduction characteristics of the device. For example, the electron-tube grid conduction can also be further classified as A1, to show that no grid current flows, or A2, to show that grid-current conduction exists during some portion of the cycle.

Push-Pull Amplifiers In a single-ended amplifier the active devices conduct continuously. The single-ended configuration is generally used in low-power applications, operated in class A. For example, preamplifiers and low-level amplifiers are generally operated single-ended, unless the output power levels necessitate the more efficient power handling of the push-pull circuit. In a push-pull configuration there are at least two active devices that alternately amplify the negative and positive cycles of the input waveform. The output connection to the load is most often transformer-coupled. An example of a transformer input and output in a push-pull amplifier is illustrated in Fig. 11.2.9. Direct-coupled push-pull amplifiers and capacitively coupled push-pull amplifiers are also feasible, as illustrated in Fig. 11.2.10.

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AMPLIFIERS AND OSCILLATORS

FIGURE 11.2.9 Transformer-coupled push-pull transistor stage.

The active devices in push-pull are usually operated either in class B or AB because of the high powerconversion efficiency. Feedback techniques can be used to stabilize gain, stabilize biasing or operating points, minimize distortion, and the like.

Output Amplifiers The function of an audio output amplifier is to interface with the preceding amplifier stages and to provide the necessary drive to the load. Thus the output-amplifier designation does not uniquely identify a particular amplifier class. When several different types of amplifiers are cascaded between the signal source and its load, e.g., a high-power speaker, the last-stage amplifier is designated as the output amplifier. Because of the high power requirements, this amplifier is usually a push-pull type operating either in class B or AB.

Stereo Amplifiers A stereo amplifier provides two separate audio channels properly phased with respect to each other. The objective of this two-channel technique is to enhance the audio reproduction process, making it more realistic

FIGURE 11.2.10 (a) Direct- and (b) capacitively coupled push-pull stages.

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and lifelike. It is also feasible to extend the system to contain more than two channels of information. A stereo amplifier is a complete system that contains its power supply and other commonly required control functions. Each channel has its own preamplifier, medium-level stages, and output power stage, with different gain and frequency responses for each mode of operation, e.g., for tape, phonograph, CD, and so forth. The input signal is selected from the phonograph input connection, tape input, or a turner output. Special-purpose trims and controls are also used to optimize performance on each mode. The bandwidth of the amplifier extends to 20 kHz or higher.

AUDIO OSCILLATORS Robert J. McFadyen General Considerations In the strict sense, an audio oscillator is limited to frequencies from about 15 to 20,000 Hz, but a much wider frequency range is included in most oscillators used in audio measurements since knowledge of amplifier characteristics in the region above audibility is often required. For the production of sinusoidal waves, audio oscillators consist of an amplifier having a nonlinear power gain characteristic, with a path for regenerative feedback. Single- and multistage transistor amplifiers with LC or RC feedback networks are most often used. The term harmonic oscillator is used for these types. Relaxation oscillators, which may be designed to oscillate in the audio range, exhibit sharp transitions in the output voltages and currents. Relaxation oscillators are treated in Section 14. The instantaneous excursions of the operating point in a harmonic oscillator is restricted to the range where the circuit exhibits an impedance with a negative real part. The amplifier supplies the power, which is dissipated in the feedback path and the load. The regenerative feedback would cause the amplitude of oscillation to grow without bound were it not for the fact that the dynamic range of the amplifier is limited by circuit nonlinearities. Thus, in most sine-wave audio oscillators; the operating frequency is determined by passive-feedback elements, whereas the amplitude is controlled by the active-circuit design. Analytical expressions predicting the frequency and required starting conditions for oscillation can be derived using Bode’s amplifier feedback theory, and the stability theorem of Nyquist. Since this analytical approach is based on a linear-circuit model, the results are approximate but usually suitable for design of sinusoidal oscillators. No prediction on waveform amplitude results, since this is determined by nonlinear-circuit characteristics. Estimates of the waveform amplitude can be made from the bias and limiting levels of the active circuits. Separate limiters and AGC techniques are also useful for controlling the amplitude to a prescribed level. Graphical and nonlinear analysis methods can also be used for obtaining a prediction of the amplitude of oscillation. A general formulation suitable for a linear analysis of almost all audio oscillators can be derived from the feedback diagram in Fig. 11.2.11. Note that the amplifier internal feedback generator has been neglected: that is, y12A is assumed to be zero. This assumption of unilateral amplification is almost always valid in the audio range even for single-stage transistor amplifiers. The stability requirements for the circuit are derived from the closed-loop-gain expression Ac = A /(1 − Aβ )

(1)

where the gain A is treated as a negative quantity for an inverting amplifier. Infinite closed-loop gain occurs when AB is equal to unity, and this defines the oscillatory condition. In terms of the equivalent circuit parameters used in Fig. 11.2.1, 1 − Aβ = 1 − y21 A

y12 β ( y11 A + y11β )( y22 A + y22 β ) − y12 β y21β

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FIGURE 11.2.11 Oscillator representations: (a) generalized feedback circuit; (b) equivalent y-parameter circuit.

In the audio range, y21A remains real, but the fractional portion of the function is complex because b is frequency-sensitive. Therefore, the open-loop gain Ab can be expressed in the general form Aβ = y21A

Ar + jAi Br + jBi

(3)

It follows from Nyquist’s stability theorem that this feedback system will be unstable if, first, the phase shift of Ab is zero and, second, the magnitude is equal to or greater than unity. Applying this criterion to Eq. (3) yields the following two conditions for oscillation: Ai Br − Ar Bi = 0

(4)

Br2 + Bi2 Ar2 + Ai2

(5)

2 y21 ≥

Equation (4) results from the phase condition and determines the frequency of oscillation. The inequality in Eq. (5) is the consequence of the magnitude constraint and defines the necessary condition for sustained oscillation. Equation (5) is evaluated at the oscillation frequency determined from Eq. (4). A large number of single-stage oscillators have been developed in both vacuum-tube and transistor versions. The transistor circuits followed by direct analogy from the earlier vacuum-tube circuits. In the following examples, transistor versions are illustrated, but the y-parameter equations apply to other devices as well.

LC Oscillators The Hartley oscillator circuit is one of the oldest forms: the transistor version is shown in Fig. 11.2.12. With the collector and base at opposite ends of the tuned circuit, the 180° phase relation is secured, and feedback occurs through mutual inductance between the two parts of the coil. The frequency and condition for oscillation are expressed in terms of the transistor y parameters and feedback inductance L, inductor coupling coefficient k, inductance ratio n, and tuning capacitance C. The frequency of oscillation is

ω2 =

1 LC (1 + 2k n + n) + nL2 (1 − k 2 )( y11A y22 A )

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FIGURE 11.2.12 Hartley oscillator circuit.

FIGURE 11.2.13 circuit.

11.27

Colpitts oscillator

The condition for oscillation is y21 A ≥

y11 A + ny22 A + nω 2 LC (1 − k 2 )( y11 A y22 A ) k n + nω 2 LC (1 − k 2 )

The admittance parameters of the bias network R1, R2, and R3, as well as the reactance of bypass capacitor C and coupling capacitor C2, have been neglected. These admittances could be included in the amplifier y parameters in cases where their effect is not negligible. If n(1 − k 2 )( y11A y22 A ) C >> L 1 + 2k n + n

(6)

the frequency of oscillation will be essentially independent of transistor parameters. The transistor version of the Colpitts oscillator is shown in Fig. 11.2.13. Capacitors C and nC in combination with inductance L determine the resonant frequency of the circuit. A fraction of the current flowing in the tank circuit is regeneratively fed back to the base through the coupling capacitor C2. Bias resistors R1, R2, R3, and RL, as well as capacitors C1 and C2, are chosen so as not to affect the frequency or conditions for oscillation. The frequency of oscillation is

ω2 =

1  1 1 (y y ) 1 +  + LC  n  nC 2 11A 22 A

The condition for oscillation is y21A ≥ ω 2 LC (nY11A + Y22 A ) − ( y11A + y22 A ) Alternatively, the bias element admittances may be included in the amplifier y parameters. In the Colpitts circuit, if the ratio of C/L is chosen so that y y C >> 11A 22 A 1+ n L the frequency of oscillation is essentially determined by the tuned-circuit parameters.

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FIGURE 11.2.14 Tuned-collector oscillator.

FIGURE 11.2.15 RC oscillator with highpass feedback network.

Another oscillator configuration useful in the audio-frequency range is the tuned-collector circuit shown in Fig. 11.2.14. Here regenerative feedback is furnished via the transformer turns ratio N from the collector to base. The frequency of oscillation is

ω2 =

1 LC + N L y11A y22 A (1 − k 2 ) 2 2

The condition for oscillation is y22 A ≥

ω 2 NLCY11 A 1 ( N 2Y11 A + Y22 A ) − (1 − k 2 ) Nk k

If the ratio of C/L is such that C >> N 2 y11A y22 A (1 − k 2 ) L

(8)

the frequency of oscillation is specified by w2 = 1/LC. This circuit can be tuned over a wide range by varying the capacitor C and is compatible with simple biasing techniques.

RC Oscillators Audio sinusoidal oscillators can be designed using an RC ladder network (of three or more sections) as a feedback path in an amplifier. This scheme originally appeared in vacuum-tube circuits, but the principles have been directly extended to transistor design. RC phase-shift oscillators can be distinguished from tuned oscillators in that the feedback network has a relatively broad frequency-response characteristic. Typically, the phase-shift network has three RC sections of either a high- or a low-pass nature. Oscillation occurs at the frequency where the total phase shift is 180° when used with an inverting amplifier. Figures 11.2.15 and 11.2.16 show examples of high-pass and low-pass feedback-connection schemes. The amplifier is a differential pair with a transistor current source, a configuration which is common in integrated-circuit amplifiers. The output is obtained at the opposite collector from the feedback connection, since this minimizes external loading on the phase-shift network. The conditions for, and the frequency of, oscillation are derived, assuming that the input resistance of the amplifier, which loads the phase-shift network, has been adjusted to equal the

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resistance R. The load resistor RL is considered to be part of the amplifier output resistance, and it is included in y22A. The frequency of oscillation for the high-pass case is

ω2 =

y22 A 2C R(2 + 3Ry22 A ) 2

The condition for oscillation for the high-pass case is y21 A ≥

 1  1 + 5 R / RL R − − 3 R  ω 2 R 2C 2 RL 

The frequency of oscillation for the low-pass case is

ω=

R 1 6+4 RC RL

The condition for oscillation for the low-pass case is y21A ≥

R R2  1  23 + 29 + 4 2  R  RL RL 

Null-Network Oscillators In almost all respects null-network oscillators are superior to the RC phase-shift circuits described in the previous paragraph. While many null-network configurations are useful (including the bridged-T and twin-T), the Wien bridge design predominates. The general form for the Wien bridge oscillator is shown in Fig. 11.2.17. In the figure, an ideal differential voltage amplifier is assumed, i.e., one with infinite input impedance and zero output impedance.

Frequency of oscillation (M = N = 1):

ω0 =

1 RC

Condition for oscillation: A≥8= FIGURE 11.2.16 RC oscillator with low-pass feedback network.

3( R1 + R2 ) R1 − 2 R2

FIGURE 11.2.17 Wien bridge oscillator circuit.

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An integrated-circuit operational amplifier that has a differential input stage is a practical approximation to this type of amplifier and is often used in bridge-oscillator designs. The Wien bridge is used as the feedback network, with positive feedback provided through the RC branches for regeneration and negative feedback through the resistor divider. Usually the resistor-divider network includes an amplitude-sensitive device in one or both arms which provides automatic correction for variation of the amplifier gain. Circuit elements such as a tungsten lamp, thermistor, and field-effect transistor used as the voltage-sensitive resistance element maintain a constant output level with a high degree of stability. Amplitude variations of less than ±1 percent over the band from 10 to 100,000 Hz are realizable. In addition, since the amplifier is never driven into the nonlinear region, harmonic distortion in the output waveform is minimized. For the connection shown in Fig. 11.2.17, an increase in V will cause a decrease in R2, restoring V to the original level. The lamp or thermistor have thermal time constants that set at a lower frequency limit on this method of amplitude control. When the period is comparable with the thermal time constant, the change in resistance over an individual cycle distorts the output waveform. There is an additional degree of freedom with the field-effect transistor, since the control voltage must be derived by a separate detector from the amplifier output. The time constant of the detector, and hence the resistor, are set by a capacitor, which can be chosen commensurate with the lowest oscillation frequency desired. At w0 the positive feedback predominates, but at harmonics of w0 the net negative feedback reduces the distortion components. Typically, the output waveform exhibits less than 1 percent total harmonic distortion. Distortion components well below 0.1 percent in the mid-audio-frequency range are also achieved. Unlike LC oscillators, in which the frequency is inversely proportional to the square root of L and C, in the Wien bridge w0 varies as 1/RC. Thus, a tuning range in excess of 10:1 is easily achieved. Continuous tuning within one decade is usually accomplished by varying both capacitors in the reactive feedback branch. Decade changes are normally accomplished by switching both resistors in the resistive arm. Component tracking problems are eased when the resistors and capacitors are chosen to be equal. Almost any three-terminal null network can be used for the reactive branch in the bridge; the resistor divider network adjusts the degree of imbalance in the manner described. Many of these networks lack the simplicity of the Wien bridge since they may require the tracking of three components for frequency tuning. For this reason networks such as the bridged-T and twin-T are usually restricted to fixed-tuned applications.

Low-Frequency Crystal Oscillators Quartz-crystal resonators are used where frequency stability is a primary concern. The frequency variations with both time and temperature are several orders of magnitude lower than obtainable in LC or RC oscillator circuits. The very high stiffness and elasticity of piezoelectric quartz make it possible to produce resonators extending from approximately 1 kHz to 200 MHz. The performance characteristics of crystal depend on both the particular cut and the mode of vibration (see Section 5). For convenience, each “cut-mode” combination is considered as a separate piezoelectric element, and the more commonly used elements have been designated with letter symbols. The audio-frequency range (above 1 kHz) is covered by elements J, H, N, and XY, as shown in Table 11.2.2. The temperature coefficients vary with frequency, i.e., with the crystal dimensions, and except for the H element, a parabolic frequency variation with temperature is observed. The H element is characterized by a

TABLE 11.2.2 Low-Frequency Crystal Elements Symbol

Cut

Mode of vibration

J H N XY

Duplex 5°X 5°X NT XY

Length-thickness flexure Length-width flexure Length-width flexure XY flexure

Frequency range, kHz 0.9–10 10–50 4–200 8–40

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negative temperature coefficient on the order of –10 ppm/°C. The other elements have lower temperature coefficients, which at some temperatures are zero because of the parabolic nature of the frequency-deviation curve. The point where the zero temperature coefficient occurs is adjustable and varies with frequency. At temperatures below this point the coefficient is positive, and at higher temperatures it is negative. On the slope of the curves the temperature coefficients for the N and XY elements are on the order of 2 ppm/°C, whereas the J element is about double at 4 ppm/°C. Although the various elements differ in both cut and mode of vibration, the electric equivalent circuit remains invariant. The schematic representation and the lumped constant equivalent circuit are shown in Fig. 11.2.18. As is characteristic of most mechanical resonators, the motional inductance L resulting from the mechanical mass in motion is large relative to that obtainable from coils. The extreme stiffness of quartz makes for very small values of the motional capacitance C, and the very high order of elasticity allows the motional resistance R to be relatively low. The shunt capacitance C0 is the electrostatic capacitance existing between crystal electrodes with the quartz plate as the dielectric and is present whether or not the crystal is in mechanical motion. Some FIGURE 11.2.18 Symbol and equivalent circuit of typical values for these equivalent-circuit parameters are a quartz crystal. shown in Table 11.2.3. The H element can have a high Q value when mounted in a vacuum enclosure; however, it then has the poorest temperature coefficient. The N element exhibits an excellent temperature characteristic, but the piezoelectric activity is rather low, so that special care is required when it is used in oscillator circuits. The J and XY elements operate well in low-frequency oscillator designs, the latter having lower temperature drift. For the same frequency the XY crystal is about 40 percent longer than the J element. Where extreme frequency stability is required, the crystals are usually controlled to a constant temperature. The reactance curve of a quartz resonator is shown in Fig. 11.2.19. The zero occurs at the frequency fs, which corresponds to series resonance of the mechanical L and C equivalences. The antiresonant frequency fp is dependent on the interelectrode capacitance C0. Between fs and fp the crystal is inductive and this frequency range is normally referred to as the crystal bandwidth BW = fs /(2C0 /C )

(9)

In oscillator circuits the crystal can be used as either a series or a parallel resonator. At series resonance the crystal impedance is purely resistive, but in the parallel mode the crystal is operated between fs and fp and is therefore inductive. For oscillator applications the circuit capacitance shunting the crystal must also be included when specifying the crystal, since it is part of the resonant circuit. If a capacitor CL, that is, a negative reactance, is placed in series with a crystal, the combination will series-resonate at the frequency fR of zero reactance for the combination.   1 f R = fs 1 +   (2C0 / C )(1 + CL / C0 ) 

(10)

TABLE 11.2.3 Typical Crystal Parameter Values Element

Frequency, kHz

L, H

C, pF

R, kΩ

C0, pF

Q, approx

J H N XY

10 10 10 10

8,000 2,500 8,000 12,000

0.03 0.1 0.03 0.02

50 10 75 30

6 75 30 20

20,000 20,000 10,000 30,000

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FIGURE 11.2.19 Quartz-crystal reactance curve.

FIGURE 11.2.20 Crystal oscillator using an integrated-circuit operational amplifier.

The operating frequency can vary in value due to changes in the load capacitance, and this variation is prescribed by ∆ fR =

fs ∆CL /C0 2C0 /C (1 + CL /C0 )2

(11)

This effect can be used to “pull” the crystal for initial alignment, or if the external capacitor is a voltagecontrollable device, a VCO with a range of about ±0.01 percent can be constructed. Phase changes in the amplifier will also give rise to frequency shifts since the total phase around the loop must remain at 0° to maintain oscillation. Although single-stage transistor designs are possible, more flexibility is available in the circuit of Fig. 11.2.20, which uses an integrated-circuit operational amplifier for the gain element. The crystal is operated in the series mode, and the amplifier gain is precisely controlled by the negative-feedback divider R2 and R3. The output will be sinusoidal if R  VD R1  1 + 3  < Vlim R1 + R  R2 

(12)

where VD is the limiting diode forward voltage drop and Vlim is the limiting level of amplifier output. Low-cost electronic wristwatches use quartz crystals for establishing a high degree of timekeeping accuracy. A high-quality mechanical watch may have a yearly accuracy on the order of 20 min, whereas many quartz watches are guaranteed to vary less than 1 min/year. Generally the XY crystal is used, but other types are continually being developed to improve accuracy, reduce size, and lower manufacturing cost. The active gain elements for the oscillator are part of the integrated circuit that contains the electronics for the watch functions. The flexure or tuning-fork frequency is set generally to 32,768 Hz, which is 215 Hz. This frequency reference is divided down on the integrated circuit to provide seconds, minutes, hours, day of the week, date, month, and so forth. A logic gate or inverter is often used as the gain element in the oscillator circuit. A typical configuration is shown in Fig. 11.2.21. The resistor R1 is used to bias the logic inverter for class A amplifier operation. The resistor R2 helps reduce both voltage sensitivity of the network and crystal power dissipation. The combination of R2 and C2 provides added phase shift for good oscillator startup. The series combination of capacitors

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C1 and C2 provides the parallel load for the crystal. C1 can be made tunable for precise setting of the crystal oscillation frequency. The inverter provides the necessary gain and 180° phase shift. The p network consisting of the capacitors and the crystal provides the additional 180° phase shift needed to satisfy the conditions for oscillation.

Frequency Stability Many factors contribute to the ability of an oscillator to hold a constant output frequency over a period of time and range from short-term effects, caused by random noise, to longer-term variations, caused by circuit parameter dependence on temperature, bias voltage, and the like. In addition to the temperature and aging effects of the frequency-determining elements, nonlinearities, impedance loading, and amplifier phase variations also contribute to instability. Harmonics generated by circuit nonlinearities are passed through the feedback network, with various phase shifts, to the input of the amplifier. Intermodulation of the harmonic frequencies produces a fundamental frequency component that differs in phase from the amplifier output. Since the condition Ab = 1 must be satisfied, the frequency of oscillation will shift so that the network phase shift cancels the phase perturbation caused by the nonlinearity. Therefore, the frequency of oscillation is influenced by an unpredictable amplifier characteristic, namely, the FIGURE 11.2.21 Crystal oscillator using a logic gate saturation nonlinearity. This effect is negligible in the Wien for the gain element. bridge oscillator, where automatic level control keeps harmonic distortion to a minimum. The relationships shown in Fig. 11.2.17 were derived assuming that the amplifier does not load the bridge circuit on either the input or output sides. In the practical sense this is never true, and changes in the input and output impedances will load the bridge and cause frequency variations to occur. Another source of frequency instability is small phase changes in the amplifier. The effect is minimized by using a network with a large stability factor, defined by S=

dφ dω / ω 0

(13) ω = ω0

For the Wien bridge oscillator, which has amplitude-sensitive resistive feedback, the RC impedances can be optimized to provide a maximum stability factor value. As shown in Fig. 11.2.17, this amounts to choosing proper values for M and N. The maximum stability-factor value is A/4, and it occurs for N = 1/2 and M = 2. Most often the bridge is used with equal resistor and capacitor values; that is, M = N = 1, in which case the stability factor is 2A/9. This represents only a slight degradation from the optimum.

Synchronization It is often desirable to lock the oscillator frequency to an input reference. Usually this is done by injecting sufficient energy at the reference frequency into the oscillator circuit. When the oscillator is tuned sufficiently close to the reference, natural oscillations cease and the synchronization signal is amplified to the output. Thus the circuit appears to oscillate at the injected signal frequency. The injected reference is amplitude-stabilized by the AGC or limiting circuit in the same manner as the natural oscillation. The frequency range over which locking can occur is a linear function of the amplitude of the injected signal. Thus, as the synchronization frequency is moved away from the natural oscillator frequency, the amplitude threshold to maintain lock increases. The phase

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error between the input reference and the oscillator output will also deviate as the input frequency varies from the natural frequency. Methods for injecting the lock signal vary and depend on the type of oscillator under consideration. For example, LC oscillators may have signals coupled directly to the tank circuit, whereas the lock signal for the Wien network is usually coupled into the center of the resistive side of the bridge, i.e., the junction of R1 and R2 in Fig. 11.2.17. If the natural frequency of oscillation can be voltage controlled, synchronization can be accomplished with a phase-locked loop. Replacing both R’s with field-effect transistors, or alternatively shunting both C’s with varicaps, provides an effective means for voltage controlling the frequency of the Wien bridge oscillator. Although more complicated in structure, the phase-locked loop is more versatile and has many diverse applications.

Piezoelectric Annunciators Another important class of audio oscillators uses piezoelectric elements for both frequency control and audiblesound generation. Because of their low cost and high efficiency these devices are finding increasing use in smoke detectors, burglar alarms, and other warming devices. Annunciators using these elements typically produce a sound level in excess of 85 dB measured at a distance of 10 ft. Usually the element consists of a thin brass disk to which a piezoelectric material has been attached. When an electric signal is applied across its surfaces, the piezoceramic disk attempts to change diameter. The brass disk to which it is bonded acts as a spring restraining force on one surface of the ceramic. The brass plate serves as one electrode for applying the electric signal to the ceramic. On the other surface a fired-on silver paste is used as an electrode. The restraining action of the brass disk causes the assembly to change from a flat to a convex shape. When the polarity of the electric signal reverses, the assembly flexes in the other direction to a concave shape. When the device is properly mounted in a suitable horn structure, this motion is used to produce high-level sound waves. One useful method is to clamp the disk at nodal points, i.e., at a distance from the center of the disk where mechanical motion is at a vibrational null. The piezoelectric assembly will produce sound levels more efficiently when excited near the series-resonant frequency. The simple equivalent circuit used for the quartz crystal (Fig. 11.2.18) also applies to the piezoceramic assembly for frequencies near resonance. Generally the piezoelectric element is used as the frequency-determining element in an audio oscillator. The advantage of this method is that the excitation frequency is inherently near the optimum value, since it is self-excited. A typical piezoceramic 1-in diameter mounted on a 13/4-in brass disk would have the following equivalent values: C0 = 0.02 µF, C = 0.0015 µF, L = 2 H, R = 500 Ω, Q = 75, fs = 2.9 kHz, and fp = 3.0 kHz. A basic oscillator, capable of producing high-level sound, is shown in Fig. 11.2.22. The inductor L1 provides a dc path to the transistor and broadly tunes the parallel input capacitance of the piezoelectric element. C1 is an optional capacitor which adds to the input shunt capacitance for optimizing the drive impedance to the element. Resistor R1 provides base-current bias to the transistor so that oscillation can start. The element has a third small electrode etched in the silver pattern. It is used to derive a feedback signal which, when resistively loaded by R1, provides an in-phase signal to the base for sustaining circuit oscillation. The circuit operates like a blocking oscillator in that the transistor is switched on and off and the collector voltage can fly above B-plus because of the inductor L1. FIGURE 11.2.22 Basic audio annunciator oscillaThe collector load consisting of L1 and C1 can be replaced tor circuit using a thin-disk piezoelectric transducer. with a resistor, in which case the audio output will be less.

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Source: STANDARD HANDBOOK OF ELECTRONIC ENGINEERING

CHAPTER 11.3

RADIO-FREQUENCY AMPLIFIERS AND OSCILLATORS G. Burton Harrold, John W. Lunden, Jennifer E. Doyle, Chang S. Kim, Conrad E. Nelson, Gunter K. Wessel, Stephen W. Tehon, Y. J. Lin, Wen-Chung Wang, Harold W. Lord

RADIO-FREQUENCY AMPLIFIERS G. Burton Harrold Small-Signal RF Amplifiers The prime considerations in the design of first-stage rf amplifiers are gain and noise figure. As a rule, the gain of the first rf stage should be greater than 10 dB, so that subsequent stages contribute little to the overall amplifier noise figure. The trade-off between amplifier cost and noise figure is an important design consideration. For example, if the environment in which the rf amplifier operates is noisy, it is uneconomic to demand the ultimate in noise performance. Conversely, where a direct trade-off exists in transmitter power versus amplifier noise performance, as it does in many space applications, money spent to obtain the best possible noise figure is fully justified. Another consideration in many systems is the input-output impedance match of the rf amplifier. For example, TV cable distribution systems require an amplifier whose input and output match produce little or no line reflections. The performance of many rf amplifiers is also specified in handling large signals, to minimize cross- and intermodulation products in the output. The wide acceptance of transistors has placed an additional constraint on first-stage rf amplifiers, since many rf transistors having low noise, high gain, and high frequency response are susceptible to burnout and must be protected to prevent destruction in the presence of high-level input signals. Another common requirement is that first rf stages be gain-controlled by automatic gain control (AGC) voltage. The amount of gain control and the linearity of control are system parameters. Many rf amplifiers have the additional requirement that they be tuned over a range of frequencies. In most receivers, regardless of configuration, local-oscillator leakage back to the input is strictly controlled by government regulation. Finally, the rf amplifier must be stable under all conditions of operation. Device Evaluation for RF Amplifiers An important consideration in an rf amplifier is the choice of active device. This information on device parameters can often be found in published data sheets. If parameter data are not available or not a suitable operating point, the following characterization techniques can be used. Network Analyzers. The development of the modern network analyzer has eliminated much of the work in device and circuit evaluation. These systems automate sweep frequency measurements of the complex device or 11.35 Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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FIGURE 11.3.1 Use of the Rx meter in device characterization.

circuit parameters and avoid the tedious calculations that were previously required. The range of measurement frequencies extends from a few hertz to 60 GHz. Network analyzers perform the modeling function by measuring the transfer and impedance function of the device by means of sine-wave excitation. These transfer voltages/currents and the reflected voltages/currents are then separated, and the proper ratios are formed to define the device parameters. There results are then displayed graphically and/or in a digital form for designer use. Newer systems allow these data to be transferred directly to computerized design programs, thus automating the total design process. The principle of actual operation is similar to that described below under Vector Voltmeter. Rx Meter.* This measurement technique is usually employed at frequencies below 200 MHz for active devices that have high input and output impedance. The technique is summarized in Fig. 11.3.1 with assumptions tacit in these measurements. The biasing techniques are shown. In particular, the measurement of h22b requires a very large resistor Re to be inserted in the emitter, and this may cause difficulty in achieving the proper biasing. Care should be taken to prevent burnout of the bridge when a large dc bias is applied. The bridge’s drive to the active device may be reduced for more accurate measurement by varying the B-plus voltage applied to the internal oscillator. Vector Voltmeter.* This characterization technique measures the S parameters; see Fig. 11.1.9. The measurement consists in inserting the device in a transmission line, usually 50 Ω characteristic impedance, and measuring the incident and reflected voltages at the two ports of the device.

*Trademark of the Hewlett Packard Co.

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FIGURE 11.3.2 Noise-measurement techniques: (a) at low frequencies; (b) at high frequencies.

Several other techniques include the use of the H-P 8743 reflectometer, the general radio bridge GR 1607, the Rhode-Schwartz diagraph, and the H-P type 8510 microwave network analyzer to measure device parameters automatically from 45 MHz to 100 GHz with display and printout features. Noise in RF Amplifiers A common technique employing a noise source to measure the noise performance of an rf amplifier is shown in Fig. 11.3.2. Initially the external noise source (a temperature-limited diode) is turned off, the 3dB pad short-circuited, and the reading on the output power meter recorded. The 3-dB pad is then inserted, the noise source is turned on, and its output increased until a reading equal to the previous one is obtained. The noise figure can then be read directly from the noise source, or calculated from 1 plus the added noise per unit bandwidth divided by the standard noise power available KT0, where T0 = 290 K and K = Boltzmann’s constant = 1.38 × 10–23 J/K. At higher frequencies, the use of a temperature-limited diode is not practical, and a gas-discharge tube or a hot-cold noise source is employed. The Y-factor technique of measurement is used. The output from the device to be measured is put into a mixer, and the noise output converted to a 30- or 60-MHz center-frequency (i.f.) output. A precision attenuator is then inserted between this i.f. output and the power-measuring device. The attenuator is adjusted to give the same power reading for two different conditions of noise power output represented by effective temperatures T1 and T2. The Y factor is the difference in decibels between the two precision attenuator values needed to maintain the same power-meter reading. The noise factor is F=

(T2 / 290) − T1Y / 290 +1 Y −1

where T1 = effective temperature at reference condition 1 T2 = effective temperature of reference condition 2 Y = decibel reading defined in the text, converted to a numerical ratio

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In applying this technique it is often necessary to correct for the second-stage noise. This is done by use of the cascade formula F1 = FT − (F2 − 1)/G1 where F1 = noise factor of first stage FT = overall noise factor measured F2 = noise factor of second-stage mixer and i.f. amplifier G1 = available gain of first stage Large-Signal Performance of RF Amplifiers The large-signal performance of an rf amplifier can be specified in many ways. A common technique is to specify the input where the departure from a straight-line input-output characteristic is 1 dB. This point is commonly called the 1-dB compression point. The greater the input before this compression point is reached, the better the large-signal performance. Another method of rating an rf amplifier is in terms of its third-order intermodulation performance. Here two different frequencies, f1 and f2, of equal powers, p1 and p2, are inserted into the rf amplifier, and the third frequency, internally generated, 2f1 – f2 or 2f2 − f1, has its power p12 measured. All three frequencies must be in the amplifier passband. With the intermodulation power p12 referred to the output, the following equation can be written: P12 = 2P1 + P2 + K12 where P12 = intermodulation output power at 2f1 − f2 or 2f2 − f1 P1 = output power at input frequency f1 P2 = output power at input frequency f2, all in decibels referred to (0 dBm) K12 = constant associated with the particular device The value of K12 in the above formula can be used to rate the performance of various device choices. Higher orders of intermodulation products can also be used. A third measure of large-signal performance commonly used is that of cross-modulation. In this instance, a carrier at fD with no modulation is inserted into the amplifier. A receiver is then placed at the output and tuned to this unmodulated carrier. A second carrier at f1 with amplitude-modulation index MI is then added. The power of PI of fI is increased, and its modulation is partially transferred to fD. The equation becomes 10 log (MK /MI) = PI + K where MK = cross-modulation index of originally unmodulated signal at fD MI = modulation index of signal FI PI = output power of signal at fI, all in decibels referred to 1 mW (0 dBm) K = cross-modulation constant Maximum Input Power In addition to the large-signal performance, the maximum power of voltage input into an rf amplifier is specified, with a requirement that device burnout must not occur at this input. There are two ways of specifying this input: by a stated pulse of energy or by a requirement to withstand a continuously applied large signal. It is also common to specify the time required to unblock the amplifier after removal of the large input. With the increased use of field effect transistors (FETs especially) having good noise performance, these overload characteristics have become a severe problem. In many cases, conventional or zener diodes, in a back-to-back configuration shunting the input, are used to reduce the amount of power the input of the active devices must dissipate. RF Amplifiers in Receivers RF amplifiers intended for the first stages of receivers have additional restrictions placed on them. In most cases, such amplifiers are tunable across a band of frequencies with one or more tuned circuits. The tuned

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circuits must track across the frequency band, and in the case of the superheterodyne, tracking of the local oscillator is necessary so that a constant frequency difference (i.f.) is maintained. The receiver’s rf section can be tracked with the local oscillator by the two- or the three-point method, i.e., with zero error in the tracking at either two or three points. A second consideration peculiar to rf amplifiers used for receivers is the AGC. This requirement is often stated by specifying a low-level rf input to the receiver and noting the power out. The rf signal input is then increased with the AGC applied until the output power has increased a predetermined amount. This becomes a measure of the AGC effectiveness. The AGC performance can also be measured by plotting a curve of rf input versus AGC voltage needed to maintain constant output, compared with the desired performance. A third consideration in superheterodynes is the leakage of the local oscillator in the receiver to the outside. This spurious radiation is specified by the Federal Communications Commission (FCC) in the United States.

Design Using Immittance and Hybrid Parameters The general gain and input-output impedance of an amplifier can be formulated, in terms of the Z or Y parameters, to be Yin = y11 −

y12 y21 y22 + yL

Yout = y22 −

y12 y21 y11 + ys

where yL = load admittance ys = source admittance Yin = input admittance Yout = output admittance GT = transducer gain and the transducer gain is GT =

4 Re ys Re yL | y21 |2 | ( y11 + ys )( y22 + yL ) − y12 y21 ) |2

for the y parameters, and interchange of z or y is allowed. The stability of the circuit can be determined by either Linvill’s C or Stern’s k factor as defined below. Using the y parameters, yij = gik + jBik, these are C=

Linvill:

| y12 y21 | 2 g11g22 − Re y12 y21

where C < 1 for stability does not include effects of load and source admittance. Stern:

k=

2( g11 + gs )( g22 + gL ) | y12 y21 | + Re y12 y21

where k > 1 for stability gL = load conductance gs = source conductance The preceding C factor defines only unconditional stability; i.e., no combination of load and source impedance will give instability. There is an invariant quantity K defined as K=

2 Re γ 11 Re γ 22 − Re γ 12γ 21 |γ 21γ 12 |

Re γ 11 > 0 Re γ 22 > 0

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where g represents either the y, z, g, or h parameters, and K > 1 denotes stability. This quantity K has then been used to define maximum available power gain Gmax (only if K > 1) Gmax = |γ 21 / γ 12 | ( K − K 2 − 1) To obtain this gain, the source and load immittance are found to be (K > 1)

γs =

γ 12γ 21 + |γ 12γ 21 | ( K + K 2 − 1) − γ 11 2 Re γ 22

γ s = sourrce immittance

γL =

γ 12γ 21 + |γ 12γ 21 | ( K + K 2 − 1) − γ 22 2 Re γ 11

γ L = load immittance

The procedure is to calculate the K factor, and if K > 1, calculate Gmax, gs, and gL. If K < 1, the circuit can be modified either by use of feedback or by adding immittances to the input-output.

Design Using S Parameters The advent of automatic test equipment and the extension of vacuum tubes and transistors to be gigahertz frequency range have led to design procedures using the S parameters. Following the previous discussion, the input and output reflection coefficient can be defined as pin = S11 + pL pout = S22 + p

S12 S21 1 − pL S22

S12 S21 1 − pS11

pL =

ZL − Z0 ZL + Z0

ps =

Zs − Z0 Zs + Z0

where Z0 = characteristic impedance pin = input reflection coefficient pout = output reflection coefficient The transducer gain can be written Gtransducer =

| S21 |2 (1− | ps |2 )(1− | pL |2 ) | (1 − S11 ps )(1 − S22 pL ) − S21S12 ps pL |2

The unconditional stability of the amplifier can be defined by requiring the input (output) impedance to have a positive real part for any load (source) impedance having a positive real part. This requirement gives the following criterion: | S11 |2 + | S12 S21 |< 1 and

η=

| S22 |2 + | S12 /S11 |< 1

1− | ∆ |2 − | S11 |2 − | S22 |2 >1 2 | S12 S21 |

∆ s = S11S22 − S12 S21

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Similarly, the maximum transducer gain, for h > 1, becomes Gmax transducer = | S21 / S12 | (η ± η2 − 1) (positive sign when |S22|2 − |S11|2 − 1 + |∆s|2 > 0) for conditions listed above. The source and load to provide conjugate match to the amplifier when h > 1 are the solutions of the following equations, which give |ps|, and |pL| less than 1 pms = C1*

B1 ± B12 − 4 |C1 |2 2 |C1 |2

pmL = C2*

B2 ± B22 − 4 |C2 |2 2 |C2 |2

where B2 = 1 + |S22|2 − |S11|2 − |∆s|2 B1 = 1 + |S11|2 − |S22|2 − |∆s|2 * * C1 = S11 − ∆ s S22 C2 = S22 − ∆ s S11 the star (∗) denoting conjugate. If |h| > 1 but h is negative or |h| < 1, it is not possible to match simultaneously the two-port with real source and load admittance. Both graphical techniques and computer programs are available to aid in the design of rf amplifiers.

Intermediate-Frequency Amplifiers Intermediate-frequency amplifiers consist of a cascade of a number of stages whose frequency response is determined either by a filter or by tuned interstages. The design of the individual active stages follows the techniques discussed earlier, but the interstages become important for frequency shaping. There are various forms of interstage networks; several important cases are discussed below. Synchronous-Tuned Interstages. The simplest forms of tuned interstages are synchronously tuned circuits. The two common types are the single- and double-tuned interstage. The governing equations are: 1. Single-tuned interstage (Fig. 11.3.3a): A( jω ) = − Ar

1 1 + jQL (ω / ω 0 − ω 0 / ω )

where QL = loaded Q of the tuned circuit greater than 10 w0 = resonance frequency of the tuned circuit = 1 √LC w = frequency variable Ar = midband gain equal to gm times the midband impedance level For an n-stage amplifier with n interstages,

AT = A ( jω ) = n

Arn

  ω2 −ω2 2 0 1 +    Bω    

− n/ 2

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where B = w0/QL = single-stage bandwidth n = number of stages w0 = center frequencies QL = loaded Q Bn = B 21/n − 1 is the overall bandwidth reduction owing to n cascades 2. Double-tuned interstage (Fig. 11.3.3b):

A( jω ) =

jω 4 3 2 C1C2 (1 − k 2 ) L1L2 ω − ja1ω − a2ω + ja3ω + a4 gm k

(for a single double-tuned stage), where

FIGURE 11.3.3 Interstage coupling circuits: (a) single-tuned; (b) double-tuned.

 1 1 a1 = ω r  +   Q Q  1 2 a3 =

a2 =

ω r2 1 + ω 2 + ω 22 Q1Q2 1 − k 2 1

ω r  ω 22 ω12   +  1 + k 2  Q1 Q2 

(

a4 =

)

ω12ω 22 1− k2

The circuit parameters are R1 = total resistance primary side C1 = total capacitance primary side L1 = total inductance primary side R2 = total resistance secondary side C2 = total capacitance secondary side L2 = total inductance secondary side M = mutual inductance = k√L1L2 k = coefficient of coupling

wr = resonant frequency of amplifier w1 = 1/√L1C1 w1 = 1/√L2C2 Q1 = primary Q at wr = wrC1R1 Q2 = secondary Q at wr = wrC2R2 gm = transconductance of active device at midband frequency

Simplification. If w1 = w2 = w0, that is, primary and secondary tuned to the same frequency, then

ωr = ω 0/ 1− k2 is the resonant frequency of the amplifier and

A( jω r ) =

+ jkgm R1R2 Q1Q2 (k 2 + 1/ Q1Q2 )

is the gain at this resonant frequency. For maximum gain, kc =

1 Q1Q2

= critical coupling

and for maximum flatness,

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FIGURE 11.3.4 Selective curves for two identical circuits in a double-tuned interstage circuit, at various values of k/kc.

kT =

1 1 1   2 + 2  = transitional coupling 2  Q1 Q2 

If k is increased beyond kT, a double-humped response is obtained. Overall bandwidth of an n-stage amplifier having equal Q circuits with transitional coupled interstages whose bandwidth is B is Bn = B(21/n − 1)1/4 The governing equations for the double-tuned-interstage case are shown above. The response for various degrees of coupling related to kT = kC in the equal-coil-Q case is shown in Fig. 11.3.4.

Maximally Flat Staggered Interstage Coupling This type of coupling consists of n single-tuned interstages that are cascaded and adjusted so that the overall gain function is maximally flat. The overall cascade bandwidth is Bn, the center frequency of the cascade is wc, and each stage is a single-tuned circuit whose bandwidth B and center frequency are determined from Table 11.3.1. The gain of each stage at cascade center frequency is A(jwc) = −gm/CT [B + j(w 2c − w 20 /wc], where CT = sum of output capacitance and input capacitance to next stage and wiring capacitance of cascade, B = stage bandwidth, w0 = center frequency of stage, and wc = center frequency of cascade.

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TABLE 11.3.1 n

Design Data for Maximally Flat Staggered n-tuples Name of circuit

2 3

Staggered pair Staggered triple

4

Staggered quadruple

5

Staggered quintuple

6

Staggered sextuple

7

Staggered septuple

No. of stages

Center frequency of stage

Stage bandwidth

2 2 1 2 2 2 2 1 2 2 2 2 2 2 1

wc ± 0.35Bn wc ± 0.43Bn wc wc ± 0.46Bn wc ± 0.19Bn wc ± 0.29Bn wc ± 0.48Bn wc wc ± 0.48Bn wc ± 0.35Bn wc ± 0.13Bn wc ± 0.49Bn wc ± 0.39Bn wc ± 0.22Bn wc

0.71Bn 0.50Bn 1.00Bn 0.38Bn 0.92Bn 0.81Bn 0.26Bn 1.00Bn 0.26Bn 0.71Bn 0.97Bn 0.22Bn 0.62Bn 0.90Bn 1.00Bn

For QL > 20

RADIO-FREQUENCY OSCILLATORS G. Burton Harrold General Considerations Oscillators at rf frequencies are usually of the class A sine-wave-output type. RF oscillators (in common with audio oscillators) may be considered either as one-port networks that exhibit a negative real component at the input or as two-port-type networks consisting of an amplifier and a frequency-sensitive passive network that couples back to the input port of the amplifier. It can be shown that the latter type of feedback oscillator also has a negative resistance at one port. This negative resistance is of a dynamic nature and is best defined as the ratio between the fundamental components of voltage and current. The sensitivity of the oscillator’s frequency is directly dependent on the effective Q of the frequencydetermining element and the sensitivity of the amplifier to variations in temperature, voltage variation, and aging. For example, the effective Q of the frequency-determining element is important because the percentage change in frequency required to produce the compensating phase shift in a feedback oscillator is inversely proportional to the circuit Q, thus the larger the effective Q the greater the frequency stability. The load on an oscillator is also critical to the frequency stability since it affects the effective Q and in many cases the oscillator is followed by a buffer stage for isolation. It is also desirable to provide some means of stabilizing the oscillator’s operating point, either by a regulated supply, dc feedback for bias stabilization, or oscillator self-biasing schemes such as grid-leak bias. This stabilizes not only the frequency but also the output amplitude, by tending to compensate any drift in the active device’s parameters. It is also necessary to eliminate the harmonics in the output since they give rise to cross-modulation products producing currents at the fundamental frequency that are not necessarily in phase with the dominant oscillating mode. The use of high-Q circuits and the control of the nonlinearity helps in controlling harmonic output. Negative-Resistance Oscillators The analysis of the negative-impedance oscillator is shown in Fig. 11.3.5. The frequency of oscillation at buildup is not completely determined by the LC circuit but has a component that is dependent upon the circuit resistance. At steady state, the frequency of oscillation is a function of 1 + R/Riv or 1 + Ric/R, depending on the particular circuit where the ratios R/Ric, Riv/R are usually chosen to be small. While R is a fixed function of the

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FIGURE 11.3.5 General analysis of negative-resistance oscillators.

loading, Ric or Riv/R must change with amplitude during oscillator buildup, so that the condition of a = 0 can be reached. Thus Riv, Ric cannot be constant but are dynamic impedances defined as the ratio of the fundamental voltage across the elements to the fundamental current into the element. The type of dc load for biasing and the resonant circuit required for the proper operation of a negativeresistance oscillator depend on the type of active element. R must be less than |Riv| or R must be greater than |Ric| in order for oscillation to build up and be sustained. The detailed analysis of the steady-state oscillator amplitude and frequency can be undertaken by graphical techniques. The magnitude of Gi or Ri is expressed in terms of its voltage dependence. Care must be taken with this representation, since the shape of the Gi or Ri curve depends on the initial bias point. The analysis of negative-resistance oscillators can now be performed by means of admittance diagrams. The assumption for oscillation to be sustaining is that the negative-resistance element, having admittance yi, must equal –yc, the external circuit admittance. This can be summarized by Gi = −Gc and Bi = −Bc. A typical set of admittance curves is shown in Fig. 11.3.6. In this construction, it is assumed that Bi = −Bc, even during the oscillator buildup. Also shown is the fact that Gi at zero amplitude must be larger than Gc so that the oscillator can be started, that is, a > 0, and that it may be possible to have two or more stable modes of oscillation. Feedback Oscillators Several techniques exist for the analysis of feedback oscillators. In the generalized treatment, the active element is represented by its y parameters whose element values are at the frequency of interest, having magnitudes

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FIGURE 11.3.6 Admittance diagram of voltage-stable negative-resistance oscillators: (a) self-starting case, a > 0; (b) circuit starts oscillating only if externally excited beyond point 1.

defined by the ratio of the fundamental current divided by fundamental voltage. The general block diagram and equations are shown in Fig. 11.3.7. Solution of the equations given yields information on the oscillator’s performance. In particular, equating the real and imaginary parts of the characteristic equation gives information on amplitude and frequency of oscillation. In many instances, many simplifications to these equations can be made. For example, if y11 and y12 are made small (as in vacuum-tube amplifiers), then y21 = −(1/z21)(y22z11 + 1) = −1/Z This equation can be solved by equating the real and imaginary terms to zero to find the frequency and the criterion for oscillation of constant amplitude. This equation can also be used to draw an admittance diagram for oscillator analysis.

FIGURE 11.3.7 General analysis of feedback oscillators.

FIGURE 11.3.8 Admittance diagram of feedback oscillator.

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FIGURE 11.3.9 S-parameter and analysis of oscillators.

These admittance diagrams are similar to those discussed under negative-resistance oscillators. The technique is illustrated in Fig. 11.3.8. At higher frequencies, the S parameters can also be used to design oscillators (Fig. 11.3.9). The basis for the oscillator is that the magnitude of the input reflection coefficient must be greater than unity, causing the circuit to be potentially unstable (in other words, it has a negative real part for the input impedance). The input reflection coefficient with a ΓL output termination is S11 ′ = S11 +

S12 S21Γ L 1 − S22 Γ L

Either by additional feedback or adjustment of ΓL it is possible to make |S¢11| > 1. Next, establishing a load Γs such that it reflects all the energy incident on it will cause the circuit to oscillate. This criterion is stated as ΓLS¢11 = 1 at the frequency of oscillation. This technique can be applied graphically, using a Smith chart as before. Here the reciprocal of S¢11 is plotted as a function of frequency since S¢11 > 1. Now choose either a parallel or a series-tuned circuit and plot its Γs. If f1 is the frequency common to 1/S¢11 and Γs, and satisfies the above criterion, the circuit will oscillate at this point.

BROADBAND AMPLIFIERS John W. Lunden, Jennifer E. Doyle Introduction In broadband amplifiers signals are amplified so as to preserve over a wide band of frequencies such characteristics as signal amplitude, gain response, phase shift, delay, distortion, and efficiency. The width of the band depends on the active device used, the frequency range, and power level in the current state of the art. As a general rule, above 100 MHz, a 20 percent or greater bandwidth is considered broadband, whereas an octave or more is typical below 100 MHz. As the state-of-the-art advances, it is becoming more common to achieve octave-bandwidth or wider amplifiers well into the microwave region using bipolar and FET active devices. Hybrid-integrated-circuit techniques and new monolithic techniques eliminate many undesired package and bonding parasitics which can limit broadband amplifier performance. Additionally, distributed amplifiers, and other approaches which use multiple devices, have become more economical with increasing levels of integration. It has become uncommon to use tube devices for new amplifier designs. Solid-state devices have replaced tubes in most amplifier applications because of superior long-term reliability and lower noise figures. In the following discussion both field-effect and bipolar transistor notations appear for generality.

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FIGURE 11.3.10 RC-coupled stages: (a) field-effect transistor form; (b) bipolar junction transistor form.

Low-, Mid-, and High-Frequency Performance Consider the basic common-source and common-emitter-broadband RC coupled configurations shown in Fig. 11.3.10. Simplified low-frequency small-signal equivalent circuits are shown in Fig. 11.3.11. The voltage gain of the FET amplifier stage under the condition that all reactances are negligibly small is the midband value (at frequency f ) ( Amid ) FET =

− gm ≈ − gm RL 1/rds + 1/ RL + 1/ Rg

FIGURE 11.3.11 Equivalent circuits of the stages shown in Fig. 11.3.10: (a) FET form; (b) bipolar form.

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If the low-frequency effects are included, this becomes ( Alow )FET =

  − gm RL 1 + 1/ jω RS CS − gm RL for RS = 0  = 1 + 1/ jω RgCg 1 + (1 + gm RS )/ jω CS RS  1 + 1/ jω RgCg 

The low-frequency cutoff is because principally of two basic time constants, RgCg and RSCS. For CS values large enough for the time constant to be much longer than that associated with Cg, a low-frequency cutoff or half-power point can be determined as ( f1 )FET =

1 2π Cg [ Rg + rds RL /(rds + RL )]

If the coupling capacitor is very large, the low-frequency cutoff is a result of CS. The slope of the actual rolloff is a function of the relative effect of these two time constants. Therefore, the design of coupling and bypass circuits to achieve very-low-frequency response requires very large values of capacitance. Similarly, for a bipolar transistor stage, the midband current gain can be determined as ( Amid ) BJT =

−α rc RL  R r (1 − α )  [ RL + rc (1 − α )]  Rie + L c  R L + rc (1 − α )  

Rie = rb +

where

≈

RL −α 1 − α RL + Rie

re 1− α

When low-frequency effects are included, this becomes ( Alow ) BJT ≈

RL −α 1 − α RL + Rie − j/ωCg

for RL  rc (1 − α )

and ( f1 ) BJT =

1 2π Cg

1 1 1 ≈ RL rc (1 − α ) 2π Cg Rie + RL Rie + RL + rc (1 − α )

If the ratio of low- to midfrequency voltage or current gain is taken, its reactive term goes to unity at f = f1, that is, the cutoff frequency. Alow 1 = Amid 1 − j ( f1 / f )

φlow = tan −1

f1 f

These quantities are plotted in Fig. 11.3.12 for a single time-constant rolloff. Caution should be exercised in assuming that reactances between input and output terminals are negligible. Although this is generally the case, gain multiplicative effects can result in input or output reactance values greater than the values assumed above, e.g., by the Miller effect: Cin = Cgs + Cgd(1 + gmR¢L)

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FIGURE 11.3.13 Gain and phase-shift curves at high frequencies.

FIGURE 11.3.12 Gain and phase-shift curves at low frequencies.

Typically, the midfrequency gain equation can be used for frequencies above that at which Xc = Rg/10 below that at which Xcg = 10RgRL/(Rg + RL) (for the FET circuit). If the frequency is increased further, a point is reached where the shunt reactances are no longer high with respect to the circuit resistances. At this point the coupling and bypass capacitors can be neglected. The highfrequency gain can be determined as ( Ahigh )FET =

− gm 1/rds + 1/ RL + jω CL

where CL is the effective total interstage shunt capacitance. ( Ahigh ) BJT ≈

−α 1− α

1  1 jωCc  1 + Rie  +  1 R −α   L

for RL  rc (1− α )

The ratio of high- to midfrequency gains can be taken and upper cutoff frequencies determined  Ahigh     Amid 

= FET

( f2 )FET =  Ahigh     Amid 

= BJT

( f2 ) BJT ≈

1 1 + jωCL 1 2π CL

1 (1/ rds ) + (1/ RL ) + (1/ Rg )

 1 1 1  + +   rds RL Rg 

1 jωCcrc RL Rie 1+ Rie [ RL + rc (1 − α )] + RL rc (1 − α ) 1− α  1 1  +   2π Cc  RL Rie 

and φhigh = −tan −1 ( f / f2 )

Dimensionless curves for these gain ratios and phase responses are plotted in Fig. 11.3.13. Compensation Techniques To extend the cutoff frequencies f1 and f2 to lower or higher values, respectively, compensation techniques can be used. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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Figure 11.3.14 illustrates two techniques for low-frequency compensation. If the condition RgCg = CXRXRL/(RX + RL) is fulfilled (in circuit a or b), the gain relative to the midband gain is Alow 1 = and Amid 1 − j (1/ ω RgCg )[ RL /( RL + RX )]

f1 =

RL 1 2π RgCg RL + RX

Hence, improved low-frequency response is obtained with increased values of RX. This value is related to RL and restricted by active-device operating considerations. Also, RL is dependent on the desired high-frequency response. It can be shown that equality of time constants RLCX = RgCg will produce zero phase shift in the coupling circuit (for RX > 1/wCx). The circuit shown in Fig. 11.3.14c is more critical. It is used with element ratios set to RL/RX = Rg/Rc and CX /Cg = Rc/RX. Various compensation circuits are also available for high-frequency-response extension. Two of the most common, the series- and shunt-compensation cases, are shown in Fig. 11.3.15. The high-frequency-gain expressions of these configurations can be written Ahigh Amid

=

1 + a1 ( f / f2 )2 + a2 ( f / f2 )4 +  1 + b1 ( f / f2 )2 + b2 ( f / f2 )4 + b3 ( f / f2 )6 + 

The coefficients of the terms decrease rapidly for the higher-order terms, so that if a1 = b1, a2 = b2, etc., to as high an order of the f / f2 ratio as possible, a maximally flat response curve is obtained. For the phase response, df/dw can also be expressed as a ratio of two polynomials in f / f2, and a similar procedure can be followed. A flat time-delay curve results. Unfortunately, the sets of conditions for flat gain and linear phase are different, and compromise values must be used.

FIGURE 11.3.14 Low-frequency compensation networks: (a) bipolar transistor version; (b), (c) FET versions.

Ahigh Amid

=

Shunt Compensation. The high-frequency gain and time delay for the shunt-compensated stage are

1 + α 2 ( f / f2 ) 2 1 + (1 − 2α )( f / f2 )2 + α 2 ( f / f2 )4

φ = −tan −1

2    f  f  1− α +   α 2   f2   f2   

where a = L/Cg R2L and Rg >> RL. A case when Rg cannot be assumed to be high, such as the input of a following bipolar transistor stage, is considerably more complex, depending on the transistor equivalent circuit used. This is particularly true when operating near the transistor fT and/or above the VHF band. Series Compensation. In the series-compensated circuit, the ratio of Cs to Cg is an additional parameter. If this can be optimized, the circuit performance is better than in the shunt-compensated case. Typically, however, control of this parameter is not available due to physical and active-device constraints. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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FIGURE 11.3.15 High-frequency compensation schemes: (a) shunt; (b) series; (c) shunt-series.

These two basic techniques can be combined to improve the response at the expense of complexity. The shunt-series-compensation case and the so-called “modified” case are examples. The latter involves a capacitance added in shunt with the inductance L or placing L between Cs and RL. For the modified-shunt case, the added capacitance Cc permits an additional degree of freedom, and associated parameter, k1 = Cc/Cs. Other circuit variations exist for specific broadband compensation requirements. Phase compensation, for example, may be necessary as a result of cascading a number of minimum-phase circuits designed for flat frequency response. Circuits such as the lattice and bridged-T can be used to alter the system response by reducing the overshoot without severely increasing the overall rise time.

Cascaded Broadband Stages When an amplifier is made up of n cascaded RC stages, not necessarily identical, the overall gain An can be written  An 1 = Amid  1 + ( f / fa )2

1/ 2

 1   1 + ( f / fb )2

1/ 2

1/ 2

1  1 + ( f / fn ) 2

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where fa, fb,…, fn are the f1 or f2 values for the respective stages, depending on whether the overall low- or highfrequency gain ratio is being determined. The phase angle is the sum of the individual phase angles. If the stages are identical, fa = fb = fx for all, and An 1 = Amid 1 + ( f / fx )2

n/ 2

Stagger Peaking. In stagger tuning a number of individual bandpass amplifier stages are cascaded with frequencies skewed according to some predetermined criteria. The most straightforward is with the center frequencies adjusted so that the f2 of one stage concludes with the f1 of the succeeding stage, and so forth. The overall gain bandwidth then becomes N

(GBW)n = ∑ (GBW)n n =1

A significant simplifying criterion of this technique is stage isolation. Isolation, in transistor stages particularly, is not generally high, except at low frequencies. Hence the overall design equations and subsequent overall alignment can be significantly complicated because of the interactions. Complex device models and computer-aided design greatly facilitate the implementation of this type of compensation. The simple shuntcompensated stage has found extensive use in stagger-tuned pulse-amplifier applications. Transient Response Time-domain analysis is particularly useful for broadband applications. Extensive theoretical studies have been made of the separate effects of nonlinearities of amplitude and phase response. These effects can be investigated starting with a normalized low-pass response function. A( jw)/A(0) = exp (amwm − jbnwn) where a and m are constants describing amplitude-frequency response and b and n are constants describing phase-frequency response. Figure 11.3.16 illustrates the time response to an impulse and a unit-step forcing function for various values of m, with n = 0. Rapid change of amplitude with frequency (large m) results in

FIGURE 11.3.16 Transient responses to unit impulse (left) and unit step (right) for various values of m.

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AMPLIFIERS AND OSCILLATORS

overshoot. Nonzero, but linear, phase-frequency characteristics (n = 1) result in a delay of these responses, without introducing distortion. Further increase in n results in increased ringing and asymmetry of the time function. An empirical relationship between rise time (10 to 90 percent) and bandwidth (3 dB) can be expressed as tr · BW = K where K varies from about 0.35 for circuits with little or no overshoot to 0.45 for circuits with about 5 percent overshoot. K is 0.51 for the ideal rectangular low-pass response with 9 percent overshoot; for the Gaussian amplitude response with no overshoot, K = 0.41. The effect on rise time of cascading a number of networks n depends on the individual network pole-zero configurations. Some general rules follow. 1. For individual circuits having little or no overshoot, the overall rise time is trt = (tr21 + tr22 + tr23 + )1/ 2 2. If tr1 = tr2 = trn, trt = 1.1 ntr1 3. For individual stage overshoots of 5 to 10 percent, total overshoot increases as n. 4. For circuits with low overshoot (∼1 percent), the total overshoot is essentially that of one stage.

FIGURE 11.3.17 Response to a unit step of n capacitively coupled stages of the same time constant.

The effect of insufficient low-frequency response of an amplifier is sag of the time response. A small amount of sag ( f f

for all f

The cutoff frequency ff is adjusted to select the output spectral lobe about zero fc < ff < 1/T − fc and will fall in the guard band between lobes. That portion of filter output R( f ) selected is R0( f ) = (1/T )F( f ) exp (–j2paf )

(3)

r0(t) = (1/T)f(t − a)

(4)

that will inverse transform as

which is identical with the signal function, with the amplitude reduced by a scale factor and function shifted by a seconds. If a = 0, signifying no delay, the filter is termed a “cardinal data hold”; otherwise, it is an “ideal low-pass filter.” Unfortunately, these filters cannot be realized in practice, since they are required to respond before they are excited. Examination of Fig. 12.3.1b gives rise to the sampling theorem accredited to Shannon and/or Nyquist, which states that when a continuous time function with band-limited spectrum – fc < f < fc is sampled at twice the highest frequency, fs = 2fc, the original time function can be recovered. This corresponds to the point where the sampling frequency fs = 1/T is decreased so that the spectral lobes of Fig. 12.3.1b are just touching. To decrease fs beyond the value of 2fc would cause spectral overlap and make recovery with an ideal filter impossible. A more general form of the sampling theorem states that any 2f independent samples per second will

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MODULATORS, DEMODULATORS, AND CONVERTERS

completely describe a band-limited signal, thus removing the restriction of uniform sampling, as long as independent samples are used. In general, for a time-limited signal of T seconds, band-limited to fc Hz, only 2fcT samples are needed to specify the signal completely. In practice, the signal is not completely band-limited, so that it is common to allow for a greater separation of spectral lobes, called the guard band. This guard band is generated simply by sampling at greater than 2fc, as in the case for Fig. 12.3.1b. Although the actual tolerable overlap depends on the signal spectral slope, setting the sampling rate at about 3fc = fs is usually adequate to recover the signal. In practice, narrow but finite-width pulse trains are used in place of the idealized impulse sampling train.

PULSE-AMPLITUDE MODULATION Pulse-amplitude modulation is essentially a sampled-data type of encoding where the information is encoded into the amplitude of a train of finite-width pulses. The pulse train can be looked upon as the carrier in much the same way as the sine wave is for continuous-amplitude modulation. There is no improvement in signal-tonoise when using PAM, and furthermore, PAM is not considered wideband in the sense of FM or PTM. Thus PAM would correspond to continuous AM, while PTM corresponds to FM. Generally, PAM is used chiefly for time-multiplex systems employing a number of channels sampled, consistent with the sampling theorem. There are a number of ways of encoding information as the amplitude of a pulse train. They include both bipolar and unipolar pulse trains for both instantaneous or square-topped sampling and for exact or top sampling. In top sampling, the magnitude of the individual pulses follows the modulating signal during the pulse duration, while for square-topped sampling, the individual pulses assume a constant value, depending on the particular exact sampling point that occurs somewhere during the pulse time. These various waveforms are shown in Fig. 12.3.2. The top-modulation bipolar sampling case is shown in Fig. 12.3.2c; it is simply sampling with a finitepulse-width train. Carrying out the convolution yields RSTB ( f ) =

τ T

∞



τn 

∑  sinc T  n = −∞ 

 n F f−  T 

(5)

The spectrum for top-modulation bipolar sampling, using a square-topped rectangular spectrum for the original signal spectrum, is shown in Fig. 12.3.3a. The signal spectrum repeats with a (sin x)/x scale factor determined by the sampling pulse width, with each repetition a replica of F( f ). Unipolar sampling can be implemented by adding a constant bias A to f(t), the signal, to produce f(t) + A, where A is large enough to keep the sum positive; that is, A > | f(t)|. Sampling the new sum signal by multiplication with the pulse train results in the unipolar top-modulated waveform of Fig. 12.3.2e. The spectrum is RSTU ( f ) =

τ T

∞



τn   

n



n

∑  sinc T   F  f − T  + Aδ  f − T   n = −∞  



(6)

The delta-function part of the summation reduces to the spectrum function of the pulse train S( f ) RSTU ( f ) = AS ( f ) +

τ T

∞



τn 

∑  sinc T  n = −∞ 

 n Ff −  T 

(7)

The resulting spectrum of top-modulation unipolar sampling is the same as with bipolar sampling plus the impulse spectrum of the sampling pulse train, as shown in Fig. 12.3.3b. For square-topped-modulation bipolar sampling, the time-domain result is rSSB(t) = rect (t/t) ∗ combT f(t)

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FIGURE 12.3.2 PAM waveforms: (a) modulation; (b) square-top sampling, bipole pulse train; (c) top sampling, bipole pulse train; (d) square-top sampling, unipolar pulse train; (e) top sampling, unipolar pulse train.

with spectrum function RSSB ( f ) =

∞  τ n (sinc f τ ) ∑ F  f −  T T   n = −∞

(9)

In this case, the signal spectrum is distorted by the sinc ft envelope, as shown in Fig. 12.3.2c. This frequency distortion is referred to as aperture effect and may be corrected by use of an equalizer sinc ft form, following the low-pass reconstruction filter. As in the previous case of unipolar sampling, the resulting spectrum for square-topped modulation will contain the pulse-train spectrum, as shown in Fig. 12.3.2d. The expression is RSSU ( f ) = AS ( f ) +

∞  τ n (sinc f τ ) ∑ F  f −  T T  n = −∞

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MODULATORS, DEMODULATORS, AND CONVERTERS

FIGURE 12.3.3 PAM spectra: (a) top modulation, bipolar sampling; (b) top modulation, unipolar sampling; (c) square-top modulation, bipolar sampling; (d) square-top modulation, unipolar sampling.

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The signal information is generally recovered, in PAM systems, by use of a low-pass filter that acts on the reduced signal energy around zero frequency, as shown in Fig. 12.3.3.

PULSE-TIME, PULSE-POSITION, AND PULSE-WIDTH MODULATION In PTM the information is encoded into the time parameter instead of, for instance, the amplitude, as in PAM. There are two basic types of PTM: pulse-position modulation (PPM) and pulse-width modulation (PWM), also known as pulse-duration (PDM) or pulse-length (PLM) modulation. The PTM allows the power-driver circuitry to operate at saturation level, thus conserving power loss. Operating driver circuitry full on, full off, is especially important for heavy-duty high-load control applications, as well as for communication applications. In PPM the information is encoded into the time position of a narrow pulse, generally with respect to a reference pulse. The basic pulse width and amplitude are kept constant, while only the pulse position is changed, as shown in Fig. 12.3.4. There are three cases of PWM which are the modulation of the leading edge, trailing edge, or both edges, as displayed in Fig. 12.3.5. In this case the information is encoded into the width of the pulse, with the pulse amplitude and period held constant. The derivative relationship existing between PPM and PWM can be illustrated by consideration of trailing-edge PWM modulation. The pulses of PPM can be derived from the edges of trailing-edge PWM (Fig. 12.3.5b) by differentiation of the PWM signal and a sign change of the trailing-edge pulse. Pulse-position modulation is essentially the same as PWM, with the information-carrying variable edge replaced by a pulse. Thus, when that part of the signal power of PWM that carries no information is deleted, the result is PPM. Generally, in PTM systems a guard interval is necessary because of the pulse rise times and system responses. Thus 100 percent of the interpulse period cannot be used without considerable channel cross-talk because of pulse overlap. It is necessary to trade off crosstalk versus channel utilization at the system design level.

FIGURE 12.3.4 PPM time waveform.

FIGURE 12.3.5 PWM time waveforms: (a) leadingedge modulation; (b) trailing-edge modulation; (c) both-edge modulation.

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PULSE MODULATION/DEMODULATION 12.34

MODULATORS, DEMODULATORS, AND CONVERTERS

Another consideration is that the information sampling rate cannot exceed the pulse repetition frequency and would be less for a single channel of a multiplexed system where channels are interwoven in time. Generation of PTM There are two basic methods of pulse-time modulation: (1) based on uniform sampling in which the pulsetime parameter is directly proportional to the modulating signal at uniformly sampled points and (2) in which there is some distortion of the pulse-time parameter because of the modulation process. Both methods of modulation are illustrated in Fig. 12.3.6 for PWM. Basically, PPM can be derived from trailing-edge PWM, as shown in Fig. 12.3.6c by use of an edge detector or differentiator and a standard narrow-pulse generator. In the uniform sampling case for PWM of Fig. 12.3.6a, the modulating signal is sampled uniformly in time and the special PAM derived by a sample-and-hold circuit as shown in Fig. 12.3.7a. This PAM signal provides a pedestal for each of the three types of sawtooth waveforms producing leading, trailing, or double-edge PWM, as shown in Fig. 12.3.7c, e, and g, respectively. The uniform sampled PPM is shown in Fig. 12.3.7h, as derived from the trailing-edge modulation of g. Nonuniformly sampled modulation, termed natural sampling by some authors, is shown in Fig. 12.3.8, and results from the method of Fig. 12.3.8b, where the sawtooth is added directly to the modulating signal. In this case the modulating waveform influences the time when the samples are actually taken. This distortion is small when the modulating-amplitude change is small during the interpulse period T. The distortion is caused by the modulating signal distorting the sawtooth wave-form when they are added, as indicated in Fig. 12.3.6b. The information in the PPM waveform is similarly distorted because it is derived from the PWM waveform, as shown in Fig. 12.3.7h.

FIGURE 12.3.6 PTM generation: (a) pulse-width-modulation generation, uniform sampling; (b) pulse-width-modulation generation, nonuniform sampling; (c) pulseposition-modulation generation.

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FIGURE 12.3.7 Pulse-time modulation, uniform sampling: (a) modulating signal and sample-and-hold waveform; (b) sawtooth added to sample-and-hold waveform; (c) leading-edge modulation; (d) sawtooth added to sample-and-hold waveform; (e) double-edge modulation; ( f ) sawtooth added to sample-and-hold waveform; (g) trailing-edge modulation; (h) pulse-position modulation (reference pulse dotted).

PULSE-TIME MODULATION SPECTRA The spectra are smeared in general, for most modulating signals, and are difficult to derive; however, it is possible to get some idea of what happens to the spectra with modulation by considering a sinusoidal modulation of form A cos 2p fst

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PULSE MODULATION/DEMODULATION 12.36

MODULATORS, DEMODULATORS, AND CONVERTERS

The amplitude A < T/2, where T is the interpulse period, assuming no guard band. For PPM with uniform sampling and unity pulse amplitude, the spectrum is given by x (t ) =

∞

τ 2τ + T T +

2τ T

2τ + T

∑ (sinc mf0 )J0 (2π Amf0 ) cos 2π mf0t

m =1

∞



∑ sinc (nfs )Jn (2π Anfs ) cos  2π nfst −

n =1 ∞

nπ  2 



∞



∑ ∑ sinc (mf0 + nfs )Jn [2π A(mf0 + nfs )] cos 2π (mf0 + nfs )t −

m = 1 n = 1

nπ  2 

 nπ   + sinc (nfs − mf0 ) J n [2π A(nfs − mf0 )] cos  2π (nfs − mf0 )t −  2   

(12)

where t = pulse width T = pulse period fs = modulation frequency Jn = Bessel function of first kind, nth order f0 = 1/T As is apparent, all the harmonics of the pulse-repetition frequency and the modulation frequency are present, as well as all possible sums and differences. The dc level is t/T, with the harmonics carrying the modulation. The pulse shape effects the line amplitudes as a sinc function, reducing the spectra for higher frequencies. The spectrum for PWM is similar to that of PPM, and for uniformly sampled trailing-edge sinusoidal modulation is given by x (t ) =

1 1 + 2 πT

∞

1

∑ mf

m =1

∞

+

1 πT

m = 1 mf0

+

1 πT

∑ nf

∑ ∞

n =1

1 1 s

0

  π cos  2π mf0t + (2m − 1)  2  

 π J 0 (2π Amf0 ) cos  2π mf0t −   2

 π  J n (2π Anfs ) cos  2π nfs t − (n + 1)  2  

 1 1 J [2π A(mf0 + nfs )]] cos +  ∑ π T m = 1  mf0 + nfs n ∞

n =1

+

 π  2π (mf0 + nfs )t − (n + 1) 2   

 1 π   J n [2π A(nfs − mf0 )] cos  2π (nfs − mf0 )t − (n + 1)   nfs − mf0 2   

(13)

The same comments apply for PWM as for PPM. A more compact form is given for PPM and PWM, respectively, as x (t ) =

1 ∞ ∑ (− j)n Jn [2π A(mf0 + nfs )]P(mf0 + nfs ) exp [ j 2π (mf0 + nfs )t ] T m=∞ n=∞

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FIGURE 12.3.8 Pulse-time modulation, nonuniform sampling; (a) modulating signal; (b) sawtooth added to modulation; (c) leading-edge modulation; (d) sawtooth added to modulation; (e) double-edge modulation; ( f ) sawtooth added to modulation; (g) trailing-edge modulation; (h) pulse-position modulation.

where P( f ) is the Fourier transform of the pulse shape p(t), and x (t ) =

1 1 ∞ 2 m−1 e j 2π mf 0 t 1 + ∑ j 2π mf − T 2 T m = −∞ 0 m≠0

(− j ) n + 1

∞

∑

m = −∞ n =−∞ |m| + |n| ≠ 0

J n [2π A(mf0 + nfs )] exp [ j 2π (mf0 + nfs )t ] 2π (mf0 + nfs )

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MODULATORS, DEMODULATORS, AND CONVERTERS

FIGURE 12.3.9 Pulse-time demodulation: (a) PWM demodulation; (b) PPM to PWM for demodulation.

DEMODULATION OF PTM Demodulation of PWM or PPM can be accomplished by low-pass filtering if the modulation is small compared with the impulse period. However, in general, it is best to demodulate on a pulse-to-pulse basis that usually requires some form of synchronization with the pulses. The distortion introduced by nonuniform sampling cannot be eliminated and will be present in the demodulated waveform. However, if the modulation is small compared with the interpulse period T, the distortion will be minimized. To demodulate PWM each pulse can be integrated and the maximum value sampled and held and low-passfiltered, as shown in Fig. 12.3.9a. To sample and reset the integrator, it is necessary to derive sync from the PWM waveform, in this case trailing-edge-modulated. Generally, PPM is demodulated by conversion to PWM and then demodulated as PWM. Although in some demodulation schemes the actual PWM waveform may not exist as such, the general demodulation scheme is the same. PPM can be converted to PWM by the configuration of Fig. 12.3.9b. The PPM signal is applied to an amplitude threshold, usually termed a slicer, that rejects noise except near the pulses. The pulses are applied to a flip-flop synchronized to one particular state by the reference pulse, and it generates the PWM as its output.

PULSE FREQUENCY MODULATION In PFM the information is contained in the frequency of the pulse train, which is composed of narrow pulses. The highest frequency possible ideally occurs when there is no more interpulse spacing left for finite-width pulses. This frequency, given by 1/t, where t is the pulse width, will not be achieved in practice, owing to the pulse rise time. The lowest frequency is determined by the modulator, usually a voltage-controlled oscillator

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FIGURE 12.3.10 PFM modulation.

(VCO), in which in practice a 100:1 ratio of high to low frequency is easily achievable. Examination of Fig. 12.3.10 indicates why PFM is used mostly for control purposes rather than communications. The wide variation and uncertainty of pulse position do not lend themselves to time multiplexing, which requires the interweaving of channels in time. Since one of the chief motivations of pulse modulation in communication systems is to be able to time-multiplex a number of channels, PFM is not used. On the other hand, PFM is a good choice for on-off control applications, especially where fine control is required. A classic example of PFM control is for the attitude control of near-earth satellites that have on-off gas thrusters where a very close approximation to a linear system response is achievable.

Generation of PFM Basically, PFM is generated by modulation of a VCO as shown in Fig. 12.3.11a. A constant reference voltage is added to the modulation so that the frequency can swing above and below the reference-determined value. For control applications it is usually required that the frequency follow the magnitude of the modulation, its sign determining which actuators are to be turned on, as shown in Fig. 12.3.11b.

FIGURE 12.3.11 Generation of PFM: (a) PFM modulation; (b) PFM for control.

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MODULATORS, DEMODULATORS, AND CONVERTERS

PULSE-CODE MODULATION In PCM the signal is encoded into a steam of digits. This differs from the other forms of pulse modulation by requiring that the sample values of the signal be quantized into a number of levels and subsequently coded as a series of pulses for transmission. By selecting enough levels, the quantized signal can be made to approximate closely the original continuous signal at the expense of transmitting more bits per sample. The PCM scheme lends itself readily to time multiplexing of channels and will allow widely different types of signals; however, synchronization is strictly required. This synchronization of the system can be on a single-sample or code-group basis. The synchronizing signal is most likely inserted with a group of samples from different channels, on a frame or subframe basis to conserve space. The motivation behind modern PCM is that improved implementation techniques of solid-state circuitry allow extremely fast quantization of samples and translation to complex codes with reasonable equipment constraints. PCM is an attractive way to trade bandwidth for signal-to-noise and has the additional advantage of transmission through regenerative repeaters with a signal-to-noise ratio that is substantially independent of the number of repeaters. The only requirement is that the noise, interference, and other disturbances be less than one-half a quantum step at each repeater. Also, systems can be designed that have error-detecting and error-correcting features.

PCM CODING AND DECODING Coding is the generation of a PCM waveform from an input signal, and decoding is the reverse process. There are many ways to code and many code groups to use: hence standardization is necessary when more than one user is considered. Each sample value of the signal waveform is quantized and represented to sufficient accuracy by an appropriate code character. Each code character is composed of a specified number of code elements. The code elements can be chosen as two-level, or binary; three-level, or ternary; or n-ary. However, general practice is to use binary, since it is not affected as much by interference introduced by the required increased bandwidth. An example of binary coding is shown in Fig. 12.3.12 for 3-bit or eight levels of quantization. Each code group is composed of three pulses, with the pulse trains shown for on-off pulses in Fig. 12.3.12b and bipolar pulses in Fig. 12.3.12c. A generic diagram of a complete system is shown in Fig. 12.3.13. The recovered signal is a delayed copy of the input signal degraded by noise because of sources such as sampling, quantization, and interference. For this type of system to be efficient, both sending and receiving terminals must be synchronized. The synchronism is

FIGURE 12.3.12 Binary pulse coding: (a) quantized samples; (b) on-off coded pulses; (c) bipolar coded pulses.

FIGURE 12.3.13 Basic operations of a PCM system.

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required to be monitored continuously and be capable of establishing initial synchronism when the system is out of frame. The synchronization is usually accomplished by use of special sync pulses that establish frame, subframe, or word sync. There are three basic ways to code, namely, feedback and subtraction, pulse counting, and parallel comparison. In feedback subtraction the sample value is compared with the most significant code-element value and that value subtracted from the sample value if the element value is less. This process of comparison and subtraction is repeated for each code-element value down to the least significant bit. At each subtraction the appropriate code element or bit is selected to complete the coding. In pulse counting a gate is established by using the PWM pulse corresponding to a sample value. Clock pulses are gated using the PWM gate and are connected in a counter. The output of a decoding network attached to the counter is read out as the PCM. Parallel comparison is the fastest method since the sampled value is applied to a number of different threshold values. The thresholders are read out as the PCM.

SYSTEM CONSIDERATIONS FOR PCM Quantization introduces an irremovable error into the system, referred to as quantization noise. This kind of noise is characterized by the fact that its magnitude is always less than one-half a quantum step, and it can be treated as uniformly distributed additive noise with zero mean value and rms value equal to 1/√12 times the total height of a quantum step. When the ratio of signal power to quantization noise power at the quantizer output is used as a measure of fidelity the improvement with quantizer levels is as shown in Fig. 12.3.14 for different kinds of signals. In general, using an n-ary code with m pulses allows transmission of nm values. For the binary code this reduces the 2m values which approximate the signal to 1 part in 2m – 1 levels. Encoding into pulse and minus pulses, assuming either pulse is equally likely, results in an average power of A2/4, which is half the on-off power of A2/2, where the total pulse amplitude, peak to peak, is A. The channel capacity for a system sampled at the Nyquist rate of 2fm and quantized into s levels is C = 2fm log2 s (bits/s)

(16)

or for m pulses of n values each C = mfm log2 n2

FIGURE 12.3.14 PCM signal-to-noise improvement with number of quantization levels.

(bits/s)

(17)

Since the encoding process squeezes one sample into m pulses, the pulse widths are effectively reduced by l /m; thus the transmission bandwidth is increased by a factor of m, or B = mfm. The maximum possible ideal rate of transmission of binary bits is C = B log2 (1 + S/N) (bits/s)

(18)

according to Shannon. For a system sampled at the Nyquist rate, quantized to Ks per level and using the plus and minus pulses, the channel capacity is C = B log2(1 + 12S/K2N) (bits/s) N = s2 where S is the average power over large time interval and s is the rms noise voltage at decoder input.

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DELTA MODULATION Delta modulation (DM) is basically a one-digit PCM system where the analog waveform has been encoded in a differential form. In contrast to the use of n digits in PCM, simple DM uses only one digit to indicate the changes in the sample values. This is equivalent to sending an approximation to the signal derivative. At the receiver the pulses are integrated to obtain the original signal. Although DM can be simply implemented in circuitry, it requires a sampling rate much higher than the Nyquist rate of 2fm and a wider bandwidth than a comparable PCM system. Most of the other characteristics of PCM apply to DM. Delta modulation differs from differential PCM in which the difference in successive signal samples is transmitted. In DM only 1 bit is used to express and transmit the difference. Thus DM transmits the sign of successive slopes.

Coding and Decoding DM There are a number of coding and decoding variations in DM, such as single-integration, double-integration, mixed-integration, delta-sigma, and high-information DM (HIDM). In addition, companding the signal which is compressing the signal at transmission and expanding it at reception is also used to extend the limited dynamic range. The simple single-integration DM of the coding-decoding scheme is shown in Fig. 12.3.15. In the encoder the modulator produces positive pulses when the sign of the difference signal (t) is positive and negative pulses otherwise; and the output pulse train is integrated and compared with the input signal to provide an error signal (t), thus closing the encode feedback loop. At the receiver the pulse train is integrated and filtered to produce a delayed approximation to the signal, as shown in Fig. 12.3.16. The actual circuit implementation with operational amplifiers and logic circuits is very simple. By changing to a double-integration network in the decoder, a smoother replica of the signal is provided. This decoder has the disadvantage, however, of not recognizing changes in the slope of the signal. This gave rise to a scheme to encode differences in slope instead of amplitude, leading to coders with double integration; however, systems of this type are marginally stable and can oscillate under certain conditions. Waveforms of a double-integrating delta coder are shown in Fig. 12.3.17. Single and double integration can be combined to give improved performance while avoiding the stability problem. These mixed systems are often referred to in the literature as delta modulators with double integration. A comparison of waveforms is shown in Fig. 12.3.18.

FIGURE 12.3.15 Basic coding-decoding diagram for DM.

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FIGURE 12.3.16 Delta-modulation waveforms using single integration.

System Considerations for DM The synthesized waveform can change only one level each clock pulse; thus DM overloads when the slope of the signal is large. The maximum signal power will depend on the type of signal, since the greatest slope that can be reproduced is the integration of one level in one pulse period. For a sine wave of frequency f, the maximumamplitude signal is Amax = fss/2p

(20)

where fs is the sampling frequency and s is one quantum step. It has been observed that a DM system will transmit a speech signal without overloading if the amplitude of the signal does not exceed the maximum permissible amplitude of an 800-Hz sine wave. The DM

FIGURE 12.3.17 Waveforms for delta coder with double integration.

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FIGURE 12.3.18 Waveforms for various integrating systems.

coder overload characteristic is shown in Fig. 12.3.19 along with the spectrum of a human voice. Notice that they decrease in frequency together, indicating that DM can be used effectively with speech transmission. Generally speaking, transmission of speech is the chief application of DM, although various modifications and improvements are being studied to extend DM to higher frequencies and transmission of the lost dc component. Among these techniques is delta-sigma modulation, where the signal is integrated and compared with an integrated approximation to form the error signal similar to (t) of Fig. 12.3.15. The decoding is accomplished with a low-pass filter and requires no integration. The signal-to-quantization noise ratio for single-integration DM is given by S /N = 0.2 fs3/ 2 / f f01/ 2

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FIGURE 12.3.19 Spectrum of the human voice compared with delta-coder overload level.

12.45

FIGURE 12.3.20 Signal-to-noise ratio for DM and PCM.

where fs = sampling frequency f = signal frequency f0 = signal bandwidth For double or mixed DM S /N = 0.026 fs5/ 2 /f f03/ 2

(22)

A comparison of signal-to-noise ratio (SNR) for DM and PCM is shown in Fig. 12.3.20, along with an experimental DM system for voice application. Note that DM at 40 kbits/s sampling rate is equal in performance with a 5-bit PCM system. Extended-Range DM A system termed high-information DM (HIDM, developed by M. R. Winkler in 1963) falls in the category of companded systems and encodes more information in the binary sequence than normal DM. Basically, the method doubles the size of the quantization step when two identical, consecutive binary values appear and takes one-half of the step after each transition of the binary train. The HIDM system is capable of reproducing the signal with smaller quantization and overload errors. This technique also increases the dynamic range. The response of HIDM compared with that of DM is shown in Fig. 12.3.21. Implementation of HIDM is similar to that of DM, as shown in Figs. 12.3.22 and 12.3.23, with the difference only in the demodulator. The flip-flop of Fig. 12.3.23 changes state on the polarity of the input pulses. While the impulse generator initializes the experimental generators each pulse time, the flip-flop selects either the positive or negative one. The integrator adds and smooths the exponential waveforms to form the FIGURE 12.3.21 Step response for a high-information delta modulation. output signal. The scheme has a dynamic range with slope limiting of 11.1 levels per pulse period, which is much greater than DM and is equivalent to a 7-bit linear-quantized PDM system.

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Clock pulses Input Difference circuit

Modulator

Demodulator

Output

Demodulator Encoder

Decoder

FIGURE 12.3.22 Block diagram of HIDM system.

FIGURE 12.3.23 Block diagram of HIDM demodulator.

DIGITAL MODULATION Digital modulation is concerned with the transmission of a binary pulse train over some medium. The output of, say, a PCM coder would be used to modulate a carrier for transmission. In PCM systems, for instance, the high-quality reproduction of the analog signal is a function only of the probability of correct reception of the pulse sequences. Thus the measure of digital modulation is the probability of error resulting from the digital modulation. The three basic types of digital modulation, amplitude-shift keying (ASK), frequency-shift keying (FSK), and phase-shift (PSK), are treated below.

AMPLITUDE-SHIFT KEYING In ASK the carrier amplitude is turned on or off, generating the waveform of Fig. 12.3.24 for rectangular pulses. Pulse shaping, such as raised cosine, is sometimes used to conserve bandwidth. The elements of a binary ASK receiver are shown in Fig. 12.3.25. The detection can be either coherent or noncoherent; however, if the added complexity of coherent methods is to be applied, a higher performance can be achieved by using one of the other methods of digital modulation. The error rate of ASK with noncoherent detection is given in Fig. 12.3.26. Note that the curves approach constant values of error for high signal-to-noise ratios. FIGURE 12.3.24 ASK modulation. The probability of error for the coherent detection scheme of Fig. 12.3.25c is shown in Fig. 12.3.27. The coherent-detection operation is equivalent to bandpass filtering of the received signal plus noise, followed by synchronous detection, as shown. At the optimum threshold shown in Fig. 12.3.27, the probability of error of marks and spaces is the same. The curves also tend toward a constant false-alarm rate, as in the noncoherent case.

FREQUENCY-SHIFT KEYING In FSK the frequency is shifted rapidly between one of two frequencies. Generally, two filters are used in favor of a conventional FM detector to discriminate between the marks and spaces, as illustrated in Fig. 12.3.28. As with ASK, either noncoherent or coherent detection can be used, although in practice coherent detection is not often used. This is because it is just as easy to use PSK with coherent detection and achieve superior performance.

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FIGURE 12.3.25 Elements of a binary digital receiver: (a) elements of a simple receiver; (b) noncoherent (envelope) detector; (c) coherent (synchronous) detector.

FIGURE 12.3.26 Error rate for on-off keying, noncoherent detection.

FIGURE 12.3.27 Error-rate for on-off keying, coherent detection.

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MODULATORS, DEMODULATORS, AND CONVERTERS

In the noncoherent FSK system shown in Fig. 12.3.29a, the largest of the output of the two envelope detectors determines the mark-space decision. Using this system results in the curve for noncoherent FSK in Fig. 12.3.30. Comparison of the noncoherent FSK error with that of the noncoherent ASK results in the conclusion that both achieve an equivalent error rate at the same average SNR at low error rates. FSK requires twice FIGURE 12.3.28 FSK waveform, rectangular pulses. the bandwidth of ASK because of the use of two tones. In ASK, in order to achieve this performance, it is required to optimize the detection threshold at each SNR. The FSK system threshold is independent of SNR, and thus is preferred in practical systems where fading is encountered. By synchronous detection of FSK (Fig. 12.3.29b) is meant the availability of an exact replica of each possible transmission at the receiver. The coherent-detection process has the effect of rejecting a portion of the bandpass noise. Coherent FSK involves the same difficulties as phase-shift keying but achieves poorer performance. Also, coherent FSK is significantly advantageous over noncoherent FSK only at high error rates. The probability of error is shown in Fig. 12.3.30.

PHASE-SHIFT KEYING Phase-shift keying is optimum in the minimum-error-rate sense from a decision-theory point of view. The PSK of a constant-amplitude carrier is shown in Fig. 12.3.31, where the two states are represented by a phase difference of p rad. Thus PSK has the form of a sequence of plus and minus rectangular pulses of a continuous sinusoidal carrier. It can be generated by double-sideband suppressed-carrier modulation by a bipolar rectangular waveform or by direct phase modulation. It is also possible to phase-modulate more complex signals than a sinusoid. There is no performance difference in binary PSK between the coherent detector and the normal phase detector, both of which are shown in Fig. 12.3.32. Reference to Fig. 12.3.32 shows that there is a 3-dB design advantage for ideal coherent PSK over ideal coherent FSK, with about the same equipment requirements. Practically, PSK can suffer if very much phase error ∆f is present in the system, since the signal is reduced by cos ∆f. This phase error can be introduced by relative drifts in the master oscillators at transmitter or receiver

FIGURE 12.3.29 Dual-filter detection of binary FSK signals: (a) noncoherent detection tone f1 signaled; (b) coherent detection tone f1 signaled.

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FIGURE 12.3.30 Error rates for several binary systems.

12.49

FIGURE 12.3.31 PSK signal, rectangular pulses.

or be a result of phase drift or fluctuation in the propagation path. In most cases this phase error can be compensated at the expense of requiring long-term smoothing. An alternative to PSK is differential phase-shift keying (DPSK), where it is required that there be enough stability in the oscillators and transmission path to allow negligible phase change from one information pulse to the next. Information is encoded differentially in terms of phase change between two successive pulses. For instance, if the phase remains the same from one pulse to the next (0° phase shift), a mark would be indicated; however, a phase shift of p from the previous pulse to the next would indicate a space. A coherent detector is still required where one input is the current pulse with the other input the previous pulse. The probability of error is shown in Fig. 12.3.30. At all error rates DPSK requires 3 dB less SNR than noncoherent FSK for the same error rate. Also, at high SNR, DPSK performs almost as well as ideal coherent PSK at the same keying rate and power level.

FIGURE 12.3.32 Two detection schemes for ideal coherent PSK: (a) phase detection; (b) coherent detection.

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MICROWAVE AMPLIFIERS AND OSCILLATORS

CHAPTER 12.4

SPREAD-SPECTRUM MODULATION Myron D. Egtvedt

SPREAD-SIGNAL MODULATION In a receiver designed exactly for a specified set of possible transmitted waveforms (in the presence of white noise and in the absence of such propagation defects as multipath and dispersion), the performance of a matched filter or cross-correlation detector depends only on the ratio of signal energy to noise power density E/no, where E is the received energy in one information symbol and no/2 is the rf noise density at the receiver input. Since signal bandwidth has no effect on performance in white noise, it is interesting to examine the effect of spreading the signal bandwidth in situations involving jamming, message and traffic-density security, and transmission security. Other applications include random-multiple-access communication channels, multipath propagation analysis, and ranging. The information-symbol waveform can be characterized by its time-bandwidth (TW) product. Consider a binary system with the information symbol defined as a bit (of time duration T ), while the fundamental component of the binary waveform is called a chip. For this direct-sequence system, the ratio (chips per bit) is equal to the TW product. An additional requirement on the symbol waveforms is that their cross-correlation with each other and the noise or extraneous signals be minimal. Spread-spectrum systems occupy a signal bandwidth much larger (>10) than the information bandwidth, while the conventional systems have a TW of well under 10. FM with a high modulation index might slightly exceed 10 but is not optimally detectable and has a processing gain only above a predetection signal-to-noise threshold.

NOMENCLATURE OF SECURE SYSTEMS While terminology is not subject to rigorous definition, the following terms apply to the following material: Security and privacy. Relate to the protection of the signal from an unauthorized receiver. They are differentiated by the sophistication required. Privacy protects against a casual listener with little or no analytical equipment, while security implies an interceptor familiar with the principles and using an analytical approach to learn the key. Protection requirements must be defined in terms of the interceptor’s applied capability and the time value of the message. Various forms of protection include: Crypto security. Protects the information content, generally without increasing the TW product. Antijamming (AJ) security. Spreads the signal spectrum to provide discrimination against energy-limited interference by using cross-correlation or matched-filter detectors. The interference may be natural (impulse noise), inadvertent (as in amateur radio or aircraft channels), or deliberate (where the jammer may transmit continuous or burst cw, swept cw, narrow-band noise, wide-band noise, or replica or deception waveforms). Traffic-density security. Involves capability to switch data rates without altering the apparent characteristics of the spread-spectrum waveform. The TW product (processing gain) is varied inversely with the data rates. 12.50 Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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Transmission security. Involves spreading the bandwidth so that, beyond some range from the transmitter, the transmitted signal is buried in the natural background noise. The process gain (TW) controls the reduction in detectable range vis-à-vis a “clear” signal. Use in Radar It is usual to view radar applications as a variation on communication; that is, the return waveforms are known except with respect to noise, Doppler shift, and delay. Spectrum spreading is applicable to both cw and pulse radars. The major differentiation is in the choice of cross-correlation or matched-filter detector. The TW product is the key performance parameter, but the covariance function properties must frequently be determined to resolve Doppler shifts as well as range delays.

CLASSIFICATION OF SPREAD-SPECTRUM SIGNALS Spread-spectrum signals can be classified on the basis of their spectral occupancy versus time characteristics, as sketched in Fig. 12.4.1. Direct-sequence (DS) and pseudo-noise (PN) waveforms provide continuous full

FIGURE 12.4.1 Spectral occupancy vs. time characteristics of spreadspectrum signals.

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coverage, while frequency-hopping (FH), time-dodging, and frequency-time dodging (F-TD), fill the frequencytime plane only in a long-term averaging sense. DS waveforms are pseudo-random digital streams generated by digital techniques and transmitted without significant spectral filtering. If heavy filtering is used, the signal amplitude statistics become quite noiselike, and this is called a PN waveform. In either case correlation detection is generally used because the waveform is dimensionally too large to implement a practical matched filter, and the sequence generator is relatively simple and capable of changing codes. In FH schemes the spectrum is divided into subchannels spaced orthogonally at 1/T separations. One or more (e.g., two for FSK) are selected by pseudo-random techniques for each data bit. In time-dodging schemes the signal burst time is controlled by pulse repetition methods, while F-TD combines both selections. In each case a jammer must either jam the total spectrum continuously or accept a much lower effectiveness (approaching 1/TW). Frequency-hopped signals can be generated using SAW chirp devices.

CORRELATION-DETECTION SYSTEMS The basic components of a typical DS type of link are shown in Fig. 12.4.2. The data are used to select the appropriate waveform, which is shifted to the desired rf spectrum by suppressed-carrier frequency-conversion

FIGURE 12.4.2 Direct-sequence link for spread-spectrum system.

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techniques, and transmitted. At the receiver identical locally generated waveforms multiply with the incoming signal. The stored reference signals are often modulated onto a local oscillator, and the incoming rf may be converted to an intermediate frequency, usually with rf or i.f. limiters. The mixing detectors are followed by linear integrate-and-dump filters, with a “greatest of” decision at the end of each period. The integrator is either a low-pass or bandpass quenchable narrowband filter. Digital techniques are increasingly being used. Synchronization is a major design and operational problem. Given a priori knowledge of the transmitted sequences, the receiver must bring its stored reference timing to within ±1/(2W) of the width of the received signal and hold it at that value. In a system having a 19-stage pn generator, a 1-MHz pn clock, and a 1-kHz data rate, the width of the correlation function is ±1/2 ms, repeating 1/2 s separations, corresponding to 524.287 clock periods. In the worst case, it would be necessary to inspect each sequence position for 1 ms; that is, 524 s would be required to acquire sync. If oscillator tolerances and/or Doppler lead to frequency uncertainties equal to or greater than the 1-kHz data rate, then parallel receivers or multiple searches are required. Ways to reduce the sync acquisition time include using jointly available timing references to start the pn generators, using shorter sequences for acquisition only; “clear” sync triggers; and paralleling detectors. Titsworth (see bibliography) discusses composite sequences which allow acquiring each component sequentially, searching N1 + N2 + N3 delays, while the composite sequence has length N1N2N3. These methods have advantages for space-vehicle ranging applications but have reduced security to jamming. Sync tracking is usually performed by measuring FIGURE 12.4.3 Sync tracking by early-late correlators. the correlation at early and late times, ±t, where t ≤ 1/W, as shown in Fig. 12.4.3. Subtracting the two provides a useful time discrimination function, which controls the pn clock. The displaced values can be obtained by two tracking-loop correlators or by time-sharing a single unit. “Dithering” the reference signal to the signal correlator can also be used, but with performance compromises. The tracking function can also be obtained by using the time derivative of one of the inputs d dX (t ) ⋅ Y (t + τ ) ϕ (τ ) = dτ XY dt

(1)

A third approach has been to add by mod 2 methods the clock to the transmitted pn waveform. The spectral envelope is altered, but very accurate peak tracking can be accomplished by phase locking to the recovered clock.

LIMITERS IN SPREAD-SPECTRUM RECEIVERS Limiters are frequently used in spread-spectrum receivers to avoid overload saturation effects, such as circuit recovery time, and the incidental phase modulation. In the usual low-input signal-noise range, the limiter tends to normalize the output noise level, which simplifies the decision circuit design. In repeater applications (e.g., satellite), a limiter is desirable to allow the transmitter to be fully modulated regardless of the input-signal

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strength. When automatic gain control (AGC) is used, the receiver is highly vulnerable to pulse jamming, while the limiter causes a slight reduction of the instantaneous signal-to-jamming ratio and a proportional reduction of transmitter power allocated to the desired signal.

DELTIC-AIDED SEARCH The sync search can be accelerated by use of deltic-aided (delay-line time compression) circuits if logic speeds permit. The basic deltic consists of a recirculating shift register (or a delay line) which stores M samples, as shown in Fig. 12.4.4. The incoming spread-spectrum signal must be sampled at a rate above W (W = bandwidth). During each intersample period the shift register is clocked through M + 1 shifts before accepting the next sample. If M ≥ 2W, a signal period at least equal to the data integration period is stored and is read out at M different delays during each period T, permitting many high-speed correlations against a similarly accelerated FIGURE 12.4.4 Delay-line time compression (deltic) (but not time-advancing) reference. configuration. For a serial-deltic and shift-register delay line the clock rate is at least 4TW2. Using a deltic with K parallel interleaved delay lines, the internal delay lines are clocked at 4TW2/K2 and the demultiplexed output has a bit rate of 4TW2/K, providing only M/K discrete delays. This technique is device-limited to moderate signal bandwidths, primarily in the acoustic range up to about 10 kHz.

WAVEFORMS The desired properties of a spread-spectrum signal include: An autocorrelation function, which is unity at t = 0 and zero elsewhere A zero cross-correlation coefficient with noise and other signals A large library of orthogonal waveforms

Maximal-Length Linear Sequences A widely used class of waveforms is the maximal-length sequence (MLS) generated by a tapped refed shift register, as shown in Fig. 12.4.5a and as one-tap unit in Fig. 12.4.5b. The mod 2 half adder () and EXCLUSIVEOR logic gate are identical for 1-bit binary signals. If analog levels +1 and –1 are substituted, respectively, for 0 and 1 logic levels, the circuit is observed to function as a l-bit multiplier.

FIGURE 12.4.5 Maximal-length-sequence (MLS) system.

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FIGURE 12.4.6 Spectrum of MLS system.

Pertinent properties of the MLS are as follows. Its length, for an n-stage shift register, is 2n – 1 bits. During 2n – 1 successive clock pulses, all n-bit binary numbers (except all zeros) will have been present. The autocorrelation function is unity at t = 0, and at each 2n – 1 clock pulses displacement, and 1/(2n – 1) at all other displacements. This assumes that the sequences repeat cyclically, i.e., the last bit is closed onto the first. The autocorrelation function of a single (noncyclic) MLS shows significant time side lobes. Titsworth (see bibliography) has analyzed the self-noise of incomplete integration over p chips, obtaining for MLSs, s2(t) = ( p – t) (p2 – 1)/p3t

(2)

which approaches 1/t for the usual case of p >> t. Since t ≈ TW, the self-noise component is usually negligible. Another self-noise component is frequently present owing to amplitude and dispersion differences, caused by filtering, propagation effects, and circuit nonlinearities. In addition to intentional clipping, the correlation multiplier is frequently a balanced modulator, which is linear only to the smaller signal, unless deliberately operated in a bilinear range. The power spectrum is shown in Fig. 12.4.6. The envelope has a (sin2 X)/X2 shape (X = pw /wclock), while the individual lines are separated by wclock/(2n – 1). An upper bound on the number of MLS for an n-stage shift register is given in terms of the Euler f function: Nu = f(2n – 1)/n ≤ 2(n – log2n) where f(k) is the number of positive integers less than k, including 1, which are relatively prime to k.

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MICROWAVE AMPLIFIERS AND OSCILLATORS

CHAPTER 12.5

OPTICAL MODULATION AND DEMODULATION Joseph L. Chovan

MODULATION OF BEAMS OF RADIATION This discussion of optical modulators is restricted to devices that operate on a directed beam of optical energy to control its intensity, phase, or frequency, according to some time-varying modulating signal. Devices that deflect a light beam or spatially modulate a light beam, such as light-valve projectors, are treated in Chap. 21. Phase or frequency modulation requires a coherent light source, such as a laser. Optical heterodyning is then used to shift the received signal to lower frequencies, where conventional FM demodulation techniques can be applied. Intensity modulation can be used on incoherent as well as coherent light sources. However, the properties of some types of intensity modulators are wavelength-dependent. Such modulators are restricted to monochromatic operation but not limited to the extremely narrow laser line widths required for frequency modulation. Optical modulation depends on either perturbing the optical properties of some material with a modulating signal or mechanical motion to interact with the light beam. Modulation bandwidths of mechanical modulators are limited by the inertia of the moving masses. Optical-index modulators generally have a greater modulation bandwidth but typically require critical and expensive optical materials. Optical-index modulation can be achieved with electric or magnetic fields or by mechanical stress. Typical modulator configurations are presented below, as in heterodyning, which is often useful in demodulation. Optical modulation can also be achieved using semiconductor junctions.

OPTICAL-INDEX MODULATION: ELECTRIC FIELD MODULATION Pockels and Kerr Effects In some materials, an electric field vector E can produce a displacement vector D whose direction and magnitude depend on the orientation of the material. Such a material can be completely characterized in terms of three independent dielectric constants associated with three mutually perpendicular natural directions of the material. If all three dielectric constants are equal, the material is isotropic. If two are equal and one is not, the material is uniaxial. If all three are unequal, the material is biaxial. The optical properties of such a material can be described in terms of the ellipsoid of wave normals (Fig. 12.5.1). This is an ellipsoid whose semiaxes are the square roots of the associated dielectric constants. The behavior of any plane monochromatic wave through the medium can be determined from the ellipse formed by the intersection of the ellipsoid with a plane through the center of the ellipsoid and perpendicular to the direction of wave travel. The instantaneous electric field vector E associated with the optical wave has components 12.56 Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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along the two axes of this ellipse. Each of these components travels with a phase velocity that is inversely proportional to the length of the associated ellipse axis. Thus there is a differential phase shift between the two orthogonal components of the electric field vector after it has traveled some distance through such a birefringent medium. The two orthogonal components of the vector vary sinusoidally with time but have a phase difference between them, which results in a vector whose magnitude and direction vary to trace out an ellipse once during each optical cycle. Thus linear polarization is converted into elliptical polarization in a birefringent medium. In some materials it is possible to induce a perturbation in one or more of the ellipsoid axes by applying an external electric field. This is the electrooptical effect. The electrooptical effect is most commonly used in optical modulators presently available. More detailed configurations using these effects are discussed later. Kaminow and Turner (1966), present design considerations for various FIGURE 12.5.1 Ellipsoid of wave normals. configurations and tabulates material properties.

Stark Effect Materials absorb and emit optical energy at frequencies which depend on molecular or atomic resonances characteristic of the material. In some materials an externally applied electric field can perturb these natural resonances. This is known as the Stark effect. Kaminow and Turner (1966) discusses a modulator for the CO2 laser on the 3- to 22-mm region. The laser output is passed through an absorption cell whose natural absorption frequency is varied by the modulating signal, using the Stark effect. Since the laser frequency remains fixed, the amount of absorption depends on how closely the absorption cell is tuned to the laser frequency––intensity modulation results.

MAGNETIC FIELD MODULATION Faraday Effect Two equal-length vectors circularly rotating at equal rates in opposite directions in space combine to give a nonrotating resultant whose direction in space depends on the relative phase between the counterrotating components. Thus any linearly polarized light wave can be considered to consist of equal right and left circularly polarized waves. In a material which exhibits the Faraday effect, an externally applied magnetic field causes a difference in the phase velocities of right and left circularly polarized waves traveling along the direction of the applied magnetic field. This results in a rotation of the electric field vector of the optical wave as it travels through the material. The amount of the rotation is controlled by the strength of a modulating current producing the magnetic field. Zeeman Effect In some materials the natural resonance frequencies at which the material emits or absorbs optical energy can be perturbed by an externally applied magnetic field. This is known as the Zeeman effect. Intensity modulation can be achieved using an absorption cell modulated by a magnetizing current in much the same manner as the Stark effect absorption cell is used. The Zeeman effect has also been used to tune the frequency at which the active material in a laser emits.

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MECHANICAL-STRESS MODULATION In some materials the ellipsoid of optical-wave normals can be perturbed by mechanical stress. An acoustic wave traveling through such a medium is a propagating stress wave that produces a propagating wave of perturbation in the optical index. When a sinusoidal acoustic wave produces a sinusoidal variation in the optical index of a thin isotropic medium, the medium can be considered, at any instant of time, as a simple phase grating. Such a grating diffracts a collimated beam of coherent light into discrete angles whose separation is inversely proportional to the spatial period of the grating. This situation is analogous to an rf carrier phase-modulated by a sine wave. A series of sidebands results which correspond to the various orders of diffracted light. The amplitude of the mth order is given by an mthorder Bessel function whose argument depends on the peak phase deviation produced by the modulating signal. The phases of the sidebands are the appropriate integral multiples of the phase of the modulating signal. The mth order of diffracted light has its optical frequency shifted by m times the acoustic frequency. The frequency is increased for positive orders and decreased for negative orders. Similarly, a thick acoustic grating refracts light mainly at discrete input angles. This condition is known as Bragg reflection and is the basis for the Bragg modulator (Fig. 12.5.2). In the Bragg modulator, essentially all the incident light can be refracted into the desired order, and the optical frequency is shifted by the appropriate integral multiple of the acoustic frequency. Figure 12.5.2 shows the geometry of a typical Bragg modulator. The input angles for which Bragg modulation occurs are given by sin q = ml /2Λ

FIGURE 12.5.2 The Bragg modulator.

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where q = angle between propagation of input optical beam and planar acoustic wavefronts l = optical wavelength in medium Λ = acoustic wavelength in medium m = ±1, ±2, ±3, . . . mq = angle between propagation direction of output optical beam and planar acoustic wavefronts The ratio of optical to acoustic wavelength is typically quite small, and m is a low integer, so that the angle q is very small. Critical alignment is thus required between the acoustic wavefronts and the input light beam. If the modulation bandwidth of the acoustic signal is broad, the acoustic wavelength varies, so that there is a corresponding variation in the angle q for which Bragg reflection occurs. To overcome this problem, a phased array of acoustic transducers is often used to steer the angle of the acoustic wave as a function of frequency in the desired manner. A limitation on bandwidth is the acoustic transit time across the optical beam. Since the phase grating in the optical beam at any instant of time must be essentially constant frequency if all the light is to be diffracted at the same angle, the bandwidth is limited so that only small changes can occur in this time interval.

MODULATOR CONFIGURATIONS: INTENSITY MODULATION Polarization Changes Linearly polarized light can be passed through a medium exhibiting an electrooptical effect and the output beam passed through another polarizer. The modulating electric field controls the eccentricity and orientation of the elliptical polarization and hence the magnitude of the component in the direction of the output polarizer. Typically, the input linear polarization is oriented to have equal components along the fast and slow axes of the birefringent medium, and the output polarizer is orthogonal to the input polarizer. The modulating field causes a phase differential varying from 0 to p rad. This causes the polarization to change from linear (at 0) to circular (at p/2) to linear normal to the input polarization (at p). Thus the intensity passing through the output polarizer varies from 0 to 100 percent as the phase differential varies from 0 to p rad. Figure 12.5.3 shows this typical configuration. The following equations relate the optical intensity transmission of this configuration to the modulation. Io/Ii = 1/2(1 – cos f) where Io = output optical intensity Ii = input optical intensity f = differential phase shift between fast and slow axes. In the Pockels effect the differential phase shift is linearly related to applied voltage; in the Kerr effect it is related to the voltage squared.  π v / V Pockels effect φ= 2  π (v / V ) Kerr effect where v is the modulation voltage and V is the voltage to produce p rad differential phase shift. Figure 12.5.4 shows the intensity transmission given by the above expression. The most linear part of the modulation curve is at f = p/2. Often a quarter-wave plate is added in series with the electrooptical material to provide this fixed bias at p/2. A fixed-bias voltage on the electrooptical material can also be used. This arrangement is probably the most commonly used broadband intensity modulator. Early modulators of this type used a uniaxial Pockels cell with the electric field in the direction of optical propagation. In this arrangement, the induced phase differential is directly proportional to the opticalpath length, but the electric field is inversely proportional to this path length (at fixed voltage). Thus the phase differential is independent of the path length and depends only on applied voltage. Typical materials require several kilovolts for a differential phase shift of p in the visible-light region.

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FIGURE 12.5.3 Electrooptical intensity modulator.

Since the Pockels cell is essentially a capacitor, the energy stored in it is 1/2 CV2 where C is the capacitance and V is the voltage. This capacitor must be discharged and charged during each modulation cycle. Discharge is typically done through a load resistor, where this energy is dissipated. The high voltages involved mean that the dissipated power at high modulation rates is appreciable. The high-voltage problem can be overcome by passing light through the medium in a direction normal to the applied electric field. This permits a short distance between the electrodes (so that a high-E field is obtained from a low voltage) and a long optical path in the orthogonal direction (so that the cumulative phase differential is experienced). Unfortunately, materials available are typically uniaxial, having a high eccentricity in the absence of electric fields. When oriented in a direction that permits the modulating electric field to be orthogonal to the propagation direction, the material has an inherent phase differential which is orders of magnitude greater than that induced by the modulating field. Furthermore, minor temperature variations cause perturbations in this phase differential which are large compared with those caused by modulation. This difficulty is overcome by cascading two crystals which are carefully oriented so that temperature effects in one are compensated for by temperature effects in the other. The modulation electrodes are then connected so that their effects add. Commercially available electrooptical modulators are of this type. The Kerr effect is often used in a similar arrangement. Kerr cells containing nitrobenzene are commonly used as high-speed optical shutters. Polarization rotation produced by the Faraday effect is also used in intensity modulation by passing through an output polarizer in a manner similar to that discussed above. The Faraday effect is more commonly used at wavelengths where materials exhibiting the electrooptical effect are not readily available. Controlled Absorption As noted above, the frequency at which a material absorbs energy because of molecular or atomic resonances can be tuned over some small range in materials exhibiting the Stark or Zeeman effect. Laser spectral widths are typically narrow compared with such an absorption line width. Thus the absorption of the narrow laser line can be modulated by tuning the absorption frequency over a range near the laser frequency. Although such modulators have been used, they are not as common as the electrooptical modulators discussed above. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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FIGURE 12.5.4 Transmission of electrooptical intensity modulator.

PHASE AND FREQUENCY MODULATION OF BEAMS Laser-Cavity Modulation The distance between mirrors in a laser cavity must be an integral number of wavelengths. If this distance is changed by a slight amount, the laser frequency changes to maintain an integral number. The following equation relates the change in cavity length to the change in frequency: ∆f =

C ∆L L λ

where ∆ f = change in optical frequency ∆L = change in laser-cavity length L = laser-cavity length l = optical wavelength of laser output C = velocity of light in laser cavity. In a cavity 1 m long, a change in mirror position of one optical wavelength produces about 300 MHz frequency shift. Thus a laser can be frequency-modulated by moving one of its mirrors with an acoustic transducer, but the mass of the transducer and mirror limit the modulation bandwidths that can be achieved. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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An electrooptical cell can be used in a laser optical cavity to provide changes in the optical-path length. The polarization is oriented so that it lies entirely along the axis of the modulated electrooptical material. This produces the same effect as moving the mirror but without the inertial restrictions of the mirror’s mass. Under such conditions, the ultimate modulation bandwidth is limited by the Q of the laser cavity. A light beam undergoes several reflections across the cavity, depending on the Q, before an appreciable portion of it is coupled out. The laser frequency must remain essentially constant during the transit time required for these multiple reflections. This limits the upper modulation frequency. Modulation of the laser-cavity length produces a conventional FM signal with modulating signal directly proportional to change in laser-cavity length. Demodulation is conveniently accomplished by optical heterodyning to lower rf frequencies where conventional FM demodulation techniques can be used.

EXTERNAL MODULATION The Bragg modulator (Fig. 12.5.2) is commonly used to modulate the optical frequency. As such it produces a single-sideband suppressed-carrier type of modulation. Demodulation can be achieved by optical heterodyning to lower rf frequencies, where conventional techniques can be employed for this type of modulation. It is also possible to reinsert the carrier at the transmitter for a frequency reference. This is done by using optical-beam splitters to combine a portion of the unmodulated laser beam with the Bragg modulator output. Conventional double-sideband amplitude modulation has also been achieved by simultaneously modulating two laser beams (derived from the same source) with a common Bragg modulator to obtain signals shifted up and down. Optical-beam splitters are used to combine both signals with an unmodulated carrier. Conventional power detection demodulates such a signal. Optical phase modulation is commonly accomplished by passing the laser output beam through an electrooptical material, with the polarization vector oriented along the modulated ellipsoid axis of the material. Demodulation is conveniently achieved by optical heterodyning to rf frequencies, FM demodulation, and integrating to recover the phase modulation in the usual manner. For low modulation bandwidths, the electrooptical material can be replaced by a mechanically driven mirror. The light reflected from the mirror is phase modulated by the changes in the mirror position. This effect is often described in terms of the Doppler frequency shift, which is directly proportional to the mirror velocity and inversely proportional to the optical wavelength.

TRAVELING-WAVE MODULATION In the electrooptical and magnetooptical modulators described thus far, it is assumed that the modulating signal is essentially constant during the optical transit time through the material. This sets a basic limit on the highest modulating frequency that can be used in a lumped modulator. This problem is overcome in a traveling-wave modulator. The optical wave and the modulation signal propagate with equal phase velocities through the modulating medium, allowing the modulating fields to act on the optical wave over a long path, regardless of how rapidly the modulating fields are changing. The degree to which the two phase velocities can be matched determines the maximum interaction length possible.

OPTICAL HETERODYNING Two collimated optical beams, derived from the same laser source and illuminating a common surface, produce straight-line interference fringes. The distance between fringes is inversely proportional to the angle between the beams. Shifting the phase of one of the beams results in a translation of the interference pattern, such that a 2p-rad phase shift translates the pattern by a complete cycle. An optical detector having a sensing area small compared with the fringe spacing has a sinusoidal output as the sinusoidal intensity of the interference pattern translates across the detector.

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A frequency difference between the two optical beams produces a phase difference between the beams that changes at a constant rate with time. This causes the fringe pattern to translate across the detector at a constant rate, producing an output at the difference frequency. This technique is known as optical heterodyning in which one of the beams is the signal beam, the other the local oscillator. The effect of the optical alignment between the beams is evident. As the angle between the two collimated beams is reduced, the spacing between the interference fringes increases, until the spacing becomes large compared with the overall beam size. This permits a large detector which uses all the light in the beam. If converging or diverging beams are used instead of collimated beams, the situation is similar, except that the interference fringes are curved instead of straight. Making the image of the local-oscillator point coincide with the image of the signal-beam point causes the desired infinite fringe spacing. Optical heterodyning provides a convenient solution to several possible problems in optical demodulation. In systems where a technique other than simple amplitude modulation has been used (e.g., single-sideband, frequency, or phase modulation), optical heterodyning permits shifting to frequencies where established demodulation techniques are readily available. In systems where background radiation, such as from the sun, is a problem, heterodyning permits shifting to lower frequencies, so that filtering to the modulation bandwidth removes most of the broadband background radiation. The required phase front alignment also eliminates background radiation from spatial positions other than that of the signal source. Many systems are limited by thermal noise in the detector and/or front-end amplifier. Cooled detectors and elaborate amplifiers are often used to reduce this noise to the point that photon noise in the signal itself dominates. This limit also can be achieved in an optical heterodyne system with noncooled detector and normal amplifiers by increasing the local-oscillator power to the point where photon noise in the local oscillator is the dominant noise source. Under these conditions, the signal-to-noise power ratio is given by the following equation: S/N = hlP/2hBC where S/N = signal-power-noise-power ratio h = quantum efficiency of photo detector l = optical wavelength h = Planck’s constant C = velocity of light B = bandwidth over which S/N is evaluated P = optical signal power received by detector

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MICROWAVE AMPLIFIERS AND OSCILLATORS

CHAPTER 12.6

FREQUENCY CONVERTERS AND DETECTORS Glenn B. Gawler

GENERAL CONSIDERATIONS OF FREQUENCY CONVERTERS A frequency converter usually consists of an oscillator (called a local oscillator or LO) and a device used as a mixer. The mixing device is either nonlinear or its transfer parameter can be made to vary in synchronism with the local oscillator. A signal voltage with information in a frequency band centered at frequency fs enters the frequency converter, and the information is reproduced in the intermediate-frequency (i.f.) voltage leaving the converter. If the local-oscillator frequency is designated fLO, the i.f. voltage information is centered about a frequency fif = fLO ± fs. The situation is shown pictorially in Fig. 12.6.1. Characteristics of interest for design in systems using frequency converters are gain, noise figure, image rejection, spurious responses, intermodulation and cross-modulation capability, desensitization, area local-oscillator to rf, and to i.f. isolation. These characteristics will be discussed at length in the descriptions of different types of frequency-converter mixers and their uses in various systems. First, explanations are in order for the above terms. Frequency-Converter Gain. The available power gain of a frequency converter is the ratio of power available from the i.f. port to the power available at the signal port. Similar definitions apply for transducer gain and power gain. Noise Figure of Frequency Converter. The noise factor is the ratio of noise power available at the i.f. port to the noise power available at the i.f. port because of the source alone at the signal port. Image Rejection. For difference mixing fif = fLO – fs and the image is 2fLO − fs. For sum mixing fif = fLO + fs, and the image is 2fLO + fs. An undesired signal at the difference mixing frequency 2fLO – fs results in energy at the i.f. port. This condition is called image response and attenuation of the image response is image rejection, measured in decibels. Spurious Responses. Spurious external signals reach the mixer and result in generation of undesired frequencies that may fall into the intermediate-frequency band. The condition for an interference in the i.f. band is mf¢s ± nf1 = ± fif where m and n are integers and f¢s represents spurious frequencies at the signal port of the mixer. There is a strong local station in the broadcast band at 810 kHz and a weak distant station at 580 kHz. A receiver is tuned to the distant station, and a whistle, or beat, at 5 kHz is heard on the receiver (refer to Fig. 12.6.2).

Example.

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FIGURE 12.6.1 Frequency-converter terminals and spectrum.

An analysis shows that the second harmonic of the local oscillator interacts with the second harmonic of the 810-kHz signal to produce a mixer output at 450 kHz in the i.f. band of the receiver: 580 + 455 = 1035 kHz = LO frequency 2 × 1035 – 2 × 810 = 450 kHz = i.f. interference frequency The interference at 450 kHz then mixes with the 455-kHz desired signal in the second detector to produce the 5-kHz whistle. Notice that if the receiver is slightly detuned upward by 5 kHz, the whistle will zerobeat. Further upward detuning will create a whistle of increasing frequency.

INTERMODULATION Intermodulation is particularly troublesome because a pair of strong signals that pass through a receiver preselector can cause interference in the i.f. passband, even though the strong signals themselves do not enter the passband. Consider two undesired signals at 97 MHz passing through a superheterodyne receiver tuned to 100 MHz. Suppose, further, that the i.f. is so selective that a perfect mixer allows no response to the signals (see Fig. 12.6.3). Third-order intermodulation in a physically realizable mixer will result in interfering signals at the i.f. frequency and 9 MHz away (corresponding to 100 and 91 MHz rf frequencies, respectively). Fifth-order intermodulation will produce interferences 3 and 12 MHz from the intermediate frequency (103 and 88 MHz rf frequencies). There is a formula for variation of intermodulation products that is quite useful. Figure 12.6.4 shows typical variations of desired output and intermodulation with input power level. Desired output increases 1 dB for each 1-dB increase of input level, whereas third-order intermodulation increases 3 dB for each 1-dB increase of input level. At some point the mixer saturates and the above behavior no longer obtains. Since the interference of the intermodulation product is primarily of interest near the system sensitivity limit (usually somewhere below –20 dBm), the 1 dB per 1 dB and 3 dB per 1 dB patterns hold. The formula can be written P21 = 2PN + PF – 2P/21 where P21 = level of intermodulation product (dBm) PN = power level of interfering signal nearest P21 PF = power interfering signal farthest from P21

FIGURE 12.6.2 Spurious response in AM receiver.

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FIGURE 12.6.3 Spurious-response analysis.

P/21 is the third-order intercept power. For proper orientation, fN = 97 MHz, fF = 94 MHz, f21 = 100 MHz in Fig. 12.6.5. The intercept power is a function of frequency. It can be used for comparisons between mixer designs and for determining allowable preselector gain in a receiving system.

FREQUENCY-CONVERTER ISOLATION There are two paths in a mixer where isolation is important. The so-called balanced mixers give some isolation of the local-oscillator energy at the rf port. This keeps the superheterodyne receiver from radiating excessively. The doubly balanced mixers also give rf-to-i.f. isolation. This keeps interference in the receiver rf environment from penetrating the mixer directly at the i.f. frequency. Less important, but still significant, is the LO-to-i.f. isolation. This keeps LO energy from overloading the i.f. amplifier. Also, in multiple-conversion receivers low LO-to-i.f. leakage minimizes spurious responses in subsequent frequency converters. Desensitization A strong signal in the rf bandwidth, not directly converted to i.f., drives the operating point of the mixer into a nonlinear region. The mixer gain is then either decreased or increased. In radar, the characteristic of concern is pulse desensitization. In television receivers the characteristic is called cross-modulation. Here the strong

FIGURE 12.6.4 Third-order intermodulation intercept power.

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FIGURE 12.6.5 Intermodulation in a superheterodyne receiver.

undesired adjacent TV station modulates the mixer gain, especially during synchronization intervals, where the signal is strongest. The result appears in the desired signal as a contrast modulation of picture with the pattern of the undesired sync periods, corresponding to mixer gain pumping by the strong adjacent channel.

SCHOTTKY DIODE MIXERS The Schottky barrier diode is an improvement over the point-contact diode. The Schottky diode has two features that make it very valuable in high-frequency mixers: (1) it has low series resistance and virtually no charge storage, which results in low conversion loss; (2) it has noise-temperature ratio very close to unity. The noise factor of a mixed-i.f. amplifier cascade is F = LM(tD + Fif – 1) where LM = mixer loss tD = diode noise-temperature ratio Fif = i.f. noise factor Since tD is near unity and LM is in the range of 2.4 to 6 dB, overall noise factor is quite good, with Fif near 1.5 dB in well-designed systems. The complete conversion matrix involves LO harmonic sums and differences, as well as signal, i.f., and image frequencies. They restrict their treatment of crystal rectifiers to the third-order matrix  I1     I 2  = [Y ]  *  I3 

V1   y11    V2  Y =  y21  * y  31 V3 

y12 y22 y32

y13   y23  y33 

where 1 denotes signal port; 2, i.f. port; and 3, image port. With point-contact diodes, the series resistance is so large that not much improvement is realized by terminating the image frequency, and terminating the other frequencies involved is less significant. With the advent of Schottky barrier diodes, which have much smaller series resistances, proper termination of pertinent frequencies, other than signal and i.f. frequencies, results in a minimizing of conversion loss. This, in turn, leads to a minimizing of noise figure. Several different configurations are used with Schottky mixers. Figure 12.6.6 shows an image-rejection mixer, which is used for low i.f. frequency systems where rf filtering of the image is impractical. There is a general rule of thumb for obtaining good intermodulation, cross-modulation, and desensitizable performance in mixers. It has been found experimentally that pumping a mixer harder extends its range of

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FIGURE 12.6.6 Mixer designed for image rejection.

linear operation. The point-contact diode had a rapidly increasing noise figure with high LO power level and could easily burn out with too much power. The Schottky diode, however, degrades in noise figure relatively slowly with increasing LO power, and it can tolerate quite large amounts of power without burnout. There is a limit to this process of increasing LO power: the Schottky diode series resistance begins to appear nonlinear. This leads to another rule of thumb: pump the diode between two linear regions, and spend as little time as possible in the transition region. Application of these two rules leads to the doubly balanced Schottky mixer. The reason for this is that one pair of diodes conducts hard and holds the other pair off. Hence large LO power is required, and one diode pair is conducting well into its linear region while the other diode pair is held in its linear nonconducting region.

DOUBLY BALANCED MIXERS The diode doubly balanced mixer, or ring modulator, is shown in Fig. 12.6.7. The doubly balanced mixer is used up to and beyond 1 GHz in this configuration. The noise-figure optimization process previously discussed applies to this type of mixer. It exhibits good LO-to-rf and LO-to-i.f. isolation, as shown in Fig. 12.6.8. Typical published data on mixers quote 30 dB rf-to-i.f. isolation below 50 MHz and 20 dB isolation from 50 to 500 MHz. Another feature of balanced mixers is their LO noise-suppression capability. Modern mixers using Schottky diodes in a ring modulator provide somewhat better LO noise suppression. The ring modulator provides suppression only to AM LO noise, not FM noise. FIGURE 12.6.7 Doubly balanced mixer.

PARAMETRIC CONVERTERS Parametric converters make use of time-varying energy-storage elements. Their operation is in many ways similar to that of parametric amplifiers (see Section 11). The difference is that output and input frequencies are the same in parametric amplifiers, while the frequencies differ in parametric converters. The device most widely Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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FIGURE 12.6.8 Generation of 920-kHz beat in TV tuners.

used for microwave parametric converters today is the varactor diode, which has a voltage-dependent junction capacitance. The time variation of varactor capacitance is provided by a local oscillator, usually called the pump. Attainable gain of a parametric converter is limited by the ratio of output to input frequencies. Therefore up conversion is generally used to achieve some gain. Because lower-sideband up conversion results in negative resistance, the upper sideband is generally used. This results in simpler circuit elements to achieve stability. There is a distinct advantage to up conversion; image rejection is easily achievable by a simple low-pass filter.

TRANSISTOR MIXERS One of the original concerns in transistor mixers was their noise performance. The base spreading resistance rb is very important in noise performance. The reason is that mixing occurs across the base-emitter junction; then the i.f. signal is amplified by transistor action; however, rb is a lossy part of the termination at the i.f. signal, image, and all other frequencies present in the mixing process. Hence rb dissipates some energy at each of the frequencies present, and all these contributions add to appear as a loss in the signal-to-i.f. conversion. This loss, in turn, degrades noise figure. Manufacturers do not promote transistors used as mixers, probably because of their intermodulation and spurious-response performance. Estimates of intermodulation intercept power go as high as +12 dBm, while one measurement gave +5 dBm at 200 MHz; however, a cascade transistor mixer is used in a commercial VHF television tuner.

MEASUREMENT OF SPURIOUS RESPONSES Figure 12.6.9 shows an arrangement for measuring mixer spurious responses. The filter following the signal generator implies that generator harmonics are down, say 40 dB. This ensures that frequency-multiplying action is owing only to the mixer under test. The attenuator following the mixer can be used to be sure that a spurious response of the receiver is not being measured. That is, a 6-dB change in attenuator setting should be accompanied by a 6-dB change on the indicator. Generally the most convenient way of performing the spurious-response test is first to obtain an indication of the indicator. Then tune the signal generator to the desired frequency and record the level required to obtain the original response. This should be repeated at one or two more levels of the undesired signal to ensure that the spur follows the appropriate laws. For example, if the response is fourth-order (four times the signal frequency ±n Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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MODULATORS, DEMODULATORS, AND CONVERTERS

FIGURE 12.6.9 Test equipment for measuring mixer spurious responses.

times the LO frequency), the measured value should change 4 dB for a 1-dB change in undesired frequency level. The order of the spurious response can be determined by either of two methods. The first method is simply by knowing with some accuracy the undesired signal frequency and the LO frequency and then determining the harmonic numbers required to obtain the i.f. frequency. The other technique entails observing the incremental changes of the i.f. frequency with known changes in the undesired signal frequency and the LO signal frequency. This completes the measurement for one spurious response. The procedure should be repeated for each of the spurious responses to be measured. The intermodulation test setup is shown in Fig. 12.6.10. In general, a diplexer is preferable to a directional coupler for keeping generator 1 signal out of generator 2. This is necessary so that the measurement is not limited by the test setup. A good idea would be to establish that no third-order intermodulation occurs becuase of the setup alone. To do this, initially remove the mixer-LO circuit. Then tune generator 1 off from center frequency to about 10 or 20 dB down on the skirt of the receiver preselector. Tune generator 2 twice this amount from the receiver center frequency. Set generator levels equal and at some initial value, say –30 dBm. Then vary one generator frequency slightly and look for a response peak on the indicator. If none is noticed, increase the generator level to –20 dBm and repeat the procedure. Usually, except for very good receivers, the thirdorder intermodulation response is found. Vary the attenuator by 6 dB, and look for a 6-dB variation in the indicator reading. If the latter is not 6 dB but 18 dB, intermodulation is occurring in the receiver. If the indicator variation is between 6 and 18 dB, intermodulation is occurring in the circuitry preceding the attenuator and in the receiver. To obtain trustworthy measurements with a mixer in the test position, the indicator should read at least 20 dB greater than without the mixer, while the generator levels should be lower by mixer gain +10 dB than they were without the mixer. This ensures that the test setup is contributing an insignificant amount to the intermodulation measurement. With the mixer in test position and the above conditions satisfied, obtain a reading on the indicator and let the power referred to the mixer input be denoted by P (dBm). Turn down both generator levels, and retune generator 1 to center frequency. Adjust generator 1 level to obtain the previous indicator reading. This essentially calibrates the measurement setup. Denote generator 1 level referred to the mixer input by P21 dBm. Then the intermodulation intercept power is given by P/21 dBm = (3P – P21)/2 The subscripts on intercept power P/21 refer to second order for the near frequency and first order for the far frequency (see Fig. 12.6.4).

FIGURE 12.6.10 Test equivalent for measurement of mixer intermodulation.

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The procedure should be repeated for one or two lower values of P. The corresponding values of P/21 should asymptomatically approach a constant value. The constant value of P/21 so obtained is then a valid number for predicting behavior of the mixer near its sensitivity limit.

DETECTORS (FREQUENCY DECONVERTERS) Detectors have become more complex and versatile since the advent of integrated circuits. Up to the mid-1950s most radio receivers used the standard single-diode envelope detector for AM and a Foster-Seeley discriminator or ratio detector for FM. Today, integrated circuits are available with i.f. amplifier, detector, and audioamplifier functions in a single package. Figure 12.6.11 shows three conventional AM detectors. In Fig. 12.6.11a an envelope detector is shown. In order for the detected output to follow the modulation envelope faithfully, the RC time constant must be chosen so that RC < 1/wm, where wm is the maximum angular modulation frequency in the envelope. Figure 12.6.11b shows a peak detector. Here the RC time constant is chosen large, so that C stays charged to the peak voltage. Usually, the time constant depends on the application. In a television fieldstrength meter, the charge on C should not decay significantly between horizontal sync pulses separated by 62.5 ms. Hence a time constant of 1 to 6 ms should suffice. On the other hand, an AGC detector for single-sideband use should have a time constant of 1 s or longer. Figure 12.6.11c shows a product (synchronous) detector. This type of detector has been used since the advent of single-sideband transmission. The product detector multiplies the signal with the LO, or beat frequency oscillator (BFO), to produce outputs at sum and difference frequencies. Then the low-pass filter passes only the difference frequency. The result is a clean demodulation with a minimum of distortion for singlesideband signals. The two classical FM detectors widely used up to the present are the Foster-Seeley discriminator and the ratio detector. Figure 12.6.12 shows the Foster-Seeley discriminator and its phasor diagrams. The circuit consists of a double-tuned transformer, with primary and secondary voltages series-connected. The diode connected to point A detects the peak value of V1 + V2/2, and the diode at B detects the peak value of V1 – V2/2. The audio output is then the difference between the detected voltages. When the incoming frequency is in the center of the passband, V2 is in quadrature with V1, the detected voltages are FIGURE 12.6.11 AM detectors: (a) AM envelope equal, and audio output is zero. Below the center fredetector; (b) peak detector; (c) product detector. quency the detected voltage from B decreases, while that from A increases, and the audio output is positive. By similar reasoning, an incoming frequency above band center produces a negative audio output. Optimum linearity requires that KQ = 2, where K is the transformer coupling and Q is the primary and secondary quality factor. Figure 12.6.12c shows a ratio detector, which has an advantage over the Foster-Seeley discriminator in being relatively insensitive to AM. The ratio detector uses a tertiary winding (winding 3) instead of the primary voltage, and one diode is reversed; however, the phasor diagrams also apply to the ratio detector. The AM

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FIGURE 12.6.12 FM detectors: (a) Foster-Seeley FM discriminator; (b) phasor diagrams; (c) ratio detector.

rejection feature results from choosing the (R1 + R2)C time constant large compared with the lowest frequency to be faithfully reproduced. The voltages EOA and EOB represent the detected values of rf voltages across OA and OB, respectively. With the large time constant above, voltage on C changes slowly with AM and the conduction angles of the diodes vary, loading the tuned circuit so as to keep the rf amplitudes relatively constant. Capacitor C0 is chosen to be an rf short circuit but small enough to follow the required audio variations. In the AM rejection process, AF voltage on C0 does not follow the AM because the charge put on by one diode is removed by the other diode. With FM variations on the rf, voltage on C0 changes to reach the condition, again, that charge put on C0 by one diode is removed by the other diode. The ratio detector is generally used with little or no previous limiting of the rf, while the FosterSeeley discriminator must be preceded by limiters to provide AM rejection. With the recent trend toward integrated circuits, there has been increased interest in using phase-locked loops and product detectors. These techniques have been selected because they do not require inductors, which are not readily available in integrated form. Figure 12.6.13 shows a phase-locked loop (PLL) as an FIGURE 12.6.13 FM detector using phase-locked loop.

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FM detector. The phase comparator merely provides a dc voltage proportional to the difference in phase between signals represented by fM and f. Initially, f and fM are unequal, but because of high loop gain, GH >> 1, f and fM quickly become locked and stay locked. Then as fM varies, f follows exactly. But because of the high loop gain, response is essentially 1/H, which is the voltage-controlled oscillator (VCO) characteristic. Hence the PLL serves as an FM detector. AM product detectors also make use of the PLL to provide a carrier locked to the incoming signal carrier. The output of the VCO is used to drive the product detector. Probably one of the most stringent uses of the product detector is in an FM stereo decoder. The left minus right (L − R) subcarrier is located at 38 kHz with sidebands from 23 to 53 kHz. There may also be an SCA signal centered about 67 kHz which is used to provide a music service for restaurants and commercial offices. The L − R product detector is driven by a 38-kHz VCO, the output of which also goes to a 2-to-1 counter. The counter output is compared with the 19kHz pilot signal in a phase comparator, and the phase-comparator output then controls the VCO. Because of the relatively small pilot signal and the presence of L + R, L − R, and SCA information, the requirement for phase locking is stringent.

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Source: STANDARD HANDBOOK OF ELECTRONIC ENGINEERING

SECTION 13

POWER ELECTRONICS Power electronics deals with the application of electronic devices and associated components to the conversion, control, and conditioning of electric power. The primary characteristics of electric power, which are subject to control, include its basic form (ac or dc), its effective voltage or current (including the limiting cases of initiation and interruption of conduction), and its frequency and power factor (if ac). The control of electric power is a means for achieving control or regulation of one or more nonelectrical parameters, e.g., the speed of a motor, the temperature of an oven, the rate of an electrochemical process, or the intensity of lighting. Aside from the obvious difference in function, power-electronics technology differs markedly from the technology of low-level electronics for information processing in that much greater emphasis is required on achieving high-power efficiency. Few low-level circuits exceed a power efficiency of 15 percent, but few power circuits can tolerate a power efficiency less than 85 percent. High efficiency is vital, first, because of the economic and environmental value of wasted power and, second, because of the cost of dissipating the heat it generates. This high efficiency cannot be achieved by simply scaling up low-level circuits; a different approach must be adopted. This different approach is attained by using electronic devices as switches, e.g., approximating ideal closed (no voltage drop) or open (no current flow) switches. This differs from low-level digital switching circuits in that digital systems are primarily designed to deliver two distinct small voltage levels while conducting small currents (ideally zero). Power electronic circuits, though, must have the capability of delivering large currents and be able to withstand large voltages. Power can be controlled and modified by controlling the timing of repetitive switch action. Because of wear and limited switching speed, mechanical switches are ordinarily not suitable, but electronic switches have made this approach feasible into the multigigawatt power region while maintaining high-power efficiencies over wide ranges of control. However, the inherent nonlinearity of the switching action leads to the generation of transients and spurious frequencies that must be considered in the design process. Reliability of the power electronics circuits is just as important as efficiency. Modern power converter and control circuits must be extremely robust, with MTBF (mean time between failure) for typical systems in the order of 1,000,000 h of operation. Power electronic circuits are often divided into categories depending on their intended function. Converter circuits that change ac into dc are called rectifiers, circuits that change the dc operating voltage or current are called dc-to-dc converters, circuits that convert dc into ac power are called inverters, and those that change the amplitude and frequency of the ac voltage and/or current without using an intermediate dc stage are ac-to-ac converters (also called cycloconverters). Rectifiers are used in many power electronics applications because of the widespread availability of ac power sources, and rectification is often a first step in the power conditioning scheme. Rectifiers are used in very low voltage systems (e.g., 3 V logic circuits) as well as very high voltage applications of commercial utilities. The control and circuit topology can vary according to the application requirements. Dc–dc converters have many implementations that depend on the intended application, and can make use of different types of input power sources. Often, ac power is rectified and filtered to supply the requisite input dc levels. An inverter section is then used to transform the dc power to high frequency ac voltage or current, which a transformer then steps up or down. The new ac from the transformer secondary is then rectified and filtered to provide the desired output dc level. Other dc–dc converters step voltage up or down without the intervening transformer. Inverters convert dc into ac power. Many applications require the production of three-phase power waveforms for speed control of large motors used in industry. The reconstruction of single-frequency, near-sinusoidal

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voltage, or current waveforms requires precisely controlled switching circuits. The exact mode and timing of the switching action in the associated power electronic devices can be complex, especially when regenerative schemes are employed to recover energy from the mechanical system and convert it back to electrical energy for more efficient operation. Inverter circuit design and control has been the subject of much research and development over the past several decades. Ac–ac power control, without changing frequency, is accomplished by simple converters that allow conduction to begin at a time past the zero-crossing of the voltage or current waveform (referred to as phase control), or more complex converters that create completely new amplitudes and frequencies for the output ac power. Note: Original contributions to this section were made by W. Newell. Portions of the material on diodes were contributed by P. F. Pittman, J. C. Engel, and J. W. Motto. D.C.

In This Section: CHAPTER 13.1 POWER ELECTRONIC DEVICES POWER ELECTRONIC DEVICE FAMILIES COMMON DEVICE CHARACTERISTICS DIODES TRANSISTORS THYRISTORS OTHER POWER SEMICONDUCTOR DEVICES BIBLIOGRAPHY

13.3 13.3 13.3 13.5 13.10 13.14 13.18 13.18

CHAPTER 13.2 NATURALLY COMMUTATED CONVERTERS INTRODUCTION BASIC CONVERTER OPERATION CONVERTER POWER FACTOR ADDITIONAL CONVERTER TOPOLOGIES REFERENCES

13.19 13.19 13.20 13.23 13.25 13.30

CHAPTER 13.3 DC-DC CONVERTERS INTRODUCTION DIRECT DC-DC CONVERTERS INDIRECT DC-DC CONVERTERS FORWARD CONVERTERS RESONANT DC-DC CONVERSION TECHNIQUES BIBLIOGRAPHY

13.31 13.31 13.31 13.37 13.41 13.45 13.49

CHAPTER 13.4 INVERTERS INTRODUCTION AN INVERTER PHASE-LEG SINGLE-PHASE INVERTERS THREE-PHASE INVERTERS MULTILEVEL INVERTERS VOLTAGE WAVEFORM SYNTHESIS TECHNIQUES CURRENT WAVEFORM SYNTHESIS TECHNIQUES INVERTER APPLICATIONS REFERENCES

13.50 13.50 13.50 13.54 13.55 13.56 13.57 13.64 13.65 13.67

CHAPTER 13.5 AC REGULATORS CIRCUITS FOR CONTROLLING POWER FLOW IN AC LOADS STATIC VAR GENERATORS REFERENCES

13.69 13.69 13.71 13.73

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Source: STANDARD HANDBOOK OF ELECTRONIC ENGINEERING

CHAPTER 13.1

POWER ELECTRONIC DEVICES Jerry L. Hudgins

POWER ELECTRONIC DEVICE FAMILIES Power electronic devices have historically been separated into three broad categories: diodes, transistors, and thyristors. Modern devices can still be classified in this way, though there is increasing overlap in device design and function. Also, new materials as well as novel designs have increased the suitability and broadened the applications of semiconductor switches in energy conversion circuits and systems. Diodes are two-terminal devices that perform functions such as rectification and protection of other components. Diodes are not controllable in the sense that they will conduct current when a positive forward voltage is applied between the anode and cathode. Transistors are three-terminal devices that include the traditional power bipolar (two types of charge carriers), power MOSFETs (metal-oxide-semiconductor field-effect transistor), and hybrid devices that have some aspect of a control-FET element integrated with a bipolar structure, such as an IGBT (insulated-gate bipolar transistor). Thyristors are also three-terminal devices that have a four-layer structure (several p-n junctions) for the main power handling section of the device. All transistors and thyristor types are controllable in switching from a forward blocking state (very little current flows) into a forward conduction state (large forward current flows). All transistors and most thyristors (except SCRs) are also controllable in switching from forward conduction back to a forward blocking state. Typically, thyristors are used at the highest energy levels in power conditioning circuits because they are designed to handle the largest currents and voltages of any device technology (systems approximately with voltages above 3 kV or currents above 100 A). Many medium-power circuits (systems operating at less than 3 kV or 100 A) and particularly low-power circuits (systems operating below 100 V or several amperes) generally make use of transistors as the main switching elements because of the relative ease in controlling them. IGBTs are also replacing thyristors (e.g., GTEs) in industrial motor drives and traction applications as the IGBT voltage blocking capability improves. Diodes are used throughout all levels of power conditioning circuits and systems.

COMMON DEVICE CHARACTERISTICS A high-resistivity region of silicon is present in all power semiconductor devices. It is this region that must support the large applied forward voltages that occur when the switch is in its off state (nonconducting). The higher the forward blocking voltage rating of the device, the thicker this region must be. Increasing the thickness of this high-resistivity region results in slower turn-on and turn-off (i.e., longer switching times and/or lower frequency of operation). For example, a device rated for a forward blocking voltage of 5 kV will by its physical construction switch much more slowly than one rated for 100 V. In addition, the thicker high-resistivity region

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POWER ELECTRONICS

of the 5 kV device will cause a larger forward voltage drop during conduction than the 100 V device carrying the same current. There are other effects associated with the relative thickness and layout of the various regions that make up modern power devices, but the major trade-off between forward blocking voltage rating and switching times and between forward blocking voltage and forward voltage drop during conduction should be kept in mind. Another physical aspect of the semiconductor material is that the maximum breakdown voltage achievable using a semiconductor is proportional to the energy difference between the conduction and valence bands (bandgap). Hence, a material with a larger bandgap energy than that in silicon (Si) can in principle achieve the same blocking voltage rating with a thinner high-resistivity region. This is one of the reasons that new semiconductor devices are being designed and are recently becoming available in materials such as silicon carbide (SiC). The time rate of rise of device current (di/dt) during turn-on and the time rate of rise of device voltage (dv/dt) during turn-off are important parameters to control for ensuring proper and reliable operation. Many power electronic devices have maximum limits for di/dt and dv/dt that must not be exceeded. Devices capable of conducting large currents in the on-state are necessarily made with large surface areas through which the current flows. During turn-on, localized regions of a device begin to conduct current. If the local current density becomes too large, then heating will damage the device. Sufficient time must be allowed for the entire area to begin conducting before the localized currents become too high and the device’s di/dt rating is exceeded. The circuit designer sometimes adds series inductance to limit di/dt below the recommended maximum value. During turn-off, current is decreasing while voltage across the device is increasing. If the forward voltage becomes too high while sufficient current is still flowing, then the device will drop back into its conduction mode instead of completing its turn-off cycle. Also, during turn-off, the power dissipation can become excessive if the current and voltage are simultaneously too large. Both of these turn-off problems can damage the device as well as other portions of the circuit. Another problem that occurs is associated primarily with thyristors. Thyristors can self-trigger into a forward conduction mode from a forward blocking mode if their dv/dt rating is exceeded (because of excessive displacement current through parasitic capacitances). Protection circuits, known as snubbers, are used with power semiconductor devices to control dv/dt. The snubber circuit specifically protects devices from a large di/dt during turn-on and a large dv/dt during turn off. A general snubber topology is shown in Fig. 13.1.1. The turn-on snubber is made by inductance L1 (often L1 is stray inductance only). This protects the device from a large di/dt during the turn-on process. The auxiliary circuit made by R1 and D1 allows the discharging of L1 when the device is turned off. The turn-off snubber is made by resistor R2 and capacitance C2. This circuit protects the power electronic device from large dv/dt during the turn-off process. The auxiliary circuit made by D2 and R2 allows the discharging of C2 when the device is turned on. The circuit of capacitance C2 and inductance L1 also limits the value of dv/dt across the device during forward blocking. In addition, L1 protects the device from reverse overcurrents. All power electronic devices must be derated (e.g., power dissipation levels, current conduction, voltage blocking, and switching frequency must be FIGURE 13.1.1 Turn-on (top elements) and turn-off (bottom reduced), when operating above room temperature elements) snubber circuits for typical power electronic devices.

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(defined as about 25°C). Bipolar-type devices have thermal runway problems, in that if allowed to conduct unlimited current, these devices will heat up internally causing more current to flow, thus generating more heat, and so forth until destruction. Devices that exhibit this behavior are pin diodes, bipolar transistors, and thyristors. MOSFETs must also be derated for current conduction and power dissipation when heated, but they do not suffer from thermal runaway as other device types do. IGBTs fall in between the behavior of MOSFETs and bipolar transistors. At low current levels they behave similar to bipolar transistors, whereas operating at high currents causes them to behave more like MOSFETs. There are many subtleties of power device fabrication and design that are made to improve the switching times, forward voltage drop during conduction, dv/dt, di/dt, and other ratings. Many of these improvements cause the loss of the ability of the device to hold-off large applied reverse voltages. In other devices the inherent structure itself precludes reverse blocking capability. In general, only some versions of two types of thyristors have equal (symmetric) forward and reverse voltage hold-off capabilities: GTOs (gate turn-off thyristor) and SCRs (silicon controlled rectifier). A simple diagram of the internal structure of the major power semiconductor devices, the corresponding circuit symbols, some simple equivalent circuits, and a summary of the principal characteristics of each device are shown in Fig. 13.1.2. A comparison between types of devices illustrating the useable switching frequency range and switched power capability is shown in Fig. 13.1.3. Switched power capability is defined here as the maximum forward hold-off voltage obtainable multiplied by the maximum continuous conduction current. Further information on power electronic devices can be obtained from manufacturer’s databooks and applications notes, textbooks (Baliga, 1987, 1996; Ghandi, 1977; Sze, 1981), and in many technical journal publications (including Azuma and Kurata, 1988; Hower, 1988; Hudgins, 1993).

DIODES Diode Types Schottky and pin diodes are used extensively in power electronic circuits. Schottky diodes are formed by placing a metal layer directly on a lightly doped (usually n-type) semiconductor. The naturally occurring potential barrier at the metal-semiconductor interface gives rise to the rectifying properties of the device. A pin diode is a pn-junction device with a lightly doped (near intrinsic) region placed between the typical diode p- and n-type regions. The lightly doped region is necessary to support large applied reverse voltages. The diode characteristic is such that current easily flows in one direction while it is blocked in the other. Power Schottky diodes are limited to about 200 V reverse blocking capability because the forward voltage drop becomes excessive in the high-resistivity region of the semiconductor and the lowering of the interface potential barrier (and associated increase in reverse leakage current) owing to the applied reverse voltage also increases (Sze, 1981). However, new Schottky structures made from SiC material are commercially available that have much higher voltage blocking capability. It is likely that these SiC diodes will be available with multi-kV ratings soon. Reverse blocking of up to 10 kV is obtainable with a pin structure in Si. These types of diodes can easily handle surge currents of tens of thousands of amperes and rms currents of several thousand amperes. The pin diode has the advantages of much higher voltage and current capabilities than the Schottky diode, though the new SiC Schottky diodes are moving into higher power ratings all the time. Also, pin diodes are inherently slower in switching speed than Schottky devices, and for low reverse-blocking values, they have a larger forward voltage drop than Schottky diodes. For devices rated for 50 V reverse blocking, a Schottky diode has a forward drop of about 0.6 V as compared to a pin diode’s forward drop of about 0.9 V at the same current density. The fast switching of the Schottky structure can be used to advantage in highfrequency power converter circuits. The Schottky’s low forward drop can be used to advantage on the output rectifiers of low-voltage converter circuits, also. There have been several structures proposed that merge the features of the pin (for high reverse-blocking capability) and Schottky (for fast switching and low forward drop) diodes (Hower, 1988; Baliga, 1987). This concept is beginning to be implemented into the newer SiC diodes.

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POWER ELECTRONICS

Structure

Circuit Symbol

Anode

pin diode

Characteristics

High forward drop, high voltage blocking, slow turn-off.

Cathode

p

i

n

K

A

Schottky diode Si, SiC Anode

K

A

Cathode Fast switching, low voltage blocking.

n Metal Source

MOSFET N-channel enhancement mode

Gate Channel

n+

Oxide Channel

n+

Highest frequency range of operation of any controllable device, low-power gate signal required, good temperature characteristics, resistive forward drop.

p+

n-

D

Body doide n+

G S Drain MOSFET Superjunction C S

D

G n+ n+ p

n+ n+ p

n+

n+ p

n+ n+ p

p n

Similar to N-channel enhancement mode.

p n p

G

n

n

S

n+

n+

D

FIGURE 13.1.2 Commonly used power electronic devices showing their circuit symbols, simplified internal structures, equivalent circuits (where appropriate), and some major characteristics.

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POWER ELECTRONIC DEVICES POWER ELECTRONIC DEVICES

Circuit Symbol

Equivalent Circuit

Structure

13.7

Characteristics

Emitter IGBT

Gate

Oxide n+ p

N-channel, punch-through with lateral gate.

Collector

n+ p

Good behavior with respect to temperature variations, moderately good range of operating frequencies, moderately good forward drop characteristics, good SOA characteristics

p+

C

Gate

n−

n+

p+

G

Emitter E Collector

Emitter Gate

Oxide n+ p

N-channel, nonpunch-through with lateral gate.

n+ p p+

Similar to above.

n−

p+

Collector FIGURE 13.1.2 (Continued )

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POWER ELECTRONIC DEVICES 13.8

POWER ELECTRONICS

Circuit Symbol

Equivalent Circuit

Structure

N+

Characteristics

N+

N-channel, punch-through, trench-gate IGBT with transparent emitter

P

Similar to above N− N+ P+

Circuit Symbol

Structure

SCR A G

Equivalent Circuit

Anode

Forward and reverse voltage blocking capability, very high voltage and current ratings avaliable, low forward drop, no turn-Off control.

Anode

p+ K

Characteristics

pnp

n

GTO A

p

Gate

npn

n+ G

K

Cathode

Anode oxide

p-type MCT A G

Similar to SCR except controllable turn-off capability.

Cathode

oxide

p p+ p n p− n+ p

Anode

p-channel On-FET Gate

D S

Off-FET

S D

Metal

K

Cathode

On-FET

No reverse blocking, low-power gate signals for control, controllable -on and -off, low forward drop.

Cathode

FIGURE 13.1.2 (Continued )

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FIGURE 13.1.3 Comparison between major power electronic devices of their maximum switched power capability in terms of associated switching frequency. The switched power refers to the maximum forward blocking voltage multiplied by the maximum forward conduction current that each device is capable of handling.

Diode Ratings* Silicon diode ratings include voltage, current, and junction temperature. A list of some of the more important parameters is shown in Table 13.1.1. The device current rating IF is primarily determined by the area of the silicon die, power dissipation, and the method of heat sinking, while the spread of voltage ratings VRRM is determined by silicon resistivity and die thickness. Reverse voltage ratings are designated as repetitive VRRM and nonrepetitive VRSM. The repetitive value pertains to steady-state operating conditions, while the nonrepetitive peak value applies to occasional transient or fault conditions. Care must be exercised when applying a device to ensure that the voltage rating is never exceeded, even momentarily. When the blocking capability of a conventional diode is exceeded, leakage currents flow through the localized areas at the edge of the crystal. The resulting localized heating can cause rapid device failure. Although even low-energy reverse overvoltage transients are likely to be destructive, the silicon diode is remarkably rugged with respect to forward current transients. This property is demonstrated by the IFSM rating that permits one-half-cycle peak surge current of over ten times the IF rating. For shorter current pulses, less than 4 ms, the surge current is specified by an I 2t rating similar to that of a fuse. Proper circuit design must ensure that the maximum average junction temperature will never exceed its design limit of typically 150°C. Good design practice for high reliability, however, limits the maximum junction temperature to a lower value. The average junction-temperature rise above ambient is calculated by multiplying the average power dissipation, given approximately by the product of VF and IF, by the thermal resistance RqJC. Transient junction temperatures can be computed from the transient thermal-impedance curve. Device ratings are normally specified at a given case temperature and operating frequency. The proper use of a device at other operating conditions requires an appreciation of certain basic device characteristics. *Major

portions of this subsection were originally contributed by P. F. Pittman, J. C. Engel, and J. W. Motto.

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TABLE 13.1.1 Symbols for Some Diode Ratings and Characteristics Maximum Ratings VRRM VRSM IF(RMS) IF(AV) IFSM I2t Tj

Peak repetitive reverse voltage Peak nonrepetitive reverse voltage RMS forward current Average forward current Surge forward current Nonrepetitive pulse overcurrent capability Junction temperature

Characteristics VF IR tRR RqjC

Forward voltage drop (at specified temperature and forward current) Maximum reverse current (at specified temperature and reverse voltage) Reverse recovery time (under specified switching of forward and reverse currents) Junction-to-case thermal resistance

This is especially true in applications where the operating conditions of a number of devices are interdependent, as in series and parallel operation. For example, the forward voltage drop of a silicon diode has a negative temperature coefficient of 2 mV/°C for currents below the rated value. This variation in forward drop must be considered when devices are to be operated in parallel. The reverse blocking voltage of a diode, at a specified reverse current, effectively decreases with an increase in temperature. The tendency to decrease comes from the fact that the reverse leakage current of a junction increases with temperature, thereby decreasing the voltage attained at a given measuring-current level. If the leakage current is very low, the maximum reverse voltage will be determined by avalanche breakdown (which has a coefficient of approximately 0.1 percent per °C in silicon). Τhus, the voltage required to cause avalanche actually increases as the temperature rises. It should be noted that the reverse blocking voltage of a conventional diode is usually determined by imperfections at the edge of the die, and thus an ideal avalanche breakdown is usually not observed. Τhe reverse recovery time of a diode causes its performance to degrade with increasing frequency. Because of this effect, the rectification efficiency of a conventional diode used in a power circuit at high frequency is poor. In order to serve this application, a family of fast-recovery diodes has been developed. The stored charge of these devices is low, with the result that the amplitude and duration of the sweep-out current are greatly reduced compared with those of a conventional diode. However, improved turnoff characteristics of the fastrecovery diodes are obtained at some sacrifice in blocking voltage and forward drop compared with a conventional diode.

TRANSISTORS Power MOSFETs MOSFETs and IGBTs have an insulating oxide layer separating the gate contact and the silicon substrate. This insulating layer provides a large effective input resistance so that the control power necessary to switch these devices is considerably lower than that for a comparable bipolar transistor. The oxide layer also makes MOSFETs and IGBTs subject to damage from electrostatic charge build-up at the gate so that care must be exercised in their handling. Because of the internal structure of the power MOSFET, a pn junction (referred to as the “body diode”) is present that conducts when a reverse voltage is applied across the drain and source. Power MOSFETs do not suffer from second breakdown as bipolar transistors do and generally switch much faster, particularly during turn-off. Power MOSFETs have a large, voltage-dependent, effective input capacitance (combination of the gate-to-source and gate-to-drain capacitances) that can interact with stray circuit inductance in the gate-drive circuit to create oscillations. An external, small-valued resistor is usually placed

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in series with the gate lead to damp the oscillatory behavior. Even with a fairly large input capacitance, power MOSFETs can be made to turn on and off faster than any other type of power electronic device. Power MOSFETs are enhancement-type devices; a nonzero gate-to-source voltage must be applied to form a conducting channel between the drain and source to allow external current to flow. N-channel MOSFETs require a positive applied voltage at the gate with respect to the source for turn-on, while p-channel MOSFETs require a negative gate-source voltage. The gate electrode must be externally shorted to the source electrode for the device to support the maximum drain-source voltage VDS, and keep the device in its forward-blocking mode. Drain current will flow if the gate-source voltage VGS is above some minimum value (threshold voltage VGS(TH)) necessary to form the conducting channel between the drain and source. In the saturated-mode of operation (i.e., drain current ID, primarily dependent only on the gate-source voltage VGS) the most important device characteristic is the forward transconductance gfs usually specified by the manufacturer with a graph showing the value as a function of ID. The linear-mode of operation is preferred for switching applications. Here, VGS is typically in the range of 10 to 20 V. In this mode, ID is approximately proportional to the applied VDS for a given value of VGS. The proportionality constant defines the on-resistance rDS(ON). The on-resistance is the total resistance between the source and drain electrodes in the on-state and it determines the maximum ID rating (based on power dissipation restrictions). As temperature increases, the ability of charge to move through the conduction channel from source to drain decreases. The effect appears as an increase in rDS(ON). The increase in rDS(ON) as a function of temperature goes approximately as T2.3. Because of the positive temperature exponent, power MOSFETs can be operated in parallel, for increased current capacity, with relative ease. In addition, the safe operating area (SOA) of MOSFETs is relatively large and the devices can be operated reliably near the SOA limits. Power MOSFETs can be obtained with a forward voltage hold-off capability BVDSS of around 1.2 kV (nchannel) and current handling capacity of up to 100 A at lower BVDSS values. P-channel devices typically have less spread in ratings and are generally not available in extremes of current handling or hold-off voltage values like n-channel devices. MOSFETs can be obtained as discretely packaged parts or with several die configured together to form various half-bridge or full H-bridge topologies in a module. Advanced MOSFETs have integrated features that provide capabilities such as current limiting, voltage clamping, and current sensing for more intelligent system design. Trench- or buried-gate technology has contributed to the reduction of the Ron × Area product in power MOSFETs (and IGBTs) by a factor of 3 or more compared to surface gate devices (see Fig. 13.1.2). The trench-gate technology has been further adapted into the newest structure called the Superjunction MOSFET (see Fig. 13.1.2). The horizontal distribution of alternating p- and n-regions modifies the electric field distribution in the forward blocking mode such that the n-regions can be designed with a smaller vertical dimension, for the same blocking capability, as the trench-gate structure. Hence, the shorter current path causes the forward drop to be greatly reduced during conduction. At 100 A/cm2 the SJ-MOSFET has been shown to have a forward drop of 0.6 V as compared to 0.9 V for the traditional MOSFET (Fujihira, 1998). Table 13.1.2 lists some of the more important power MOSFET ratings and characteristics. IGBTs. Insulated-gate bipolar transistors are designated as n-type or p-type. The n-type of device dominates the marketplace because of its ease of use (it is controlled by a positive gate-emitter voltage). The n-type device can be thought of as an n-channel enhancement-mode MOSFET controlling the base current of a pnp bipolar transistor, as shown in Fig. 13.1.2. The naming convention is somewhat confusing because the external leads are labeled with the idea of an IGBT being a direct replacement for an npn transistor with a gate lead replacing the base lead (i.e., the emitter of the equivalent pnp, in Fig. 13.1.2, is the collector of the IGBT, and so forth). Applying a positive gate voltage above the threshold value, VGE(TH), turns the IGBT on. For switching applications, VGE is typically in the range of 10 to 20 V. The IGBT has a saturated mode of operation (similar to a MOSFET), where the collector current is relatively independent of collector-to-emitter voltage VCE. The base-collector junction, of the equivalent pnp, can never become forward biased because of drain current flow through the equivalent MOSFET. Therefore, the IGBT always has a forward drop, during conduction, of at least one pn junction (typically around 1 V). This is why the forward voltage drop VCE(ON) of the IGBT is greater than a comparable bipolar transistor, but less than a pure MOSFET structure at rated current flow. The switching times of the IGBT are shorter than comparable bipolar transistors (resulting in higher frequency of operation) and are not as susceptible to failure modes as are bipolars. The turn-off of an IGBT is characterized by two distinct portions of its current waveform. The first portion is characterized by a steep drop associated with the interruption of base-current to the equivalent pnp transistor (i.e., the internal MOSFET turns off). The second

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TABLE 13.1.2 Symbols for Some MOSFET Ratings and Characteristics Maximum Ratings VDS ID IDM Tj PD

Drain-source voltage Continuous drain current Pulsed drain current Junction temperature Maximum power dissipation

Characteristics BVDSS VGS(TH) IDSS ID(on) rDS(ON) gfs CISS COSS CRSS td(on) tr td(off ) tf Qg Qgs Qgd LD LS RqJC

Drain-source breakdown voltage Gate threshold voltage Zero gate-voltage drain current On-state drain current Static drain-source on-state resistance Common-source forward transconductance Input capacitance Output capacitance Reverse transfer capacitance Turn-on delay time Rise time Turn-off delay time Fall time Total gate charge (gate-source + gate-drain) Gate-source charge Gate-drain (“Miller”) charge Internal drain inductance Internal source inductance Junction-to-case thermal resistance

Body Diode Ratings IS ISM VSD trr QRR tON

Continuous source current Pulse source current Diode forward voltage drop Reverse recovery time Reverse recovered charge Forward turn-on time

portion is known as the current-tail and can be very long in time. This is associated with final turn-off of the bipolar transistor structure. Much of the IGBT design efforts are aimed at modifying this current-tail to control switching time and/or power dissipation during turn-off. If a large collector current is allowed to flow, the self-heating can cause the internal parasitic thyristor structure to latch into conductance (the gate thus loses the ability to turn the device off). This behavior is known as the short-circuit, shoot-through, or latch-up current limit. The maximum current that can flow (limited only by the device impedance), before latch-up occurs, must usually be limited to less than 10 ms duration. The behavior as a function of temperature is complicated for IGBTs. At low collector current values, the forward drop dependency as a function of temperature is similar to bipolar transistors. At high collector current values, the forward drop dependency on temperature is closer to that of a MOSFET. The exact design and fabrication steps used in the production of the device plays a strong role in the exact behavior because of temperature changes. Further details are available from Baliga (1987) and Hefner (1992). IGBTs can now be obtained with hold-off voltage ratings of up to 6.3 kV and pulsed forward current capability of over 200 A. These devices can be obtained as discrete components or with several parallel die (to form one switch) and then several sets of switches configured into bridge or half-bridge topologies in modules. They are also

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available with an integrated current sensing feature for active monitoring of device performance. There are two types of IGBT designs—punch through (PT) and non-punch through (NPT). NPT structures have no n+ buffer layer next to the p+ emitter (see Fig.13.1.2). This means that the applied forward blocking voltage can extend the associated depletion region all the way across the n– base causing breakdown at the p-emitter/n-base junction if the applied voltage is high enough. In a PT structure (shown in Fig. 13.1.2) the depletion region is pinned to the n+ buffer layer, thus allowing a thinner n– base (high-resistivity region) to be used in the device design. Previous generation IGBTs have a punch-through structure designed around a p+ Si substrate with two epitaxial regions (n− base region and n+ buffer layer). Carrier lifetime reduction techniques are often used in the drift region to modify the turn-off characteristics. Recently, trench-gate devices have been designed with local lifetime control in the buffer layer (Motto, 1998). High-voltage devices (>1.2 kV) have been created using a non-punchthrough structure beginning with the n− base region as the substrate upon which a shallow (transparent) p+ emitter is formed (Cotorogea, 2000). Cross-sections of typical unit cells for planar-gate IGBTs are shown in Fig. 13.1.2. Third-generation IGBTs make use of improved cell density and shallow diffusion technologies that create fast switching devices with lower forward drops than have been achieved with previous devices. These lateral channel structures have nearly reached their limit for improvements. New trench-gate technologies offer the promise of greatly improved operation (Santi, 2001). Trench technologies can create an almost ideal IGBT structure because it connects in series the MOSFET and a p-n diode. There is no parasitic JFET as is created by the diffused p-wells in a lateral channel device (see Fig. 13.1.2). A simplified cross-section of the trenchgate IGBT is shown in Fig. 13.1.2. The forward drop in a trench-gate device is reduced significantly from the value in a third-generation lateral-gate IGBT. For example, in devices rated for 100 A and 1200 V, the forward drop, VCE, is 1.8 V in a trench-gate IGBT as compared to 2.7 V in a lateral-gate (third generation) IGBT at the same current density, gate voltage, and temperature (Motto, 1998.) Local lifetime control is obtained in the n+ base layer by using proton irradiation. This helps decrease the effective resistance in the n– base by increasing the on-state carrier concentration. The surface structure of the gate is such that the MOS-channel width is increased (causing a decrease in channel resistance). The trend is for devices to be of the PT type as processing technology is improved. Table 13.1.3 lists some of the more important IGBT ratings and characteristics. Bipolar Transistors. Power bipolar transistors and bipolar Darlingtons are seldom used in modern converter systems because of the amount of power required by the control signal and the limited SOA of the traditional

TABLE 13.1.3 Symbols for Some IGBT Ratings and Characteristics Maximum Ratings VCES VCGR VGE IC Tj PD

Collector-emitter voltage Collector-gate voltage Gate-emitter voltage Continuous collector current Junction temperature Maximum power dissipation

Characteristic BVCES VGE(TH) ICES VCE(ON) QG(ON) tD(ON) tRl tD(OFF) tFl WOFF RqJC

Collector-emitter breakdown voltage Gate threshold voltage Zero gate-voltage collector current (at specified Tj and VCE value) Collector-emitter on-voltage (at specified Tj, IC, and VGE values) On-state gate charge (at specified IC and VCE values) Turn-on delay time (for specified test) Rise time (for specified test) Turn-off delay time (for specified test) Fall time (or specified test) Turn-off energy loss per cycle Junction-to-case thermal resistance

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power bipolar transistor. Because of their declining use, no further discussion will be given. Further details should be obtained from manufacturers’ databooks.

THYRISTORS There are four major types of thyristors: (i) silicon-controlled rectifier (SCR), (ii) gate turn-off (GTO) thyristor, (iii) MOS-controlled thyristor (MCT) and related forms, and (iv) static induction thyristor (SITh). MCTs are so-named because many parallel enhancement-mode, MOSFET structures of one charge type are integrated into the thyristor for turn-on and many more MOSFETs of the other charge type are integrated into the thyristor for turn-off. A static induction thyristor (SITh), or field-controlled thyristor (FCTh), has essentially the same construction as a power diode with a gate structure that can pinch-off anode current flow. The advantage of using MCTs, derivative forms of the MCT, or SIThs is that they are essentially voltage-controlled devices, (e.g., little control current is required for turn-on or turn-off) and therefore require simplified control circuits attached to the gate electrode (Hudgins, 1993). Less important types of thyristors include the Triac (a pair of low-power, anti-parallel SCRs integrated together to form a bi-directional current switch) and the programmable unijunction transistor (PUT). A thyristor used in some ac power circuits (50 or 60 Hz in commercial utilities or 400 Hz in aircraft) to control ac power flow can be made to optimize internal power loss at the expense of switching speed. These thyristors are called phase-control devices, because they are generally turned from a forward-blocking into a forward-conducting state at some specified phase angle of the applied sinusoidal anode-cathode voltage waveform. A second class of thyristors is used in association with dc sources or in converting ac power at one amplitude and frequency into ac power at another amplitude and frequency, and must generally switch on and off relatively quickly. The associated thyristors used are often referred to as inverter thyristors. SCRs and GTOs. The voltage hold-off ratings for SCRs and GTOs is above 6 kV and continuing development will push this higher. The pulsed current rating for these devices is easily tens of kiloamperes. A gate signal of 0.1 to 100 A peak is typical for triggering an SCR or GTO from forward blocking into forward conduction. These thyristors are being produced in silicon with diameters greater than 100 mm. The large wafer area places a limit on the rate of rise of anode current, and hence a di/dt limit (rating) is specified. The depletion capacitances around the pn junctions, in particular the center junction, limit the rate of rise in forward voltage that can be applied even after all the stored charge, introduced during conduction, is removed. The associated displacement current under application of forward voltage during the thyristor blocking state sets a dv/dt limit. Some effort in improving the voltage hold-off capability and over-voltage protection of conventional SCRs is underway by incorporating a lateral high-resistivity region to help dissipate the energy during breakover. Most effort, though, is being placed in the further development of high-performance GTO thyristors because of their controllability and to a lesser extent in optically triggered structures that feature gate circuit isolation. Optically gated thyristors have traditionally been used in power utility applications where series stacks of devices are necessary to achieve the high voltages required. Isolation between gate-drive circuits for circuits such as static VAR compensators and high voltage dc to ac inverters have driven the development of this class of devices. One of the most recent devices can block 6 kV forward and reverse, conduct 2.5 kA average current, and maintain a di/dt capability of 300 A/ms and a dv/dt capability of 3000 V/ms, with a required trigger power of 10 mW. High-voltage GTO thyristors with symmetric blocking capability require thick n-base regions to support the high electric field. The addition of an n+ buffer-layer next to the p+-anode allows high voltage blocking capability and yet produces a low forward voltage drop during conduction because of the thinner n−-base required. Many other design modifications have been introduced by manufacturers so that GTOs with a forward blocking capability of around 8 kV and anode conduction of 1 kA have been produced. Also, a reverse conducting GTO has been fabricated that can block 6 kV in the forward direction, interrupt a peak current of 3 kA, and has a turn-off gain of about 5. A modified GTO structure, called a gate-commutated thyristor (GCT), has been designed and manufactured that commutates all of the cathode current away from the cathode region and diverts it out the gate contact. The GCT is similar to a GTO in structure except that it has a low-loss n-buffer region between the n-base and

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p-emitter. The GCT device package is designed to result in very low parasitic inductance and is integrated with a specially designed gate-drive circuit (IGCT). The specially designed gate drive and ring-gate package circuit allows the GCT to be operated without a snubber circuit and switch with higher anode di/dt, than a similar GTO. At blocking voltages of 4.5 kV and higher, the IGCT seems to provide better performance than a conventional GTO. The speed at which the cathode current is diverted to the gate (diGQ /dt) is directly related to the peak snubberless turn-off capability of the GCT. The gate-drive circuit can sink current for turn-off at diGQ /dt values in excess of 7000 A/ms. This hard gate drive results in a low-charge storage time of about 1 ms. The low storage time and the fail-short mode makes the IGCT attractive for high-voltage series applications. The bi-directional control thyristor (BCT) is an integrated assembly of two anti-parallel thyristors on one Si wafer. The intended application for this switch is VAR compensators, static switches, soft starters, and motor drives. These devices are rated up to 6.5 kV blocking. Cross-talk between the two halves has been minimized. The small gate-cathode periphery necessarily restricts the BCT to low-frequency applications because of its di/dt limit. The continuing improvement in GTO performance has caused a decline in the use of SCRs, except at the very highest power levels. In addition, the improvement in IGBT design further reduces the attractiveness of SCRs. These developments make the future use of SCRs seemingly diminish. MCTs. There is a p-channel and an n-channel MOSFET integrated into the MCT, one FET-structure for turnon and one for turn-off. The MCT itself comes in two varieties: p-type (gate voltage applied with respect to the anode) and an n-type (gate voltage applied with respect to the cathode). Just as in a GTO, the MCT has a maximum controllable cathode current value. The inherent optimization for good switching and forward conduction characteristics make the MCT unable to block reverse applied voltages. MCTs are presently limited to operation at medium power levels. The seeming variability in fabrication of the turn-off FET structure continues to limit the performance of MCTs, particularly current interruption capability, though these devices can handle two to five times the conduction current density of IGBTs. All MCT device designs center on the problem of current interruption capability. Turn-on is relatively simple, by comparison, with it and conduction properties approaching the one-dimensional thyristor limit. Other types of integrated MOS-thyristor structures can be operated at high power levels, but these devices are not commonly available or are produced for specific applications. Typical MCT ratings are for 1 kV forward blocking and a peak controllable current of 75 A. A recent version of the traditional MCT design is a diffusion-doped (instead of the usual epitaxial growth) device. They are rated for 3 kV forward blocking, have a forward drop of 2.5 V at 100 A, and are capable of interrupting around 300 A with a recovery time of 5 ms. An MCT that uses trench-gate technology, called a depletion-mode thyristor (DMT), has been designed. A similar device is the base resistance controlled thyristor (BRT). Here, a p-channel MOSFET is integrated into the n-drift region of the MCT. These devices operate in an “IGBT” mode until the current is large enough to cause the thyristor structure to latch. Another new MCT-type structure is called an emitter switched thyristor (EST), and uses an integrated lateral MOSFET to connect a floating thyristor n-emitter region to an n+ thyristor cathode region. All thyristor current flows through the lateral MOSFET so it can control the thyristor current. Integrating an IGBT into a thyristor structure has been proposed. One device, called an IGBT triggered thyristor (ITT), is similar in structure and operation to the EST. The best designed EST, however, is the dual gate emitter switched thyristor (DGEST). The device has two gate electrodes. One gate controls an integrated IGBT section, while the other gate controls a thyristor section. The DG-EST is intended to be switched in IGBT mode, to exploit the controllability and snubberless capabilities of an IGBT. During forward conduction, the thyristor section takes over and thus the DG-EST takes advantage of a low forward drop and the latching nature of a thyristor. Static Induction Thyristors. A static induction thyristor (SITh) or field controlled thyristor (FCTh) is essentially a pin diode with a gate structure that can pinch-off anode current flow. High-power SIThs have a subsurface gate (buried-gate) structure to allow larger cathode areas to be used, and hence larger current densities can be conducted. Other SITh configurations have surface gate structures. Planar gate devices have been fabricated with blocking capabilities of up to 1.2 kV and conduction currents of 200 A, while step-gate (trench-gate) structures have been produced that are able to block up to 4 kV and conduct 400 A. Similar devices with a “Verigrid” structure have been demonstrated that can block 2 kV and conduct 200 A, with claims of up to 3.5 kV blocking and 200 A conduction. Buried gate devices that block 2.5 kV and conduct 300 A have also been fabricated.

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An integrated light-triggered and light-quenched SITh has been produced that can block 1.2 kV and conduct up to 20 A (at a forward drop of 2.5 V). This device is an integration of a normally off buried-gate static induction photothyristor and a normally off p-channel Darlington surface-gate static induction phototransistor. The optical trigger and quenching power required is less than 5 and 0.2 mW, respectively. Thyristor Behavior. The thyristor is a three-terminal semiconductor device comprising four layers of silicon so as to form three separate pn junctions. In contrast to the linear relation that exists between load and control currents in a transistor, the thyristor is bistable. The four-layer structure of the thyristor is shown in Fig. 13.1.2. The anode and cathode terminals are connected in series with the load to which power is to be controlled. The thyristor is turned on by application of a low-power control signal between the third terminal, or gate, and the cathode (between gate and anode for p-type MCT). The reverse characteristic is determined by the outer two junctions, which are reverse-biased in this operating mode. With zero gate current, the forward characteristic in the off- or blocking-state is determined by the center junction, which is reverse biased. However, if the applied voltage exceeds the forward blocking voltage, the thyristor switches to its on- or conducting state. The effect of gate current is to lower the blocking voltage at which switching takes place. This behavior can be explained in terms of the two-transistor analog shown in Fig. 13.1.2. The two transistors are regeneratively coupled so that if the sum of their current gains (a’s) exceeds unity, each drives the other into saturation. In the forward blocking-state, the leakage current is small, both a’s are small, and their sum is less than unity. Gate current increases the current in both transistors, increasing their a’s. When the sum of the two a’s equals 1, the thyristor switches to its on-state (latches). The form of the gate-to-cathode VI characteristic of SCRs and GTOs is similar to that of a diode. With positive gate bias, the gate-cathode junction is forward-biased and permits the flow of a large current in the presence of a low voltage drop. When negative gate voltage is applied to an SCR, the gate-cathode junction is reverse-biased and prevents the flow of current until the avalanche breakdown voltage is reached. In a GTO, a negative gate voltage is applied to provide a low impedance for anode current to flow out of the device instead of out of the cathode. In this way the cathode region turns off, thus pulling the equivalent npn transistor out of conduction. This causes the entire thyristor to return to its blocking state. The problem with the GTO is that the gate-drive circuitry is typically required to sink from 5 to 10 percent of the anode current to achieve turn-off. The MCT achieves turn-off by internally diverting current through an integrated MOSFET. Switching the equivalent MOSFET only requires a voltage signal to be applied at the gate electrode. A summary is provided in Table 13.1.4 of some of the ratings which must be considered when choosing a thyristor for a given application. Both forward and reverse repetitive and nonrepetitive voltage ratings must be considered, and a properly rated device must be chosen so that the maximum voltage ratings are never exceeded. In most cases, either forward or reverse voltage transients in excess of the nonrepetitive maximum ratings result in destruction of the device. The maximum rms or average current ratings given are usually those which cause the junction to reach its maximum rated temperature. Because the maximum current will depend on the current waveform and on thermal conditions external to the device, the rating is usually shown as a function of case temperature and conduction angle. The peak single half-cycle surge-current rating must be considered, and in applications where the thyristor must be protected from damage by overloads, a fuse with an I 2t rating smaller than the maximum rated value for the device must be used. Maximum ratings for both forward and reverse gate voltage, current, and power also must not be exceeded. The maximum rated operating junction temperature TJ must not be exceeded, since device performance, in particular voltage-blocking capability, will be degraded. Junction temperature cannot be measured directly but must be calculated from a knowledge of steady-state thermal resistance RqJC and the average power dissipation. For transients or surges, the transient thermal impedance (ZqJC) curve must be used. The maximum average power dissipation PT is related to the maximum rated operating junction temperature and the case temperature by the steady-state thermal resistance. In general, both the maximum dissipation and its derating with increasing case temperature are provided. The number of thyristor characteristics specified varies widely from one manufacturer to another. Some characteristics are given only as typical values of minima or maxima, while many characteristics are displayed graphically. Table 13.1.4 summarizes some of the characteristics provided. Thyristor types shown in parentheses

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TABLE 13.1.4 Symbols for Some Thyristor Ratings and Characteristics Maximum Ratings VRRM VRSM (SCR & GTO) VDRM VDSM (SCR & GTO) IT(RMS) IT(AV) (IK for MCT) ITSM (IKSM for MCT) ITGO (IKC for MCT) I2t (SCR & GTO) PT (MCT) di/dt dv/dt PGM(PFGM for GTO) PRGM (GTO) VFGM VRGM IFGM (SCR & GTO) IRGM (GTO) Tj

Peak repetitive reverse voltage Peak nonrepetitive reverse voltage Peak repetitive forward off-state voltage Peak nonrepetitive forward off-state voltage RMS forward current Average forward current Surge forward current Peak controllable current Nonrepetitive pulse overcurrent capability Maximum power dissipation Critical rate of rise of on-state current Critical rate of rise of off-state voltage Peak gate forward power dissipation Peak gate reverse power dissipation Peak forward gate voltage Peak reverse gate voltage Peak forward gate current Peak reverse gate current Junction temperature

Characteristics VTM IDRM IRRM CISS (MCT) VGT (SCR & GTO) VGD (SCR & GTO) IGT (SCR & GTO) tgt (GTO) tq (SCR & GTO) tD(ON) (MCT) t Rl (MCT) tD(OFF) (MCT) tFl (MCT) WOFF (MCT) RqJC

On-state voltage drop (at specified temperature and forward current) Maximum forward off-state current (at specified temperature and forward voltage) Maximum reverse blocking current (at specified temperature and reverse voltage) Input capacitance (at specified temperature and gate and anode voltages) Gate trigger voltage (at specified temperature and forward applied voltage) Gate nontrigger voltage (at specified temperature and forward applied voltage) Gate trigger current (at specified temperature and forward applied voltage) Turn-on time (under specified switching conditions) Turn-off time (under specified switching conditions) Turn-on delay time (for specified test) Rise time (for specified test) Turn-off delay time (for specified test) Fall time (for specified test) Turn-off energy loss per cycle Junction-to-case thermal resistance

indicate a characteristic unique to that device or devices. Gate conditions of both voltage and current to ensure either nontriggered or triggered device operation are included. The turn-on and turn-off transients of the thyristor are characterized by switching times like the turn-off time listed in Table 13.1.4. The turn-on transient can be divided into three intervals—gate-delay interval, turnon of initial area, and spreading interval. The gate-delay interval is simply the time between application of a turn-on pulse at the gate and the time the initial area turns on. This delay decreases with increasing gate drive current and is of the order of a few microseconds. The second interval, the time required for turn-on of the initial area, is quite short, typically less than 1 ms. In general, the initial area turned on is a small percentage of the total useful device area. After the initial area turns on, conduction spreads (spreading interval) throughout the device in tens of microseconds. It is during this spreading interval that the di/dt limit must not be exceeded. Typical di/dt values range from 100 to 1000 A/ms. Special inverter-type SCRs and GTOs are made that have increased switching speed (at the expense of higher forward voltage drop during conduction) with di/dt values in the range of 2000 A/ms. The rate

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of application of forward voltage is also restricted by the dv/dt characteristic. Typical values range from 100 to 1000 V/ms. Thyristors are available in a wide variety of packages, from small plastic ones for low-power (i.e., TO-247), to stud-mount packages for medium-power, to press-pack (also called flat-pack) for the highest power devices. The press-packs must be mounted under pressure to obtain proper electrical and thermal contact between the device and the external metal electrodes. Special force-calibrated clamps are made for this purpose.

OTHER POWER SEMICONDUCTOR DEVICES Semiconductor materials such as silicon carbide (SiC), gallium arsenide (GaAs), and gallium nitride (GaN) are being used to develop pn-junction and Schottky diodes, power MOSFET structures, some thyristors, and other switches. SiC diodes are commercially available now. No other commercial power devices made from these materials yet exist, but will likely be available in the future. Further information about advanced power semiconductor materials and device structures can be found in (Baliga, 1996) and (Hudgins, 1993, 1995, 2003).

BIBLIOGRAPHY Azuma, M. and M. Kurata, “GTO thyristors,” IEEE Proc., pp. 419–427, April, 1988. Baliga, B. J., “Modern Power Devices,” Wiley, 1987. Baliga, B. J., “Power Semiconductor Devices,” PWS, 1996. Busatto, G., G. F. Vitale, G. Ferla, A. Galluzzo, and M. Melito, “Comparative analysis of power bipolar devices,” IEEE PESC Rec., pp. 147–153, 1990. Cotorogea, M., A. Claudio, and J. Aguayo, “Analysis by measurements and circuit simulations of the PT- and NPT-IGBT under different short-circuit conditions,” IEEE APEC Rec., pp. 1115–1121, 2000. Fujihira, T., and Y. Miyasaka, “Simulated superior performances of semiconductor superjunction devices,” IEEE Proc. ISPSD, pp. 423–426, 1998. Ghandhi, S. K., “Semiconductor Power Devices,” Wiley, 1977. Hefner, A. R., “A dynamic electro-thermal model for the IGBT,” IEEE Industry Appl. Soc. Ann. Mtg. Rec., pp. 1094–1104, 1992. Hower, P. L., “Power semiconductor devices: An overview,” IEEE Proc., Vol. 76, pp. 335–342, April, 1988. Hudgins, J. L., “A review of modern power semiconductor devices,” Microelect. J., Vol. 24, pp. 41–54, 1993. Hudgins, J. L., “Streamer model for ionization growth in a photoconductive power switch,” IEEE Trans. PEL, Vol. 10, pp. 615–620, September, 1995. Hudgins, J. L., G. S. Simin, E. Santi, and M. A. Khan, “A new assessment of wide bandgap semiconductors for power devices,” IEEE Trans. PEL, Vol. 18, pp. 907–914, May 2003. Motto, E. R., J. F. Donlon, H. Takahashi, M. Tabata, and H. Iwamoto, “Characteristics of a 1200 V PT IGBT with trench gate and local lifetime control,” IEEE IAS Annual Mtg. Rec., pp. 811–816, 1998. Nishizawa, J., T. Terasaki, and J. Shibata, “Field effect transistor versus analog transistor: static induction transistor,” IEEE Tran. ED, Vol. ED-22, pp. 185–197, 1975. Santi, E., A. Caiafa, X. Kang, J. L. Hudgins, P. R. Palmer, D. Goodwine, and A. Monti, “Temperature effects on trench-gate IGBTs,” IEEE IAS Annual Mtg. Rec., pp. 1931–1937, 2001. Sze, S. M., “Physics of Semiconductor Devices,” 2nd ed., Wiley, 1981. Venkataramanan, G., A. Mertens, H. Skudelny, and H. Grunig, “Switching characteristics of field controlled thyristors,” Proc. EPE—MADEP ’91, pp. 220–225, 1991.

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Source: STANDARD HANDBOOK OF ELECTRONIC ENGINEERING

CHAPTER 13.2

NATURALLY COMMUTATED CONVERTERS Arthur W. Kelley

INTRODUCTION The applications for this family of naturally commutated converters embrace a very wide range, including dc power supplies for electronic equipment, battery chargers, dc power supplies delivering many thousands of amperes for electrochemical and other industrial processes, high-performance reversing drives for dc machines rated at thousands of horsepower, and high-voltage dc transmission at the gigawatt power level. The basic feature common to this class of converters is that one set of terminals is connected to an ac voltage source. The ac source causes natural commutation of the converter power electronic devices. In these converters, a second set of terminals operates with dc voltage and current. This class of converters is divided in function depending on the direction of power flow. In ac-to-dc rectification, the ac source, typically the utility line voltage, supplies power to the converter, which in turn supplies power to a dc load. In dc-to-ac inversion, a dc source, typically a battery or dc generator, provides power to the converter, which in turn transfers the power to the ac source, again, usually the utility line voltage. Because natural commutation synchronizes the power semiconductor device turn on and turn off to the ac source, this converter is also known as a synchronous inverter or a line-commutated inverter. This process is different from supplying power to an ac load, which usually requires forced commutation. The power electronic devices in these converters are typically either silicon controlled rectifiers (SCRs) diodes. To simplify the discussion that follows, the SCRs and diodes are assumed to (1) conduct forward current with zero forward voltage drop, (2) block reverse voltage with zero leakage current, and (3) switch instantaneously between conduction and blocking. Furthermore, stray resistive loss is ignored and balanced three-phase ac sources are assumed.

Converter Topologies Basic Topologies. The number of different converter topologies is very large (Schaeffer, 1965; Pelly, 1971; Dewan, 1975; Rashid, 1993). Using SCRs as the power electronic devices, Table 13.2.1 illustrates four basic topologies from which many others are derived. These ac-to-dc converters are rectifiers that provide a dc voltage VO to a load. The rectifier often uses an output filter inductor LO and capacitor CO, but one or the other or both are often omitted. Rectifiers are usually connected to the ac source through a transformer. Note that the transformer is often utility equipment, located separately from the rectifier. The transformer adds a series leakage inductance LS, which is often detrimental to rectifier operation. Rectifier topologies are classified by whether the rectifier operates from a single- or three-phase source and whether the rectifier uses a bridge connection or transformer midpoint connection. The single-phase bridge rectifier shown in Table 13.2.1a requires four SCRs and a two-winding transformer. The single-phase midpoint

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TABLE 13.2.1 Basic Converter Topologies

rectifier shown in Table 13.2.1b requires only two SCRs but requires a transformer with a center-tapped secondary to provide the midpoint connection. The three-phase bridge rectifier shown in Table 13.2.1c requires six SCRs and three two-winding transformers. The three-phase midpoint rectifier shown in Table 13.2.1d requires three SCRs and three transformers using a Y-connected “zig-zag” secondary. The Y-connected secondary provides the necessary midpoint connection and the zig-zag winding prevents unidirectional secondary winding currents from causing magnetic saturation of the transformers. The bridge rectifier is better suited to using the simple connection provided by the typical utility transformer. For the same power delivered to the load, the bridge rectifier often requires a smaller transformer. Therefore, in the absence of other constraints, the bridge rectifier is often preferred over the midpoint rectifier. Pulse Number. Converters are also classified by their pulse number q, an integer that is the number of current pulses appearing in the rectifier output current waveform iX per cycle of the ac source voltage. Higher pulse number rectifiers generally have higher performance but usually with a penalty of increased complexity. Of the rectifiers shown in Table 13.2.1, both single-phase rectifiers are two-pulse converters (q = 2) with one current pulse in iX for each half-cycle of the ac source voltage. The three-phase midpoint rectifier is a threepulse converter (q = 3) with one current pulse in iX for each cycle of each phase of the three-phase ac source voltage. The three-phase bridge rectifier is a six-pulse converter (q = 6) with one current pulse in iX for each half cycle of each phase of the three-phase ac source voltage.

BASIC CONVERTER OPERATION Given a certain operating point, rectifier operation and performance are dramatically influenced by the values of source inductance LS, output filter inductance LO, and output filter capacitance CO. Operation with Negligible Ac Source Inductance. Figures 13.2.1 and 13.2.2 show example time waveforms for the single- and three-phase bridge rectifiers of Table 13.2.1a and 13.2.1c, respectively. In these

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FIGURE 13.2.1 Time waveforms for single-phase bridge rectifier with a = 40°: (a) CCM and (b) DCM.

FIGURE 13.2.2 Time waveforms for three-phase bridge rectifier with a = 20°: (a) CCM and (b) DCM.

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examples LS is comparatively small and its influence is neglected. The value of CO is relatively large so that the ripple in the output voltage VO is relatively small. Operation of single- and three-phase phase-controlled rectifiers is described in detail in (Kelley, 1990). Figure 13.2.1a shows time waveforms for the single-phase bridge rectifier when the current iX in LO flows continuously without ever falling to zero. The rectifier is said to be operating in the continuous conduction mode (CCM). The CCM occurs for relatively large LO, heavy loads, and small a. Figure 13.2.1b shows time waveforms for the single-phase bridge rectifier when iX drops to zero twice each cycle and the rectifier is said to be operating in the discontinuous conduction mode (DCM). The DCM occurs for relatively small LO, light loads, and large a. Figure 13.2.1 also shows the conduction intervals for SCRs Q1 to Q4 and the rectifier voltage, vX. A controller, not shown in Fig. 13.2.1, generates gating pulses for the SCRs. The controller gates each SCR at a firing angle a (alpha) with respect to a reference that is the point in time at which the SCR is first forward biased. The SCR ceases conduction at the extinction angle b (beta). The reference, a, and b for Q1 are illustrated in Fig. 13.2.1. The SCR conduction angle g (gamma) is the difference between b and a. In DCM the SCR ceases conduction because iX falls naturally to zero, while in the CCM the SCR ceases conduction even though iX is not zero because the opposing SCR is gated and begins conducting iX. Therefore in CCM, g is limited to a maximum of one-half of an ac source voltage cycle, while in DCM g depends on LO, load, and a. Note that vX equals vS when Q1 and Q4 are conducting and that vX equals –vS when Q2 and Q3 are conducting. The output filter LO and CO reduces the ripple in vX and delivers a relatively ripple-free voltage VO to the load. The firing angle a determines the composition of vX and ultimately the value of VO. Increasing a reduces VO and is the mechanism by which the controller regulates VO against changes in ac source voltage and load. This method of output voltage regulation is referred to as phase control, and a rectifier using it is said to be a phase-controlled rectifier. Since in CCM the conduction angle is always one half of a source voltage cycle, the dc output voltage is easily found from vX as VO =

2 2 VS cos α π

(1)

where VS is the rms value of the transformer secondary voltage vS. Unfortunately, the conduction angle in DCM depends on LO, the load, and a, and VO cannot be calculated except by numerical methods. For the three-phase bridge rectifier, Figures 13.2.2a and 13.2.2b show time waveforms for CCM and DCM, respectively. Operation is similar to the single-phase rectifier except that vX equals each of the six line-to-line voltages—vAB, vAC, vBC, vBA, vCA, and vCB—in succession. In CCM, the SCR conduction angle g is one-third of an ac source voltage cycle, and in DCM g depends on LO, load, and a. In CCM the dc output voltage VO is found from vX as VO =

FIGURE 13.2.3 Time waveforms for three-phase bridge rectifier with appreciable LS.

3 3 2 VS cos α π

(2)

where VS is the rms value of the transformer secondary line-to-neutral voltage. In DCM, the value of VO must be calculated by numerical means. To produce a ripple-free output voltage VO , the time waveform of vX for the threephase rectifier naturally requires less filtering than the time waveform of vX for the single-phase rectifier.

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Therefore, if a three-phase ac source is available, a three-phase rectifier is always preferred over a single-phase rectifier. Operation with Appreciable Ac Source Inductance. The preceding discussion assumes that the value of LS is small and does not influence circuit operation. In practice the effect of LS must often be considered. The threephase rectifier CCM time waveforms of Fig. 13.2.2 are repeated in Fig. 13.2.3 but for an appreciable LS. Since iX is always nonzero in CCM, the principal effect of LS is to prevent instantaneous transfer of iX from one transformer secondary winding to the next transformer secondary winding as the SCRs are gated in succession. This process is called commutation and the interval during which it occurs is called commutation overlap. For example, at some point in time Q1 is conducting iSA equal to iX and Q3 is gated by the controller. Current iSA through Q1 falls while iSB through Q3 rises. During this interval both Q1 and Q3 conduct simultaneously and the sum of iSA and iSB is equal to iX. As a result transformer secondary vSA is directly connected to transformer secondary vSB effectively creating a line-to-line short circuit. This connection persists until iSA falls to zero and Q1 ceases conduction. The duration of the connection is the commutation angle m (mu). During this interval vSA experiences a positive-going voltage “notch” while vSB experiences a negative-going voltage notch. The enclosed area of the positive-going notch equals the enclosed area of the negative-going notch and represents the flux linkage or “volt seconds” necessary to produce a change in current through LS equal to iX. If LO is sufficiently large so that iX is relatively constant with value IX during the time that both SCRs conduct, then the notch area is used to find cosα − cos( µ + α ) =

2 (2π f LS I X / VS ) 3

(3)

which can be solved numerically for m. Note that the commutation angle is always zero in DCM since iX is zero when each SCR is gated to begin conduction.

CONVERTER POWER FACTOR Source Current Harmonic Composition. The time waveforms of the prior section show that the rectifier is a nonlinear load that draws a highly distorted nonsinusoidal waveform iS. Fourier series is used to decompose iS into a fundamental-frequency component with rms value IS(1) and phase angle fS(1) with respect to vS, and into harmonic-frequency components with rms value IS(h) where h is an integer representing the harmonic number. In general, the IS(h) are zero for even h. Furthermore, depending on converter pulse number q, certain IS(h) are also zero for some odd h. Apart from h = 1 for which IS(1) is always nonzero, the IS(h) are nonzero for h = kq ± 1 (k integer ≥ 1)

(4)

Therefore harmonic currents for certain harmonic numbers are eliminated for higher pulse numbers. For example, the single-phase bridge rectifier with q = 2 produces nonzero IS(h) for h = 1, 3, 5, 7, 9, . . . , while the threephase bridge rectifier with q = 6 produces nonzero IS(h) for h = 1, 5, 7, 11, 13, . . . . If rectifier operation is unbalanced, then harmonics are produced for all h. An unbalanced condition can result from asymmetrical gating of the SCRs or from voltage or impedance unbalance of the ac source. The effect is particularly pronounced for three-phase rectifiers with a comparatively small LO and a comparatively large CO since these rectifiers act like “peak detectors” and CO charges to the point where VO approaches the peak value of the line-to-line voltage. One phase needs to be only several percent below the other two phases for it to conduct a greatly reduced current and shift most of the current to the other two phases. An unbalanced condition is always evident from the waveform of iX because the heights of the pulses are not all the same. Power Factor.

The rms value IS of iS is found from I S = I S (1) 2 + ∑ I S ( h ) 2 h >1

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(5)

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The ac source is rated for apparent power S, which is the product of VS and IS (in volt-amperes, VA). However, the source delivers real input power PI (in watts, W), which the rectifier converts to dc and supplies to the load. The total power factor PF is the ratio of the real input power and the apparent power supplied by the ac source PF =

PI P = I S VS I S

(6)

and measures the fraction of the available apparent power actually delivered to the rectifier. The source voltage vS is an undistorted sine wave only if LS is negligible. In this case power is delivered only at the fundamental frequency so that PI = VSIS(1) cos fS(1)

(7)

Note that the harmonics IS(h) draw apparent power from the source by increasing IS but do not deliver real power to the rectifier. Using this assumption, the expression for power factor reduces to PF = cos φS (1)

I S (1) (8)

IS

The displacement power factor cosfS(1) is the traditional power factor used in electric power systems for sinusoidal operation and is unity when the fundamental of iS is in phase with vS. The purity factor IS(1)/IS is unity when iS is a pure sine wave and the rms values of IS(h) are zero so that IS equals IS(1). The distortion of iS is often and equivalently represented by the total harmonic distortion for current THDi

THDi = 100

I S (h) ∑ h >1 I S (1)

2

= 100

1 −1 ( I S (1) /I S )2

(eexpressed in percent)

(9)

The purity factor IS(1)/IS is also called the distortion power factor, which is easily confused with the total harmonic distortion THDi. The theoretical maximum power factor for the single-phase bridge rectifier is 0.90, which occurs for a = 0° and usually requires an uneconomically large value of LO. The actual power factor often ranges from 0.5 to 0.75. The theoretical maximum power factor for the three-phase bridge rectifier is 0.96 which also occurs for a = 0°. Because the three-phase bridge rectifier requires less filtering, it is often possible to approach this theoretical maximum power factor with an economical value of LO. However, for cost reasons, LO is often omitted in both the single- and three-phase rectifiers which dramatically reduces the power factor and leaves it to depend on the value of LS. Source Voltage Distortion and Power Quality. The time waveforms of Fig. 13.2.3 show that with appreciable LS the rectifier distorts the voltage source vS supplying the rectifier. Fourier series is also used to represent vS as a fundamental voltage of rms value VS(1) and harmonic voltages of rms value VS(h). The distortion of vS is often represented by the total harmonic distortion for voltage THDv

THDv = 100

VS ( h ) ∑ h >1 VS (1)

2

(expressed in percentt)

(10)

Note that the definition of power factor (Eq. (7)) is valid for appreciable LS and distorted vS but (Eq. (8)) is strictly valid only when LS is negligible and vS is undistorted. Voltage distortion can cause problems for other loads sharing the rectifier ac voltage source. Computerbased loads, which have become very common, appear to be particularly sensitive. Issues of this kind have been receiving increased attention and fall under the general heading of power quality. Increasingly strict

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power factor and harmonic current limits are being placed on ac-to-dc converters (IEEE-519, 1992; IEC-1000, 1995). In particular, limits on the total harmonic distortion of the current THDi, the rms values IS(h) of the harmonics, and the rms values of the harmonics relative to the fundamental IS(h)/IS(1) are often specified. These limits present new challenges to the designers of ac-to-dc converters.

ADDITIONAL CONVERTER TOPOLOGIES This section summarizes the large number of converters that are based on the rectifiers of Table 13.2.1. These converters are shown in Table 13.2.2. Uncontrolled Diode Rectifier. Replacing SCRs with diodes produces an uncontrolled rectifier as shown in Table 13.2.2a. In contrast to the SCRs, which are gated by a controller, the diodes begin conduction when initially forward biased by the circuit so that an uncontrolled diode rectifier behaves like a phase-controlled rectifier operated with a = 0°. Details of uncontrolled diode rectifier operation are described in Kelley (1992). Half-Controlled Bridge Rectifier. In the half-controlled bridge rectifier the even-numbered SCRs (Q2 and Q4 for the single-phase rectifier, and Q2, Q4, and Q6 for the three-phase rectifier) are replaced with diodes as shown in Table 13.2.2b. The remaining odd-numbered SCRs (Q1 and Q3 for the single-phase rectifier, and Q1, Q3, and Q5 for the three-phase rectifier) are phase controlled to regulate the dc output voltage VO. This substitution is advantageous because diodes are cheaper than SCRs and the cathodes of the remaining SCRs are connected to a common point that simplifies SCR gating. Note that the diodes begin conduction when first forward biased while the SCRs begin conduction only after being gated while under forward bias. As a result, during a certain portion of each cycle, iX freewheels through the series connection of a diode and SCR, thereby reducing iS to zero. For example, in the single-phase bridge rectifier iX freewheels through Q1 and D2 for one part of the cycle and through Q3 and D4 for another part of the cycle. In the three-phase rectifier iX freewheels through Q1 and D2, Q3 and D4, and Q5 and D6 during different parts of the cycle. This freewheeling action prevents vX from changing polarity and improves rectifier power factor as a increases and VO decreases. Freewheeling Diode. The same effect is achieved if a freewheeling diode DX is connected across terminals 1 and 2 of the rectifier as shown in Table 13.2.2c. The freewheeling diode is used with both the bridge and midpoint rectifier connections. Dc Motor Drive. Any of the phase-controlled rectifiers described above can be used as a dc motor drive by connecting the motor armature across terminals 1 and 2 as shown in Table 13.2.2d. Phase control of SCR firing angle a controls motor speed. Battery Charger. Phase-controlled rectifiers are widely used as battery chargers as shown in Table 13.2.2e. Phase control of SCR firing angle a regulates battery charging current. Line Commutated Inverter. A line-commutated inverter transfers power from the dc terminals 1 and 2 of the converter to the ac source. As shown in Table 13.2.2f, the dc terminals are connected to a dc source of power such as a dc generator or a battery. The polarity of each SCR is reversed and the rectifier is operated with a > 90°. This circuit is called a line-commutated inverter or a synchronous inverter. Note that the half-controlled bridge and the freewheeling diode cannot be used with a line-commutated inverter because they prevent a change in the polarity of vX. Operation with a > 90° causes the majority of the positive half cycle of iS to coincide with the negative half cycle of vS . Similarly, the negative half cycle of iS coincides with the positive half cycle of vS. It is this mechanism that, on average, causes power flow from the dc source into the ac source. In principal a could approach 180°, but in practice a must be limited to 160° or less to permit sufficient time for the SCRs to stop conducting and regain forward voltage blocking capability before forward voltage is reapplied to them. This requirement is particularly important when LS is appreciable.

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TABLE 13.2.2 Additional Converter Topologies

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TABLE 13.2.2 Additional Converter Topologies (Continued)

(Continued)

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TABLE 13.2.2 Additional Converter Topologies (Continued )

Alternate Three-Phase Transformer Connections. Both primary and secondary transformer windings may be either Y-connected or ∆-connected, as shown in Table 13.2.2g except for the midpoint connection, which requires a Y-connected secondary winding. If the connection is Y-Y or ∆-∆ the waveform of secondary current iS is scaled by the transformer turn ratio to become the waveform of primary current iP. Therefore, the secondary current fundamental IS(1) and harmonics IS(h), when scaled by the turn ratio, become the primary fundamental IP(1) and harmonics IP(h). Similarly, if the transformer connection is Y-∆ or ∆-Y, the secondary current fundamental IS(1) and harmonics IS(h), when scaled by the turn ratio, become the primary fundamental IP(1) and harmonics IP(h). However, the Y-∆ and ∆-Y transformer connections introduce different phase shifts for each harmonic so that the primary current waveform iP differs in shape from the secondary current wave-form iS. Rectifier power factor remains unchanged; however, this phase shift is used to produce harmonic cancellation in rectifiers with high pulse numbers as described subsequently. Bidirectional Converter. Many applications require bidirectional power flow from a single converter. Table 13.2.2h illustrates one example in which a phase-controlled rectifier is, effectively speaking, connected in parallel with a line commutated inverter by replacing each SCR with a pair of SCRs connected in antiparallel. The load is replaced either by a battery or by a dc motor. In the bidirectional converter, one polarity of SCRs is used to transfer energy from the ac source to the battery or motor while the opposite polarity of SCRs is used to reverse the power flow and transfer energy from the battery or motor to the ac source. For example, using the battery, the converter operates as a battery charger to store energy when demand on the utility is low and at a subsequent time the converter operates as a line commutated inverter to supply energy

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when demand on the utility is high. Using a dc motor, the converter operates as a dc motor drive to supply power to a rotating load. Depending on the direction of motor rotation and on which polarity of SCRs is used, the bidirectional converter can both brake the motor efficiently by returning the energy stored in the rotating momentum back to the ac source and subsequently reverse the motors direction of rotation. Active Power Factor Corrector. In many instances the basic converter topologies of Table 13.2.1 and the additional converter topologies of Table 13.2.2a to 13.2.2g cannot meet increasingly strict power factor and harmonic current limits without the addition of expensive passive filters operating at line frequency. The active power factor corrector, illustrated in Table 13.2.2i, is one solution to this problem (Rippel, 1979; Kocher, 1982; Latos, 1982). The output filter inductor LO is replaced by a high-frequency filter and a dcto-dc converter. The dc-to-dc converter uses high-frequency switching and a fast control loop to actively control the waveshape of iX, and therefore control the waveshape of iS, for near unity displacement power factor and near unity purity factor resulting in near unity power factor ac-to-dc conversion (Huliehel, 1992). A high-frequency filter is required to prevent dc-to-dc converter switching noise from reaching the ac source. A slower control loop regulates VO against changes in source voltage and load. Because the dc-to-dc converter regulates VO over a wide range of source voltage, the active power factor corrector can be designed for a universal input that allows the corrector to operate from nearly any ac voltage source. The active power factor corrector is used most commonly for lower powers. Higher Pulse Numbers. When strict power factor and harmonic limits are imposed at higher power levels, and the active factor corrector cannot be used, the performance of the basic rectifier is improved by increasing the pulse number q and elimination of current harmonics IS(h) for certain harmonic numbers as shown by Eq. (4). Table 13.2.2j and 13.2.2k illustrate two examples based on the three-phase six-pulse bridge rectifier (q = 6) of Table 13.2.1c. The six-pulse rectifiers are shown connected in series in Table 13.2.2j and in parallel in Table 13.2.2k. The parallel connection in Table 13.2.2k requires an interphase reactor to prevent commutation of the SCRs in one rectifier from interfering with commutation of the SCRs in the other rectifier. The interphase reactor also helps the two rectifiers share the load equally. Both approaches use a Y-Y transformer connection to supply one six-pulse rectifier and a ∆-Y transformer connection to supply the second six-pulse rectifier. The primary-to-secondary voltage phase shift of the ∆-Y transformer means the two rectifiers operate out of phase with each other producing 12-pulse operation (q = 12). As described previously, the ∆-Y transformer also produces a secondary-to-primary phase shift of the current harmonics. As a result, at the point of connection to the ac source, harmonics from the ∆-Y connected six-pulse rectifier cancel the harmonics from the Y-Y connected six-pulse rectifier for certain harmonic numbers. For example, the harmonics cancel for h = 5 and 7, but not for h = 11 and 13. Thus the total harmonic distortion for current THDi and the total power factor for the 12-pulse converter is greatly improved in comparison to either six-pulse converter alone. The 12-pulse output voltage ripple filtering requirement is also greatly reduced compared to a single six-pulse rectifier. This principle can be extended to even higher pulse numbers by using additional six-pulse rectifiers and transformer phase-shift connections. High Voltage Dc Transmission. High Voltage dc (HVDC) Transmission is a method for transmitting power over long distances while avoiding certain problems associated with long distance ac transmission. This requirement often arises when a large hydroelectric power generator is located a great distance from a large load such as a major city. The hydroelectric generator’s relatively low ac voltage is stepped up by a transformer, and a phase-controlled rectifier converts it to a dc voltage of a megavolt or more. After transmission over a long distance, a line commutated inverter and transformer convert the dc back to ac and supply the power to the load. Alternately, the rectifier and inverter are co-located and used as a tie between adjacent utilities. The arrangement can be used to actively control power flow between utilities and to change frequency between adjacent utilities operating at 50 and 60 Hz. With power in the gigawatt range, this is perhaps the highest power application of a power electronic converter. To ensure a stable system, the control algorithms of the rectifier and inverter must be carefully coordinated. Note that since the highest voltage rating of an individual SCR is less than 10 kV, many SCRs are connected in series to form a valve capable of blocking the large dc voltage. Both the rectifier and inverter use a high pulse number to minimize filtering at the point of connection to the ac source.

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REFERENCES Dewan, S. B., and A. Straughen, “Power Semiconductor Circuits,” Wiley, 1975. Huliehel, F. A., F. C. Lee, and B. H. Cho, “Small-signal modeling of the single-phase boost high power factor converter with constant frequency control,” Record of the 1992 IEEE Power Electronics Specialists Conference (PESC ’92), pp. 475–482, June 1992. IEC-1000 Electromagnetic Compatibility (EMC), Part 3: Limits, Section 2: Limits for Harmonic Current Emissions (formerly IEC-555-2), 1995. IEEE Standard 519, “IEEE Recommended Practices and Requirements for Harmonic Control in Electrical Power Systems,” 1992. Kelley, A. W., and W. F. Yadusky, “Phase-controlled rectifier line-current harmonics and power factor as a function of firing angles and output filter inductance,” Proc. IEEE Applied Power Electronics Conf., pp. 588–597, March 1990. Kelley, A. W., and W. F. Yadusky, “Rectifier design for minimum line-current harmonics and maximum power factor,” IEEE Trans. Power Electronics, Vol. 7, No, 2, pp. 332–341, April 1992. Kocher, M. J., and R. L. Steigerwald, “An ac-to-dc converter with high-quality input waveforms,” Record of the 1982 IEEE Power Electronics Specialists Conference (PESC ’82), pp. 63–75, June 1982. Latos, T. S., and D. J. Bosak, “A high-efficiency 3-kW switchmode battery charger,” Record of the 1982 IEEE Power Electronics Specialists Conference (PESC ’82), pp. 341–349, June 1982. Pelley, B. R., “Thyristor Phase-Controlled Converters and Cycloconverters,” Wiley, 1971. Rashid, M. “Power Electronics: Circuits, Devices, and Applications,” 2nd ed., Prentice Hall, 1993. Rippel, W. E., “Optimizing boost chopper charger design,” Proceedings of the Sixth National Solid-State Power Conversion Conference (POWERCON6), pp. D1-1–D1-20, 1979. Schaeffer, J., “Rectifier Circuits: Theory and Design,” Wiley, 1965.

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Source: STANDARD HANDBOOK OF ELECTRONIC ENGINEERING

CHAPTER 13.3

DC-DC CONVERTERS Philip T. Krein

INTRODUCTION Power conversion among different dc voltage and current levels is important in applications ranging from spacecraft and automobiles to personal computers and consumer products. Power electronics technology can be used to create a dc transformer function for power processing. Today, most dc power supplies rectify the incoming ac line, then use a dc-dc converter to provide a transformer function and produce the desired output voltages. Dc-dc designs often use input voltages near 170 V (the peak value of rectified 120-V ac) or 300–400 V (the peak values of 230, 240 V ac, and many three-phase sources). For direct dc inputs, 48-V sources and 28-V sources reflect practice in the telecommunications and aerospace industries. Universal input power supplies commonly handle rectified power from sources ranging between 85 and 270 V ac. There are a number of detailed treatments of dc-dc converters in the literature. The book by Severns and Bloom (1985) explores a wide range of topologies. Mitchell (1988) offers detailed analysis and extensive treatment of control issues. Chryssis (1989) compares topologies from a practical standpoint, and addresses many aspects associated with actual implementation. Middlebrook has published several exhaustive treatments of various topologies; one example (Middlebrook, 1989) addresses some key attributes of analysis and control. The discussion here follows the treatment in Krein (1998). More recently, Erickson and Maksimovich (2001) have detailed many operation and control aspects of modern dc-dc converters.

DIRECT DC-DC CONVERTERS The most general dc-dc conversion process is based on a switch matrix that interconnects two dc ports. The two dc ports need to have complementary characteristics, since Kirchhoff’s laws prohibit direct interconnection of unlike voltages or currents. A generic example, called a direct converter, is shown in Fig. 13.3.1a. A more complete version is shown in Fig. 13.3.1b, in which an inductor provides the characteristics of a current source. In the figure, only four switch combinations can be used without shorting the voltage source or opening the current source: Combination

Result

Close 1,1 and 2,2 Close 2,1 and 2,2 Close 1,1 and 1,2 Close 1,2 and 2,1

Vd Vd Vd Vd

= = = =

VIN 0 0 –VIN

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FIGURE 13.3.1 Dc voltage to dc current direct converter: (a) general arrangement; (b) circuit realization.

Switch action selects among –Vin, 0, and +Vin to provide a desired average output. The energy flow is controlled by operating the switches periodically, then adjusting the duty ratio to manipulate the average behavior. Duty-ratio control, or pulse width modulation, is the primary control method for most dc-dc power electronics. The switching frequency can be chosen somewhat arbitrarily with this method. Typical rates range from 50 kHz to 500 kHz for converters operating up to 200 W, and from 20 kHz to 100 kHz for converters operating up to 2 kW. In dc-dc circuits that use soft switching or resonant switching techniques, the switching frequency is usually adjusted to match internal circuit resonances. Switching functions q(t) can be defined for each switch in the converter. A switching function has the value 1 when the associated switch is on, and 0 when it is off. The converter voltage vd in Figure 13.3.1b can be written in terms of the switching functions in the compact form vd (t) = q1,1q2,2Vin – q1,2q2,1 Vin

(1)

For power flow in one direction, two switches suffice. The usual practice is to establish a common ground between the input and output, equivalent to permanently turning on switch 2,2 and turning off switch 1,2 in Fig. 13.3.1. This simplified circuit is shown in Fig. 13.3.2. The transistor is generic: a BJT, MOSFET, IGBT, or other fully controlled device can be used. The voltage vd(t) in this circuit becomes vd (t) = q1(t)Vin. Of interest is the dc or average value of the output, indicated by the angle brackets as 〈vout(t)〉. The inductor cannot sustain an average voltage in the periodic steady state, so the resistor voltage average value 〈vout(t)〉 = 〈vd(t)〉. The voltage vd(t) is a pulse train with period T, amplitude Vin, and an average value related to the duty ratio of the switching function. Therefore, 〈vd (t )〉 = 〈vout (t )〉 =

1 T

T

∫0 q1(t )Vin dt = D1Vin

(2)

where T is the switching period and D1 is the duty ratio of the transistor. (Typically, an average value in a dcdc converter is equivalent to substituting a switch duty ratio D for a switching function q.) If the L-R pair serves

FIGURE 13.3.2 converter).

Common-ground direct converter

(buck

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TABLE 13.3.1 Buck Converter Characteristics Characteristic

Value

Input–output relationships Device ratings Open-loop load regulation Open-loop line regulation Ripple

Vout = D1Vin, Iin = D1Iout Must handle Vin when off, and Iout when on. Load has no direct effect on output. No line regulation: line changes are reflected directly at the output. Feedback control is required. Governed by choice of inductor. Typically 50 mV peak–to–peak or 1 percent (whichever is higher) can be achieved.

as an effective low-pass filter, the output voltage will be a dc value Vout = 〈vd(t)〉. The circuit has the basic characteristics of a transformer, with the restriction that Vout ≤ Vin. The name buck converter is used to reflect this behavior. The buck converter, sometimes called a buck regulator, or a step-down converter, is the basis for many more sophisticated dc-dc converters. Some of its characteristics are summarized in Table 13.3.1. Load regulation is perfect in principle if the inductor maintains current flow. Line regulation requires closed-loop control. Although these relationships are based on ideal, lossless switches, the analysis process applies to more detailed circuits. The following example illustrates the approach. Example: Relationships in a dc-dc converter. The circuit of Fig. 13.3.3 shows a dc-dc buck converter with switch on-state voltage drops taken into account. What is the input–output voltage relationship? How much power is lost in the converter? To analyze the effect of switch voltages, KVL and KCL relations can be written in terms of switching functions. When averages are computed, variables such as inductor voltages and capacitor currents are eliminated since these elements cannot sustain dc voltage and current, respectively. Circuit laws require vd(t) = q1(t) (Vin – Vs1) – q2(t)Vs2, Vout = vd(t) – vL iin(t) = q1(t)IL, Iout(t) = IL – iC(t)

(3)

In this circuit, the inductor will force the diode to turn on whenever the transistor is off. This can be represented with the expression q1(t) + q2(t) = 1. When the average behavior is computed, the duty ratios must follow the relationship D1 + D2 = 1. The average value of vd(t) must match Vout, and the average input will be the duty ratio of switch 1 multiplied by the inductor current. These relationships reduce to

FIGURE 13.3.3 Buck converter with switch forward drop models.

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FIGURE 13.3.4 Buck converter waveforms.

Vout = D1(Vin – Vs1 + Vs2) – Vs2 〈iin(t)〉 = D1Iout Pin = 〈iin(t)Vin〉 = D1VinIout

(4)

Pout = VoutIout = D1(Vin – Vs1 + Vs2)Iout – Vs2Iout When the switch voltage drops Vs1 and Vs2 have similar values, the loss fraction is approximately the ratio of the diode drop to the output voltage. The primary design considerations are to choose an inductor and capacitor to meet requirements on output voltage ripple. The design process is simple if a small ripple assumption is used: since Vout is nearly constant, the voltage across the inductor will be a pulsed waveform at the switching frequency. The current iL(t) will exhibit triangular ripple. Some waveform samples appear in Fig. 13.3.4. The current swings over its full peakto-peak ripple during either the transistor on time or the diode on time. The example below takes advantage of the triangular variation to compute the expected ripple. Example: Buck converter analysis. A buck converter circuit with an R-L load and a switching frequency of 200 kHz is shown in Fig. 13.3.5. The transistor exhibits on-state drop of 0.5 V, while the diode has a 1 V forward drop. Determine the output ripple for 15 V input and 5 V output. From Eq. (5), the duty ratio of switch 1 should be 6/15.5 = 0.387. Switch 1 should be on for 1.94 ms, then off for 3.06 ms. At 5 V output, the inductor voltage is 9.5 V with switch 1 on and –6 V with switch 1 off. The inductor current has di/dt = (9.5 V)/(200 mH) = 47.5 kA/s when #1 is on and di/dt = –30 kA/s when #2 is on. During the on time of switch 1, the current increases (47500 A/s)·(1.93 ms) = 0.092 A. Here, the time constant L/R = 200 ms, which is 65 times the switch 2 on time. It would be expected that the current change is small and linear. The current change of 0.092 A produces an output voltage change of 0.092 V for this 1 Ω load. Figure 13.3.6 shows some of the important waveforms in idealized form. The output voltage is nearly constant, with Vout = 5 ± 0.046 V, consistent with the assumptions in the analysis. The output power is 25 W. The input average current is D1Iout = 0.387(5 A) = 1.94 A. The input power therefore is 29.0 W, and the efficiency is 86 percent. This neglects any energy consumed in the commutation process.

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FIGURE 13.3.5 Buck converter example.

More generally, the buck converter imposes Vin – Vout on the inductor while the transistor is on. The current derivative di/dt over a given time interval is the linear change ∆iL/∆t. For the on-time interval ∆t = D1T, the peak-to-peak ripple ∆iL is ∆iL =

(Vin − Vout ) D1T Vin (1 − D1 ) D1T = L L

(5)

If only inductive filtering is used, the output voltage ripple is the load resistance times the current ripple. If an output capacitor is added across the load resistor, its effect can be found by treating the inductor as an equivalent triangular current source, then solving for the output voltage. Assuming that the capacitor handles the full ripple current, it is straightforward to integrate the triangular current to compute the ripple voltage. The process is illustrated in Fig. 13.3.7. Voltage vC(t) will increase whenever iC(t) > 0. The voltage increase is given by ∆vC =

1 C

T /2

∫0

iC (t ) dt

(6)

The integral is the triangular area 1/2 (T/2)(∆iL/2), so ∆vC =

T ∆iL 8C

FIGURE 13.3.6 Buck converter inductor voltage and output current.

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FIGURE 13.3.7 Output ripple effect given the addition of capacitive filter.

This expression is accurate if the capacitor is large enough to provide significant voltage ripple reduction. An alternative direct dc-dc converter has a current source input and voltage source output. The relationships for this boost converter are dual to those of the buck circuit. The input current and output voltage act as fixed source values, while the input voltage and output current are determined by switch matrix action. For the common-ground version in Fig. 13.3.8b, the transistor and diode must operate in complement, so that q1 + q2 = 1 and D1 + D2 = 1. For ideal switches, q 1 + q2 = 1 vt(t) = q2Vout = (1 – q1)Vout iout = q2Iin = (1 – q1)Iin

(8)

〈vt〉 = D2Vout = (1 – D1)Vout 〈iout〉 = (1 – D1)Iin With these energy storage devices, notice that Vin = 〈vt〉 and Iout = 〈iout〉. The relationships can be written Vout =

1 V 1 − D1 in

and

I in =

1 I 1 − D1 out

(9)

The output voltage will be higher than the input. The boost converter uses an inductor at the input to create current-source behavior and a capacitor at the output to provide voltage source characteristics. The capacitor

FIGURE 13.3.8 Boost dc-dc converter: (a) general arrangement; (b) common-ground version.

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TABLE 13.3.2 Relationships for the Boost Converter Characteristic

Value

Input–output relationships Open-loop load regulation Open-loop line regulation Device ratings Input–output relationships with switch drops Inductor ripple relationship

Vout = Vin/(1 – D1), Iout = Iin(1 – D1) Load does not alter output Unregulated without control Must handle Vout when off or Iin when on Vout = (Vin – Vs2 – D1Vs1 + D1Vs2)/(1 – D1), Iout = Iin(1 – D1) ∆iL = VinD1T/L ( if ∆iL is small compared to the input current) ∆vC = IoutD1T/C

Capacitor ripple relationship

is exposed to a square-wave current signal, and produces a triangular ripple voltage in response. Table 13.3.2 provides a summary of relationships, based on ideal switches.

INDIRECT DC-DC CONVERTERS Cascade arrangements of buck and boost converters are used to avoid limitations on the magnitude of Vout. A buck-boost cascade is developed in Fig. 13.3.9. This is an example of an indirect converter because at no point in time does power flow directly from the input to the output. Some of the switches in the cascade are redundant, and can be removed. In fact, only two switches are needed in the final result, shown in Fig. 13.3.10. The current source, called a transfer current source, has been replaced by an inductor. The voltage across the inductor, vt, is Vin when switch 1 is on, and –Vout when switch 2 is on. The transfer current source value is Is. The inductor cannot sustain dc voltage drop, so 〈vt〉 = 0. The voltage relationships are q1 + q2 = 1 vt = q1Vin – q2Vout 〈vt〉 = 0 = D1Vin – D2Vout

FIGURE 13.3.9 Cascaded buck and boost converters. (From Krein (1998), copyright  1998 Oxford University Press, Inc., U.S.; used by permission.)

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FIGURE 13.3.10 Buck-boost converter.

The last part of Eq. (10) requires D1Vin = D2Vout in steady state. The switches must act in complement, so D1 + D2 = 1, and Vout =

D1 V 1 − D1 in

(11)

A summary of results is given in Table 13.3.3. The cascade process produces a negative voltage with respect to the input. This polarity reversal property is fundamental to the buck-boost converter. A boost-buck cascade also allows full output range with a polarity reversal. As in the buck-boost case, many of the switches are redundant in the basic cascade, and only two switches are required. The final circuit, with energy storage elements in place, as shown in Fig. 13.3.11. The center capacitor serves as a transfer voltage source. The transfer source must exhibit 〈it〉 = 0, since a capacitor cannot sustain dc current. Some of the major relationships are summarized in Table 13.3.4. In the literature, this arrangement is called a C´uk converter, after the developer who patented it in the mid-1970s (Middlebrook and C´uk, 1977). The transfer capacitor must be able to sustain a current equal to the sum of the input and output currents. The RMS capacitor current causes losses in the capacitor’s internal equivalent series resistance (ESR), so low ESR components are usually required. Figure 13.3.12 shows the single-ended primary inductor converter or SEPIC circuit (Massey and Snyder, 1977). This is a boost-buck-boost cascade. As in the preceding cases, the cascade arrangement can be simplified to require only two switches. The transfer sources Ct and Lt carry zero average power to be consistent with a capacitor and an inductor as the actual devices. The relationships are vin = q2(Vout + Vt1), iout = q2(Iin + It2), it1 = –q1It2 + q2Iin,

〈vin〉 = D2(Vout + Vt1) 〈iout〉 = D2(Iin + It2) 〈it1〉 = 0 = – D1It2 + D2Iin

TABLE 13.3.3 Buck-Boost Converter Relationships Characteristic

Value

Input–output voltage relationship

|Vout| = VinD1/1 – D1), Iin = |Iout| D1/(1 – D1), output is negative with respect to input Must handle |Vin| + |Vout| when off, |Iin| + |Iout| when on IL = |Iin| – |Iout| Perfect load regulation. No open-loop line regulation ∆iL = VinD1T/L ∆vC = |Iout| D1T/C Ideally, any negative voltage can be produced

Device ratings Inductor current Regulation Inductor ripple current Capacitor ripple voltage Output range

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FIGURE 13.3.11 Boost-buck converter.

vt2 = –q1Vt1 + q2Vout, q1 + q2 = 1,

〈vt2〉 = 0 = –D1Vt1 + D2Vout

D1 + D2 = 1

Some algebra will bring out the transfer source values and input-output ratios: It 2 =

D2 1 − D1 I in = I D1 D1 in

Vt1 =

D2 1 − D1 V = V D1 out D1 out

(13)

  1− D 1 − D1 1 〈vin 〉 = D2  Vout + Vout  = V D1 D1 out   This is the same input–output ratio as the buck-boost converter, except that there is no polarity reversal. These and related indirect converters provide opportunities for the use of more sophisticated magnetics such as coupled inductors. In the C´uk converter, for example, the input and output filter inductors are often coupled on a single core to cancel out part of the ripple current (Middlebrook and C´uk, 1981). In a buck-boost converter, the transfer source inductor can be split by providing a second winding. One winding can be used to inject energy into the inductor, while the other can be used to remove it. The two windings provide isolation. This arrangement is known as a flyback converter because diode turn-on occurs when the inductor output coil voltage “flies back” as the input switch turns off. An example is shown in Fig. 13.3.13. The flyback converter is one of the most common low-power dc-dc converters. It is functionally equivalent to the buck-boost converter. This is easy to see if the turns ratio between the windings is unity. The possibility of a nonunity turns ratio is a helpful extra feature of the flyback converter. Extreme step-downs, such as the 170-V to 5-V converter, often used in a dc power supply, can be supported with reasonable duty ratios by selecting an appropriate turns ratio. In general, flyback converters are designed to keep the nominal duty ratio close to 50 percent. This tends to minimize the energy storage requirements, and keeps the sensitivity to variation as TABLE 13.3.4 Relationships for Boost-Buck Converter Characteristic Input–output relationships Device ratings Regulation

Value |Vout| = D1Vin/(1 – D1), Iin = D1|Iout|(1 – D1) Must handle |Vin| + |Vout| when off. Must handle |Iin| + |Iout| when on Perfect load regulation, no line regulation

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FIGURE 13.3.12 The SEPIC converter. Two transfer sources permit any input-to-output ratio without polarity reversal.

FIGURE 13.3.13 Flyback converter.

low as possible. An additional advantage appears when several different dc supplies are needed: if it is possible to use two separate coils on the magnetic core of the inductor, it should be just as reasonable to use three, four, or even more coils. Each can have its own turns ratio with mutual isolation. This is the basic for many types of multi-output dc power supplies. One challenge with a flyback converter, as shown in Fig. 13.3.14, is the primary leakage inductance. During transistor turn-off, the leakage inductance energy must be removed. A capacitor or other snubber circuit is used to avoid damage to the active switch during turn-off.

FIGURE 13.3.14 Leakage inductance issue in flyback converter.

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FORWARD CONVERTERS Coupled inductors in indirect converters, unlike transformers, must store energy and carry a net dc current. Basic buck and boost circuits lack a transfer source, so a coupled inductor will not give them isolation properties. Instead, a buck or boost converter can be augmented with a transformer, inserted at a location with only ac waveforms. Circuits based on this technique are called forward converters. A transformer can be added either by providing a catch winding tertiary or other circuitry for flux resetting, or by using an ac link arrangement. With either alternative, the objective is to avoid saturation because of dc current. Figure 13.3.15 shows the catch-winding alternative in a buck converter. The tertiary allows the core flux to be reset while the transistor is off. Operation is as follows: the transistor carries the primary current i1 and also the magnetizing current im when it is on. Voltage Vin is imposed on the primary, and the flux increases. When the transistor turns off, the magnetizing inductance will maintain the current flow in coil 1, such that i1 = –im. The diode D3 permits current i3 = im(N1/N3) to flow. The tertiary voltage v3 flies back to –Vin, resetting the flux. If N1 = N3, the duty ratio of switch 1 must not exceed 50 percent so that there will be enough time to bring the flux down sufficiently. If it is desired to reach a higher duty ratio, the ratio N1/N3 must be at least D1/(1 – D1). With a catch winding, the primary carries a voltage v1 = –N1/N3 after the transistor turns off. The transistor must be able to block Vin(1 + N1/N3) to support this voltage. For power supplies, this can lead to extreme ratings. For example, an off-line supply designed for 350 Vdc input with N1/N3 = 1.5 to support duty ratios up to 60 percent requires a transistor rating of about 1000 V. This extreme voltage rating is an important drawback of the catch-winding approach. The secondary voltage v2 in this converter is positive whenever the transistor is on. The diode D1 will exhibit the same switching function as the transistor, and the voltage across D2 will be just like the diode voltage of a buck converter except for the turns ratio. The output and its average value will be vout = q1Vin

N2 N , 〈vout 〉 = D1Vin 2 N1 N1

(14)

so this forward converter is termed a buck-derived circuit. The ac link configuration comprises an inverter-rectifier cascade, such as the buck-derived half-bridge converter in Fig. 13.3.16. With adjustment of duty ratio, a waveform such as that shown in Fig. 13.3.17a is typically used as the inverter output. The signal has no dc component, and therefore a transformer can be used. Once full-wave rectification is performed, the result will be the square wave of Fig. 13.3.17b. The average output is 〈vout〉 = 2aDVin

FIGURE 13.3.15 Catch-winding forward converter. (From Krein (1998), copyright  1998 Oxford University Press. Inc., U.S.; used by permission.)

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FIGURE 13.3.16 Half-bridge forward converter.

reflecting the fact that there are two output pulses during each switching period. No switch on the inverter side will be on more than 50 percent of each cycle, and the transistors block only Vin when off. Four other forward converter topologies are shown in Fig. 13.3.18. The full bridge circuit in particular has been used successfully for power levels up to a few kilowatts. The others avoid the complexity of four active switches, although possibly with a penalty. For example, the push-pull converter in the figure has the important advantage that both switch gate drives share a common reference node with Vin. Its drawback is that the transistor must block 2Vin when off, because of an autotransformer effect of the center-tapped primary. The topologies are compared in Table 13.3.5. The full-bridge converter perhaps offers the most straightforward operation. The switches always provide a path for magnetizing and leakage inductance currents, and circuit behavior is affected little by these extra inductances. In other circuits, these inductances are a significant complicating factor. For example, magnetizing inductance can turn on the primary-side diodes in a half-bridge converter, altering the operation of duty

FIGURE 13.3.17 Typical waveforms in inverter-rectifier cascade. (From Krein (1998), copyright  1998 Oxford University Press, Inc., New York, U.S.; used by permission.)

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FIGURE 13.3.18 Four alternative forward converter topologies.

DC-DC CONVERTERS

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TABLE 13.3.5 Characteristics of Common Buck-Derived Forward Converters Forward Converter Topology

Transistor OffState Voltage

Full-bridge

Vin

Half-bridge

Vin

Single-ended

Vin

Push-pull

2Vin

Clamp

Vin + Vz

Flux Behavior Full variation from –fmax to +fmax Full variation

Variation only between 0 and +fmax Full variation

Variation only between 0 and +fmax

Comments Preferred for high power levels by many designers Capacitive divider avoids any dc offset in flux. Preferred at moderate power levels by many designers Less effective use of core, but only two transistors Common-ground gate drives. Timing errors can bias the flux and drive the core into saturation Similar to catch winding circuit, except that energy in magnetizing inductance is lost

ratio control. Leakage inductance is a problem in the push-pull circuit, particularly since both transistors must be off to establish the portion of time when no energy is transferred from input to output. Snubbers are necessary parts of this converter. These issues are discussed at length in at least one text (Kassakian, Schlecht, and Verghese, 1991). The boost converter also supports forward converter designs. A boost-derived push-pull forward converter is shown in Fig. 13.3.19. Like the boost converter, this circuit has an output higher than the input but now with a turns ratio. The operation differs from a buck-derived converter in an important way: both transistors must turn on to establish the time interval when no energy flows from input to output. In effect, each transistor has a minimum duty ratio of 50 percent, and control is provided by allowing the switching functions to overlap. The output duty ratio associated with each diode becomes 1 – D, where D is the duty ratio of one of the transistors over a full switching period. The output voltage is Vout =

N 2 Vin N1 2(1 − D)

The other forward converter arrangements also have boost-derived counterparts.

FIGURE 13.3.19 Boost-derived push-pull converter.

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In each of the converters discussed so far, it has been assumed that energy storage components have been sufficiently large to be treated as approximate current or voltage sources. This is not always the case. If values of inductance or capacitance are chosen below a certain value, the current or voltage, respectively, will reach zero when energy is extracted. This creates discontinuous mode behavior in a dc-dc converter. The values of L and C sufficient to ensure that this does not occur are termed critical inductance and critical capacitance, respectively. The usual effect of subcritical inductance is that all switches on the converter turn off together for a time. Subcritical capacitance in a boost-buck converter creates times when all switches are on together. In discontinuous mode, converter load regulation degrades, and closed-loop output control becomes essential. However, discontinuous mode can be helpful in certain situations. It implies fast response times since there is no extra time required for energy buildup. It provides an additional degree of freedom—the extra configuration when all switches are off or on—for control purposes. Discontinuous mode behavior can be analyzed through the techniques of this subsection, with the additional constraint that all energy in the storage element is removed during each switching period. The literature (Mitchell, 1988; Mohan, Undeland, and Robbins, 1995) provides a detailed analysis, including computation of critical inductance and capacitance.

RESONANT DC-DC CONVERSION TECHNIQUES The dc-dc converters examined thus far operate their switches in a square-wave or hard-switched mode. Switch action is strictly a function of time. Since switch action requires finite time, hard-switched operation produces significant switching loss. Resonant techniques for soft switching attempt to maintain voltages or currents at low values during switch commutation, thereby reducing losses. Zero-current switching (ZCS) or zero-voltage switching (ZVS) can be performed in dc converters by establishing resonant combinations. Resonant approaches for soft switching are discussed extensively in Kazimierczuk and Czarkowski (1995). The SCR supports natural zero-current switching, since turn-off corresponds to a current zero crossing. A basic arrangement, given in Fig. 13.3.20, is often used as the basis for soft switching in transistor-based dc-dc converters as well as for inverters. Starting from rest, the top SCR is triggered. This applies a step dc voltage 1 to the RLC set. If the quality factor of the RLC set is more than 2 , the current is underdamped, and will oscillate. When the current swings back to zero, the SCR will turn off with low loss. After that point, the lower SCR can be triggered for the negative half-cycle. The SCR inverter represents a series resonant switch configuration and provides ZCS action. However, SCRs are not appropriate for high-frequency dc-dc conversion because of their long switching times and control limitations. The circuit of Fig. 13.3.21 shows an interesting arrangement for dc-dc conversion, similar to the SCR circuit, but based on a fast MOSFET. In this case, an inductor and a capacitor have been added to a standard buck converter to alter the transistor action. Circuit behavior will depend on the relative values.

FIGURE 13.3.20 SCR soft-switching inverter. (From Krein (1998), copyright  1998 Oxford University Press, Inc., U.S.; used by permission.)

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FIGURE 13.3.21 A soft-switching arrangement for a buck converter.

If the capacitor Ct is large, its behavior during the transistor’s off interval will introduce opportunities for resonant switching. In this case, the basic circuit action is as follows: • When the transistor turns off, the input voltage excites the pair Lin and Ct. The input inductor current begins to oscillate with the capacitor voltage. The capacitor can be used to keep the transistor voltage low as it turns off. • The capacitor voltage swings well above Vin, and the main output diode turns on.

FIGURE 13.3.22 Input current and diode voltage in a resonant buck converter. (From Krein (1998), copyright  1998 Oxford University Press. Inc., U.S.; used by permission.)

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• The capacitor voltage swings back down. There might be an opportunity for zero-voltage turn-on of the transistor when the capacitor voltage swings back to zero. This represents ZVS action. When the transistor is on and the main diode is off, the input inductor forms a resonant pair with Cd. This pair provides an opportunity for zero-current switching at transistor turn-off, very much like the zero-current switch action in the SCR inverter. The action is as follows in this case: • When the transistor is turned on, Lin limits the rate of rise of current. The diode remains on initially, and the current builds up linearly because Vin appears across the inductor. • When the current arises to the level Iout, the diode shuts off and the transistor carries the full current. The pair Lin and Cd form a resonant LC pair, and the current oscillates. • The current rises above Iout because of resonant action, but then swings back down toward the origin. • When the current swings negative, the transistor’s reverse body diode begins to conduct, and the gate signal can be shut off. When the current tries to swing positive again, the switch will turn off. • The transistor on-time is determined by the resonant frequency and the average output current. Figure 13.3.22 shows the input current and main diode voltage for a choice of parameters that gives ZCS action in the circuit of Fig. 13.3.21. Resonant action changes the basic control characteristics substantially. The gate control in both ZVS and ZCS circuits must be properly synchronized to match the desired resonance characteristics. This means that pulse-width modulation is not a useful control option. Instead, resonant dc converters are adjusted by changing the switching frequency—in effect setting the portion of time during which resonant action is permitted. In a ZCS circuit, for example, the average output voltage can be reduced by dropping the gate pulse frequency. In general, ZCS or ZVS action is very beneficial for loss reduction. Lower switching losses permit higher switching frequencies, which in turn allow smaller energy storage elements to be used for converter design. Without resonant action, it is difficult to operate a dc-dc converter above perhaps 1 MHz. Resonant designs have been tested to frequencies as high as 10 MHz (Tabisz, Gradzki, and Lee, 1989). Designs even up to 100 MHz have been considered for aerospace applications. In principle, resonance provides size reduction of more than an order of magnitude compared to the best nonresonant designs. However, there is one important drawback: The oscillatory behavior substantially increases the on-state currents and off-state voltages that a switch must handle. Under some circumstances, the switching loss improvements of resonance are offset by the extra onstate losses caused by current overshoot. There are magnetic techniques to help mitigate this issue (Erickson, Hernandez, and Witulski, 1989), but they add complexity to the overall conversion system. The switching loss trade-offs tend to favor resonant designs at relatively low voltage and current levels. More sophisticated resonant design approaches, based on Class E methods (Kasimierczuk and Czarkowski, 1995), can further reduce losses. Example: Input-output relationships in a ZCS dc-dc converter.

Let us explore ZCS switching in a dc-dc converter and analyze the results. The approach in this example follows an analysis in Kassakian, Schlecht, and Verghese (1991). The circuit in Fig. 13.3.21 is the focus, with Ct selected to be small and Lout selected to be large. Parameters are Vin = 24 V, Ct = 200 pF, Lin = 2 mH, Cd = 0.5 mF, Lout = 50 mH, and a 10-Ω load in parallel with an 8 mF filter capacitor. The FET is supplied with a 5-ms pulse with a period of 12 ms. In periodic steady-state operation, the inductor Lout will carry a substantial current. The output time constant is long enough to ensure that the current will not change very much. As a result, the output inductor can be modelled as a current source, with value Iout. The diode provides a current path while the transistor is off. Consider the moment at which the transistor turns on. Since the current in Lin cannot change instantly, the diode remains on for a time while the input current rises. We have iin (t ) =

Vin t Lin

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until the current iin reaches the value Iout. At the moment ton = IoutLin/Vin, the diode current reaches zero and the diode turns off. The input circuit becomes an undamped resonant tank determined by Lin and Cd. For Cd, circuit laws require .. Vin – vCd(t) – LinCdvCd(t) = 0, vCd(ton) = 0, vCd(ton) = 0 (18) This has the solution

1 vCd (t) = Vin {1 – cos[wr(t – ton)]},

where wr =

(19)

LinC d

For the input current, the corresponding solution is iin (t ) = I out +

Vin sin[ω r (t − ton )] , Zc

where Z c =

Lin Cd

(20)

With the selected parameters, Zc = 2 Ω and wr = 106 rad/s, corresponding to about 160 kHz. The inductor current will cross zero again a bit more than one half-period after ton. In this example, Iout might be on the order of 1 A, so ton corresponds to only about 83 ns. The half-period of the resonant ring signal will be about 3.2 ms. Therefore, a 5-ms gate pulse should ensure that the transistor remains on until the zero crossing point. When the current crosses zero, the FET turns off, but its reverse body diode turns on and maintains negative flow for approximately another half-cycle, at approximately t = 6.4 ms. Since the gate signal is removed between the zero crossings, the FET and its diode will both turn off at the second zero crossing. Figure 13.3.22 is a SPICE simulation for these circuit parameters. The ZCS action should be clear: since the gate pulse is removed while the FET’s reverse body diode is active, the complete FET will shut off at a rising current zero crossing. The shut-off point toff is determined by 0 = I out +

Vin sin[ω r (toff − ton )] , Zc

 −I Z  ω r (toff − ton ) = sin −1  out   Vin 

(21)

In solving this expression, it is crucial to be careful about the quadrant for sin –1(x). The rising zero crossing is sought. Once the FET is off, capacitor Cd carries the full current Iout. The voltage vCd(t) will fall quickly with slope –Iout/Cd until the diode becomes forward biased and turns on. The voltage vCd(t) is of special interest, since the output is Vout = 〈vCd(t)〉. The average is 〈vCd 〉 =

t(diodeon)  toff 1 1 V ( − cos[ ω ( t − t )] dt + ∫ r on T  t∫ in t on

off

vCd (toff ) −

 I out t dt   Cd 

(22)

The second integral is a triangular area 1/2vCd(toff)2(Cd /Iout). For Iout ≈ 1 A, the time toff – ton can be found from Eq. (21) to be 6.20 ms. The value vCd(toff) is therefore 83 mV. The average value is Vout = 12.6 V. This corresponds to Iout = 1.26 A. In this example, the average value comes out very close to Vout =

4.8 × 10 −6 π T

(23)

for T > 6.4 ms. The solution comes out quite evenly because the current zero-crossing times nearly match those of the resonant sine wave. In the ZCS circuit, the on time of the transistor is determined by resonant action, provided the gate pulse turns off during a time window when reverse current is flowing through the device’s diode. The gate pulses need to have fixed duration to tune the circuit, but the pulse period can be altered to adjust the output voltage.

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BIBLIOGRAPHY Baliga, B. J., “Modern Power Devices,” Wiley, 1987. Baliga, B. J., “Power Semiconductor Devices,” PWS, 1966. Chryssis, G. C., “High-Frequency Switching Power Supplies,” McGraw-Hill, 1989. Erickson, R. W., A. F. Hernandez, and A. F. Witulski, “A nonlinear resonant switch,” IEEE Trans. Power Electronics, Vol. 4, No. 2, pp. 242–252, 1989. Erikson, R. W., and D. Maksimovich, “Fundamentals of Power Electronics,” 2nd ed., Kluwer Academic Publishers, 2001. Hower, P. L., “Power semiconductor devices: An overview,” IEEE Proc., Vol. 82, pp. 1194–1214, 1994. Hudgins, J. L., “A review of modern power semiconductor devices,” Microelect. J., Vol. 24, pp. 41–54, 1993. Kassakian, J. G., M. F. Schlecht, and G. C. Verghese, “Principles of Power Electronics,” Addison-Wesley, 1991. Kazimierczuk, M. K., and D. Czarkowski, “Resonant Power Converters.” Wiley, 1995. Krein, P. T., “Elements of Power Electronics,” Oxford University Press, 1998. Portions used by permission. Massey, R. P., and E. C. Snyder, “High voltage single-ended dc-dc converter,” Record, IEEE Power Electronics Specialists Conf., pp. 156–159, 1977. Middlebrook, R. D., “Modeling current-programmed buck and boost regulators,” IEEE Trans. Power Electronics, Vol. 4, No. 1, pp. 36–52, 1989. Middlebrook, R. D., and S. C´ uk, “A new optimum topology switching dc-to-dc converter,” Record, IEEE Power Electronics Specialists Conf., pp. 160–179, 1977. Mitchell, D. M., “Dc-Dc Switching Regulator Analysis,” McGraw-Hill, 1988. Mohan, N., T. M. Undeland, and W. P. Robbins, “Power Electronics: Converters, Applications and Design,” 2nd ed., Wiley, 1995. Severns, R. P., and E. J. Bloom, “Modern dc-to-dc Switchmode Power Converter Circuits,” Van Nostrand Reinhold, 1985. Tabisz, W. A., P. M. Gradzki, and F. C. Y. Lee, “Zero-voltage-switched quasi-resonant buck and flyback converters—experimental results at 10 MHz,” IEEE Trans. Power Electronics, Vol. 4, pp. 194–204, 1989. Vithayathil, J., “Power Electronics: Principles and Applications,” McGraw-Hill, 1995.

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Source: STANDARD HANDBOOK OF ELECTRONIC ENGINEERING

CHAPTER 13.4

INVERTERS David A. Torrey

INTRODUCTION Inverters are used to convert dc into ac. This is accomplished through alternating application of the source to the load, achieved through proper use of controllable switches. This section reviews the basic principles of inverter circuits and their control. Four major applications of inverter circuits are also reviewed. Both voltage- and current-source inverters are used in practice. The trend, however, is to use voltage-source inverters for the vast majority of applications. Current-source inverters are still used at extremely high power levels, though voltage-source inverters are gradually filling even these applications. Because of the dominance of voltage-source inverters, this section focuses exclusively on this type of inverter. There are many issues involved in the design of an inverter. The more prominent issues involve the interactions among the power circuit, the source, the load, and the control. Other subtle issues involve the control of parasitics and the protection of controllable switches through the use of snubber and clamp circuits, and the juxtaposition of controller speed with the desire for increased switching frequency, while maintaining high efficiency. The technical literature contains abundant information on inverters. A set of technical papers is found in Bose (1992). In addition to technical papers, most power electronics textbooks have a section on inverters (Mohan, Undeland, and Robbins, 1995; Kassakian, Schlecht, and Verghese, 1991; Krein, 1998).

AN INVERTER PHASE-LEG An inverter phase-leg is shown in Fig. 13.4.1. It comprises two fully controllable switches and two diodes in antiparallel to the controllable switches. This phase-leg is placed in parallel with a voltage source. The center of the phase-leg is taken to the load. The basic circuit shown in Fig. 13.4.1 is usually augmented with a snubber circuit or clamp to shape the switching locus of the controllable switches. Insulated gate bipolar transistors (IGBTs) are shown as the controllable switches in Fig. 13.4.1. While the IGBT finds significant application in inverters, any fully controllable device, such as an FET or a GTO, may be used in its place; see Chapter 13.1 for a description of the fully controllable switches that can be used in an inverter. Basic Principles. In the phase-leg of Fig. 13.4.1, there are two restrictions on the use of the controllable switches. First, at most one controllable switch may be conducting at any time. The dc supply is shorted if both switches are conducting. In practice, one switch is turned off before the other is turned on. This blanking time, also known as dead time, compensates for the tendency of power devices to turn on faster than they turn off. Second, at least one controllable switch (or an associated diode) must be on at all times if the load current is to be nonzero. If the upper switch is conducting, the load is connected to the positive side of Vdc. If the lower switch is conducting, the load is connected to the negative side of Vdc. It follows that the voltage applied to the load will, on 13.50 Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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average, fall somewhere between 0 and Vdc. When the phase-leg of Fig. 13.4.1 is used with one or more additional phase legs, the load voltage can be made to alternate. The details of how it alternates is the responsibility of the controller. The peak voltage seen by each switch is the total dc voltage across the phase-leg. This is determined by recognizing that one of the two switches is always conducting. The peak current that must be supported by each switch is the peak current of the load. Under balanced control of the two switches, each switch must support the same peak current; each diode must support the same peak current as the switches. In an effort to improve the efficiency and spectral performance of inverters, the use of inverters with a FIGURE 13.4.1 An inverter phase-leg. resonant dc link has been reported in the technical literature (Divan, 1989; Murai and Lipo, 1988). Through periodic resonance of the dc bus voltage to zero, or the dc bus current to zero, the inverter switches can change states in synchronism with these zero crossings in order to reduce the switching losses in the power devices. Figure 13.4.2 shows a schematic for the basic resonant dc link converter (Divan, 1989). The resonance of Lr and Cr forces the bus voltage (the voltage applied to the controllable switches) to swing between zero and 2Vdc. The inverter switches change states when the voltage across Cr is zero. It is often necessary to hold the bus voltage at zero for a brief time to ensure that sufficient energy has been put into Lr to force resonance back to zero voltage across Cr. The bus can be clamped at zero voltage by turning on both switches in an inverter phaseleg. One drawback of the resonant dc link is the increased voltage or current imposed on the power devices. Auxiliary clamp circuits have been implemented to minimize this drawback (Divan and Skibinski, 1989; He and Mohan, 1991; Simonelli and Torrey, 1994). The control of a resonant link inverter is complicated by the simultaneous need to manage energy flow to the load while managing energy in the resonant link. Snubber Circuits and Clamps. Snubber circuits are used to control the voltage across and the current through a controllable switch as that device is turning on or off. A complete snubber will typically limit the rate of rise in current as the device is turning on and limit the rate of rise in voltage as the device is turning off. Additional circuit components are used to accomplish this shaping of the switching locus. Figure 13.4.3 shows three snubber circuits that are used with inverter legs, one of which has auxiliary switches (McMurray, 1987; McMurray, 1989;

FIGURE 13.4.2 A basic resonant dc link inverter system.

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FIGURE 13.4.3 A number of snubber circuits for an inverter phase-leg: (a) a McMurray snubber (McMurray, 1987); (b) a resonant snubber with auxilliary switches (McMurray, 1989); and (c) the Undeland snubber (Undeland, 1976).

Undeland, 1976). Snubber circuits become increasingly important as the power rating of the inverter increases, where the additional cost of small auxiliary devices is justified by improved efficiency and spectral performance. Clamps differ from snubbers in that a clamp is used only to limit a switch variable, usually the voltage, to some maximum value. The clamp does not dictate how quickly this maximum value is attained. Figure 13.4.4 shows three clamp circuits that are commonly used with inverter legs. The clamp circuits generally become more complex with increasing power level. Interfacing to Controllable Switches. The interface to the controllable switches within the inverter phase-leg of Fig. 13.4.2 requires careful attention. Power semiconductor devices are generally controlled by manipulating the control terminal, usually relative to one of the power terminals. For example, Figure 13.4.2 shows insulated gate bipolar transistors (IGBTs) as the controllable switches. These devices are turned on and off through the voltage level applied to the gate relative to the emitter. Because the emitter of the upper IGBT moves around, the control of the upper IGBT must accommodate this movement. The emitter voltage of the upper IGBT moves from the positive side of the dc bus when the IGBT is conducting to the negative side of the dc bus when Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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FIGURE 13.4.4 Clamp circuits for an inverter phase-leg: (a) low power (~ 50 A); (b) medium power (~ 200 A); and (c) high power (~300 A).

the lower IGBT is conducting. The circuit responsible for turning the power semiconductor on and off as commanded by a controller is usually known as a gate-drive circuit. Some gate-drive circuits incorporate protection mechanisms for over current or over temperature. There are a number of approaches that are used to control the semiconductor devices within the inverter. The choice among these approaches is often dictated by the power levels involved, the switching frequency supported by the switches, and the preference of the designer, among others. It is possible to purchase highvoltage integrated circuits (HVICs) that perform the level shifting necessary to take a logic signal referenced to the negative side of the dc bus and control the upper controllable switch in the phase-leg. This approach is generally limited to applications where the controllable switches do not require a negative bias to hold them in the blocking state. High-frequency applications may use transformer-coupled gate drives that are insensitive to the common-mode voltage between the primary and secondary. This approach runs into problems at lower frequencies because the size of the transformer core begins to get large. High-power applications may use optocouplers to optically couple the control information to the gate drive, where the gate drive is supported by an isolated power supply. Often the power supply is the dominant factor in the overall cost of the gate drive. Figure 13.4.5a shows how an HVIC is interfaced to a phase-leg. The capacitors are used as local power supplies for the upper and lower gate drives. In this implementation, the upper capacitor is charged through the diode while the lower switch is conducting. Figure 13.4.5b shows a transformer-coupled gate drive for a highfrequency application (Internatonal Rectifier). It is important to design a mechanism for resetting the core in Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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FIGURE 13.4.5 Three common approaches to interfacing to controllable switches: (a) the use of an HVIC; (b) the use of transformer coupling; and (c) the use of an optocoupler.

a transformer-coupled gate drive. In Fig. 13.4.5b, the core is reset by driving the transformer primary with a bipolar voltage that provides sufficient volt-seconds to drive the transformer into saturation. This need for core reset may place unacceptable limitations on the duty ratio of the switches for some applications. Figure 13.4.5c shows the use of an optocoupler to provide isolation of the control signal going to the gate drive. The isolated power supply required to support the use of the optocoupler is not shown.

SINGLE-PHASE INVERTERS There are two ways to form a single-phase inverter. The first way is shown in Fig. 13.4.6, where the phase leg of Fig. 13.4.1 is used to control the voltage applied to one side of the load. The other side of the load is connected to the common node of two voltage sources. The half-bridge inverter of Fig. 13.4.6 applies positive voltage to the load when the upper switch is conducting and negative voltage to the load when the lower switch is conducting. It is not possible for the half-bridge inverter to apply zero voltage to the load.

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FIGURE 13.4.6 A single-phase inverter using one phase-leg and two dc voltage sources.

A single-phase inverter is also formed by placing the load between two inverter phase-legs, as shown in Fig. 13.4.7. This circuit is often referred to as a full- or H-bridge inverter. Through appropriate control of the inverter switches, positive, negative, and zero voltage can be applied to the load. The zero voltage state is achieved by having both upper switches, or both lower switches, conducting at the same time. Note that this state requires one switch and one diode to be supporting the load current.

THREE-PHASE INVERTERS A three-phase inverter is used to support both ∆- and Y-connected three-phase loads. The three-phase inverter topology can be derived by using three single-phase full-bridge inverters, with each inverter supporting one phase of the load. Upon careful examination of the resulting connection of the 12 controllable switches with the load, it is seen that there are six redundant switches because phase-legs are connected in parallel. Elimination of the six redundant switches yields the topology shown in Fig. 13.4.8. There are six switches in the three-phase inverter topology of Fig. 13.4.8. Considering all combinations of the switch states, there are seven possible voltages that may be applied to the load; the cases of all three upper switches being closed and all three lower switches being closed are functionally indistinguishable. The controller is responsible for applying the appropriate voltage to the load according to the method used for synthesizing the output voltage.

FIGURE 13.4.7 A single-phase inverter using two phase-legs and one dc voltage source.

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FIGURE 13.4.8 The three-phase inverter topology.

MULTILEVEL INVERTERS The three-phase inverter of Fig. 13.4.8 applies one of two voltages to each output load terminal. The output voltage is Vdc when the upper switch is conducting, and it is zero when the lower switch is conducting. Accordingly, this inverter could be called a two-level inverter. Multilevel inverters are based on extending this concept and are becoming the inverter of choice for higher-voltage and higher-power applications. The discussion here focuses on a three-level inverter; extensions to five or more levels can be found in the technical literature (Lai and Peng, 1996; Peng, 2001). Among their advantages, multilevel inverters allow the synthesis of voltage waveforms that have a lower harmonic content than a two-level inverter for the same switching frequency. This is because each output terminal is switched among at least three voltages, not just two. In addition, the input dc bus voltage can be higher because multiple devices are connected in series to support the full bus voltage. Figure 13.4.9 shows one phase-leg of a three-level inverter. In the three-level inverter the dc bus is partitioned into two equal levels of Vdc/2. The four controllable switches with antiparallel diodes, S1 through S4, are connected in series to form a phase-leg. In addition, two steering diodes, D5 and D6, are used to support current flow to and from the midpoint of the dc bus. Additional phase-legs would be connected in parallel across the full dc bus. Operation of four switches is used to connect the load output terminal to either Vdc, Vdc/2, or zero. Switches S1 and S2 are used to connect the load to Vdc, switches S2 and S3 are used to connect the load to Vdc/2, and switches S3 and S4 are used to connect the load to zero. While switches S1 and S2 are conducting, diode D6 ensures that the voltage across switch S4 does not exceed Vdc/2. Similarly, when switches S3 and S4 are conducting, diode D5 ensures that the voltage across switch S1 does not exceed Vdc/2. While switches S2 and S3 are conducting, the voltage across both S1 and S4 is clamped at Vdc/2; diode D5 and switch S2 support positive load current, while diode D6 and switch S3 support negative load current. A three-phase, three-level inverter provides substantially increased flexibility for voltage synthesis over the conventional three-phase inverter of Fig. 13.4.8. The three-phase inverter of Fig. 13.4.8 offers eight switch combinations that support seven different voltage combinations among the three output terminals. A threephase, three-level inverter offers 27 switch combinations, supporting 19 different voltage combinations among the three output terminals. Further, the increased redundancy of certain voltages provides additional degrees of freedom in designing the voltage synthesis algorithm. These additional degrees of freedom could, for example, be used to minimize the common mode voltage between the three outputs. Issues within the design and control of the multilevel inverter include the dynamic balancing of the voltages within each level of the dc bus and the switching patterns needed to best synthesize the desired output voltage. One would expect that symmetric operation of the phase-leg should be sufficient for maintaining balanced voltages across each level of the dc bus. The variation in capacitor values, however, will cause the midpoint of the

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FIGURE 13.4.9 A phase-leg for a three-level inverter.

dc bus to move to a voltage other than Vdc/2 for symmetric load currents. This shift in voltage will have repercussions on the synthesis of the output voltage.

VOLTAGE WAVEFORM SYNTHESIS TECHNIQUES There are three principal ways to synthesize the output voltage waveform in an inverter: harmonic elimination, harmonic cancellation, and pulse-width modulation. The synthesis technique that is applied is generally driven by consideration of the required output quality, the inverter power rating (which is closely tied to the speed of the controllable switches), the computational power of the available controller, and the acceptable cost of the inverter. This subsection reviews some of the common techniques used to synthesize the inverter output voltage.

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FIGURE 13.4.10 Elimination of the third harmonic.

Harmonic Elimination. Harmonic elimination implies that the output waveform shape is controlled to be free of specific harmonics through the selection of switch transitions (Patel and Hoft, 1973; Patel and Hoft, 1974). That is, the switches are controlled so that one or more harmonics are never generated. This is often accomplished by notching the output waveform. Examples of harmonic elimination are shown in Figs. 13.4.10 and 13.4.11, which respectively show the elimination of only the third harmonic and simultaneous elimination of the third and fifth harmonics from the output of a single-phase inverter. As suggested by Figs. 13.4.10 and 13.4.11, additional switch transitions must be inserted in the output waveform for each harmonic that is to be eliminated. As the number of notches gets very large, the output voltage waveform begins to resemble something which could be produced by pulse-width modulation. Harmonic

FIGURE 13.4.11 Simultaneous elimination of the third and fifth harmonics: (a) shows the fifth harmonic superimposed on the waveform of Fig. 13.4.10: (b) shows the switch transitions introduced to eliminate the fifth harmonic without reintroducing the third harmonic.

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FIGURE 13.4.12 The superposition of two waveforms to cancel the third harmonic.

elimination is sometimes referred to as programmed PWM because the switching angles of the output voltage are programmed according to the intended harmonic content (Enjeti, Ziogas, and Lindsay, 1985). Harmonic Cancellation. Harmonic cancellation uses the superposition of two or more waveforms to cancel undesired harmonics (Kassakian, Schlecht, and Verghese, 1991). Figure 13.4.12 shows how two waveforms that contain the third harmonic may be phase-shifted and superimposed in order to create a waveform that is free of the third harmonic. The circuit of Fig. 13.4.13 can be used to synthesize the waveform of Fig. 13.4.12. By combining harmonic cancellation and harmonic elimination, it is possible to create relatively high-quality voltage waveforms. This quality comes at the expense of a more complicated circuit. This additional complexity may be warranted depending on the power level and the specified quality. Pulse-Width Modulation. Pulse-width modulation (PWM) is a method of voltage synthesis through which high-frequency voltage pulses are applied to the inverter load (Holtz, 1994). The width of the pulses are made to vary at the desired frequency of the output voltage. Successful application of PWM generally involves a wide frequency separation between the carrier frequency and the modulation frequency. This frequency separation moves the distortion in the output voltage to high frequencies, thereby simplifying the required filtering. This subsection reviews two of the more common techniques used for synthesizing voltage waveforms using modulation.

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FIGURE 13.4.13 A circuit capable of synthesizing the waveforms of Fig. 13.4.12.

Sinusoidal PWM. Sinusoidal PWM implies that the pulse widths of the output voltage are distributed sinusoidally. The pulse widths are generally determined by comparing a sinusoidal reference waveform with a triangular waveform. The sinusoidal waveform sets the modulation (output) frequency and the triangular waveform sets the switching frequency. Sinusoidal PWM is routinely applied to single- and three-phase inverters. In a single-phase inverter, the implementation of sinusoidal PWM depends on whether or not both phaselegs are operated at high frequency. Referring to Fig. 13.4.7, we see that it is not necessary for both phase-legs to operate at high frequency. We could, for example, operate switches S1 and S2 at high frequency to control the shape of the voltage, while switches S3 and S4 are operated at the frequency of the reference sinusoid to dictate the polarity of the output voltage. One advantage of this approach is that the inverter is more efficient because only two of the switches are operated at high frequency. Figure 13.4.14 shows how the sinusoidal pulse widths are created by a comparator and a unipolar triangular carrier (Kassakian, Schlecht, and Verghese, 1991). An alternative approach is to use switches S2 and S4 to control the polarity of the output voltage. While switch S4 is conducting, switches S1 and S2 are used to control the shape of the voltage. Similarly, switches S3 and S4 are used to control the shape of the voltage, while switch S2 is conducting. This approach tends to equalize the stress on the two phase-legs, and can simplify the control logic necessary to implement the PWM.

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FIGURE 13.4.14 The generation of sinusoidally distributed pulse widths using a unipolar triangular carrier.

A second way of implementing sinusoidal PWM in a single-phase inverter is to operate both phase-legs at high frequency (Vithayathil, 1995). This method of control gives the same output voltage waveform as the highfrequency/low-frequency approach. The basic difference in control structures between the two is that the first method uses a unipolar triangular carrier, while the second way uses a bipolar triangular carrier. Figure 13.4.15 shows how the bipolar triangular carrier is used to create the sinusoidally distributed pulse widths. Space-Vector PWM. Space-vector modulation is a technique that is becoming the standard method for controlling the output voltage of three-phase inverters. The technique bears great similarity to the field-oriented control techniques which are applied to ac electric machines (Van der Broeck, Skedulny, and Stanke, 1988; Holtz, Lammert, and Lotzkat, 1986; Trzynadlowski and Legowski, 1994). A balanced set of three-phase quantities can be transformed into direct and quadrature components through the transformation  xd   =  x q 

2 . 1  3  0

−1/2   3/2 − 3/2 

−1/2

 xa     xb     xc 

FIGURE 13.4.15 The generation of sinusoidally distributed pulse widths using a bipolar triangular carrier.

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(1)

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FIGURE 13.4.16 The eight space vectors that can be produced by the three-phase inverter of Fig. 13.4.8.

where x is a voltage or current. A similar transformation exists for taking direct and quadrature components back to phase quantities, though space-vector modulation does not need to use the inverse transformation. Applying Eq. (1) to the three-phase inverter of Fig. 13.4.8, we see that each distinct switch state of the inverter corresponds with a different space vector. The zero vector can be produced by the electrically equivalent topologies of all upper switches conducting and all lower switches conducting. It is important to note that the six nonzero space vectors created by the inverter states are of the same magnitude (√2/3Vdc) and are symmetrically displaced. Figure 13.4.16 shows the connection between the three-phase inverter of Fig. 13.4.8 and the generation of the eight space vectors. Any desired output voltage, up to the magnitude of Vdc/ √2 may be synthesized by taking the three adjacent space vectors in proper proportion. Figure 13.4.17 shows how the desired voltage V* is synthesized from the space vectors V1, V2, and V0. Over one sampling interval, the duty ratios of V1, V2, and V0 are, respectively, d1 = d2 =

2 / 3| V * | sin (60° − γ ) 2 / 3Vdc 2 / 3 |V * | sin γ 2 / 3Vdc

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The order used in implementing the space vectors is driven by the desire to minimize the number of switching operations. Careful examination of Figs. 13.4.16 and 13.4.17 reveals that within any of the six segments delimited by space vectors, the move from one vector to the next requires changing the state of only one switch. In practice, the switching in adjacent sampling intervals would apply the sequence … |V1|V2|V0|V0|V2|V1| …. Different approaches use different criteria for selecting the best implementation of V0 (Trzynadlowski and Legowski, 1994). Extension of the space-vector concept is possible with multilevel inverters (Holmes and McGrath, 2001; Tolbert, Peng, and Habetler, 2000). Multilevel inverters, however, offer a substantially greater number of space vectors from which to choose. With three-level inverters, for example, there are now 19 different space vectors. FIGURE 13.4.17 The synthesis of voltage V* using space Additional levels would increase the number of space vector modulation. vectors still further. The number of redundant space vectors also increases in multilevel inverters, thereby offering additional degrees of freedom within the voltage synthesis algorithm. Figure 13.4.18 shows the space vectors that can be created by a three-phase three-level inverter based on the phase-leg of Fig. 13.4.12. The numbers adjacent to each space vector represent the switch configuration of phases a, b, and c, respectively. Space vectors with more than one set of numbers can be achieved with any of the switch combinations indicated. Referring to Fig. 13.4.12, a 0 indicates that switches S3 and S4 are connecting the output terminal to the negative side of the dc bus. Similarly, a 1 indicates switches S2 and S3 are connecting the output terminal to the midpoint of the dc bus. Finally, a 2 indicates that switches S1 and S2 are connecting the load terminal to the positive side of the dc bus.

FIGURE 13.4.18 The achievable space vectors associated with a three-phase three-level inverter.

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FIGURE 13.4.19 The principles of hysteretic current control.

CURRENT WAVEFORM SYNTHESIS TECHNIQUES While voltage-source inverters always output a voltage waveform, there are many applications where the details of the voltage waveform are driven by the creation of a current with a specific shape. In this context, the controller is determining the state of each inverter switch based on how well the inverter output currents are tracking commanded output currents. While the PWM techniques of the previous subsection can often be applied to transform a voltage-source inverter into a controlled current source (Brod and Novotny, 1985; Habetler, 1993), there are some additional techniques that are useful in this type of operation. The control techniques described in this subsection are amenable to synthesizing current waveforms with inverters. Hysteresis and Sliding-Mode Control. Hysteresis and sliding-mode control are very similar in nature. In both of these control approaches, a reference current waveform is established and the switching of the inverter is tied to the relative location of the actual current and the reference waveform (Brod and Novotny, 1985; Bose, 1990; Slotine and Li, 1991; Torrey and Al-Zamel, 1995). Under hysteretic control, a hysteresis band is introduced around the reference waveform in order to limit the switching frequency. Figure. 13.4.19 illustrates the principles of hysteretic control. Sliding-mode control can be implemented in a manner which is indistinguishable from hysteretic control, or it can be implemented as shown in Fig. 13.4.20 where there is a known upper limit on the switching frequency. A common problem with hysteretic control is that the switching frequency is not fixed and may vary widely over one cycle of the output. This can complicate the design of filters and may raise reliability concerns relative

FIGURE 13.4.20 One method of implementing sliding-mode control.

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to the safe operation of the switches. Fixing the switching frequency is possible (Kazerani, Ziogas, and Joos, 1991), at the expense of a hysteresis band that changes throughout each cycle of the output. Predictive Current Regulation. Predictive current regulation is similar to hysteresis and sliding-mode control in the establishment of a reference current and acceptable error bounds (Holtz, 1994; Wu, Dewan, and Slemon, 1991). The predictive controller uses a model of the system in conjunction with measurements of the system state in order to predict how long the next switching state is to be maintained so that the actual current remains within the established error bounds. In contrast to hysteresis and sliding-mode control, the predictive controller is always looking ahead one sampling interval into the future.

INVERTER APPLICATIONS This subsection reviews four important applications of inverters: uninterruptible power supplies, motor drives, active power filters, and utility interfaces for distributed generation. Uninterruptible power supplies have become an extremely large market in support of the expanding use of personal computers and other critical loads. These systems are able to support computer operation in the face of unreliable utility power, thereby preventing the loss of data. Motor drives allow for adjustable speed operation of electric motors, thereby providing a better match between the motor output and the power required by the load. The proper application of adjustable speed drives can result in significant energy savings. The increasing application of active power filters and active power line conditioners is a reflection of increasing harmonic distortion on power systems, and the regulatory responses to this distortion. Distributed generation sources (fuel cells, solar photovoltaics, wind turbines, and microturbines) often function as sources of dc power, thereby requiring an inverter to deliver this power to the ac utility grid. Uninterruptible Power Supplies. An uninterruptible power supply (UPS) uses a battery to provide energy to a critical load in the event of a power system disturbance. There are two basic topologies used in UPS systems, as shown in the block diagrams of Figs. 13.4.21 and 13.4.22 (Mohan, Undeland, and Robbins, 1995). Both single- and three-phase UPS systems are available. In Fig. 13.4.21, the critical load is always supplied through an inverter. This inverter is fed from either the utility or the battery bank, depending on the availability of the utility. The battery is continually charged when the utility is present. This type of UPS provides effective protection of the critical load by isolating it from utility under- and over-voltages. In Fig. 13.4.22, the functions of battery charging and the inverter are combined. While the utility is present, the inverter is run as a controlled rectifier to support battery charging. When the utility fails, the load is supplied from the battery-fed inverter. Because an inverter does not have the ability to deliver a larger voltage than that of the dc source, it may be necessary to include a bidirectional dc/dc converter if a low voltage battery is used in the UPS. Motor Drives. Motor drives can be found in a very wide range of power levels, from fractional horsepower up to hundreds of horsepower (Bose, 1986; Murphy and Turnbull, 1988). These applications range from very

FIGURE 13.4.21 A block diagram for one configuration of a UPS system.

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FIGURE 13.4.22 A block diagram for a second UPS system configuration.

precise motion control to adjustable speed operation of pumps and compressors for saving energy. In a motor drive, the inverter is used to provide an adjustable frequency ac voltage to the motor, thereby enabling the motor to operate over a wide range of speeds without derating the torque production of the motor. In order to prevent the motor from being pushed into magnetic saturation, the amplitude of the synthesized voltage is usually tied to the output frequency. In the simplest adjustable speed drives, the ratio of peak output voltage to output frequency is maintained nominally constant, with a small boost at low frequencies to compensate to the resistance of the motor windings. More sophisticated adjustable speed drives implement sensorless flux vector control (Bose, 1997). Active Power Filters. Active power filters are able to simultaneously provide compensation for the reactive power drawn by other linear loads while compensating for the harmonic currents being drawn by still other nonlinear loads (Gyugyi and Strycula, 1976; Akagi, Kanazawa, and Nabae, 1984; Akagi, Nabae, and Atoh, 1986; Torrey and Al-Zamel, 1995). It is possible to compensate for multiple loads at one point. The basic idea of an active power filter is shown in Fig. 13.4.23. The active power filter is formed by putting an inverter in parallel with the loads for which compensation is needed. The inverter switches are then controlled to force the line current drawn from the utility to be of the desired quality. The inverter is controlled to draw currents that precisely compensate for the undesired components in the currents drawn by the loads. The undesired components may be either reactive or harmonic in nature. In Fig. 13.4.23, iutility is forced to be of the desired quality and phase through the superposition of ifilter and inonlinear loads. With control over ifilter, the utility current can be forced to track its intended shape and amplitude.

FIGURE 13.4.23 A one-line diagram of an active filter system.

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Distributed Generation. There is an ever-increasing interest in the integration of distributed generation sources into the electric utility system. Distributed generation sources include fuel cells, solar photovoltaics, wind energy, hydroelectric, and microturbines, among others. Their application is sometimes driven by the utility in an effort to use a local resource such as hydroelectric energy, to increase generating capacity without having to increase the capacity of their transmission lines, to add generation capacity incrementally without the large capital investment required of a more traditional generating station, or to increase the reliability of the supply for critical customers. Distributed generation sources are sometimes used by electricity customers to reduce their electricity costs or to increase the reliability of their electricity supply. Some distributed generation sources naturally provide energy through dc, thereby requiring an inverter to deliver the energy to the utility grid. Fuel cells and solar photovoltaics fall into this category. Other distributed generation sources provide energy through ac with variable frequency and amplitude. Wind turbines, microturbines, and some hydroelectric systems fall into this category. This ac energy is usually delivered to the utility by first rectifying the variable ac into dc and then using an inverter to provide fixed frequency ac with a fixed amplitude to the utility grid. In some cases the rectification process is facilitated by an inverter structure where the flow of energy is from the ac side to the dc side. In this way phase currents can be controlled far more precisely than would be possible with an uncontrolled rectifier. A significant issue with the deployment of distributed generation sources is the prevention of a situation known as islanding. An inverter that is unable to detect the presence or absence of the utility may continue to feed a section of the utility system even after the utility has taken actions to deenergize that section. This creates a serious safety issue for any utility workers who may be working on the utility system. For this reason, any inverter that is designed to interact with the ac utility must include anti-islanding controls that actively and continuously verify the presence of the larger ac utility system. Techniques for accomplishing this are described in Stevens et al. (2000) for photovoltaic systems, but the techniques described are applicable to other energy sources. Inverters for distributed generation systems are designed to be either utility interactive or utility independent. The difference between them is found in the control. Utility interactive inverters are controlled to behave as a current source, delivering power to the utility with near-unity power factor. Utility independent inverters behave as voltage sources, where the phase difference between the output voltage and the load current is dictated by the load on the inverter.

REFERENCES 1. Akagi, H., Y. Kanazawa, and A. Nabae, “Instantaneous reactive power compensators comprising switching devices without energy storage components,” IEEE Trans. Ind. Appl., Vol. IA-20, pp. 625–630, 1984. 2. Akagi, H., A. Nabae, and S. Atoh, “Control strategy of active power filters using multiple voltage-source PWM converters,” IEEE Trans. Ind. Appl., Vol. IA-22, pp. 460–465, 1986. 3. Bose, B. K., “An adaptive hysteresis-band current control technique of a voltage-fed PWM inverter for machine drive system,” IEEE Trans. Ind. Electron., Vol. 37, pp. 402–408, 1990. 4. Bose, B. K. ed., “Modern Power Electronics: Evolution, Technology, and Applications,” IEEE Press, 1992. 5. Bose, B. K. ed., “Power Electronics and Variable Frequency Drives,” IEEE Press, 1997. 6. Brod, D. M., and D. W. Novotny, “Current control of VSI-PWM inverters,” IEEE Trans. Ind. Appl., Vol. IA-21, pp. 562–570, 1985. 7. Divan, D. M., “The resonant dc link converter—a new concept in static power conversion,” IEEE Trans. Ind. Appl., Vol. 25, pp. 317–325, 1989. 8. Divan, D. M., and G. Skibinski, “Zero-switching-loss inverters for high-power applications,” IEEE Trans. Ind. Appl., Vol. 25, pp. 634–643, 1989. 9. Enjeti, P. N., P. D. Ziogas, and J. L. Lindsay, “Programmed PWM techniques to eliminate harmonics: A critical evaluation,” IEEE Trans. Ind. Appl., Vol. 26, pp. 302–316, 1985. 10. Gyugyi, L., and E. C. Strycula, “Active ac power filter,” IEEE/IAS Annual Meeting Conference Record, pp. 529–535, 1976. 11. He, J., and N. Mohan, “Parallel resonant dc link circuit—a novel zero switching loss topology with minimum voltage stresses,” IEEE Trans. Power Electron., Vol. 6, pp. 687–694, 1991.

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12. Habetler, T. G., “A space vector-based rectifier regulator for ac/dc/ac converters,” IEEE Trans. Power Electron., Vol. 8, pp. 30–36, 1993. 13. Holmes, D. G., and B. P. McGrath, “Opportunities for harmonic cancellation with carrier-based PWM for a two-level and multilevel cascaded inverters,” IEEE Trans. Ind. Appl., Vol. 37, pp. 574–582, 2001. 14. Holtz, J., P. Lammert, and W. Lotzkat, “High-speed drive system with ultrasonic MOSFET PWM inverter and singlechip microprocessor control,” IEEE/IAS Annual Meeting Conference Record, pp. 12–17, 1986. 15. Holtz, J., “Pulsewidth modulation for electronics power conversion,” IEEE Proc., Vol. 82, pp. 1194–1214, 1994. 16. International Rectifier, “Transformer-isolated gate driver provides very large duty cycle ratios,” Application Note AN-950. Available through URL http://www.irf.com/technical-info/appnotes.htm. 17. Kazerani, M., P. D. Ziogas, and G. Joos, “A novel active current waveshaping technique for solid-state input power factor conditioners,” IEEE Trans. Ind. Electron., Vol. 38, pp. 72–78, 1991. 18. Kassakian, J. G., M. F. Schlecht, and G. C. Verghese, “Principles of Power Electronics,” Addison-Wesley, 1991. 19. Krein, P. T., “Elements of Power Electronics,” Oxford University Press, 1998. 20. Lai, J.-S., and F. Z. Peng, “Multilevel converters—a new breed of power converters,” IEEE Trans. Ind. Appl., Vol. 32, pp. 509–517, 1996. 21. McMurray, W., “Efficient snubbers for voltage-source GTO inverters,” IEEE Trans. Power Electron., Vol. PE-2, pp. 264–272, 1987. 22. McMurray, W. “Resonant snubbers with auxiliary switches,” IEEE/IAS Annual Meeting Conference Record, pp. 829–834, 1989. 23. Mohan, N., T. M. Undeland, and W. P. Robbins, “Power Electronics: Converters, Applications and Design,” 2nd ed., John Wiley & Sons, 1995. 24. Murai, Y., and T. A. Lipo, “High frequency series resonant dc link power conversion,” IEEE/IAS Annual Meeting Conference Record, pp. 772–779, 1998. 25. Patel, H. S., and R. G. Hoft, “Generalized techniques of harmonic elimination and voltage control in thyristor inverters: Part I–Harmonic elimination techniques,” IEEE Trans. Ind. Appl., Vol. IA-9, pp. 310–317, 1973. 26. Patel, H. S., and R. G. Hoft, “Generalized techniques of harmonic elimination and voltage control in thyristor inverters: Part II–Voltage control techniques,” IEEE Trans. Ind. Appl., Vol. IA-10, pp. 666–673, 1974. 27. Peng, F. Z., “A generalized multilevel inverter topology with self voltage balancing,” IEEE Trans. Ind. Appl., Vol. 37, pp. 611–618, 2001. 28. Simonelli, J. M., and D. A. Torrey, “An alternative bus clamp for resonant dc link converters,” IEEE Trans. Power Electron., Vol. 9, pp. 56–63, 1994. 29. Slotine, J. J., and W. Li, “Applied Nonlinear Control,” Prentice Hall, 1991. 30. Stevens, J., R. Bonn, J. Ginn, S. Gonzalez, and G. Kern, “Development and testing of an approach to anti-islanding in utility-interconnected photovoltaic systems,” Report SAND 2000-1939, Sandia National Laboratories, August 2000. 31. Tolbert, L. M., F. Z. Peng, and T. G. Habetler, “Multilevel PWM methods at low modulation indices,” IEEE Trans. Power Electron., Vol. 15, pp. 719–725, 2000. 32. Torrey, D. A., and A. M. Al-Zamel, “Single-phase active power filters for multiple nonlinear loads,” IEEE Trans. Power Electron., Vol. 10, pp. 263–272, 1995. 33. Trzynadlowski, A. M., and S. Legowski, “Minimum-loss vector PWM strategy for three-phase inverters,” IEEE Trans. Power Electron., Vol. 9, pp. 26–34, 1994. 34. Undeland, T. M., “Switching stress reduction in power transistor converters,” IEEE/IAS Annual Meeting Conference Record, pp. 383–392, 1976. 35. Van der Broeck, H. W., H. C. Skudelny, and G. Stanke, “Analysis and realization of a pulse width modulator based on space vector theory,” IEEE Trans. Ind. Appl., Vol. IA-24, pp. 142–150, 1988. 36. Vithayathil, J., “Power Electronics: Principles and Applications,” McGraw-Hill, 1995. 37. Wu, R., S. Dewan, and G. Slemon, “Analysis of a PWM ac to dc voltage source converter under predicted current control with fixed switching frequency,” IEEE Trans. Ind. Appl., Vol. 27, pp. 756–764, 1991.

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CHAPTER 13.5

AC REGULATORS Peter Wood

CIRCUITS FOR CONTROLLING POWER FLOW IN AC LOADS Switch configurations such as those in Fig. 13.5.1 can be used to control ac waveforms. The control may be merely transistory, as in soft starting an induction motor or limiting the inrush current to a transformer, or perpetual, as in the control of resistive heating elements, incandescent lamps, and the reactors of a static reactive volt-ampere (VAR) generator. The basic single-phase ac regulator is depicted in Fig. 13.5.2, using a triac as the ac switch (but any of the ac switch combinations shown in Fig. 13.5.1 is applicable). The various three-phase arrangements possible are shown in Fig. 13.5.3. The first of these, the wye-connected regulator with a neutral connection (Fig. 13.5.3a), exhibits behavior identical to that of the single-phase regulator, since it is merely a threefold replica of the single-phase version. The delta-connected regulator arrangement of Fig. 13.5.3b is also essentially similar in behavior to the single-phase regulator insofar as load voltages and currents are concerned. Because of the delta connection, however, any symmetrical zero sequence components of the load currents will not flow in the supply lines but will only circulate in the delta-connected loads. The three-phase three-wire wye-switched regulator of Fig. 13.5.3c behaves differently because two switches must be closed for current to flow in any load. Shown delta-loaded, it may also have the loads wyeconnected without a neutral return. In this connection, each ac switch may consist of the antiparallel combination of a thyristor and a diode. The normal wye-delta transformations apply to load voltages and currents. The “British delta” circuit of Fig. 13.5.3d behaves in the same way as a wye-switched regulator in which thyristors with inverse parallel connected diodes are used as the switches and is unique in that only unidirectional current capability is required of its switches. When the loads are essentially resistive, two methods of control are currently employed. The technique known as integral-cycle control operates the regulator by keeping the switch(es) closed for some number m of complete cycles of the supply and then keeping the switch(es) open for some number n of cycles. The power delivered to the load(s) is then simply m/(m + n) times the power delivered if the switch(es) are kept permanently closed, for the single-phase, wye with neutral, and delta-connected regulators. For the wye-switched (without neutral) and British delta regulators, the power delivered is slightly greater than m/(m + n) times the power at full switch conduction, and dc and unbalanced ac components develop in the supply unless special control techniques are used. These phenomena arise because of the transient conditions, inevitably attending the first cycle of operation of these circuits. An undesirable consequence of integral-cycle control is that the load voltages and currents, and hence the supply currents, contain sideband components having frequencies fs[1 ± pm/(m + n)], where fs is the supply frequency and p is any integer, 1 to infinity. Many of these frequencies are obviously lower than the supply frequency and may create problems for the supply system and other connected loads. The existence of this type of unwanted components in the voltage and current spectra makes integral-cycle control unsuitable for inductive loads (including loads fed by transformers). Since none of the sidebands are zero sequence, the line currents of an integral-cycle-controlled delta regulator are identical to the properly transposed load currents. 13.69 Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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FIGURE 13.5.1 Single-phase ac switches.

FIGURE 13.5.2 Single-phase ac regulator.

Integral-cycle control results in unity displacement factor (the cosine of the angle between the fundamental component of supply current and the supply voltage). The power factor of the burden they impose on the supply with pure resistive loads is [m/(m + n)]0.5. This is true because any regulator that forces the load current to flow in the supply while reducing the rms voltage applied to a resistive load has a power factor equal to the rms load voltage divided by the rms supply voltage. The other method of control commonly used is termed phase-delay control. It is implemented by delaying the closing of the switch(es) by an angle a (called the firing angle) from each zero crossing of the supply voltage(s) and allowing the switch(es) to open again on each succeeding current zero. The load voltages and currents in this case contain only harmonics of the supply frequency as unwanted components, and except for the regulator shown in Fig. 13.5.3c, using thyristor-inverse diode switches, only odd-order harmonics are present. Thus, this control technique can be used with inductive loads.

FIGURE 13.5.3 Three-phase ac regulators.

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13.71

The general expressions for the load voltages and currents produced by the single-phase regulator are very cumbersome but simplify considerably for the two cases of greatest practical importance, pure resistive and pure inductive loads. For a pure resistive load with a supply voltage V cos ws t, the fundamental component of load voltage is given by  α sin 2α  sin 2 α VDIR = 1 − + V sin ω s t  V cos ω s t + π 2π   π

(1)

and the total rms load voltage by VRMSR =

V  α sin 2α  1 − +  2π  2 π

1/ 2

(2)

where a is the firing angle measured from the supply-voltage zero crossings. For pure inductive load it is convenient to define the firing angle a′ = a − p/2, so that at full output a′ = 0. The fundamental voltage component is then given by  2α ′ sin 2 α ′  − VDIL = 1 −  V cos ω s t π π  

(3)

and the total rms voltage by VRMSL =

V  2α ′ sin 2α ′  − 1 −  π π  2

1/ 2

(4)

The same relationships apply to the three-phase circuits, which are in effect triplicates of the single-phase circuit (Fig. 13.5.3a and 13.5.3b); more complex relationships exist for the remaining three-phase circuits. The use of phase-delay control results in decreasing lagging displacement factor with increasing firing angle. Maximum displacement factor is obtained at full output, equaling the power factor of the given load. At a reduced power setting the power factor is less than the displacement factor; the ratio of the two equals the ratio of the fundamental line currents versus the total rms line currents. This ratio is less than unity because of the presence of harmonic currents. The load voltages and currents and, more importantly, the line currents of phase-delay-controlled regulators have lower total rms distortion than those of integral-cycle-controlled regulators. Among the circuits shown, the delta regulator of Fig. 13.5.3b is most beneficial; since the triple n harmonics (those of orders which are integer multiples of 3) in its load currents are zero sequence, they do not flow in the supply lines and the circuit has both a better power factor and lower total line-current distortion than integral-cycle regulators or the phase-delay-controlled wye regulators with neutral. For the wye regulator without neutral, the range of a is 0 to 7p/6 rad, provided fully bilateral switches are used; for the British delta regulator and the wye regulator without neutral using thyristor-inverse diode switches, the range is 0 to 5p/6 rad. When phase-delay regulators are used with inductive loads, the range of a used for control is reduced because current-zero crossings lag voltage-zero crossings and thus abrogate part of the delay obtained with resistive loads. The regulators most commonly used with inductive loads are the single-phase, wye with neutral and the delta, for which the range of a becomes f to p, where f is the load-phase angle.

STATIC VAR GENERATORS The delta regulator with purely inductive loading finds extensive use in the static VAR generator (SVG) (Gyugyi et al., 1978, 1980). A basic SVG consists of three delta-connected inductors with phase-controlled switches (p/2 ≤ a ≤ p) and three fixed capacitive branches which may be delta-or wye-connected. The

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capacitive branches draw a fixed current from the supply, leading the voltage by p/2 rad. The fundamental current in the inductors is lagging the voltage by p/2 rad. Its amplitude can be varied, by phase controlling the switches, from the full inductor current to zero. Hence the net reactive volt-ampere burden on the supply can be continuously controlled from the full capacitive VAR, when a = p and the inductor currents are zero, to the difference between the capacitive- and inductive-branch VARs when a = p /2 and full inductor currents flow. This difference will be zero if inductive-branch VARs are made equal to capacitive-branch VARs and become an inductive burden if inductive VARs at full conduction exceed the capacitive VARs. Since the firing angle a can be varied on a half-cycleto-half-cycle basis, extremely rapid changes in VAR supply (capacitive burden) or demand (inductive burden) can be accomplished. SVGs can be used to supply shunt-reactive compensation on ac transmission and distribution systems, helping system stability and voltage regulation. They can also be used to provide damping of the subsynchronous resonances, which often prove troublesome during transient disturbances on series capacitor-compensated transmission systems, and to reduce the voltage fluctuations (flicker) produced by arc-furnace loads. In the latter application, their ability to accomplish dynamic load balancing is especially valuable. An SVG which can provide control of reactive power supply or demand can obviously compensate for an unbalanced reactive load. It can also act as a Steinmetz balancer, providing the reactive power exchange between phases necessary to transform an unbalanced resistive load into a perfectly balanced and totally active (real) power load on the supply system. This action can be explained as follows. Suppose a single-phase resistive load is connected between lines A and B of a three-phase system. Then the current it draws will be in phase with the AB voltage, and thus the A-line current created will lead the A-phase (line-to-neutral) voltage by p/6 rad and the B-line current will lag the B-phase voltage by p /6 rad. If equal-impedance purely reactive loads are now connected to the BC and CA line pairs, capacitance on BC and inductive on CB, they create currents with the following phase relationships to the phase voltages: In the A line, lagging by 2p/3 rad In the B line, leading by 2p/3 rad In the C line, one leading by p/3 rad and the other lagging by p/3 rad The result in the C line is clearly an in-phase, wholly real current. If the impedances are of appropriate magnitude, their lagging and leading quadrature contributions in the A and B lines, respectively, can be made to cancel the lagging and leading quadrature currents created therein by the single-phase resistive load. The impedance required is √3 times the resistance. Obviously an SVG capable of providing either leading or lagging line-to-line loading on any of the line pairs can be used to balance a single-phase resistive load on any one line pair; by extension, it can be used to balance any unbalanced load. It can respond rapidly to changes in the degree of imbalance existing and thus dynamically balance the load despite the fluctuating imbalance typically created by an arc furnace. In addition to a varying reactive fundamental current, an SVG operating other than at full or zero conduction in its reactive branches generates harmonic currents. Thus at least part of the capacitive branch is usually realized in the form of tuned harmonic filters to limit harmonic injection to the ac supply system. Maximum harmonic amplitudes relative to maximum fundamental are: Harmonic order Maximum amplitude percent

3d 13.8

5th 5.05

7th 2.59

9th 1.57

11th 1.05

13th 0.752

with diminishing amplitudes of the higher-order components. When the SVG is in balanced operation, the triple n harmonics (3d and 9th in the table above) do not flow in the supply, being zero sequence. When operation is unbalanced in order to balance an unbalanced real load, positive and negative sequence components of the triple n harmonics develop and of course do flow in the supply unless filtering is provided for them.

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REFERENCES Gyugyi, L., R. A. Otto, and T. H. Putnam, “Principles and applications of static, thyristor controlled shunt compensators,” IEEE Trans. Power Apparatus and Systems, Vol. PAS-97, No. 5, 1978. Gyugyi, L., and E. C. Strycula, “Active ac power filter,” IEEE Ind. Appl. Soc. Annual Meeting Rec., pp. 529–535, 1976. Gyugyi, L., and E. R. Taylor, “Characteristics of static, thyristor-controlled shunt compensators for power transmission system applications,” IEEE Trans. Power Eng. Soc., Vol. F 80, p. 236, 1980.

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Source: STANDARD HANDBOOK OF ELECTRONIC ENGINEERING

SECTION 14

PULSED CIRCUITS AND WAVEFORM GENERATION Pulsed circuits and waveform generation are very important to testing and identification in a whole range of electrical and electronic circuits and systems. There are essentially two types of such networks, those that are considered passive and the rest that can be lumped into active wave shaping (which includes those done digitally). Passive circuits are lumped into linear and nonlinear. Linear are most commonly, single pole RC and RL networks. Nonlinear networks are usually designed around diodes with or without capacitors and inductors. A common element used in waveform generation is the switch. Mechanical switches are cleaner giving better electrical characteristics; however, they do have serious limitations. Electronic switches can be compensated so that they can come close to the mechanical switches without the serious limitations such as contact bounce. In addition, electronic switches can be made smaller and are able to work at much higher frequencies. Active networks are either analog or digital. Analog networks have been in use for a long period of time and still have many practical uses. Digital networks have advantages especially in the area of noise, speed, and accuracy and have successfully replaced most of the analog networks in most applications. C.A.

In This Section: CHAPTER 14.1 PASSIVE WAVEFORM SHAPING LINEAR PASSIVE NETWORKS NONLINEAR-PASSIVE-NETWORK WAVESHAPING

14.5 14.5 14.12

CHAPTER 14.2 SWITCHES THE IDEAL SWITCH BIPOLAR-TRANSISTOR SWITCHES MOS SWITCHES TRANSISTOR SWITCHES OTHER THAN LOGIC GATES

14.15 14.15 14.15 14.19 14.22

CHAPTER 14.3 ACTIVE WAVEFORM SHAPING ACTIVE CIRCUITS RC OPERATIONAL AMPLIFIER-INTEGRATOR SWEEP GENERATORS SAMPLE-AND-HOLD CIRCUITS NONLINEAR NEGATIVE FEEDBACK WAVEFORM SHAPING POSITIVE FEEDBACK WAVEFORM SHAPING INTEGRATED-CIRCUIT FLIP-FLOPS SYNCHRONOUS BISTABLE CIRCUITS

14.25 14.25 14.25 14.25 14.29 14.29 14.30 14.33 14.34

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INTEGRATED-CIRCUIT SCHMITT TRIGGERS INTEGRATED MONOSTABLE AND ASTABLE CIRCUITS

14.38 14.40

CHAPTER 14.4 DIGITAL AND ANALOG SYSTEMS INTEGRATED SYSTEMS COUNTERS SHIFT REGISTERS MULTIPLEXERS, DEMULTIPLEXERS, DECODERS, ROMS, AND PLAS MEMORIES DIGITAL-TO-ANALOG CONVERTERS (D/A OR DAC) ANALOG-TO-DIGITAL (A/D) CONVERTERS (ADC) DELTA-SIGMA CONVERTERS VIDEO A/D CONVERTERS FUNCTION GENERATORS

14.43 14.43 14.43 14.45 14.46 14.49 14.53 14.57 14.61 14.67 14.71

On the CD-ROM: Dynamic Behavior of Bipolar Switches

Section References: 1. Ebers, J. J., and J. L. Moll, “Large-signal behavior of junction transistors,” Proc. IRE, December 1954, Vol. 42, pp. 1761–1772. 2. Moll, J. L., “Large-signal transient response of junction transistors,” Proc. IRE, December 1954, Vol. 42, pp. 1773– 1784. 3. Glaser, L. A., and D. W. Dobberpuhl, “The Design and Analysis of VLSI Circuits,” Addison-Wesley, 1985. 4. Horowitz, P., and W. Hill, “The Art of Electronics,” Cambridge University Press, 1990. 5. Eccles, W. H., and F. W. Jordan, “A trigger relay utilizing three electrode thermionic vacuum tubes,” Radio Rev., 1919, Vol. 1, No. 3, pp. 143–146. 6. Schmitt, O. H. A., “Thermionic trigger,” J. Sci. Instrum., 1938, Vol. 15, p. 24. 7. Tietze, U., and C. Schenk, “Advanced Electronic Circuits,” Springer, 1978. 8. Masakazu, S., “CMOS Digital Circuit Technology, ATT,” Prentice Hall, 1988. 9. Stein, K. U., and H. Friedrich, “A 1-m/12 single-transistor cell in n-silicon gate technology,” IEEE J. Solid-State Circuits, 1973, No. 8, pp. 319–323. 10. Jespers, P. G. A., “Integrated Converters, D. to A. and A. to D. Architecture, Analysis and Simulation,” Oxford University Press, 2001. 11. Van den Plassche, R. J., “Dynamic element matching for high-accuracy monolithic D/A converters,” IEEE J. Solid-State Circuits, December 1976, Vol. SC-11, No. 6, pp. 795–800; Van den Plassche, R. J., and D. Goedhart, “A monolithic 14 bit D/A converter,” IEEE J. Solid-State Circuits, June 1979, Vol. SC-14, No. 3, pp. 552–556. 12. Schoeff, J. A., “An inherently monotonic 14 bit DAC,” IEEE J. Solid-State Circuits, December 1979, Vol. SC-14, pp. 904–911. 13. Tuthill, M. A, “16 Bit monolithic CMOS D/A converter,” ESSCIRC, Digest of Papers, 1980, pp. 352–353. 14. Caves, J., C. H. Chen, S. D. Rosenbaum, L. P. Sellars, and J. B. Terry, “A PCM voice codec with on-chip filters,” IEEE J. Solid-State Circuits, February 1979, Vol. SC-14, pp. 65–73. 15. McCreavy, J. L., and P. R. Gray, “All-MOS charge redistribution analog-to-digital conversion techniques—Part I,” IEEE J. Solid-State Circuits, December 1975, Vol. SC-10, No. 6, pp. 371–379. 16. Chao, K. C.-H., S. Nadeem, W. Lee, and C. Sodini, “A higher order topology for interpolative moderators for oversampling A / D converters,” IEEE Trans. Circuits Syst., March 1990, Vol. 37, No. 3, pp. 309–318. 17. Peterson, J. G., “A monolithic, fully parallel, 8 bit A/D converter,” ISSCC Digest, 1979, pp. 128–129. 18. Song, B. S., S. H. Lee, and M. F. Tompsett, “A 10 bit 15 MHz CMOS recycling two-step A-D convertor,” IEEE JSSC, December 1990, Vol. 25, No. 6., pp. 1328–1338.

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19. Wegmann, G., E. A. Vittoz, and F. Rahali, “Charge injection in MOS switches,” IEEE JSSC, December 1987, Vol. SC-22, No. 6. pp. 1091–1097. 20. Norsworthy, S. R., R. Schreier, and G. C. Temes, “Delta–Sigma Data Converters, Theory, Design and Simulation,” IEEE Press, 1997.

Section Bibliography: Wegmann, G., E. A. Vittoz, and F. Rahali, “Charge injection in MOS switches.” IEEE JSSC, Vol. SC-22, No. 6. December 1987.

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Page 14.5

Source: STANDARD HANDBOOK OF ELECTRONIC ENGINEERING

CHAPTER 14.1

PASSIVE WAVEFORM SHAPING Paul G. A. Jespers

LINEAR PASSIVE NETWORKS Waveform generation is customarily performed in active nonlinear circuits. Since passive networks, linear as well as nonlinear, enter into the design of pulse-forming circuits, this survey starts with the study of the transient behavior of passive circuits. Among linear passive networks, the single-pole RC and RL networks are the most widely used. Their transient behavior in fact has a broad field of applications since the responses of many complex higher-order networks are dominated by a single pole; i.e., their response to a step function is very similar to that of a first-order system. Transient Analysis of the RC Integrator The step-function response of the RC circuit shown in Fig. 14.1.1a, after closing of the switch S, is given by V(t) = E[1 – exp (–t/T)]

(1)

where T = time constant = RC. The inverse of T is called the cutoff pulsation w0 of the circuit. The Taylor-series expansion of Eq. (1) yields V (t ) = E

t T

  t t2 1 − +  2!T 3!T 2 −   

(2)

When the values of t are small compared with T, a first-order approximation of Eq. (2) is V(t) ≈ Et/T

(3)

In other words, the RC circuit of Fig. 14.1.1 behaves like an imperfect integrator. The relative error  with respect to the true integral response is given by

=−

t t2 t2 + − + 2 2!T 3!T 4!T 3

The theoretical step-function response of Eq. (1) and the ideal-integrator output of Eq. (3) are represented in Fig. 14.1.1b. Small values of t with respect to T correspond in the frequency domain (Fig. 14.1.1c) to frequency components situated above w0, that is, the transient signal whose spectrum lies to the right of w0 in the figure. In that case, the difference is small between the response curve of the RC filter and that of an ideal integrator 14.5 Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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FIGURE 14.1.1 (a) RC integrator circuit; (b) voltage vs. time across capacitor; (c) attenuation vs. angular frequency.

FIGURE 14.1.2 (a) RC differentiator circuit; (b) voltage across resistor vs. time; (c) attenuation vs. angular frequency.

(represented by the –6 dB/octave line in the figure). The circuit shown in Fig. 14.1.1a thus approximates an integrator, provided either of the following conditions is satisfied: (1) the time under consideration is much smaller than T or (2) the spectrum of the signal lies almost entirely above w0. Transient Analysis of the RC Differentiator When the resistor and the capacitor of the integrator are interchanged, the circuit (Fig. 14.1.2a) is able to differentiate signals. The step-function response (Fig. 14.1.2b) of the RC differentiator is given by v(t) = E exp (–t/T)

(4)

The time constant T is equal to the product RC, and its inverse w0 represents the cutoff of the frequency response of the circuit. As the values of t become large compared with T, the step-function response becomes more like a sharp spike; i.e., it increasingly resembles the delta function. The response differs from the ideal delta function, however, because both its amplitude and its duration are always finite quantities. The area under the exponential pulse, equal to ET, is the important quantity in applications where such a signal is generated to simulate a delta function, as in the measurement of the impulse response of a system. These considerations may be transported in the frequency domain (Fig. 14.1.2a).

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FIGURE 14.1.3 RL current-integrator circuit, the dual of the circuit in Fig. 14.1.1a.

FIGURE 14.1.5 RL voltage integrator.

14.7

FIGURE 14.1.4 RL current-differentiator circuit, the dual of the circuit in Fig. 14.1.2a.

FIGURE 14.1.6 RL voltage differentiator.

Transient Analysis of RL Networks Circuits involving a resistor and an inductor are also often used in pulse formation. Since integration and differentiation are related to the functional properties of first-order systems rather than to the topology of actual circuits, RL networks may perform the same function as RC networks. The duals of the circuits represented in Figs. 14.1.1 and 14.1.2, respectively, are shown in Figs. 14.1.3 and 14.1.4 and exhibit identical functional properties. In the first case, the current in the inductor increases exponentially from zero to I with a time constant equal to L/R, while in the second case it drops exponentially from the initial value I to zero, with the same time constant. Similar behavior can be obtained regarding voltage instead of current by changing the circuit from Fig. 14.1.3 to that of Fig. 14.1.5 and from Fig. 14.1.4 to Fig. 14.1.6, respectively. This duality applies also to the RC case. Compensated Attenuator The compensated attenuator is a widely used network, e.g., as an attenuator probe used in conjunction with oscilloscopes. The compensated attenuator (Fig. 14.1.7) is designed to perform the following functions: 1. To provide remote sensing with a very high input impedance, thus producing a minimum perturbation to the circuit under test. 2. To deliver a signal to the receiving end (usually the input of a wide-band oscilloscope) which is an accurate replica of the signal at the input of the attenuator probe. These conditions can be met only by introducing substantial attenuation to the signal being measured, but this is a minor drawback since adequate gain to compensate the loss is usually available. Diagrams of two types of oscilloscope attenuator probes are given in Fig. 14.1.9, similar to the circuit of Fig. 14.1.7. In both cases, the coaxial-cable parallels the input capacitance of the receiver end; Cp represents the sum of both capacitances. The shunt resistor Rp has a high value, usually 1 MΩ, while the series resistor Rs is typically 9 MΩ. The dc attenuation ratio of the attenuator probe therefore is 1:10, while the input impedance of the probe is 10 times that of the receiver. At high frequencies the parallel and series capacitors Cp and Cs play the same role as the resistive attenuator. Ideally these capacitors should be kept as low as possible to achieve a high input impedance even at high frequencies. Since it is impossible to reduce Cp below the capaciFIGURE 14.1.7 Compensated attenuator circuit. tance of the coaxial cable, there is no alternative other than

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FIGURE 14.1.8 Voltage vs. time responses of attenuator, showing correctly compensated condition at K = 1.

to insert the appropriate value of Cs to achieve a constant attenuation ratio over the required frequency band. In consequence, as the frequency increases, the nature of the attenuator changes from resistive to capacitive. However, the attenuation ratio remains unaffected, and no signal distortion is produced. The condition that ensures constant attenuation ratio is given by RpCp = RsCs

(5)

The step-function response of the compensated attenuator, which is illustrated in Fig. 14.1.8, clearly shows how distortion occurs when the above condition is not met. The output voltage V(t) of the attenuator is given by V (t ) =

Cs Cs + C p

  1 − (1 − K ) 1 − exp  

 t     − T    E  

(6)

where K represents the ratio of the resistive attenuation factor to that of the capacitive attenuation factor K=

Rp Rp + Rs

Cs C p + Cs

and T = (Rp || Rs) (Cs + Cp)

(7)

The || sign stands for the parallel combination of two elements, e.g., in the present case Rp || Rs = RpRs/(Rp + Rs). Only when K is equal to 1, in other words when Eq. (5) is satisfied, will no distortion occur, as shown in Fig. 14.1.8. In all other cases there is a difference between the initial amplitude of the step-function response (which is controlled by the attenuation ratio of the capacitive divider) and the steady-state response (which depends on the resistive divider only). A simple adjustment to compensate the attenuator consists of trimming one capacitor, either Cp and Cs, to obtain the proper step-function response. Adjustments of this kind are provided in attenuators like those shown in Fig. 14.1.9. Compensated attenuators may be placed in cascade to achieve variable levels of attenuation. The conditions imposed on each cell are like those enumerated above, but an additional requirement is introduced, namely, the requirement for constant input impedance. This introduces a different structure compared with the compensated attenuator, as shown in Fig. 14.1.10. The resistances Rp and Rs must be chosen so that the impedance is kept constant and equal to R. The capacitor Cs is adjusted to compensate the attenuator, while Cp provides the required additional capacitance to make the input susceptance equal to that of the load.

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14.9

FIGURE 14.1.9 Coaxial-cable type of attenuator circuit: (a) series adjustment; (b) shunt adjustment.

Periodic Input Signals Repetitive transients are typical input signals to the majority of pulsed circuits. In linear networks there is no difficulty in predicting the response of circuits to a succession of periodic step functions, alternatively positive and negative, since the principle of superposition holds. We restrict our attention here to two simple cases, the squarewave response of an RC integrator and an RC differentiator. Figure 14.1.11 represents, at the left, the buildup of the response of the RC integrator, assuming that the period t of the input square wave is smaller than the time constant of the circuit T. On the right in the figure the steady-state response is shown. The triangular waveshape represents a fair approximation to the integral of the input square wave. The triangular wave is superimposed on a dc pedestal of amplitude E/2. Higher repetition rates of the input reduce the amplitude of the triangular wave without affecting the dc pedestal. FIGURE 14.1.10 Compensated attenuator suitable for When the frequency of the input square wave is high use in cascaded circuits. enough, the dc component is the only remaining signal; i.e., the RC integrator then acts like an ideal low-pass filter. A similar presentation of the behavior of the RC differentiator is shown in Fig. 14.1.12a and b. The steadystate output in this case is symmetrical with respect to the zero axis because no dc component can flow through the series capacitor. When, as shown in Fig.14.1.12b, no overlapping of the pulses occurs, the steady-state solution is obtained from the first step. Pulse Generators The step function and the delta function (Dirac function) are widely used to determine the dynamic behavior of physical systems. Theoretically the delta function is a pulse of infinite amplitude and infinitesimal duration but having a finite area (product of amplitude and time). In practice the question of the equivalent physical impulse arises. The answer involves the system under consideration as well as the impulse itself.

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FIGURE 14.1.11 RC integrator with square-wave input of period smaller than RC: (a) initial buildup; (b) steady state.

FIGURE 14.1.12 RC differentiator with square-wave input: (a) period of input signal smaller than RC; (b) input period longer than RC.

FIGURE 14.1.13 RC pulse-generator circuit with large series resistance R1.

FIGURE 14.1.14 Coaxial-cable version of RC pulse generator.

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14.11

FIGURE 14.1.15 Use of mercury-wetted switch contacts in coaxial pulse generator.

The spectrum of the delta function has a constant amplitude over the whole frequency spectrum from zero to infinity. Other signals of finite area (amplitude × time) have different spectral distributions. On a logarithmic scale of frequency, the spectrum of any finite-area transient signal tends to be constant between zero and a cutoff frequency that depends on the shape of the signal. The shorter the duration of the signal, the wider the constant-amplitude portion of the spectrum. If such a signal is used in a system whose useful frequency band is located below the cutoff frequency of the signal spectrum, the system response is indistinguishable from its delta impulse response. Any transient signal with a finite area, whatever its shape, can thus be considered as a delta function relative to the given system, provided that the flat portion of its spectrum embraces the whole system’s useful frequency range. A measure of the effectiveness of a pulse to serve as a delta function is given by the approximation of useful spectrum bandwidth B = 1/t, where t represents the midheight duration of the pulse. Very short pulses are used in various applications in order to measure their delta-function response. In the field of radio interference, for instance, the basic response curve of the CISPR receiver* is defined in terms of its response to regularly repeated pulses. In this case, the amplitude of the uniform portion of the pulse spectrum must be calibrated, i.e., the area under the pulse must be a known constant which is a function of a limited number of circuit parameters. The step-function response of an RC differentiator provides such a convenient signal. Its area is given by the amplitude of the input step multiplied by the time constant RC of the circuit. Moreover, since the signal is exponential in shape, its –3-dB spectrum bandwidth is equal to 1/RC. In the circuit of Fig. 14.1.13, R1 is much larger than R; when the switch S is open, the capacitor charges to the voltage E of the dc source. When the switch is closed, the capacitor discharges through R, producing an exponential signal of known amplitude and duration (known area). A circuit based on the same principle is shown in Fig. 14.1.14. Here the coaxial line plays the role of energy storage source. If the line is lossless, its characteristic impedance is given by R0, the propagation delay is equal to t, and the Laplace transform of the voltage drop across R is V(p) = (1/p)E[1 + (R0/R) coth pt]–1

(8)

When the line is matched to the load, Eq. (8) reduces to V( p) = (1/2p)E(1 – e–p2t )

(9)

which indicates that V(t) is a square wave of amplitude E/2 and duration 2t. The area of the pulse is equal to the product of E and the time constant t. Both quantities can be kept reasonably constant. The bandwidth is larger than that of an exponential pulse of the same area (Fig. 14.1.13) by the factor p. Very wide bandwidth pulse generators based on this principles use a coaxial mercury-wetted switch built into the line (Fig. 14.1.15) to achieve low standing-wave ratios. A bandwidth of several GHz can be obtained in this manner. In coaxial circuits, any impedance mismatch causes reflections to occur at both ends of the line, replacing the desired square-wave signal by a succession of steps of decreasing amplitude. The cutoff frequency of the *International Electrotechnical Commission (IEC), “Specification, de l’apparelloge de mesure CISPR pour les frequences comprises entre 25 et 300 MHz,” 1961.

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spectrum is lowered thereby, and its shape above the uniform part can be drastically changed. Below cutoff frequency, however, the spectrum amplitude is given by EtR/R0. When the finite closing time of the switch is taken into account, it can be shown that only the width of the spectrum is reduced without affecting its value below the cutoff frequency. Stable calibrated pulse generators can also be built using electronic instead of mechanical switches.

NONLINEAR-PASSIVE-NETWORK WAVESHAPING Nonlinear passive networks offer wider possibilities for waveshaping than linear networks, especially when energy-storage elements such as capacitors or inductors are used with nonlinear devices. Since the analysis of the behavior of such circuits is difficult, we first consider purely resistive nonlinear circuits. Diode Networks without Storage Elements Diodes provide a simple means for clamping a voltage to a constant value. Both forward conduction and avalanche (zener) breakdown are well suited for this purpose. Avalanche breakdown usually offers sharper nonlinearity than forward biasing, but consumes more power. Clamping action can be obtained in many different ways. The distinction between series and parallel clamping is shown in Fig. 14.1.16. Clamping occurs in the first case when the diode conducts; in the second when it is blocked. Since the diode is not an ideal device, it is useful to introduce an equivalent network that takes into account some of its imperfections. The complexity of the equivalent network is a trade-off between accuracy and ease of manipulation. The physical diode is characterized by I = Is[exp (V/VT) – 1] where IS is the leakage current and VT = kT/q, typically 26 mV at room temperature.

FIGURE 14.1.16 Diode clamping circuit and voltage vs. time responses: (a) shunt diode; (b) series diode.

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(10)

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FIGURE 14.1.17 Actual and approximate currentvoltage characteristics of ideal and real diodes.

14.13

FIGURE 14.1.18 (a) DC restorer circuit; (b) input signal; (c) output signal.

The leakage current is usually quite small, typically 100 pA or less. Therefore, V must be at least several hundred millivolts, typically 600 mV or more, to attain values of forward current I in the range of milliamperes. A first approximation of the forward-biased real diode consists therefore of a series combination of the ideal diode and a small emf (Fig. 14.1.17). Moreover, to take into account the finite slope of the forward characteristic, a better approximation is obtained by inserting a small resistance in series. Diode Networks with Storage Elements There is no simple theory to represent the behavior of nonlinear circuits with storage elements, such as capacitors or inductances. Acceptable solutions can be found, however, by breaking the analysis of the circuit under investigation into a series of linear problems. A typical example is the dc restorer circuit hereafter. The circuit shown in Fig. 14.1.18 resembles the RC differentiator but exhibits properties that differ substantially from those examined previously. The diode D is assumed to be ideal first to simplify the analysis of the circuit, which is carried out in two steps, i.e., with the diode forward- and reverse-biased. In the first step, the output of the circuit is short-circuited; in the second, the diode has no effect, and the circuit is identical to the linear RC differentiator. When a series of alternatively positive and negative steps is applied at the input, after the first positive step is applied, no output voltage is obtained. The first positive step causes a large transient current to flow through the diode and charges the capacitor. Since D is assumed to be an ideal short circuit, the current will be close to a delta function as long as the internal impedance of the generator connected at the input is zero. In practice, the finite series resistance of the diode must be added to the generator internal impedance, but this does not affect the load time constant significantly, since it is assumed to be much smaller than the time between the first positive step and the following negative step. This allows the circuit to attain the steady-state conditions between steps. When the input voltage suddenly returns to zero, the output voltage undergoes a large negative swing whose magnitude is equal to that of the input step. The diode is then blocked, and the capacitor discharges slowly through the resistor. If the time constant is assumed to be much larger than the period of the

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input wave, the output voltage swings back to zero when the second positive voltage step is applied and only a small current flows through the forward-biased diode to restore the charge lost when the diode was under the reverse-bias condition. If the finite resistance of the diode is taken into consideration, a series of short positive exponential pulses must be added to the output signal, as shown in the lower part of Fig. 14.1.18. The first pulse, which corresponds to the initial full charge on the capacitor, is substantially higher than the next pulse, but this is of little importance in the operation of the circuit. An interesting feature of the dc restorer circuit lies in the fact that although no dc component can flow from input to output, the output signal has a well-defined nonzero dc level, although determined only by the amplitude of the negative steps (assuming, of course, that the lost charge between two steps is negligible). This circuit is used extensively in video systems to prevent the average brightness level of the image from being affected by its varying video content. In this case, the reference steps are the line-synchronizing pulses.

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Source: STANDARD HANDBOOK OF ELECTRONIC ENGINEERING

CHAPTER 14.2

SWITCHES Paul G. A. Jespers

THE IDEAL SWITCH An ideal switch is a two-pole device that satisfies the following conditions: Closed-switch condition. The voltage drop across the switch is zero whatever the current flowing through the switch may be. Open-switch condition. The current through the switch is zero whatever the voltage across the switch may be. Mechanical switches are usually electrically ideal, but they suffer from other drawbacks; e.g., their switching rate is low, and they exhibit jitter. Moreover, bouncing of the contacts may be experienced after closing, unless mercury-wetted contacts are used. Electronic switches do not exhibit these effects, but they are less ideal in their electrical characteristics.

BIPOLAR-TRANSISTOR SWITCHES The bipolar transistor approximates an open switch between emitter and collector when its base terminal is open or when both junctions are reverse-biased or even only slightly forward-biased. Inversely, under saturated conditions, the transistor resembles a closed switch with a small voltage drop in series, typically 50 to 200 mV. This drop may be considered negligible in many applications. Static Characteristics A more rigorous approach to the transistor static characteristics is based on the Ebers and Moll transport equations   1 IE  1   exp (VE /VT ) − 1 − β − 1      F    = IS  1   exp (V /V ) − 1 I  1 1 − −   C C T    β R   

(1)

where VE, VC = voltage drops across emitter and collector junctions, respectively (positive voltages stand for forward bias, negative for reverse bias); VT = kT/q (typically 26 mV at room temperature); IS = saturation current; and bF, bR represent forward (IC /IB) and reverse (IE /IB) current gains, respectively, with VE > 0, VC < 0 in the first case and VE < 0, VC > 0 in the second.

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The saturation current IS governs the leakage current flowing through the transistor under blocked conditions. It is always exceedingly small, and since it usually amounts to 10–14 or 10–15 A, it is difficult to measure. A standard procedure is to draw the plot representing the collector current in log scale versus the emitter forward bias VE in linear scale. To find the saturation current, one must extrapolate the part of the curve, which can be assimilated to a straight line with a slope of 60 mV/decade to the intercept with the vertical axis for which VE = 0. The saturation current can also be obtained with emitter and collector terminals permutated. The current gains bF and bR can be evaluated by means of the same experimental setup. An additional ammeter is required to measure IB. It is common practice to rewrite Eq. (1) so that the emitter and collector currents are expressed as functions of IF = IS[exp (VE /VT) – 1]

(2)

IR = IS[exp (VC /VT) – 1]

(3)

and

With these definitions Eq. (1) can be expressed as IC = IF – IR – IR /bR

(4)

IE = –IF – (IF /bF) + IR

(5)

Hence, the Ebers and Moll transport model is found. This is illustrated by the equivalent circuit of Fig. 14.2.1. The leakage currents of the two diodes D1 and D2 are given respectively by IS /bF and IS /bR. With this model, it is possible to compute the currents flowing through the transistor under any circumstance. For instance, if the collector junction is reverse-biased and a small positive bias of, for example, +100 mV is established across the emitter-junction, the reverse current IR is almost equal to – IS and IF is equal to IS exp (100/26) or 46.8 IS. Hence, from Eqs. (4) and (5), the collector current is found to be equal to 48IS, and the emitter current is approximately the same with opposite sign. With the assumption that IS is equal to 10 pA, both IC and IE are essentially negligible. A fortiori, IB as derived FIGURE 14.2.1 Equivalent circuit of the Ebers from Eqs. (4) and (5) is also small: and Moll transport model of the bipolar transistor.

IB = (IF /bF) + (IR /bR)

(6)

To drive current through the transistor, the voltage across one of the two junctions must reach at least 0.5 V, according to: VE = VT ln (IF /IS)

(7)

VC = VT ln (IR /IS)

(8)

or

derived from Eqs. (2) and (3). The transistor operates in the saturation region when it approximates a closed switch. The voltage drop between the emitter and collector terminals is then given by VCE ,sat = VT ln

n + (n + βF )/βR n −1

(9)

where n represents the ratio bF IB /IC, assumed larger than 1. For most transistors, this voltage drop lies between 50 and 200 mV. The inevitable resistance in series with the collector increases this voltage by a few tens of millivolts.

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SWITCHES SWITCHES

14.17

An interesting situation arises when IC is almost equal to zero; e.g., when the bipolar transistor is used to set the potential across a capacitor. In this case, Eq. (9) becomes VCE,sat = VT ln (1 + 1/bR)

(10)

Similarly, with interchanged emitter and collector terminals, the voltage drop is given by VEC,sat = VT ln (1 + 1/bF)

(11)

Since bF is normally much larger than bR, VEC,sat may be smaller than 1 mV provided bF is at least equal to 25. Consequently, inverted bipolar transistors are switches with a very small series voltage drop, provided that the current flowing through the transistor is kept small. The two situations examined so far (open or closed switch) correspond in Fig. 14.2.2, respectively, to IB = 0 and to the part of the curves closely parallel to the collector-current axis. The fact that all the curves have nearly the same vertical shape means that the series resistance of the saturated transistor is quite small. Since the characteristics do not coincide with the vertical coordinate axis, a small series emf must be considered, however, as previously stated. A third region exists where the transistor plays the FIGURE 14.2.2 Typical common-emitter characteristics role of a current switch instead of a voltage switch. It of the bipolar transistor. VA is called the Early voltage. concerns the switching from blocked conditions to any point within the active region or vice versa. Conceptually, the transistor may be compared to a controlled current source, which is switched on or off. However, because of the Early effect, the current is a function of the collector to emitter voltage. The Ebers and Moll model is inappropriate to describe this effect. A better expression of IC is IC = IS exp (VE /VT)(1 + VCE /VA)

(12)

where VA is called the Early voltage. Equation (12) is illustrated in Fig. 14.2.2. The finite output conductance of the transistor is given by IC /VA.

Dynamic Characteristics The dynamic behavior of bipolar transistors suffers from a drawback called “charge storage in the base,’’ which takes place every time transistors are driven in or out of saturation. The phenomenon is related to the majority carriers supplementing the minority carrier in the base to guarantee neutrality. The question is how to remove these extra carriers when the transistor is supposed to desaturate. Zeroing the base current is not a satisfactory solution for the majority carriers can only recombine with minority carriers. This requires a lot of time for lifetimes in the base are generally large in order to maximize the current gain. A better technique is to reverse the polarity of the base current. The larger this current, the more rapidly the majority carriers disappear and the faster the transistor gets out of saturation. Current continues to flow, however, until one of the two junctions gets reverse biased (usually the collector junction). Only then the transistor enters the active region and the collector current may start to decrease. When all majority carriers are swept away, both junctions are reverse-biased and the impedance of the base contact unfolds from a low impedance to an open circuit. A quantitative analysis of the desaturation mechanism can be found in the CD-ROM together with an example. Charge storage is generally associated with the base of bipolar transistors, although the same phenomenon takes place near the depleted region in the emitter neutral region also. The reason why this is not considered is related to the doping profile in the emitter comparatively to the base region. The emitter doping is much larger

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FIGURE 14.2.3 A Schottky diode D prevents T from going into saturation.

FIGURE 14.2.4 Planar npn transistor and Schottky diode in integrated-circuit form.

than the base doping because it increases the emitter’s efficiency, which controls the current gain (the emitter efficiency is the ratio of emitter-base current over base-emitter current). Junction diodes suffer from the same drawback. The diffusion length in the less-doped region being much longer than the base width of a bipolar transistor, charge storage problems should be worse. This is not the case, however, as diodes are generally bipolar transistors with their base and collector terminals shorted, making their charge storage effects similar to those of bipolar transistors. In order to reduce the delay between the control signal applied to the base and the moment the collector current begins to decay, several techniques have been developed. Two of these are reviewed hereafter. The first takes advantage of Schottky diodes, which exploit field emission and, therefore, ignore charge storage phenomena. Shottky diodes exhibit a slightly smaller voltage drop under forward bias than junction diodes (of the order of 0.4 V instead of 0.7 V), which is currently exploited to prevent bipolar transistors from getting saturated. The idea is illustrated in Fig. 14.2.3, which represents a bipolar transistor whose collector junction is paralleled by a Schottky diode. When the transistor is nearing saturation, the Schottky diode starts conducting before the collector junction does. This prevents the transistor from entering saturation. The base current in excess to what is needed to sustain the actual collector current flows directly to ground through the series combination of the forward-biased Schottky diode and emitter junction. Figure 14.2.4 shows how the combination of a Shottky diode and a bipolar transistor can be implemented. The Schottky diode consists of the metal contact that overlaps the lightly doped collector, whereas in the base region the metal to the P-type semiconductor resumes to an Ohmic contact. Such combination is currently used in Schottky logic, a family of fast bipolar logic circuits. The second way to avoid charge storage is to devise circuits that never operate in saturation. The switch shown in Fig. 14.2.5, which involves two transistors controlled by a pair of square waves with opposite polarities is a good example. When Q1 is on, Q2 is off or vice versa. Current is switched either left or right. Although the circuit looks like a differential pair, it operates in a quite different manner: the conducting transistor is in the common base configuration, while the other is blocked. Since the output current is taken from the collector of the common base transistor, the output impedance is very large. This means that the switch is a current-mode

FIGURE 14.2.5 A bipolar current switch.

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switch instead of a voltage-mode switch. Very short switching times are feasible this way for none of the two transistors ever saturates. Emitter-coupled logic (ECL) takes advantage of this circuit configuration.

MOS SWITCHES Insulated gate field-effects (IGFETs, also called MOS transistors) and junction field-effect transistors (JFETs) can be put to use in order to mimic switches. They resemble an ideal closed switch in series with a linear resistor when “on” and an open switch when “off.” The leakage current, however, is larger than with bipolar transistors. Static Characteristics When a field-effect transistor is turned on, its characteristics differ substantially from those of a bipolar switch. Since no residual emf in series with the switch is experienced, the transistor is comparable to a resistor whose conductance G is given by G = µCox

W (V − VT 0 − λV ) L G

(13)

where m is the mobility in the inversion layer, Cox the gate oxide capacitance per unit area, VG the gate-tosubstrate voltage, VT0 the gate threshold voltage under zero bias, V the source or drain voltage, and l a dimensionless factor that does take into account the so-called substrate effect (the value of l lies somewhere between 1.3 and 1.5). The dependance on source and drain voltages of the conductance G represents a problem that impairs severely the performances of MOS switches. Consider, for instance, a MOS switch in series with a grounded capacitor to implement a simple sample-and-hold circuit. Since the MOS transistor is similar to a resistor when its gate voltage is high, the circuit may be assimilated to an RC network with a time constant that varies like the reciprocal of the difference in the right part of Eq. (13). Hence, when the input voltage V equals (VG – VT0)/l the conductance becomes equal to zero and the switch resumes to an open circuit. In practice, V must be well below this limit to sample the input within a small enough time window. Single MOS switches are not favored therefore. For instance, in logic circuits, where the logic 1s and 0s are set by the power supply and ground, respectively, the logic high signal may be substantially corrupted and the speed reduced. CMOS switches are preferred threfore to single MOS switches. A typical CMOS transmission switch is shown in Fig. 14.2.6. It consists of the parallel combination of an

FIGURE 14.2.6 The complementary MOS switch.

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N-MOS and a P-MOS transistor controlled by complementary logic signals. The idea is simply to counterbalance the decreasing conductance of the N-MOS transistor when the input goes from low to high by the increasing conductance of the P-MOS transistor. Thanks to the parallel combination, the series resistance is kept large and almost unchanged for any input voltage. The same holds true as long as the time is constant. Dynamic Characteristics MOS transistors ignore charge storage phenomena for they are unipolar devices. Their transient behavior is controlled by the parasitic capacitances associated with their gate, source, and drain. Source and drain are reverse-biased junctions, which exhibit parasitic capacitances with respect to the substrate. The gate capacitance relates to the inversion layer and to the regions overlaping source and drain. These capacitances control the dynamic behavior of the switch in conjunction with the parasitics associated to the elements connected to the MOS transistor terminals. What happens with the inversion layer charge when the transistor is switched off is considered hereafter. Since charge cannot simply vanish, it must go somewhere, either to the source or drain or to both. This introduces generally a short spike in memoryless circuits that does not affect the performances significantly except at high frequency. In circuits that exhibit memory, like in the MOS sampling network discussed earlier, the impact is more serious. The part of the inversion layer charge left on the capacitive terminal is “integrated,” which leads to a DC offset. The charge partition problem in memory circuits is illustrated by the simple circuit shown in Fig 14.2.7, which consists of a MOS switch between two capacitors C1 and C2. We start from the situation where the voltages V1 and V2 across the capacitors are equal and no current is flowing through the transistor, supposed to be “on.” As soon as the gate voltage starts to decrease, the charge in the inversion layer tends to divide equally between MOS terminals for these are at the same potential. If the capacitors are not identical, a voltage difference starts to build up as soon as charge is being transferred. This causes current to flow in the MOS transistor,

FIGURE 14.2.7 The inversion layer charge divides between C1 and C2. after cutoff.

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FIGURE 14.2.8 Fraction of the inversion layer charge left in C2 after cutoff vs. the parameter B defined under Eq. (14).

which tend to reduce the voltage difference between the capacitors. This re-equilibration mechanism holds on as long as the gate voltage exceeds the effective threshold voltage although it is getting weaker and weaker as the transistor is nearing cut-off. When finally the MOS transistor is cut-off, a nonzero voltage difference is left over, which may be assimilated to an offset. The size of this offset is a function of several factors including the gate slewing-rate. It is obvious that an abrupt gate voltage step, which does not leave time for re-equilibration, will split the inversion layer charge equally between the two capacitors, whereas slow cut-off will tend to keep the voltages across the capacitors more alike. The problem is addressed in Ref. 19. The fraction of the total inversion layer charge that is stored in capacitor C2 versus the parameter B defined below is illustrated in Fig. 14.2.8: B = (VGon − VT )i

β aC2

(14)

VGon is the gate voltage prior to switching, VT the effective threshold voltage of the MOS transistor equal to (VT 0 + lVin), b the well-known factor mCoxW/L and a the gate voltage slewing rate defined as (VGon – VT0 ) divided by the fall time. Notice that fast switching yields small values of B, whereas long switching times lead to large values of B. When B is small the inversion layer charge divides equally. Voltage equalization tends to prevail when B is large, as can be found from the large differences experienced once the ratio C2 /C1 departs from one. Let us consider, for instance, a MOS transistor with a b equal to 10–4 A/V2, a gate capacitance CG of 0.1 pF, VGon and VT 0, respectively, equal to 5 and 0.7 V, a large capacitor C1 to mimic a voltage generator and a load capacitance C2 equal to 1 pF. For fall times between 1 ps and 1 ns, the factor B varies from 0.021 until 0.626. The offset voltage is large and varies little from 215 to only 200 mV since reequilibration cannot take place in such a short time. A 10 ns fall time reduces the final offset to 125 mV, and 100 ns, 1 ms, and 10 ms fall times yield, respectively, 41, 13, and 4 mV offset. In any case, these are still large offsets in terms of analog signals. To get smaller offsets the switching times must be very long. Hence, switching noise cannot be avoided as such. A second important problem is nonlinear distortion. Less time is needed to block the MOS transistor when the input voltage is close to VGon for the effective threshold voltage becomes quite large. The amount of charge stored in C2 varies with the magnitude of the input signal and the offset is thus a nonlinear replica of the input.

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FIGURE 14.2.9 Switching noise nonlinearity can be lessened by means of the transistor S2 in series with the storage capacitor.

This makes nonlinear distortion figures less than –70 dB hard to achieve unless a technique such as the one described hereafter is put to use. In the circuit illustrated in Fig 14.2.9, the lower end of capacitor C2 is tied to the ground by means of a second switch S2. During the acquisition time, both S2 and S1 are conducting. Sampling occurs when the switch S2 opens, shortly before S1 opens. Suppose switching times of both transistors are short enough to avoid charge re-equilibration. When S2 opens, the charge in the inversion layer divides equally between C2 and ground. When S1 opens, since C2 is already open-ended, the signal dependent charge of S1 has no other way out than to flow back to the generator. Thus, C2 stores only charge from S2, which is constant since the lower end of C2 is tied always to ground. In fact, one exchanges a signal-dependent offset against a constant offset, which does not impair linearity. This offset moreover can be compensated easily by taking advantage of differential architectures that turn a constant offset into a common mode signal, which is ignored further on.

TRANSISTOR SWITCHES OTHER THAN LOGIC GATES Transistor switches are extensively used in applications other than logic gates, covering a wide variety of both digital and analog applications. A typical illustration is the circuit converting the frequency of a signal into a proportional current, the so-called diode pump. This circuit (Fig. 14.2.10) consists of a capacitor C, two diodes D1 and D2, and a switch formed by a transistor T1 and a resistor R. The transistor is assumed to be driven periodically by a square-wave source, alternatively on and off. When T1 is blocked, the capacitor C charges through the diode D1, while D2 has no effect. As soon as the voltage across C has reached its steady-state value Ecc, T1 may be turned on abruptly. The voltage with respect to ground at point A becomes negative, and D1 is blocked, while D2 is forward-biased. The capacitor thus discharges itself in the load (in Fig. 14.2.10 an ammeter, but it could be any other circuit element that does not exhibit storage), allowing VA to reach 0 V before T1 is again turned FIGURE 14.2.10 Diode-pump circuit.

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off. The charge fed to the load thus amounts to CEcc coulombs. If we suppose that this process is repeated periodically, the average current in the load is given by I = fCEcc

(15)

where f represents the switching repetition rate. The diode-pump circuit provides a pulsed current whose average value is proportional to the frequency of the square-wave generator controlling the switching transistor T1. The proportionality would of course be lost if the load exhibited storage, e.g., if the load were a parallel combination of a resistor and a capacitor in order to obtain the average current. Using an operational amplifier, as shown in the right side of Fig. 14.2.10, circumvents the problem. The requirements on the switching transistor in this application are different and in many respects more stringent than for logic gates. The transistor in a logic circuit provides a way of defining two well-distinguished states, logic 1 and 0. Nothing further is required whether these states approach an actual short circuit or an open circuit. In the diode-pump circuit, however, the actual switching characteristics are important, since the residual voltage drop across the saturated transistor of Fig. 14.2.10 influences the charge transfer from C to the load, thereby also introducing unwanted temperature sensitivity. The main difference lies in the fact that while T1 is operated as a logical element, the purpose of the circuit actually is to deliver an analog signal. There are many other examples where the characteristics of switching transistors influence the accuracy of given circuits or instruments. An even more critical problem pertains to amplitude gating, since this class of applications requires switches which correctly transfer analog signals without introducing too much distortion. Furthermore, positive and negative signals must be transmitted equally well, and noise introduced by the gating signals must be minimized. Analog gating. A typical high-frequency gating network for analog signals is shown in Fig. 14.2.11. Gating is performed by means of the diode bridge in the center. All remaining circuitry controls the on-off switching. In order to transmit the analog signal, the current sources Qbar and Q must, respectively, be on and off. The current 2I from transistor T1 is split into two equal components, one that flows through T3, the other that flows vertically through T4 and the bridge. The second forward biases all the diodes. Current, moreover, is injected horizontally from the signal source, left, to the output terminal, right. Those in- and out-currents representing the analog signal are equal since the sum of all currents injected in the bridge must necessarily be zero and the vertical current components though the bridge are balanced by the network. Voltage drops across the diodes are supposed to compensate each other. When the path between source and load must be interrupted, the current sources Q and Qbar take opposite states. No current then flows through the bridge and the extra-currents supplied by T2 and T3 are diverted, respectively, through T6 and T5. The two vertical nodes of the bridge are now connected to low impedance nodes so that the equivalent high-frequency network between in- and output terminals consist actually of two branches, each with two small parasitic capacitances representing series reverse-biased diodes short circuited in their middle to ground. This ensures an excellent separation between in- and output terminals making this type of gating network well suited for the sampling of high-frequency signals, like those used in sampling oscilloscopes. Field-effect transistors also are extensively used to perform analog gating. A typical application is switched-capacitor filters. Figure 14.2.12a illustrates an elementary switched-capacitor network. In this circuit, the capacitor C is connected alternatively between the two terminals so that a charge C(V1 – V2) is transferred at each cycle. Hence, if the repetition rate is f, the switched-capacitor network allows an average direct-current C(V1 – V2)f to flow from one terminal to the other. It is thus equivalent to a resistor whose value is 1/Cf. If another capacitor Co is connected at the output port, an elementary sampled-data RC circuit is built with a time constant equal to Co/Cf. This time constant depends only on the clock frequency f and on the ratio of two capacitors. Hence, relatively large time constants can be achieved with good accuracy using very small capacitors and MOS transistor switches. In practice, MOS capacitors of a few picofarads match better than 0.1 percent. In addition, a slight modification (see Fig. 14.2.12b) of the circuit avoids the stray capacitance, which would otherwise affect the accuracy adversely. Hence, fully integrated switched-capacitor RC active filters can be designed to tight specifications, e.g., for telephone applications.

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FIGURE 14.2.11 High-frequency gating network.

FIGURE 14.2.12 (a) Switched capacitor resistor; (b) the circuit is not affected by stray capacitances.

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Source: STANDARD HANDBOOK OF ELECTRONIC ENGINEERING

CHAPTER 14.3

ACTIVE WAVEFORM SHAPING Paul G. A. Jespers

ACTIVE CIRCUITS Linear active networks used currently for waveshaping take advantage of negative or positive feedback circuits to improve the performance. Of the linear negative feedback active wave-shaping circuits, the operational amplifier-integrator is widely used.

RC OPERATIONAL AMPLIFIER-INTEGRATOR In Fig. 14.3.1 it is assumed that the operational amplifier has infinite input impedance, zero output impedance, and a high negative gain A. The overall transfer function is A 1 + p(1 − A)T

where T = RC

(1)

This function represents a first-order system with gain A and a cutoff frequency, which is approximately |A| times lower than the inverse of the time constant T of the RC circuit. In Fig. 14.3.1b the frequency response of the active circuit is compared with that of the passive RC integrator. The widening of the spectrum useful for integration is clearly visible. For instance, an integrator using an operational amplifier with a gain of 104 and an RC network having a 0.1 s time constant has a cutoff frequency as low as 1.6 MHz. In the time domain, the Taylor expansion of the amplifier-integrator response to the step function is V (t ) = E

 t  t t2 + −  1 − T  2! | A | T 3!(| A | T )2 

(2)

This shows that almost any desired degree of linearity of V(t) can be achieved by providing sufficient gain.

SWEEP GENERATORS4 Sweep generators (also called time-base circuits) produce linear voltage or current ramps versus time. They are widely used in applications such as oscilloscopes, digital voltmeters, and television. In almost all circuits the linearity of the ramp results from charging or discharging a capacitor through a constant-current source. The difference between circuits used in practice rests in the manner of realizing the constant-current source. Sweep generators may also be looked upon as integrators with a constant-amplitude input signal. The latter point of view shows that RC operational amplifier-integrators provide the basic structure for sweep generation. 14.25 Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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FIGURE 14.3.1 frequency.

(a) Operational amplifier-integrator; (b) gain vs. angular

Circuits delivering a linear voltage sweep fall into two categories, the Miller time base and bootstrap time base. A simple Miller circuit (Fig. 14.3.2) comprises a capacitor C in a feedback loop around the amplifier formed by T1. Transistor T2 acts like a switch. When it is on, all the current flowing through the base resistor RB is driven to ground, keeping T1 blocked, since the voltage drop across T2 is lower than the normal base-to-emitter voltage of T1. The output signal VCE of T1 is thereby clamped at the level of the power-supply voltage Ecc, and the voltage drop across the capacitor C is approximately the same. When T2 is turned off, it drives T1 into the active region and

FIGURE 14.3.2 Miller sweep generator: (a) circuit; (b) input and output vs. time.

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FIGURE 14.3.3 Bootstrap sweep generator: (a) circuit; (b) input and output vs. time.

causes collector current to flow through RL. The resulting voltage drop across RL is coupled capacitively to the base of T1, tending to minimize the base current; i.e., the negative-feedback loop is closed. The collector-to-emitter voltage VCE of T1 subsequently undergoes a linear voltage sweep downward, as illustrated in Fig. 14.3.2b. The circuit behaves in the same manner as the RC operational amplifier above. Almost all the current flowing through RB is derived through the feedback capacitor, and only a very small part is used for controlling the base of T1. The feedback loop opens when T1 enters into saturation, and the voltage gain of the amplifier becomes small. When T2 is subsequently turned on again, blocking T1 and recharging C through RL and the saturated switch, the output voltage VCE rises again according to an exponential with time constant RLC. Figure 14.3.3 shows a typical bootstrap time-base circuit. It differs from the Miller circuit in that the capacitor C is not a part of the feedback loop. Instead the amplifier is replaced by an emitter-follower delivering an output signal Vout which reproduces the voltage drop across the capacitor. C is charged through resistor RB from a floating voltage source formed by the capacitor C0(C0 is large compared with C). First, we consider that the switch T2 is on. Current then flows through the series combination formed by the diode D, the resistor RB, and the saturated transistor T2. The emitter follower T1 is blocked since T2 is saturated. Moreover, the capacitor C0 can charge through the path formed by the diode D and the emitter resistor RE, and the voltage drop across its terminals is equal to ECC. When T2 is cut off, the current through RB flows into the capacitor C, causing the voltage drop across its terminals to rise gradually, driving T1 into the active region. Because T1 is a unity-gain amplifier, Vout is a replica of the voltage drop across C. Since C0 acts as a floating dc voltage source, diode D is reverse-biased immediately. The current flowing through RB is supplied exclusively by C0. Since C0 >> C, the voltage across RB remains practically constant and equal to the voltage drop across C0 minus the base-to-emitter voltage of T1. Considering that the base current of T1 represents only a small fraction of the total current flowing through RB, it is evident that the charging of capacitor C occurs under constant-current and that therefore a linear voltage ramp is obtained as long as the output voltage of T1 is not clamped to the level of the power-supply voltage ECC. The corresponding output waveforms are shown in Fig. 14.3.3b. After T2 is switched on again, C discharges rapidly, causing Vout to drop, while the diode D again is forward-biased and the small charge lost by C0 is restored. In practice, C0 should be at least 100 times larger than C to ensure a quasi-constant voltage source. More detailed analysis of the Miller and bootstrap sweep generators reveals that they are in fact equivalent. We redraw the Miller circuit as shown at the left of Fig. 14.3.4. Remembering that the operation of the sweep generator is independent of which output terminal is grounded, we ground the collector of T1 and redraw the corresponding circuit. As shown at the right in the figure, this is a bootstrap circuit, so that the two circuits are equivalent. Any sweep generator can be regarded as a simple loop (Fig. 14.3.5) comprising a capacitor C delivering a voltage ramp, a loading resistor RB, and the series combination of two sources: a constant voltage source Ecc and a variable source whose emf E reproduces the voltage drop V across the capacitor. The voltage drop across

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FIGURE 14.3.4 Equivalency of the Miller and bootstrap sweep generators.

RB consequently remains constant and equal to Ecc making the loop current also constant. The voltage ramp consequently is given by E = V = (Ecc/RBC)t

(3)

Grounding terminal 1 yields the Miller network, while grounding terminal 2 leads to the bootstrap circuit. Since linearity is one of the essential features of sweep generators, we consider the equivalent networks represented in Fig. 14.3.6. Starting with the Miller circuit, we determine the impedance in parallel with C |A|(RB || h11)

(4)

where |A| is the absolute value of the voltage gain of the amplifier | A| = (h21/h11)RL Next, considering the bootstrap circuit, we calculate the input impedance of the unity-gain amplifier to determine the loading impedance acting on C. This impedance is FIGURE 14.3.5 Basic loop of sweep-generator circuits.

RLh21RB /(RB + h11)

(5)

which turns out to be the same as that given in Eq. (4); i.e., the two circuits are equivalent. To determine the degree of linearity it is sufficient to consider the common equivalent circuit of Fig. 14.3.7 and to calculate the Taylor expansion of the voltage V V=

 ECC  t t2 − . . . + t 1 − 2 RBC  2! | A| ( RB || h11 )C 3![| A| ( RB || h11 )C ] 

FIGURE 14.3.6 Equivalent forms of (a) Miller and (b) bootstrap sweep circuits.

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(6)

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FIGURE 14.3.7 Common equivalent circuit of sweep generators.

14.29

FIGURE 14.3.8 Typical sample-and-hold circuit.

The higher the voltage gain |A|, the better the linearity. Thus, an integrated operational amplifier in place of T1 leads to excellent performance in both the Miller and the bootstrap circuit. Voltage gains as high as 10,000 are easily obtained for this purpose.

SAMPLE-AND-HOLD CIRCUITS4 Sample-and-hold circuits are widely used to store analog voltages accurately over time ranging from microseconds to minutes. They are basically switched-capacitor networks, but since the analog voltage across the storage capacitor in the hold mode must be sensed under low impedance, a buffer amplifier is needed. Op-amps with FET input are commonly used for this purpose to minimize the hold-mode droop. The schematic of a widely used integrated circuit is shown in Fig. 14.3.8. Storage and readout are achieved by the FET input op-amp in the hold mode. During the acquisition time, transistor S2 is conducting, while S1 is blocked. Current is supplied by the voltage-dependent current source to minimize the voltage difference between input and output terminals. As soon as S1 and S2 change their states, Vout ceases to follow Vin and remains unchanged. The main requirements for sample-and-hold circuits are low hold-mode droop, short settling time in the acquisition mode, low offset voltage, and small hold-mode feedthrough. The hold-mode droop is dependent on the leakage current of the op-amp inverting node. Short settling times require high-slew-rate op-amps and large current-handling capabilities for both the current source and the op-amp. The offset voltage is determined by the differential amplifier which controls the current source. Finally, feedthrough is a result of imperfect isolation between the current source and the op-amp. For this reason, a double switch is preferred to a single series switch. Another important feedthrough problem is related to the unavoidable gate-to-source or drain-overlap capacitance of the MOS switch S2. When the gate-control signal is switched off, some small charge is always transferred capacitively to the storage capacitor and a small voltage step is superimposed on the output terminal when the circuit enters the hold state. Minimization of this effect can be achieved by increasing the ratio of the storage capacitance to the switch-overlap capacitance. Since the latter cannot be made equal to zero, the storage capacitance must be chosen sufficiently large, but this inevitably lengthens the settling time. One means of alleviating the problem is to compensate the switching charge because of the control signal by injection of an equal and opposite charge on the inverting input node of the op-amp. This can be achieved by means of a dummy transistor controlled by the inverted signal.

NONLINEAR NEGATIVE FEEDBACK WAVEFORM SHAPING The use of nonlinear devices with negative feedback accentuates the character of waveshaping networks. In many circumstances, this leads to an idealization of the nonlinear character of the devices considered. A good example of this is given by the ideal rectifier circuit. The negative-feedback loop in the circuit shown in Fig. 14.3.9 is formed by two parallel branches. Each comprises a diode connected in such manner that if V1 is positive, the current injected by resistor R1 flows

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through D1, and if V1 is negative, through D2. A resistor R2 is placed in series with D1, and the output voltage V2 is taken at the node between R2 and D1. Hence, V2 is given by –(R2/R1)V1 when V1 is positive, independently of the forward voltage drop across D1. When D1 is forward-biased, the voltage V at the output of the op-amp adjusts itself to force the current flowing through D1 and RL to be exactly the same as through R1. This means that V may be much larger than V2, especially when V2 (and thus also V1) is of the order of millivolts. In fact, V exhibits approximately the same shape as V2 plus an additional pedestal of approximately 0.6 to 0.7 V. Typical waveforms obtained with a sinusoidal voltage of a few tens of millivolts are shown in Fig. 14.3.10. FIGURE 14.3.9 The precision rectifier using negative The quasi-ideal rectification characteristic of this cirfeedback is almost an ideal rectifier. cuit is readily understood by considering the Norton equivalent network seen from R2 and D1 in series. In consists of a current source delivering the current V1/R1 in parallel with an almost infinite resistor |A| R, where A represents the voltage gain of the op-amp. Hence, the current flowing through the branch formed by R2 and D1 is delivered by a quasi-ideal current source, and the voltage drop across R2 is unaffected by the series diode D1. As for D2, it is required to prevent the feedback loop from being opened when V1 is negative. If this could happen, the artificial ground at the input of the op-amp would be lost and V2 would not be zero. Other negative-feedback configurations leading to very high output impedances are equally powerful in achieving ideal rectification characteristics. For instance, the unity-gain amplifier used in instrumentation has wide linear ac measurement capabilities (Fig. 14.3.11).

POSITIVE FEEDBACK WAVEFORM SHAPING Positive feedback is used extensively in bistable, monostable, and astable (free-running) circuits. Astable networks include free-running relaxation circuits whether self-excited or synchronized by external trigger pulses. Monostable and bistable circuits also exist, with one and two distinct stable states, respectively. The degree to which positive feedback is used in harmonic oscillators differs substantially from that of astable, monostable, or bistable circuits. In an oscillator the total loop gain must be kept close to 1. It needs to compensate only for small losses in the resonating tank circuit. In pulsed circuits, positive feedback permits

FIGURE 14.3.10 Waveforms of circuit in Fig. 14.3.9.

FIGURE 14.3.11 Feedback rectification circuit used in precision measurements.

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fast switching from one state to another, e.g., from cutoff to saturation and vice versa. Before and after these occur, the circuit is passive. Switching occurs in extremely short times, typically a few ns. After switching, the circuit evolves more slowly, approaching steady-state conditions. It is common practice to call the switching time the regeneration time and the time needed to reach final steady-state conditions the resolution time. The resolution time may range from tens of nanoseconds to several seconds or more, depending on the circuit. An important feature of triggered regenerative circuits is that their switching times are essentially independent of the steepness of the trigger-signal waveshape. Once instability is reached the transition occurs at a rate fixed by the total loop gain and the reactive parasitics of the circuit itself but independent of the rate of change of the trigger signal itself. Regenerative circuits, therefore, provide means of restoring short rise times. Positive-feedback pulse circuits are necessarily nonlinear. The most conventional way to study their behavior is to take advantage of piecewise-linear analysis techniques. Bistable Circuits5 (Collector Coupled) Two cascaded common-emitter transistor stages implement an amplifier with a high positive gain. Connecting the output to the input (Fig. 14.3.12) produces an unstable network known as the Eccles-Jordan bistable circuit or flip-flop. Under steady-state conditions one transistor is saturated and the other is blocked. Suppose the circuit of Fig. 14.3.12 has the value RL = 1 kΩ, R = 2.2 kΩ, and Ecc = 5 V. Suppose T1 is at cutoff, and consider the equivalent network connected to the base of T2. It can be viewed as an emf of 5 V and series resistances of 3.2 kΩ. The base current of T2 is given by IB2 = (5 – 0.7)/3.2 = 1.34 mA

(7)

T2 being saturated, the collector current is equal to ECC /RL or 5 mA. A current gain of 4 would be sufficient to ensure saturation of T2. Hence the collector-to-emitter voltage across T2 will be very small (VCE,sat), and consequently T1 will be blocked, as stated initially. The reverse situation, with T1 saturated and T2 cut off, is governed by identical considerations for reasons of symmetry. Two distinct stable states thus are possible. When one of the transistors is suddenly switched from one state to the opposite, the other transistor automatically undergoes an opposite transition. At a given time both transistors conduct simultaneously, which increases the loop gain from zero to a high positive value. This corresponds to the regenerative phase, during which the circuit becomes active. It is difficult to compute the regeneration time since the operating points of both transistors move through the entire active region, causing large variations of the small-signal parameters. Although determination of the regeneration time on the basis of a linear model is unrealistic and leads only to a rough approximation, we briefly examine this problem since it illustrates how the regeneration phase of unstable networks may be analyzed.

FIGURE 14.3.12 The Eccles-Jordan bistable circuit (flip-flop): (a) in the form of two cascaded amplifiers with output connected to input; (b) as customarily drawn, showing symmetry of connections.

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FIGURE 14.3.13 Flip-flop circuit showing capacitances that determine time constants.

First, we introduce two capacitors in parallel with the two resistors R. These capacitors provide a direct connection from collector to base under transient conditions and hence increase the high-frequency loop again. The circuit can now be described by the network of Fig. 14.3.13, which consists of a parallel combination of two reversed transistors without extrinsic base resistances (for calculation convenience) and with two load admittances Y which combine the load and resistive input of each transistor. Starting from the admittance matrix of one of the transistors with its load, we equate the determinant of the parallel combination

p(Cp + CTC ) I − pCTC VT

− pCTC pCTC + Y

(8)

to zero to find the natural frequencies of the circuit. This leads to pCp + (I/VT) + Y = 0

(9)

p(Cp + 4CTC) + Y – I/VT = 0

(10)

and

where Cp stands for the parallel combination of CTE and the diffusion capacitance tF I/VT . Only Eq. (10) has a zero with a real positive pole, producing an increasing exponential function with time constant approximately equal to t = (Cp + 4CTC) VT /I

(11)

Since the diffusion capacitance overrules the transition capacitances at high current, Eq. (11) reduces finally to tF. This yields extremely short switching times. For instance, a transistor with a maximum transition frequency fT of 300 MHz and a tF equal to 0.53 ns, exhibits a regeneration time (defined as the time elapsing between 10 and 90 percent of the total voltage excursion from cutoff to saturation or vice versa) equal to 2.2tF , or 1.2 ns. A more accurate but much more elaborate analysis, taking into account the influence of the extrinsic base resistance and nonlinear transition capacitances in the region of small-collector current, requires a computer simulation based on the dynamic large-signal model of the bipolar transistor. Nevertheless, Eq. (11) clearly pinpoints the factors controlling the regeneration time; the transconductance and unavoidable parasitic capacitances. This is verified in many other positive-feedback switching circuits. We consider next which factors control the resolution time still with the same numerical data. We suppose T1 initially nonconducting and T2 saturated. The sudden turnoff of T2 is simulated by opening the short-circuit switch S2 in Fig. 14.3.14a. Immediately, VCE2 starts increasing toward Ecc. The base voltage VBE1 of T1 consequently rises with a time constant fixed only by the total parasitic capacitance CT at the collector of T2 and base of T1 times the resistor RL. Hence this time constant is t1 = RLCT

(12)

This time is normally extremely short; e.g., a parasitic capacitance of 1 pF yields a time constant of 1 ns. The charge accumulated across C evidently cannot change, for C is much larger than CT . So VBE1 and VCE2 increase at the same rate. This situation is illustrated in Fig. 14.3.14b. When VBE1 reaches approximately 0.7 V, T1 starts conducting and a new situation arises, illustrated in Fig. 14.3.14 by the passage from (b) to (c). This is when regeneration actually takes place, forcing T1 to go into saturation very rapidly. With the regeneration period neglected, case (c) is characterized by the time constant t2 = (RL/R)C

(13)

For instance, if C is equal to 10 pF, t2 yields 7 ns. Although this time constant is much longer than t1, it is still not the longest, for we have not yet considered the evolution of VBE2.

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FIGURE 14.3.14 Piecewise analysis of flip-flop switching behavior. Transistor T2 is assumed to be on before (a). The opening of S2 simulates cutoff. The new steadystate conditions are reached in (c).

It is considered in Fig. 14.3.15, where the saturated transistor T1 is replaced by the closing of S1. The problem is the same as for the compensated attenuator. Since overcompensation is achieved, VBE2 undergoes a large negative-voltage swing almost equal to Ecc before climbing toward its steady-state value 0 V. The time constant of this third phase is given by t3 = RC

(14)

In the present case, t3 equals 22 ns. The voltage variations versus time of the flip-flop circuit thus far analyzed are reviewed in Fig. 14.3.16 with the assumption that the regeneration time is negligible. Clearly C plays a double role. The first is favorable since it ensures fast regeneration and efficiently removes excess FIGURE 14.3.15 The longest time constant is expericharges from the base of the saturated transistor, but the enced when T1 is turned on. This is simulated by the closecond is unfavorable since it increases the resolution time sure of switch S1. and sets an upper limit to the maximum repetition rate at which the flip-flop can be switched. The proper choice of C as well as of RL and R must take this fact into consideration. Small values of the resistances make high repetition rates possible at the price of increased dc power consumption.

INTEGRATED-CIRCUIT FLIP-FLOPS The Eccles-Jordan circuit (Fig. 14.3.12) is the basic structure of integrated bistable circuits. The capacitor C is not present. The integrated flip-flop can be viewed as two cross-coupled single-input NOR or NAND circuits. In fact, integrated flip-flops vary only in the way external signals act upon them for control purposes. A typical example is given in Fig. 14.3.17 with the corresponding logic-symbol representation. The triggering inputs are called set S and reset R terminals. Transistors T3 and T4 are used for triggering. The truth for NOR and NAND bistable circuits are NOR bistable

NAND bistable

R

S

Q1

Q2

Line

Q1

Q2

Line

0 0 1 1

0 1 0 1

Q 1 0 0

Q 0 1 0

1 2 3 4

1 1 0 Q

1 0 1 Q

5 6 7 8

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FIGURE 14.3.16 Voltage variations vs. time of flipflop circuit.

Lines 1 and 8 correspond to situations where the S and R inputs are both inactive, leaving the bistable circuit in one of its two possible states indicated in the tables above by the letters Q and Q (Q may be either 1 or 0). If a specified output state is required, a pair of adequate complementary dc trigger signals is applied to the S and R inputs simultaneously. For instance, if the output pair is to be characterized by Q1 = 1 and Q2 = 0, the necessary input combination, for NOR and NAND bistable circuits, is S = 1 and R = 0. Changing S back from 1 to 0 does not change anything in the output state in the NOR bistable. The same is true if S is made equal to 1 in the NAND bistable. In both cases, the flip-flop exhibits infinite memory of the stored state. The name sequential circuit is given to this class of networks as opposed to previous circuits, which are called combinational circuits. Lines 4 and 5 must be avoided, for the passage from line 4 to line 1 or from line 5 to line 8 leads to uncertainty regarding the final state of the bistable circuit. In fact, the final transition is entirely out of the control of the input, since in both cases it results solely from small imbalances between transistor parasitics that allow faster switching of one or another inverter.

SYNCHRONOUS BISTABLE CIRCUITS 4 Sequential networks may be either synchronous or asynchronous. The asynchronous class describes circuits in which the application of an input control signal triggers the bistable circuit immediately. This is true of the circuits thus far considered. In the synchronous class, changes of state occur only at selected times, after a clock signal has occurred. Synchronous circuits are less sensitive to hazard conditions. Asynchronous circuits may be severely troubled by this effect, which results from differential propagation delays. These delays, although individually very small (typically of the order of a few nanoseconds), are responsible for introducing skew between signals that travel through different logic layers. Unwanted signal combinations may therefore appear for short periods and be interpreted erroneously.

FIGURE 14.3.17 DC-coupled version of flip-flop, customarily used in integrated-circuit versions of this circuit.

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Synchronous circuits do not suffer from this limitation because they conform to the control signals only when the clock pulse is present, usually after the transient spurious combinations are over. A simple synchronous circuit is shown in Fig. 14.3.18. The inhibition action provided by the absence of the clock signal is provided by a pair of input AND circuits. Otherwise nothing is changed with respect to the bistable network. A difficulty occurs in cascading bistable circuits, to achieve FIGURE 14.3.18 Synchronous flip-flop. time-division. Instead of each circuit controlling its closest neighbor, when a clock signal is applied, the set and reset signals of the first bistable jump from one circuit to the next, traveling throughout the entire chain in a time which may be shorter than the duration of the clock transition. To prevent this, a time delay must be introduced between the gating NAND circuits and the actual bistable network, so that changes of state can occur only after the clock signal has disappeared. One approach is to take advantage of storage effects in bipolar transistors, but the so-called master-slave association, shown in Fig. 14.3.19, is preferred. In this circuit, intermediate storage is realized by an auxiliary clocked bistable network controlled by the complement of the clock signal. The additional circuit complexity is appreciable, but the approach is practical in integrated-circuit technology. The master-slave bistable truth table can be found from that of the synchronous circuit in Fig. 14.3.18, which in turn can be deduced from the truth table given in the previous section. One problem remains, however, the forbidden 1,1 input pair, which is responsible for ambiguous states each time the clock goes to zero. To solve this problem, the JK bistable was introduced (see Fig. 14.3.20). The main difference is the introduction of a double feedback loop. Hence the S and R inputs become, respectively, JQ and KQ. As long as the J and K inputs are not simultaneously equal to 1, nothing in fact is changed with respect to the behavior of the SR synchronous circuit. When J and K are both high, the cross-coupled output signals fed back to the input gates cause the flip-flop to toggle under control of the clock signal. The truth table then becomes

J

K

Qn +1

0 1 0 1

0 0 1 1

Qn 1 0 Qn

Line 1 2 3 4

Qn+1 stands for Q at the clock time n + 1 and Qn for Q at clock time n. Lines 1 to 3 match the corresponding lines of the NOR bistable truth table. Line 4 indicates that state transitions occur each time the clock signal goes from high to low. The corresponding logic equation of the JK flip-flop, therefore, is Qn + 1 = JQn + KQn

FIGURE 14.3.19 Master-slave synchronous flip-flop.

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FIGURE 14.3.20 JK Flip-flop.

When only one control signal is used, J, for instance, and K is obtained by negation of the J signal, a new type of bistable is found, which is called the D flip-flop. The name given to the J input is D. Since K is equal to J, Eq. (15) reduces to Qn+1 = D

(16)

Hence, in this circuit the output is set by the input D after a clock cycle has elapsed. Notice that the flipflop is insensitive to changes of D occurring while the clock is high. D flip-flops without the master-slave configuration also exist, but their output state follows the D signal if changes occur while the clock is high. These bistables can be used to latch data. Several D flipflops controlled by the same clock form a register for data storage. The clock signal then is called an enable signal. Bistable Circuits, Emitter-Coupled Bistables (Schmitt Circuits)6 In the basic Schmitt circuit represented in Fig. 14.3.21 bistable operation is obtained by a positive-feedback loop formed by the common-base and common-collector transistor pair (respectively T1 and T2). The Schmitt circuit can be considered as a differential amplifier with a positive-feedback loop, which is a series-parallel association. Emitter-coupled bistables are fundamentally different from Eccles-Jordan circuits, since no transistor saturates in either of the two stable states. Storage effects therefore need not be considered. The two permanent states are examined in Fig. 14.3.22. In each state, (a) as well as (b), one transistor operates in the common-collector configuration while the other is blocked. In Fig. 14.3.22a, the collector voltage VC1 of T1 and base voltage VB2 of T2 are given by VC1 = Ecc FIGURE 14.3.21 Emitter-coupled Schmitt circuit, showing positive-feedback loop.

VB 2

R1 + R2 R1 + R2 + Rc

R1 = Ecc = Vh R1 + R2 + Rc

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FIGURE 14.3.22 Execution of transfer in Schmitt circuit: (a) with T1 blocked; (b) with T1 conducting.

When the other stable state (b) is considered, VC1 = ( Ecc − Rc I )

VB 2

R1 + R2 R1 + R2 + Rc

R1 = ( Ecc − Rc I ) = Vl R1 + R2 + Rc

(18)

The situation depicted in Fig. 14.3.22 remains unchanged as long as the input voltage VB1 applied to T1 is kept below the actual value Vh. In the other state (b), T2 will be off as long as VB1 is larger than Vl. A range of input voltages between Vh and Vl thus exists where either of the two states is possible. To alleviate the ambiguity, let us consider an input voltage below the smallest of the two possible values of VB2 so that the transistor T1 necessarily is blocked. This corresponds to the situation of Fig. 14.3.22a. Now let the input voltage be gradually increased. Nothing will happen until VB1 approaches Vh. When the difference between the two base voltages is reduced to 100 mV or less, T1 will start conducting and the voltage drop across Rc will lower VB2. The emitter current of T2 will consequently be reduced, and more current will be fed back to T1. Hence, an unstable situation is created, which ends when T1 takes over all the current delivered by the current source and T2 is blocked. Now the situation depicted in Fig. 14.3.22b is reached. The base voltage of T2 becomes Vl, and the input voltage may either continue to increase or decrease without anything else happening as long as VB1 has not reached Vl. When VB1 approaches Vl, another unstable situation is created causing the switching from (b) to (a). Hence, the input-output characteristic of the Schmitt trigger is as shown in Fig. 14.3.23 with a hysteresis loop. Schmitt triggers are suitable for detecting the moment when an analog signal crosses a given DC level. They are widely used in oscilloscopes to achieve time-base synchronization. This is illustrated in Fig. 14.3.24, which FIGURE 14.3.23 Input-output characteristic of Schmitt shows a periodic signal triggering a Schmitt circuit and the circuit, showing rectangular hysteresis. corresponding output waves. It is possible to modify the switching levels by changing the operating points of the transistors electrically, e.g., by modifying the current delivered by the current source. In many applications, the width of the hysteresis does not play a significant role. The width can be decreased, however, by increasing the attenuation of the resistive divider formed by R1 and R2, but one should not go below 1 V because sensitivity to variations in circuit components or supply voltage may occur.

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FIGURE 14.3.24 Trigger input and output voltage of Schmitt circuit; solid line delivered by a current source; broken line delivered by a resistor.

FIGURE 14.3.25 Bipolar integrated version of a comparator.

Furthermore, the increased attenuation in the feedback loop must be compensated for by a corresponding increase in the differential amplifier gain. Otherwise the loop gain may fall below 1, preventing the Schmitt circuit from functioning. A hysteresis of a few millivolts is therefore difficult to achieve. A much better solution is to use comparators instead of Schmitt triggers when hysteresis must be avoided. A typical integrated comparator is shown in Fig. 14.3.25. It is a medium-gain amplifier (103 to 104) with a very fast response ( a few nanoseconds) and an excellent slew rate. Comparators are not designed to be used as linear amplifiers like op-amps. Their large gain-bandwidth product makes them inappropriate for feedback configurations. They inevitably oscillate in any type of closed loop. In the open-loop configuration they behave like clipping circuits with an exceedingly small input range, which is equal to the output-voltage swing, usually 5 V, divided by the gain. The main difference compared with Schmitt triggers is the fact that comparators do not exhibit hysteresis. This makes a significant difference when considering very slowly varying input signals. In the circuit of Fig. 14.3.21 the common-emitter current source can be replaced by a resistor. This solution introduces some common-mode sensitivity. The output signal does not look square, as shown in Fig 14.3.24 by the dashed lines. If unwanted, this effect can be avoided by taking the output signal at the collector of T2 through an additional resistor, since the current flowing through T2 is constant. An additional advantage of the latter circuit is that the output load does not interfere with the feedback loop.

INTEGRATED-CIRCUIT SCHMITT TRIGGERS7 Basically a Schmitt trigger can always be implemented by means of an integrated differential amplifier and an external positive-feedback loop. If the amplifier is an op-amp, poor switching characteristics are obtained unless an amplifier with a very high slewing rate is chosen. If a comparator is considered instead of an op-amp, switching will be fast but generally the output signal will exhibit spurious oscillations during the transition period. The oscillatory character of the output signal is due to the trade-off between speed and stability which is typical of comparators compared with op-amps. Any attempt to create a dominant pole, in fact, inevitably would ruin their speed performance.

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The integrated-circuit counterpart of the Schmitt trigger is shown in Fig. 14.3.26. It consists of two comparators connected to a resistive divider formed by three equal resistors R. Input terminals 2 and 6 are normally tied together. The output signals of the two comparators control a flip-flop. When the input voltage is below Ecc/3, the flip-flop is set. Similarly when the input voltage exceeds 2Ecc/3, the circuit is reset. The actual state of the flip-flop in the range between Ecc/3 and 2Ecc/3 will depend on how the input voltage enters the critical zone. For instance, if the input voltage starts below Ecc/3 and is increased so that it changes the state of comparator C2 but not that of comparator C1, both S and R are equal to 1 and the flip-flop remains set. The FIGURE 14.3.26 Precision integrated Schmitt trigger. state changes only if the input voltage exceeds the limit 2Ecc/3. Similarly, if the input voltage is lowered, setting the flip-flop will occur only when Ecc/3 is reached. Hence the circuit of Fig. 14.3.26 behaves like a Schmitt trigger with a hysteresis width Ecc/3 depending only on the resistive divider 3R and the offset voltages of the two comparators C1 and C2. This circuit can therefore be considered as a precision Schmitt trigger and is widely used as such.

Monostable and Astable Circuits (Discrete Components)4 Figures 14.3.27 and 14.3.28 show monostable and astable collector-coupled pairs, respectively. The fundamental difference between these circuits and bistable networks lies in the way DC biasing is achieved. In Fig. 14.3.27a, T2 is normally conducting except when a negative trigger pulse drives this transistor into the cutoff region. T1 necessarily undergoes the inverse transition, suddenly producing a large negative voltage step at the base of T2 shown in Fig. 14.3.27b. VBE2, however, cannot remain negative since its base is connected to the positive-voltage supply through the resistor R1. The base voltage rises toward Ecc, with a time constant R1C. As soon as the emitter junction of T2 becomes forward-biased, the monostable circuit changes its state again and the circuit remains in that state until another trigger signal is applied. The time T between the application of a trigger pulse and the instant T2 saturates again is given approximately by T = t ln 2 = 0.693t

FIGURE 14.3.27 Monostable collector-coupled pair: (a) circuit; (b) output vs. time characteristics.

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FIGURE 14.3.28 istics.

Astable (free-running) flip-flop: (a) circuit; (b) output vs. time character-

where t = R1C. The supply voltage ECC is supposed to be large compared with the forward-voltage drop of the emitter junction of T2 for this expression to apply. The astable collector-coupled pair, or free-running multivibrator (Fig. 14.3.28), operates according to the same scheme except that steady-state conditions are never reached. The base-bias networks of both transistors are connected to the positive power supply. The period of the multivibrator thus equals 2T if the circuit is symmetrical, and the repetition rate F, is given by Fr =

1 0.7 ≈ 2 τ ln 2 RC

(20)

INTEGRATED MONOSTABLE AND ASTABLE CIRCUITS7 The discrete component circuits discussed above are interesting only because of their inherent simplicity and exemplative value. Improved means to integrate monostable and astable are shown below. The circuit shown in Fig. 14.3.29 is derived from the Schmitt trigger. It is widely used in order to implement high-frequency (100 MHz) relaxation oscillators. The capacitor C provides a short circuit between the emitters of the two transistors, closing the positive-feedback loop during the regeneration time. As long as one or the other of the two transistors is cut off, C offers a current sink to the current source connected to the emitter of the blocked transistor. The capacitor thus is periodically charged and discharged by the two current sources, and the voltage across its terminal exhibits a triangular waveform. The collector current of T1 is either zero or I1 + I2, so that the resulting voltage step across Rc is (RB || RC)(I1 + I2). Since the base of T2 is directly connected to the collector of T1, the same voltage step controls T2 and determines the width of the input hysteresis, i.e., the maximum amplitude of the voltage sweep across C. The period of oscillation is computed from

FIGURE 14.3.29 Discrete-component emitter-coupled astable circuit.

1 1 T = C  +  ( RB || RC )( I1 + I 2 )  I1 I 2 

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FIGURE 14.3.30 Waveforms of circuit in Fig. 14.3.29.

When, as is usual, both current sources deliver equal currents, the expression for T reduces to T = 4(RB || RC)C

(22)

T does not depend, in this case, on the amplitude of the current because changes in current in fact modify the amplitude and the slope of the voltage sweep across C in the same manner. A review of the waveforms obtained at various points of the circuit is given in Fig. 14.3.30. Integrated monostable and astable circuits can be derived from the precision Schmitt trigger circuit shown in Fig. 14.3.26. The monostable configuration is illustrated in Fig. 14.3.31. Under steady-state conditions, the flip-flop is set and the transistor T saturated. The input voltage Vin is kept somewhere between the two triggering levels Ecc/3 and 2Ecc/3. To initiate the monostable condition, it is sufficient that Vin drops below Ecc/3 even for a very short time, in order to reset the flip-flop and prevent T from conducting. The current flowing through R1 then charges C until the voltage VC reaches the triggering level

FIGURE 14.3.31 Monostable precision Schmitt trigger: (a) circuit; (b) waveforms.

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FIGURE 14.3.32 Astable precision Schmitt trigger: (a) circuit; (b) waveforms.

2Ecc/3. Immediately thereafter, the circuit switches to the opposite state and transistor T discharges C. The monostable circuit remains in that state until a new triggering pulse Vin is fed to the comparator C2. The waveforms Vin, VC, and Vout are shown in Fig. 14.3.31b. This circuit is also called a timer because it provides constant-duration pulses, triggered by a short input pulse. A slight modification of the external control circuitry may change this monostable into a retriggerable timer. The astable version of the precision Schmitt trigger is shown in Fig. 14.3.32. Its operation is easily understood from the preceding discussion. The capacitor C is repetitively discharged through R2 in series with the saturated transistor T and recharged through R1 + R2. The voltage VC therefore consists of two distinct exponentials clamped between the triggering levels Ecc/3 and 2Ecc/3. The frequency is equal to 1.44/(R1 + 2R2)C. Because of the precision of the triggering levels (10–3 to 10–4) short-term frequency stability can be achieved.

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Source: STANDARD HANDBOOK OF ELECTRONIC ENGINEERING

CHAPTER 14.4

DIGITAL AND ANALOG SYSTEMS Paul G. A. Jespers

INTEGRATED SYSTEMS With the trend toward ever higher integration levels, an increasing number of ICs combine some of the circuits seen before in order to build large systems, digital as well as analog, or mixed, such as wave generators and A/D and D/A converters. Some of these are reviewed below.

COUNTERS4,7 To count any number N of events, at least k flip-flops are required, such that 2k ≥ N

(1)

Ripple Counters JK flip-flops with J and K inputs equal to 1 are divide-by-2 circuits. Hence, a cascade of k flip-flops with each output Q driving the clock of the next circuit forms a divide-by-2k chain, or a binary counter (see Fig. 14.4.1). The main drawback of this circuit is its increasing propagation delay with k. When all the flip-flops switch, the clock signal must ripple through the entire counter. Hence, enough time must be allowed to obtain the correct count. Furthermore, the delays between the various stages of the counter may produce glitches, e.g., when parallel decoding is achieved. Synchronous Binary Counters Minimization of delay and glitches can be achieved by designing synchronous instead of asynchronous counters. In a synchronous counter all the clock inputs of the JK flip-flops are driven in parallel by a single clock signal. The control of the counter is achieved by driving the J input by means of the AND combination of all the preceding Q outputs, as shown in Fig. 14.4.2. In this manner, all state changes occur on the same trailing edge of the clock signal. The only remaining requirement is to allow enough time between clock pulses for the propagation through a single flip-flop and an AND gate. The drawback of course is increased complexity with the order k. Divide-by-N Synchronous Counters When the number N of counts cannot be expressed in binary form, auxiliary decoding circuitry is required. This is true also for counters that provide truncated and irregular count sequences. Their synthesis is based 14.43 Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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FIGURE 14.4.1 Ripple counter formed by cascading flip-flops.

FIGURE 14.4.2 Synchronous counter.

on the so-called transition tables. The basic transition table of the JK flip-flop is derived easily from its truth table. Qn

Qn +1

J

K

Line

0 0 1 1

0 1 0 1

0 1 × ×

× × 1 0

1 2 3 4

Line 1, for instance, means that in order to maintain Q equal to 0 after a clock signal has occurred, the J input must be made equal to 0 whatever K may be (X stands for “don’t care”). This can be easily verified with the truth table (lines 1 and 3). Hence, the synthesis of a synchronous counter consists simply of determining the J and K inputs of all flip-flops that are needed to obtain a given sequence of states. Once the J and K truth tables have been obtained, classical minimization procedures can be used to synthesize the counter. For instance, consider the design of a divide-by-5 synchronous counter for which a minimum of three flip-flops is required. First, the present and next states of the flip-flops are listed. Then the required J and K inputs are found by means of the JK transition table: Present state Q3 Q2 Q1

Next state Q3 Q2 Q1

J3

K3

0 0 0 0 1

0 0 0 1 0

0 0 0 1 ×

× × × × 1

0 1 2 3 4

0 0 1 1 0

0 1 0 1 0

0 1 1 0 0

1 0 1 0 0

JK inputs J2 K2 0 1 × × 0

× × 0 1 ×

J1

K1

1 × 1 × 0

× 1 × 1 ×

Using Karnaugh minimization techniques, one finds J3 = Q1Q2 K3 = 1 K2 = Q1 J2 = Q1 J1 = Q3 K1 = 1 The corresponding counter is shown in Fig. 14.4.3. With this procedure it is quite simple to synthesize a decimal counter with four flip-flops. The same method also applies to the synthesis with D flip-flops.

Up-Down Counters Upward and downward counters differ from the preceding ones only by the fact that an additional bit is provided to select the proper J and K controls for up or down count. The same synthesis methods are applicable. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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Presettable Counters Since a counter is basically a chain of flip-flops, parallel loading by any number within the count sequence is readily possible. This can be achieved by means of the set terminals. Hence, the actual count sequence can be initiated from any arbitrary number.

SHIFT REGISTERS3 Shift registers are chains of flip-flops connected so that the state of each can be transferred to its next left or right neighbor under control of the clock signal. Shift registers can be built with JK as well as D flip-flops. An example of a typical bidirectional shift register is shown in Fig. 14.4.4. Shift registers, such as counters, may be loaded in parallel or serial mode. This is also true for reading out. In MOS technology, dynamic shift registers can be implemented in a simple manner. Memorization of states occurs electrostatically rather than by means of flip-flops. The information is stored in the form of charge on the gate of an MOS transistor. The main advantage of MOS dynamic shift registers is area saving resulting from the replacement of flip-flops by single MOS transistors. A typical dynamic 2-phase shift register (Fig. 14.4.5) conFIGURE 14.4.3 Synchronous divide-by-5 circuit. sists of two cascaded MOS inverters connected by means of series switches. These switches, T3 and T6, are divided into two classes: odd switches controlled by the clock f1, and even switches controlled by f2. The control signals determine two nonoverlapping phases. When f1 turns on the odd switches, the output signal of the first inverter controls the next inverter but T6 prevents the information from going further. When f2 turns on, data are shifted one half cycle further. The signal jumps from one inverter to the next until it reaches the last stage.

FIGURE 14.4.4 Bidirectional shift register.

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FIGURE 14.4.5 A 2-phase MOS dynamic shift register.

MULTIPLEXERS, DEMULTIPLEXERS, DECODERS, ROMS, AND PLAS3–8 A multiplexer is a combinatorial circuit that selects binary data from multiple input lines and directs them to a single output line. The selected input line is chosen by means of an address word. A representation of a 4-input multiplexer (MUX) is shown in Fig. 14.4.6 as well as a possible implementations. MOS technology lends itself to the implementation of multiplexers based on pass transistors. In the example illustrated by Fig. 14.4.7 only a single input is connected to the output through two conducting series transistors according to the S1 S0 code address. Multiplexers may be used to implement canonical logical equations. For instance, the 4-input MUX considered above corresponds to the equation y = x 0 S0 S1 + x1S0 S1 + x 2 S0 S1 + x3S0 S1

FIGURE 14.4.6 A 4-input multiplexer (MUX) with a 2-bit (S1S0) address.

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FIGURE 14.4.7 (a) NMOS and (b) CMOS implementations of multiplexers.

Hence, logical functions of the variables S0 and S1 can be synthesized by means of multiplexers. For instance, an EXOR circuit corresponds to x0 = x3 = 0 and x1 = x2 = 1. Demultiplexers (DEMUX) perform the inverse passage from a single input line to several output lines under the control of an address word. They implement logic functions that are less general than those performed by multiplexers because only miniterms are involved. The symbolic representation of a 4-input DEMUX is shown in Fig. 14.4.8 with a possible implementation. The MUX represented in Fig. 14.4.7 may seem attractive for the purpose to achieve demultiplexation but one should not forget that when a given channel is disconnected, the data across the corresponding output remain unchanged. In a DEMUX, unselected channels should take a welldefined state, whether 0 or 1.

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FIGURE 14.4.8 A 4-output demultiplexer (DEMUX).

A decoder is a DEMUX with a constant input. Decoders are currently used to select data stored in memories. Figure 14.4.9 shows a simple NMOS decoder. In this circuit, all unselected outputs are grounded while the selected row is at the logical 1. Any row may be viewed as a circuit implementing a miniterm. For instance, the first row corresponds to y0 = S1 + S0 = S1 S0

FIGURE 14.4.9 An NMOS decoder circuit.

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FIGURE 14.4.10 A ROM memory.

When a decoder drives a NOR circuit, a canonical equation is obtained again. Figure 14.4.10 shows a decoder driving several NOR circuits which are implemented along vertical columns. This circuit is called a read-only memory (ROM). One can easily recognize an EXOR function ( y1) and its complement (y0) in the example. The actual silicon implementation strictly follows the pattern illustrated by Fig. 14.4.10. Notice that the decoder block and ROM column block both have the same structure after turning them by 90°. When a ROM is used to implement combinatorial logic, the number of outputs usually is restricted to only those miniterms which are necessary to achieve the desired purpose. The ROM is then called a programmable logic array (PLA) ROMs as well as PLAs are extensively used in integrated circuits because they provide the means to implement logic in a very regular manner. They contribute substantially to area minimization and lend themselves to automatic layout, reducing design time (silicon compilers). A large number of functions can be implemented by means of the circuits described above: circuits converting the format of digital data, circuits coding pure binary into binary-coded decimal (BCD) or decimal data, and so forth. The conversion from a 4-bit binary-coded number into a 7-segment display by means of a PLA is illustrated by Fig. 14.4.11. All the required OR functions are obtained by means of the right-plane decoder, while the left one determines the AND functions (they are called, respectively, OR-AND planes). In applications where multiple-digit displays are required, rather than repeating the circuit of Fig. 14.4.11 as many times as there are digits, a combination of MUX and DEMUX circuit and a single PLA can be used. An example is shown in Fig. 14.4.12. The 4-input codes representing 4 digits are multiplexed in a quadruple MUX in order to drive a PLA 7-segment generator. Data appear sequentially on the seven common output lines connected to the four displays. Selection of a given display is achieved by a decoder driven by the same address as the MUX circuit. If the cyclic switching is done at a speed of 60 Hz or more, the human eye cannot detect the flicker.

MEMORIES 3 Memories provide storage for large quantities of binary data. Individual bits are stored in minimum-size memory cells that can be accessed within two- or three-dimensional arrays. Read-only memories (ROMs) provide access only to permanently stored data. Programmable ROMs (PROMs) allow data modifications only during special write cycles, which occur much less frequently than readout cycles. Random access memories (RAMs) provide equal opportunities for read and write operations. RAMs store data in bistable circuits (flip-flops, SRAMs), or in the form of charge across a capacitor (DRAM).

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FIGURE 14.4.11 A 7-segment PLA driver.

Static Memories Static memory cells are arrays of integrated flip-flops. The state of each flip-flop represents a stored bit. Readout is achieved by selecting a row (word-line: WL) and a column (but or bit-lines: BL) crossing each other over the chosen cell. Writing occurs in the same manner. A typical six-transistor MOS memory cell is shown in Fig. 14.4.13. The word-line controls the two transistors that connect the flip-flop to the read-write bus (BL and BLbar). In order to read out nondestructively the data stored in the cell, the read-write bus must be precharged. The inverter that is in the low-state discharges the corresponding bit-line. Writing data either confirms or changes the state of the flip-flop. When a change must happen, the high bit-line must overrule the corresponding low-state inverter, while the low bit-line simply discharges the output node of the high inverter. The second event takes less time than the first for the big differences between bus and inverter node capacitances. Bus capacitances are at least 10 times larger than cell node capacitances. The rapid discharge of the high inverter output node blocks the other half of the flip-flop before it has a chance to discharge the high bus. In order to prevent a read cycle from Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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FIGURE 14.4.12 A 4-digit, 7-segment multiplexed display.

becoming a write-cycle, it is important to equalize the voltages of the bit-lines prior to any attempt to read out. This is achieved by means of a single equalizing transistor on top of the read-write bus. This transistor shorts the two bit-lines for just long enough time to neutralize any bit-line voltage difference whatever the mean voltage may be. The pull-up circuitry precharging the read-write bus accommodates conflicting requirements. It must load the bitlines as fast as possible but not counteract the discharge of the bit-line, which is tied to the low data during read out. Usually, the pull-up circuitry is clocked and driven by the same clock that controls the equalizing transistor. Cell size and power consumption are the two key items that determine the performances and size of present memory chips which may count as much as several million transistors. Cell sizes have shrunken continuously until they are a few tens of microns square. Static power is minimized by using CMOS instead of resistively loaded inverters. Most of the power needed is to provide fast load and discharge cycles of the line capacitances. Therefore a distinction is generally made between standby and active conditions. The load-discharge processes imply short but very large currents. The design of memories (static as well as dynamic) has always been at the forefront of the most advanced technologies.

FIGURE 14.4.13 The basic six-transistor circuit of a static MOS memory cell.

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FIGURE 14.4.14 The one-transistor MOS memory cell; (a) IC implementation; (b) equivalent circuit.

Dynamic Memories8,9 The trend toward ever larger memory chips has led to the introduction of single transistor memory cells. Here the word-line controls the gate of the MOS switch that connects the single bit line to a storage capacitor (Fig. 14.1.14). Charge is pumped from (or fed back to) the bit-line by properly choosing the voltage of the bit-line. The actual data consist of charge (or absence of charge) stored in the capacitor in the inversion layer below a field plate. Typical storage capacitances are 100 to 50 fF. The useful charge is quite small, around 0.1 or 0.2 pC. In order to read data, this charge is transferred to the bit-line capacitance, which is usually one order of magnitude larger. The actual voltage change of the bit-line is thus very small, typically 100 to 200 mV. In order to restore the correct binary data, amplification is required. The amplifier must fulfill a series of requirements: It must fit in the small space between cells, be sensitive and respond very rapidly, but also distinguish data from inevitable switching noise injected by the overlap capacitance of the transistor in series with the storage capacitor. To solve this problem, dynamic memories generally use two bit-line output lines instead of a single one. Read-out of a cell always occurs in the same time as the selection of a single identical dummy cell. This compensates switching noises as far as tracking of parasitic capacitances of both switching transistors is achieved. The key idea behind the detection amplifier is the metastable state of a flip-flop. The circuit is illustrated in Fig. 14.4.15. Before read-out, the common source terminal is left open. Hence, assuming the bit-line voltages are the same, the flip-flop behaves like two cross-coupled diode-connected transistors.

FIGURE 14.4.15 The readout amplifier of dynamic one-transistor-per-cell MOS memories consists of a flip-flop in the metastable state in order to enhance sensitivity and speed and to minimize silicon area.

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The common source voltage adjusts itself to the pinch-off voltage of the transistors. After read-out has occurred, a small voltage imbalance is experienced between bit-lines. The sign of this imbalance is determined by the actual data previously stored in the cell. If then the common source node voltage is somewhat reduced, one of the two transistors becomes slightly conducting while the other remains blocked. The conducting transistor slightly discharges the bit-line with the lowest voltage, increasing the voltage imbalance. The larger this difference, the faster the common source node can be lowered without risk to switch-on of the second transistor. After a short time, the imbalance is large enough to connect the common source to ground. The final state of the flip-flop reproduces the content of the selected cell. Notice that data read during the read-out cycle are now available for rewriting in the cell. Permitting the transistor in series with the storage capacitor to conduct longer performs automatic rewriting. Because storage is likely to be corrupted by leakage current, this same procedure is repeated regularly, even when data are not demanded, in order to keep the memory active. Dynamic memories are the densest circuits designed. Memory sizes currently attain 16 Mbits, and 256 Mbits memories are being developed. Commercially Available Memory Chips Memory arrays usually consist of several square arrays packed on a single chip. In order to access data, the user provides an address. The larger the memory size, the longer the address. In order to reduce pin count, address words are divided in fields controlling less pins in a sequential manner. Many memories are accessed by a row address strobe (RAS) followed by a column address strobe (CAS), each one requiring only half of the total number of address bits. Memories represent a very substantial part of the semiconductor market. Besides RAMs (random access memories), a large share of nonvolatile memories is available comprising ROMs (read-only memories), programmable read-only memories (PROMs), and electrically alterable readonly memories (EAROMs), which are considered below. RAM. Random access memories (RAMs) are either static or dynamic memory arrays like those described above. They are used to read and write binary data. Storage is warranted as long as the power supply remains on. ROM. In read-only memories, the information is frozen. Information can only be read out. Access is the same as in RAMs. Memory elements are single transistors. Whether a cell is conducting or not has been determined during the fabrication process. Some MOS transistors have a thin gate oxide layer; others have a thick oxide layer, or some are connected to the access lines, while others are not. PROM. The requirements for committing to a fixed particular memory content, inherent in the structure of ROMs, is a serious disadvantage in many applications. PROMs (programmable ROMs) allow the manufacturer or the user to program ROMs. Various principles exist:

• With mask programmable ROMs, a single mask is all the manufacturer needs to implement the client code. • With fuse link programmable ROMs, the actual content is written in the memory by blowing a number of microfuses. This allows the customer to program the ROM, but the final stage is irreversible as in mask programmable ROMs. EPROM. In electrically programmable ROMs the data are stored as shifts of the threshold voltages of the memory transistors. Floating-gate transistors are currently used for this purpose. Loading the gate occurs by hot electrons tunneling through the oxide from an avalanching junction toward the isolated gate. The charges trapped in the gate can only be removed by ultraviolet light, which provides the energy required to cross the oxide barrier. EEPROM. Electrically erasable PROMs use metal-nitride-oxide-silicon transistors in which the charges are trapped at the nitride oxide interface. The memory principle is based on Fowler-Nordheim tunneling to move charges from the substrate in the oxide or vice versa. The electric field is produced by a control gate. EAROMs (electrically alterable ROMs) use the same principle to charge or discharge a floating gate with some additional features providing better yields.

DIGITAL-TO-ANALOG CONVERTERS (D/A OR DAC)10 Converting data from the digital to the analog domain may be achieved in a variety of ways. One of the most obvious is to add electrical quantities such as voltages, currents or charges following a binary weighted scale. Circuits illustrating this principle follow. They are of two kinds: first, converters aiming at integral linearity and, second, converters exchanging integral linearity for differential linearity. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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FIGURE 14.4.16 Integral linearity converters. Switching is implemented by (a) MOS transistors and (b) bipolar circuits.

Integral Linearity Converters A binary scale of voltages and currents is easily obtained by means of the well-known R-2R network. In the circuit shown in Fig. 14.4.16a, binary weighted currents flowing in the vertical resistances are either dumped to ground or injected into the summing node of an operational amplifier. The positions of the switches reproduce the code of the digital word to be converted. Practical switches are implemented by means of MOS transistors. Their widths double going from left to right to keep the voltage drops constant between drains and sources. The resulting constant offset voltage can be compensated easily. Another approach, better suited for bipolar circuits, is illustrated in Fig. 14.4.16b. Here the currents are injected into the emitters of transistors whose outputs feed bipolar current switches performing the digital code conversion. To keep all emitters at the same potential, small resistors are placed between bases of the transistors. They introduce voltage drops of 18 mV (UT.ln2) to compensate for the small base to emitter voltages changes resulting from the systematic halving of collector current going from left to right.

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FIGURE 14.4.17 Capacitive D/A converter with charge integration op-amp.

The accuracy of R-2R circuits is based on the matching of the resistances. It does not exceed 10 bits in practice, and may reach 12 bits when laser trimming is used. Switched capacitors are used also to perform D/A conversion. Capacitors are easy to integrate and offer superior temperature characteristics compared to thin-film resistors. However, they suffer from several drawbacks and require special care in order to provide good matching. Integrated capacitors are sandwiches of metal-oxide-silicon layers (MOS technology) or polysilicon-oxide-polysilicon (double poly technology). The latter exhibit a highly linear behavior and extremely small temperature coefficient (typically 10 to 20 ppm/°C). In order to improve geometrical tracking, any capacitor must be a combination of “unit” capacitors that represent the minimum-sized element available (typically 100 fF). MOS capacitors have relatively large stray capacitances to the substrate through their inversion layer, about 10 to 30 percent of their nominal value, depending on the oxide thickness. Doubly poly capacitors offer better figures, but their technology is more elaborate. Whatever choice is made, the circuits must be designed to be inherently insensitive to stray capacitance. This is the case for the circuit shown in Fig. 14.4.17. In this circuit, a change of the position of a switch results in a charge redistribution among a weighted capacitor and the feedback capacitor C0. The transferred charge is stored on the feedback capacitor so that the output voltage stays constant, provided leakage currents are small (typically 10–15 A). The stray capacitors are illustrated in Fig. 14.4.17. They have no influence on the converter accuracy. Indeed, Ca and Cc are loaded and discharged according to position changes of switch S3, but the currents through those capacitors do not flow through the summing junction. On the other hand, Cb as well as Cd is always discharged and therefore do not influence the accuracy. Another version of a capacitive D/A converter is shown in Fig. 14.4.18. In this network, changing the position of switches S3 and S′ produces a charge redistribution between the capacitor at the extreme left and the parallel combination of all other capacitors that represent a total of 8 C. Hence the upper node undergoes a voltage swing equal to Vref /2. A binary scale of voltages consequently may be produced according to the various switches. Switch S′ fixes the initial potential of the upper node and allows the discharge of all capacitors prior to conversion. There is no specific requirement that the upper node be connected to ground or to any fixed potential V0, provided Vout is evaluated against V0.

FIGURE 14.4.18 Capacitive D/A converter with unity-gain buffer.

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FIGURE 14.4.19 Dynamic element matching converter principle.

Notice that the stray capacitance Cb degrades the converter accuracy, while Ca has no effect at all. Careful layout therefore is required to minimize Cb, unless this stray capacitance is included in the evaluation of the capacitor C at the extreme right. For this reason, only small numbers of bits should be considered. The unavoidable exponential growth of capacitances with the number of bits is relieved to some extent because the capacitance area increases as the square of dimensions. Another widely used technique to perform D/A conversion is paralleling of many identical transistors controlled by a single base-to-emitter or gate-to-source voltage source. The output terminals are tied together in order to implement banks of binary weighted current sources. This requires 2(N+1) transistors to make an N-bit converter, which is very efficient for transistors are the smallest on-chip devices available. Usually all the transistors are placed in an array and controlled by a row and column decoder, as in memories. One of the interesting features of this type of converter is its inherent monotonicity. Furthermore, if access to the individual transistors follows a pseudorandom pattern, many imperfections resulting from processing, such as an oxide gradient in the MOS process, have counterbalancing effects. Hence, an accuracy of 10 bits may be achieved with transistors whose standard deviation is much worse. A converter11 with excellent absolute accuracy is illustrated in Fig. 14.4.19. It is based on high-accuracy divide-by-2 blocks like those shown in the right part of the illustration. Each block consists of a Widlar circuit with equal resistances in the emitters of transistors T1 and T2 in order to split the current I approximately into two equal currents: I1 and I2 (1 percent tolerance). A double-throw switch is placed in series with the Widlar circuit in order to alternate I1 and I2 at the rate of the clock f. Provided the half clock periods t1 and t2 can be made equal within 0.1 percent, a condition that can easily be met, one obtains two currents whose averages I3 and I4 represent I/2 with an accuracy approaching 10–5. This technique, known as the dynamic element matching method, has been successfully integrated in bipolar technology offering an accuracy of 14 bits without expensive element trimming. A band-gap current generator provides the reference current Iref, which is compared to the right-side output current of the first divide-by-2 block. A high current-gain amplifier closes the feedback loop controlling the base terminals of T1 and T2 of the first block. Segment Converters In some applications, accuracy does not imply absolute linearity but rather differential linearity, which is very critical because errors between two successive steps larger than a half LSB cannot be tolerated. The difficulty occurs when changes of MSBs occur. To overcome the problem, segment converters were designed. The idea is to divide the full conversion scale into segments. A D/A converter with a maximum of 10 bits is used within segments. Passing from one segment to another is achieved in a smooth manner as in the circuit illustrated by Fig. 14.4.20.12 In this circuit, the 10-bit segment converter is powered by one of the four bottom current sources. A 2-bit decoder,

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FIGURE 14.4.20 Segment D/A converter.

which is controlled by the two MSBs, makes the appropriate connections. When the two MSBs are 00, current source I1 is chosen and the three others are short-circuited to ground. When the MSB pattern changes to 01, the switches take the positions illustrated in the figure. Then I2 supplies the 10-bit converter while I1 is injected directly into the summing node of the op amp. Hence, no change occurs in the main current component. The differential linearity is entirely determined by the 10-bit converter. The price paid for this improvement is a degradation of absolute linearity. Small discrepancies among the four current sources introduce slope or gain changes between segments. The absolute linearity specifications thus do not reach the differential linearity specs of the converter. Voltage segment converters can also be integrated. Instead of parallel current sources, series voltage sources are required. This is achieved by means of a chain of equal resistors dividing the reference voltage into segments. The D/A converter is connected along the chain by means of two unity-gain buffers in order not to affect input voltages. Passing from one segment to the next implies that the buffers are interchanged in order to avoid the degradation of the differential linearity, which could result from different offsets in the buffers. An integrated 16-bit D/A converter has been built along these lines.13 When a switched-capacitor D/A converter is embedded in a voltage segment converter, no buffer amplifiers are needed because no dc current drain is required. This property simplifies greatly the design of moderate accuracy converters and has been extensively used in the design of integrated codecs. Codecs. Codecs are nonlinear converters used in telephony. To cover the wide dynamic range of speech satisfactorily with only 8 bits, steps of variable size must be considered: small steps for weak signals, and large steps when the upper limit of the dynamic range is approached. The four LSBs of a codec-coded word define a step size within a segment whose number is given by the three following bits. The polarity of the sample is given by the MSB. Going from one segment to the next implies doubling the step size in order to generate the nonlinear conversion law (mlaw). In the codec circuit of Fig. 14.4.21,14 bottom plates are connected either in the middle of the resistive divider considered as an ac ground (position 1), or to Vlow or Vhigh (position 2 plus switch S1 or S2) representing, respectively, the negative and positive reference voltage sources, or to a third position (position 3) connecting a single capacitor to an appropriate node of the resistive voltage divider. Hence, the resistive divider determines the step size (four LSBs), the capacitive divider defines the segment (three following bits), and switches S1 or S2 control the sign (MSB).

ANALOG-TO-DIGITAL (A/D) CONVERTERS (ADC)10 Some analog-to-digital converters are in fact D/A converters embedded in a negative feedback loop with appropriate logic (see Fig. 14.4.22). The analog voltage to be converted is sensed against the analog output of a D/A converter, which in turn is controlled by a logic block so as to minimize the difference sensed by the

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FIGURE 14.4.21 Segment type codec.

comparator. Various strategies have been proposed for the logic block, depending on the type of D/A converter used. Most of the converters described previously have been implemented as ADCs in this manner. In particular, ladder and capacitive D/A converters are used in the so-called successive approximation D/A converter. In those devices, the logic block first sets the MSB; then the comparator determines whether the analog input voltage is larger or smaller than the half-reference voltage. Depending on the result, the next bit is introduced, leaving the MSB unchanged if the analog signal is larger and resetting the MSB in the opposite state. The algorithm is repeated until the LSB is reached. Successive approximation ADCs are moderately fast, for conversion time is strictly proportional to the number of bits and is determined by the settling time of the op-amp. The algorithm implies that the analog input voltage remains unaltered during the conversion time; otherwise it may fail. To avoid this, a sample-andhold (SH) circuit must be placed in front of the converter. A capacitive A/D converter is shown in Fig. 14.4.23.15 The conversion is accomplished by a sequence of three operations. During the first, the unknown analog input voltage is sampled. The corresponding positions of the switches are as illustrated in Fig. 14.4.23a. The total stored charge is proportional to the input voltage Vin. In the second step, switch SA is opened and the positions of all Si switches are changed (Fig. 14.4.23b). The bottom plates of all capacitors are grounded, and consequently the voltage at the input node of the comparator

FIGURE 14.4.22 A D/A converter within a feedback loop forms an A/D converter.

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FIGURE 14.4.23 An integrated switched-capacitor A/D converter: (a) sample mode; (b) hold mode; and (c) redistribution mode.

equals –Vin. The third step is initiated when raising the bottom plate of the MSB capacitor from ground to the reference voltage Vref (Fig. 14.4.23c). This is done by changing again the position of the MSB switch and connecting Sb to Vref instead of Vin. The voltage at the input node of the comparator is thus increased by Vref /2, so that the comparator’s output is a logic 1 or 0, according to the sign of (Vref /2 – Vin). The circuit operates similarly to any successive approximations converter. That is, V is compared to (Vref / 2 + Vref /4) when the result of the previous operation is negative, or the MSB switch returns to its initial position and only the comparison with Vref /4 is considered. After having carried out the same test until the LSB is reached, the conversion is achieved and the digital output may be determined from the position of the switches. The voltage of the common capacitive node is approximately equal to, or smaller than, the smallest incremental step.

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FIGURE 14.4.24 A typical MOS comparator for an A/D converter.

Since this is almost negligible, the stray capacitance of the upper common node is practically discharged. It thus has no effect on the overall accuracy of the converter. Hence the problem in the circuit of Fig. 14.4.18 does not occur. The name “charge redistribution A/D converter” was given to this circuit because the charge stored during the first sequence is redistributed among only those capacitors whose bottom plates are connected to Vref after the conversion algorithm is completed. The design of comparators able to discriminate steps well below the offset voltage of MOS amplifiers is a problem deserving careful attention. An illustration of an MOS comparator is shown in Fig. 14.4.24.15 The amplifier comprises three parts: a double inverter, a differential amplifier, and a latch. The input-output nodes of the first inverter may be short-circuited by means of transistor T0 to bias the gates and drains of the identical two first inverters at approximately half the supply voltage. This procedure occurs during the “sampling” phase of the converter and corresponds to the grounding of switch SA in Fig. 14.4.23. As stated above in the comments concerning the circuit of Fig. 14.4.17, there is no necessity to impose zero voltage on this node during sampling; any voltage is suitable as long as the impedance of the voltage source is kept small. This is what occurs when T0 is on, since the input impedance of the converter is then minimum because of the negative-feedback loop across the first stage. Once the double inverter is preset, T0 opens and the output voltage of the second inverter is stored across the capacitor C1, momentarily closing switch S1. Then the floating input node of the comparator senses the voltage change resulting from charge redistribution during a test cycle and reflects the amplified signal at the output of the second inverter. Switch S2 in turn samples the new output so that the differential amplifier sees only the difference between the two events. Any feed through noise from T0 is ignored since it only affects the common mode of the voltages sampled on C1 and C2. Hence, the overall offset voltage of this comparator is equal to the offset voltage of the differential amplifier divided by the gain of the double inverter input stage. Signals in the millivolt range can be sensed correctly regardless of the poor behavior of MOS transistors’ offset voltages. Another integrated converter widely accepted in the field of electrical measurements is the dual-ramp A/D converter.13 FIGURE 14.4.25 The dual-slope A/D converter The principle of this device is first to integrate the unknown principle. voltage Vx during a fixed duration t1 (see Fig. 14.4.25). Then the input signal Vx is replaced by a reference voltage Vref. Since the polarities of both signals are opposite, the integrator provides an output ramp with opposite slope. It takes a time t2 for the integrator output voltage to return from V0 to zero. Hence V0 = −

1 RC

t1

∫0

Vx dt

(5)

and V0 = (Vref /RC)t2

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Consequently, if Vx is a constant Vx = –Vref t 2 /t1

(7)

the time t1 is determined by a counter. At the moment the counter overflows, switching of the input signal from Vx to Vref occurs. The counter is automatically reset, and a new counting sequence initiated. When the integrator output voltage has returned to zero, the comparator stops the counting sequence. Thus the actual count is a direct measure of t2. The dual-ramp converter has a number of interesting features. Its accuracy is not influenced by the value of the integration time constant RC; neither is it sensitive to the long-term stability of the clock-frequency generator. The comparator offset can easily be compensated by autozeroing techniques. The only signal that actually controls the accuracy of the A/D converter is the reference voltage Vref. Excellent thermal stability of Vref can be achieved by means of band-gap reference sources. Another interesting feature of the dual-ramp A/D converter is the fact that since Vx is integrated during a constant time t1, any spurious periodic signal with zero mean whose period is a submultiple of t1 is automatically canceled. Hence, by making t1 equal to an entire number of periods of the power supply one obtains excellent hum rejection.

DELTA-SIGMA CONVERTERS 10,20 Because the development of integrated systems is driven mainly by digital applications, mixed analog-digital circuits, especially converters, should be implementable equally well without loss of accuracy in digital technologies, even the most advanced ones. Short channels, however, do not just improve bandwidth, they also negatively affect other features, such as dynamic range and 1/f noise, because both supply voltage and gate area of the MOS transistors get even smaller. Therefore, a trade-off of speed and digital complexity for resolution in signal amplitude is needed. Delta-Sigma converters illustrate this trend. Their object is to abate the quantization noise to enhance the signal-to-noise ratio (SNR) of the output data (quantization noise is the difference between the continuous analog data and their discrete digital counterpart). When the number of steps of a converter increases the quantization noise decreases. Similarly, if we enhance the SNR the resolution increases. Delta-Sigma converters take advantage of oversampling and noise shaping techniques to improve the SNR. Oversampling refers to the Nyquist criterion, which requires a sampling frequency twice the baseband to keep the integrity of sampled signals. Oversampling does not improve the signal. Neither does it increase the quantization noise power, nor is it a way to spread the quantization noise power density over a large spectrum, thereby lessening its magnitude to keep the noise power unchanged. If we restrict the bandwidth of the oversampled signal to the signal baseband in compliance with the Nyquist criterion, the amount of noise power left in the baseband is divided automatically by the ratio of the actual sampling frequency over the Nyquist frequency. We improve thus the SNR and consequently increase the resolution. Noise shaping is the other essential feature of Delta-Sigma converters. It refers to the filtering step oversampled data must undergo. The purpose is to further decrease the amount of noise left in the baseband by shifting a large part of the remaining quantization noise outside the baseband. During the step, the SNR is substantially improved. Both A/D and D/A converters lend themselves to Delta-Sigma architectures. The same principles prevail, but their implementation differs. We consider both separately. A/D Delta-Sigma Converters16,26 In A/D converters, oversampling is done simply by increasing the sampling frequency of the analog input signal. Noise shaping is achieved by means of a nonlinear filter like the one illustrated in the upper part of Fig. 14.4.26. As stated already above, the goal is to shift most quantization noise out of the baseband. The noise shaper consists of a feedback loop similar to the linear circuit shown in the lower part. In the upper figure, the quantization noise is produced by the A/D converter. This converter is followed by a D/A converter, which is required because the difference between the continuous analog input signal and the discrete digital output signal delivered by the

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FIGURE 14.4.26 Principle of sigma-delta converters.

A/D converter must be sensed in the analog domain. This difference is amplified and low-passed by means of the analog loop filter H. The idea is truly to minimize the signal fed to the amplifier as in the continuous circuit shown below. Consequently, the output signal becomes a replica of the input. This requires some caution, however, because matching continuous input data and discrete output data is not feasible. The situation is very different from the one illustrated in the lower part of Fig. 14.4.26 where the quantization noise is simulated by means of an independent analog continuous noise source. Clearly, if the loop gain is high, the signal outputted by the amplifier should be the sum of the input signal minus the noise in order to make ua look like xa. In the upper circuit, however, the amplifier senses steps whose magnitude is determined by the A/D and D/A quantizer. The signal delivered by the amplifier is an averaged image over time of the difference between the input and the discrete signal fed back. The latter tracks the input the best it can—thanks to the feedback loop. A look at the signals displayed in Fig. 14.4.27 confirms this statement. The figure represents output data of a third-order noise shaper with a 3-bit quantizer. The loop filter consists of three integrators in cascade. Their outputs are respectively illustrated in the three upper plots. The signal delivered by the third integrator is applied to the quantizer whose output is shown below. It is obvious that notwithstanding the poor resolution of the A/D converter, the noise shaper tracks the input sine wave pretty well by correcting its output data continuously. Once the bandwidth of the signal outputted by the noise shaper has been restricted to the baseband, we get a signal whose SNR may be very high. To illustrate this, consider Fig. 14.4.28, which shows a plot of the signal-to-noise improvement that can be obtained with the linear circuit shown in Fig. 14.4.26. Although the actual noise shaper differs from its analog counterpart because the quantization noise is correlated with the input and the quantizer is a nonlinear device, results are comparable. Large SNR figures, 60 or 80 dB and even better, are readily achievable. It is obvious that large OSRs are not the only way to get high SNRs; these can also be obtained by increasing the order of the loop filters (assuming of course stability is achieved, which is not always easy in a nonlinear system). Another interesting feature that stems from the above figure is that A/D and D/A converters with few bits resolution only do not impair the resolution of the Delta-Sigma converter given the large SNRs noise shapers can achieve. Even a single-bit quantizer, notwithstanding its large amount of quantization noise, suffices. In practice the above converters are parallel devices in order not to slow down needlessly the conversion rate. The A/D converter is a flash converter and the D/A converter a unit-elements converter. The accuracy of the A/D converter is not critical as it is a part of the forward branch and it does not control the overall accuracy like

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FIGURE 14.4.27 quantizer.

Waveforms observed in a third-order noise shaper making use of a 3-bit

FIGURE 14.4.28 Plot of the quantization noise attenuation vs. the oversampling rate (OSR) and the loop filter order. The case n = 0 corresponds to oversampling without noise shaping.

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FIGURE 14.4.29 The generic Delta-Sigma A/D converter.

in any feedback loops. The D/A accuracy is more critical because it is located in the feedback branch and impairs the overall accuracy since the feedback loop minimizes only the difference between the oversampled input signal and the signal delivered by the D/A converter. This puts, of course, a heavy toll on the D/A converter unless we use a single-bit architecture. In single-bit quantizers, the A/D converter resumes to a comparator and the D/A converter to a device whose output can take only two states. No possibility exists that steps of unequal heights are found as in multi-bit D/As. This explains why single-bit quantizers are preferred generally to multi-bit. Multi-bit quantizers, however, are not evaded; they offer better alternatives for large bandwidth converters where the sampling frequency can be bound by the technology and the OSRs may take large values. To improve the performances of the D/A converter, randomization of their unit elements is generally recommended. This spreads the impairments of the unit elements mismatch over a large bandwidth. Without randomization, the same impairments produce harmonic distortion, which is a lot more annoying than white noise in terms of SNRs. A generic A/D Delta-Sigma converter is shown in Fig. 14.4.29. Besides the noise shaper, two additional items are visible—an anti-alias filter at the input and a decimator at the output. The anti-alias filter is not specific to Delta-Sigma converters, but its implementation is much less demanding than in Nyquist converters. The reason therefore stems from the fact that the sampling frequency is much larger than the signal baseband so that a third- or second-order analog filter already is enough. At the output of the noise shaper, the decimator restricts the bandwidth to the baseband and lowers the sampling rate from oversampled to the Nyquist frequency. Since the signal inputted in the decimator is taken after the A/D converter, the decimator is in fact a digital filter. This is important for decimation is a demanding operation that cannot be done easily in the analog domain. The decimator is indeed supposed not only to restrict the bandwidth of the converted data but also to get rid of the large amounts of high-frequency noise lying outside the baseband. Therefore the decimator consists of two or three cascaded stages, an finite impulse response (FIR) filter and one or two accumulate-anddump filters. The FIR filter takes care of the steep low-pass frequency characteristic that fixes the baseband, while the accumulate-and-dump filters attenuate the high-frequency noise. An illustration of the input-output signals of a fourth-order decimator fed by the third-order noise shaper considered in Fig. 14.4.27 is shown in Fig. 14.4.30. The signal from the noise shaper is shown in Fig. 14.4.27. The output of the decimator is illustrated below together with continuous analog input sine wave. The down-sampling rate in the example is equal to 8 and the effective number of bits (ENOB) of the decimated signal reaches 9.6 bits. In practice, resolutions of 16, even 24 bits, are obtained. The resolution of Delta-Sigma converters is determined by the ENOB, which is derived from the relation linking quantization noise to number of bits: ENOB =

SNR dB − 1.8 6

(8)

The SNR is measured by comparing the power of a full-scale pure sine wave to the quantization noise power taking advantage of the fast Fourier transform (FFT) algorithm. The measured noise consists of two

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FIGURE 14.4.30 (Above) The quantizer output signal of Fig. 14.4.28. (Below) The same after decimation (order 4) compared to the input signal.

components—the actual quantization noise, which is a measure of the resolution, and the noise caused by the converter impairments. The first does not represent a defect; the second is unwanted and inevitable. The magnitude of this extra noise generally increases very rapidly when the input signal gets large because more and more nonlinear distortion tends to enter the picture. In order to avoid the impact of distortion on the ENOB evaluation, the SNR is evaluated generally as follows. The magnitude of the input signal is varied from a very low level, for instance, 60 dB below full scale, until full scale and the measured SNRs are plotted versus the magnitude of the input signal. As long as distortion does not prevail, the SNR varies like the power of the input signal, but beyond this it departs from ideal. The figure that must be considered in the above equation is the SNR obtained after extrapolating the linear portion of the SNR plot until full scale. D/A Delta-Sigma Converters10,20 The principles underlying A / D converters can be transposed in D/A Delta-Sigma converters (Fig. 14.4.31). Oversampling and noise shaping are applied concurrently but in a different way since the input data are digital words and the output is an analog signal. An interpolation step is needed first in order to generate additional samples interleaved with the input data. The output of the interpolator is then noise shaped before being applied to a low-resolution D/A converter whose analog output is filtered by means of a low-order analog low-pass filter. The quantization noise is evaluated and fed back to the loop filter before closing the feedback loop of the noise shaper. One of the differences with respect to A/D Delta-Sigma converters is the manner quantization noise is measured. All that is needed is to split the words delivered by the noise shaper in two fields—an MSB field and an LSB field. The MSB field, which consists of a few bits, or even a single-bit, controls the D/A converter, while the LSB field closes the feedback loop after the digital loop filter.

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FIGURE 14.4.31 Block diagram of a Delta-Sigma D/A converter.

FIGURE 14.4.32 Interpolation (above) the principle (below) spectrum of a fourfold interpolated sine wave.

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FIGURE 14.4.33 Timing of signals in a D/A Delta-Sigma converter: (0) the 13-bit digital input sine wave, (1) after a first fourfold interpolation, (2) after the second interpolation, (3) the noise shaped 3-bit signal, and (4) the analog output signal.

Interpolators are the counterpart of decimators. Instead of down-sampling they add data between samples as shown in the upper part of Fig. 14.4.32. In the figure, three zeros are placed between every sample. This multiplies already the sampling frequency by 4 but does not suffice because the spectrum of the resulting oversampled signal is like the one shown in Fig. 14.4.32b. One must erase part of the spectrum and multiply the signal by 4 in order to get the correct spectrum shown under Fig. 14.4.32c. This is done by means of a digital filter with a sharp cutoff frequency at the edge of the baseband. In practice this filter consists of several cascaded filters like in the decimator. An FIR filter takes care of the sharp cutoff frequency, whereas one or two low-pass filters perform the rest. The FFT of a sine wave after a fourfold interpolator with a single FIR filter is shown in the lower part of Fig. 14.4.32. The fundamental ray that is reproduced three times lies approximately 80 dB below the quantization noise floor and does no harm. A second more elaborate example is shown in Fig. 14.4.33. It illustrates the changes signals undergo versus time. The input is a 13-bit sine wave represented by large black dots. After a first interpolation, which multiplies the sampling frequency by 4, we get the data marked (1). A second interpolation by 4 yields data (2). The signal is then noise shaped. The three MSBs control the D/A converter whose analog output (3) consists of large steps that approximate the signal from the second interpolator. When the signal outputted by the D/A converter is filtered by means of a third-order low-pass, the continuous sine wave (4) is obtained, which is the actual output signal of the converter. With an SNR of nearly 80 dB, the 13-bit accuracy of the digital input signal is still met.

VIDEO A/D CONVERTERS10 Video applications require extremely short conversion times. Few of the previous converters meet the required speed. An obvious solution is full parallel conversion with as many comparators and reference levels as there are quantization steps. Fortunately, most video applications do not require accuracies higher than 8 bits, so 256 identical channels are sufficient. Only integrated circuits offer an economical solution in this respect.

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FIGURE 14.4.34 A flash converter.

A typical parallel video converter, called a flash converter, is shown in Fig. 14.4.34.17 The architecture of the converter is simple. A string of 255 identical thin-film aluminum or polysilicon resistors is used in order to produce 28 reference levels. The input voltage V produces at the outputs of the comparators a vector which may be divided into two fields of 1s and 0s. An additional layer of logic transforms this vector into a new vector with 0s everywhere except at the boundary between the two fields. The new vector is further decoded to produce an 8-bit coded output. No sample-and-hold (SH) circuit is required since all comparators are synchronously driven by the same clock, but extremely fast comparators are required. An 8-bit resolution and a 5-MHz bandwidth imply binary decisions in a time as short as 250 ps. This is achieved by means of ECL logic drivers and storage flipflops. Signal propagation across the chip also requires careful layout. The resistive divider impedance may not exceed 50 to 100 Ω. Another particular feature is the inevitable high-input capacitance, which results from the paralleling of many comparators. The huge area and power consumption inherent to flash devices has stimulated the design of less greedy converters. Although these cannot compete with flash converters as far as speed is concerned, they offer conversion times short enough to comply with the requirements of a number of “fast” applications. Their principle comes to fragment the conversion process into several cycles, eventually two, during which strings of bits are evaluated by means of a subconverter. The process starts with the bits representing the MSB field. The other sets are evaluated one after another until the correct output word can be reconfigured by concatenating the individual segment codes. Each conversion step requires a single clock. This means, of course, that all subconverters must be fast devices, like flash converters. A 9-bit converter, for instance, operating by means of 3- bit segments requires three cycles for full conversion. Although only three clock cycles are required, the real conversion time is always much longer than three times what is needed for the 9-bit flash converter. Segmentation supposes indeed that some kind of analog memory be used in order to store intermediate results. Op-amps are thus required, which is a drawback with respect to flash converters, for the latter don’t need op-amps, and consequently ignore dominant poles. The most stringent difference between flash converters and segmented A/D converters is the number of comparators. In a flash converter, the number of comparators increases exponentially with the number of bits.

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FIGURE 14.4.35 A subranging converter.

In a segmented converter, less comparators are required. Not only is the area much smaller, but the power consumption is drastically reduced. Figure 14.4.35 shows the implementation of a two-cycle segmented A/D converter called a subranging converter. The coarse A/D converter evaluates first the M1 MSBs. For the remaining M2 LSBs, an analog replica of the MSBs is subtracted from the analog input signal. This is done by means of the M1-bit wide D/A converter whose output is subtracted from the input signal. The difference, which is nothing but coarse conversion quantization noise, is fed to the fine A/D flash converter, which evaluates the LSBs. The output code word is obtained by concatenation of the M1 and M2 segment codes. The total number of comparators in this type of converter is drastically reduced. For instance, in a 10-bit converter taking advantage of two 5-bit segments, each flash converter requires 31 comparators, that is, a total of 62 comparators, which is very little compared to the 1023 comparators required by a true 10-bit flash converter. Naturally the coarse D/A converter, which is a unit-elements parallel device, and the sample-and-hold, which holds the input while A/D and D/A conversions take place, must be brought into the picture also. In any case, segmented converters save a lot of area and power. The number of comparators can be decreased further if we consider the recycling converter 24 shown in Fig. 14.4.36. In this circuit the difference between the input and its coarse quantized approximation is fed back to the input, stored in the sample-and-hold device, and recycled through the A/D converter. Eventually a second cycle may be envisaged. Each cycle, a new set of lower rank bits is generated. The fine flash converter is not needed, but an interstage amplifier is required. Its purpose is to amplify the quantization noise so that it spans exactly over the full dynamic range of the A/D and D/A converters. If this were not the case, we would be forced to adapt continuously the resolution of the converters to cope with the decreasing magnitude of the difference signal.

FIGURE 14.4.36 A recycling converter.

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PULSED CIRCUITS AND WAVEFORM GENERATION

FIGURE 14.4.37 A pipelined converter.

Of course, it is useless to try to repeat this procedure over and over again because the errors generated in every new cycle pile up and corrupt the difference signal. It is very important to determine which sources of errors are important. The main ones are the interstage gain error, the D/A and the A / D nonlinearities. The A/D errors can easily be corrected by extending the dynamic range of both converters. Errors from the flash converter are corrected automatically during recycling. The other errors are more difficult to correct but one should not overlook the fact that they affect only bits generated after the first cycle. The conversion time of recycling converters varies, of course, like the number of cycles. Pipelined converters offer a good means to keep the conversion time equal to a single cycle time, however, at the expense of area. Such a converter is shown in Fig. 14.4.37. The idea is simply to exchange time for space. In other words, we cascade blocks identical to the circuit of Fig. 14.4.36, but each circuit feeds its neighbor instead of recycling its own data. Every bloc thus deals with data that belong to different time samples. In order to reconfigure the correct output words, one must reshuffle the code segments in order to recover time consistency. This is done by means of registers. Recycling and pipelined converters that operate with segments only 1-bit wide are currently designated algorithmic converters. They are not fast devices since they require as many cycles as number of bits to

FIGURE 14.4.38 A typical integrated wave generator that can deliver a square wave, a triangular wave, and a sine wave.

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output code words. Algorithmic converters are similar to successive approximation converters although they operate differently.

FUNCTION GENERATORS Integrated function generators consist generally of a free-running relaxation oscillator controlling a nonlinear shaping circuit. A typical block diagram of a function generator is shown in Fig. 14.4.38. The relaxation oscillator is a combination of a time-base generator and a Schmitt trigger. The time base in the present case is obtained by successive loading and discharging of a capacitor using two current sources. One is a constant current source I1 and the other a controlled current source delivering a current step equal to –2I1 or zero. Hence, the voltage across the capacitor C is a sawtooth. The switching of the controlled current source is monitored by the logical output signal of the Schmitt trigger. This last circuit is in fact a precision Schmitt trigger. The oscillating voltage across C is obtained in the same manner. The output sawtooth signal is buffered and drives a network consisting of resistors and diodes which changes the sawtooth into a more or less sinusoidal voltage. The advantage of function generators over RC or op-amp oscillators is their excellent amplitude stability versus frequency. Also frequency modulation can easily be achieved by changing the current delivered by the two current sources. This type of function generator can be frequency-swept over a wide dynamic range without spurious amplitude transients since no selective network is involved.

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Source: STANDARD HANDBOOK OF ELECTRONIC ENGINEERING

SECTION 15

MEASUREMENT SYSTEMS Measurement circuits are critical in the analysis, design, and maintenance of electronic systems. For those who work in electronics, these circuits and systems become the eyes into the world of the electron that cannot be directly seen. The main objective of such systems is to not influence what is being measured or observed. This is accomplished by a range of types of measurement circuits. All of these are considered in this section. A key element of systems that measure is how the measurement is actually made. Without an understanding of how the measurement is made, one cannot understand the limitations. It is possible to make a measurement and be off by several orders of magnitude. We look at the process of making measurements and what to look for so that one can have a level of confidence in the measurement. Substitution and analog measurements have been an important mainstay of this field. Unlike measurements that involve some digital systems, the accuracy and precision of the measurements depend totally on the precision of elements used in the measurement systems. We look at a variety of measurement techniques using substitution and look at analog devices like ohmmeters. Digital instruments have many advantages especially when used in data acquisition systems. An important component of measurement systems is the transducer. The transducer converts a physical quantity into an electrical signal that can be measured by a measurement system. Knowing the characteristics, especially its limitations, helps in understanding the precision with which measurements can be made. It is in the area of transducers and sensors that we have seen some of the most dramatic advances. Bridge circuits gave us the first opportunity to actually make measurements without “loading” the circuit being measured. The accuracy of the measurements merely depended on the precision of the elements used in the bridge. We need AC impedance measurements to develop the small signal characteristics of a circuit or system and to evaluate the stability of the circuit or system. These kinds of measurements are important in a variety of applications from the space station to how well your television works. C.A.

In This Section: CHAPTER 15.1 PRINCIPLES OF MEASUREMENT CIRCUITS DEFINITIONS AND PRINCIPLES OF MEASUREMENT TRANSDUCERS, INSTRUMENTS, AND INDICATORS MEASUREMENT CIRCUITS

15.3 15.3 15.5 15.5

CHAPTER 15.2 SUBSTITUTION AND ANALOG MEASUREMENTS VOLTAGE SUBSTITUTION DIVIDER CIRCUITS DECADE BOXES ANALOG MEASUREMENTS DIGITAL INSTRUMENTS

15.6 15.6 15.8 15.9 15.11 15.14

CHAPTER 15.3 TRANSDUCER-INPUT MEASUREMENT SYSTEMS TRANSDUCER SIGNAL CIRCUITS

15.18 15.18

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CHAPTER 15.4 BRIDGE CIRCUITS, DETECTORS, AND AMPLIFIERS PRINCIPLES OF BRIDGE MEASUREMENTS RESISTANCE BRIDGES INDUCTANCE BRIDGES CAPACITANCE BRIDGES FACTORS AFFECTING ACCURACY BRIDGE DETECTORS AND AMPLIFIERS MISCELLANEOUS MEASUREMENT CIRCUITS

15.25 15.25 15.27 15.30 15.32 15.33 15.35 15.35

CHAPTER 15.5 AC IMPEDANCE MEASUREMENT

15.43

Section Bibliography: Andrew, W. G., “Applied Instrumentation in the Process Industries,” Gulf Pub. Co., 1993. Bell, D. A., “Electronic Instrumentation and Measurements,” Prentice Hall, 1994. Carr, J. J., “Elements of Electronic Instrumentation and Measurement,” 3rd ed., Prentice Hall, 1996. Considine, D. M., and S. D. Ross (eds.), “Handbook of Applied Instrumentation,” Krieger, 1982. Coombs, C. F., Jr., “Electronic Instrument Handbook,” 2nd ed., McGraw-Hill, 1995. Decker, T., and R. Temple, “Choosing a phase noise measurement technique,” H-P RF and Microwave Measurement Symposium, 1989. Erickson, C., Switches in Automated Test Systems, Chap. 41 in Coombs’s “Electronic Instrument Handbook,” 2nd ed., McGraw-Hill, 1995. “Direct Current Comparator Potentiometer Manual, Model 9930,” Guideline Instruments, April 1975. Harris, F. K., “Electrical Measurements,” Wiley, 1952. IEEE Standard Digital Interface for Programmable Instrumentation, ANSI/IEEE Std. 488.1, 1987. Keithley, J. R., J. R. Yeager, and R. J. Erdman, “Low Level Measurements,” 3rd ed., Keithley Instruments, June 1984. Manassewitsch, V., “Frequency Synthesizers: Theory and Design,” Wiley, 1980. McGillivary, J. M., Computer-Controlled Instrument Systems, Chap. 43 in Coombs’s “Electronic Instrument Handbook,” 2nd ed., McGraw-Hill, 1995. Mueller, J. E., Microprocessors in Electronic Instruments, Chap. 10 in Coombs’s “Electronic Instrument Handbook,” 2nd ed., McGraw-Hill, 1995. Nachtigal, C. L., “Instrumentation and Control: Fundamentals and Applications,” Wiley, 1990. “Operation and Service Manual for Model 4191A RF Impedance Analyzer,” Hewlett-Packard, January 1982. “Operation and Service Manual for Model 4342A Q Meter,” Hewlett-Packard, March 1983. Reissland, M. V., “Electrical Measurement: Fundamentals, Concepts, Applications,” Wiley, 1989. Santoni, A., “IEEE-488 Instruments,” EDN, pp. 77–94, October 21, 1981. Schoenwetter, H. K., “A high-speed low-noise 18-bit digital to analog converter,” IEEE Trans. Instrum. Meas., Vol. IM-27, No. 4, pp. 413–417, December, 1978. Souders, R. M., “A bridge circuit for the dynamic characteristics of sample/hold amplifiers,” IEEE Trans. Instrum. Meas., Vol. IM-27, No. 4, December, 1978. Walston, J. A., and J. R. Miller (eds.),“Transistor Circuit Design,” McGraw-Hill, 1963. Witte, R. A., “Electronic Test Instruments: Theory and Practice,” Prentice Hall, 1993. Workman, D. R., “Calibration status: a key element of measurement systems management,” 1993 National Conference of Standards Laboratories Symposium.

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Source: STANDARD HANDBOOK OF ELECTRONIC ENGINEERING

CHAPTER 15.1

PRINCIPLES OF MEASUREMENT CIRCUITS Francis T. Thompson*

DEFINITIONS AND PRINCIPLES OF MEASUREMENT Precision is a measure of the spread of repeated determinations of a particular quantity. Precision depends on the resolution of the measurement means and variations in the measured value caused by instabilities in the measurement system. A measurement system may provide precise readings, all of which are inaccurate because of an error in calibration or a defect in the system. Accuracy is a statement of the limits that bound the departure of a measured value from the true value. Accuracy includes the imprecision of the measurement along with all the accumulated errors in the measurement chain extending from the basic reference standards to the measurement in question. Errors may be classified into two categories, systematic and random. Systematic errors are those which consistently recur when a number of measurements are taken. Systematic errors may be caused by deterioration of the measurement system (weakened magnetic field, change in a reference resistance value), alteration of the measured value by the addition or extraction of energy from the element being measured, response-time effects, and attenuation or distortion of the measurement signal. Random errors are accidental, tend to follow the laws of chance, and do not exhibit a consistent magnitude or sign. Noise and environmental factors normally produce random errors but may also contribute to systematic errors. The arithmetic average of a number of observations should be used to minimize the effect of random errors. The arithmetic average or mean X of a set of n readings X1, X2, . . . , Xn is X = ∑Xi /n The dispersion of these reading about the mean is generally described in terms of the standard deviation s, which can be estimated for n observations by s=

∑( X i − X )2 n −1

where s approaches s as n becomes large.

*The author is indebted to I. A. Whyte, L. C. Vercellotti, T. H. Putnam, T. M. Heinrich, T. I. Pattantyus, and R. A. Mathias for suggestions and constructive criticism for Chap. 15.1.

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MEASUREMENT SYSTEMS

A confidence interval can be determined within which a specified fraction of all observed values may be expected to lie. The confidence level is the probability of a randomly selected reading falling within this interval. Detailed information on measurement errors is given in Coombs (Chap. 15.5). Standardization and calibration involve the comparison of a physical measurement with a reference standard. Calibration normally refers to the determination of the accuracy and linearity of a measuring system at a number of points, while standardization involves the adjustment of a parameter of the measurement system so that the reading at one specific value is in correspondence with a reference standard. The numerical value of any reference standard should be capable of being traced through a chain of measurements to a National Reference Standard maintained by the National Institute of Standards and Technology (formerly the National Bureau of Standards). The range of a measurement system refers to the values of the input variable over which the system is designed to provide satisfactory measurements. The range of an instrument used for a measurement should be chosen so that the reading is large enough to provide the desired precision. An instrument having a linear scale, which can be read within 1 percent at full scale, can be read only within 2 percent at half scale. The resolution of a measuring system is defined as the smallest increment of the measured quantity which can be distinguished. The resolution of an indicating instrument depends on the deflection per unit input. Instruments having a square-law scale provide twice the resolution of full scale as linear-scale instruments. Amplification and zero suppression can be used to expand the deflection in the region of interest and thereby increase the resolution. The resolution is ultimately limited by the magnitude of the signal that can be discriminated from the noise background. Noise may be defined as any signal that does not convey useful information. Noise is introduced in measurement systems by mechanical coupling, electrostatic fields, and magnetic fields. The coupling of external noise can be reduced by vibration isolation, electrostatic shielding, and electromagnetic shielding. Electrical noise is often present at the power-line frequency and its harmonics, as well as at radio frequencies. In systems containing amplification, the noise introduced in low-level stages is most detrimental because the noise components within the amplifier passband will be amplified along with the signal. The noise in the output determines the lower limit of the signal that can be observed. Even if external noise is minimized by shielding, filtering, and isolation, noise will be introduced by random disturbances within the system caused by such mechanisms as the Brownian motion in mechanical systems, Johnson noise in electrical resistance, and the Barkhausen effect in magnetic elements. Johnson noise is generated by electron thermal agitation in the resistance of a circuit. The equivalent rms noise voltage developed across a resistor R at an absolute temperature T is equal to 4kTR ∆f , where k is Boltzmann’s constant (1.38 × 10–23 J/K) and ∆ f is the bandwidth in hertz over which the noise is observed. The bandwidth ∆ f of a system is the difference between the upper and lower frequencies passed by the system (Chap. 15.2). The bandwidth determines the ability of the system to follow variations in the quantity being measured. The lower frequency is zero for dc systems, and their response time is approximately equal to 1/(3∆ f ). Although a wider bandwidth improves the response time, it makes the system more susceptible to interference from noise. Environmental factors that influence the accuracy of a measurement system include temperature, humidity, magnetic and electrostatic influences, mechanical stability, shock, vibration, and position. Temperature changes can alter the value of resistance and capacitance, produce thermally generated emfs, cause variations in the dimensions of mechanical members, and alter the properties of matter. Humidity affects resistance values and the dimensions of some organic materials. DC magnetic and electrostatic fields can produce an offset in instruments which are sensitive to these fields, while ac fields can introduce noise. The lack of mechanical stability can alter instrument reference values and produce spurious responses. Mechanical energy imparted to the system in the form of shock or vibration can cause measurement errors and, if severe enough, can result in permanent damage. The position of an instrument can affect the measurements because of the influence of magnetic, electrostatic, or gravitational fields.

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15.5

TRANSDUCERS, INSTRUMENTS, AND INDICATORS Transducers are used to respond to the state of a quantity to be measured and to convert this state into a convenient electrical or mechanical quantity. Transducers can be classified according to the variable to be measured. Variable classifications include mechanical, thermal, physical, chemical, nuclear-radiation, electromagneticradiation, electrical, and magnetic, as detailed in Sec. 8. Instruments can be classified according to whether their output means is analog or digital. Analog instruments include the d’Arsonval (moving-coil) galvanometer, dynamometer instrument, moving-iron instrument, electrostatic voltmeter, galvanometer oscillograph, cathode-ray oscilloscope, and potentiometric recorders. Digital-indicator instruments provide a numerical readout of the quantity being measured and have the advantage of allowing unskilled people to make rapid and accurate readings. Indicators

are used to communicate output information from the measurement system to the observer.

MEASUREMENT CIRCUITS Substitution circuits are used in the comparison of the value of an unknown electrical quantity with a reference voltage, current, resistance, inductance, or capacitance. Various potentiometer circuits are used for voltage substitution, and divider circuits are used for voltage, current, and impedance comparison. A number of these circuits and the reference components used in them are described in Chap. 15.2. Analog circuits are used to embody mathematical relationships, which permit the value of an unknown electrical quantity to be determined by measuring related electrical quantities. Analog-measurement techniques are discussed in Chap. 15.2, and a number of special-purpose measurement circuits are described in Chap. 15.4. Digital instruments combine analog circuits with digital processing to provide a convenient means of making rapid and accurate measurements. Digital instruments are described in Chaps. 15.2 and 15.4. Digital processing using the computational power of microprocessors is discussed in Chap. 15.3. Bridge circuits provide a convenient and accurate method of determining the value of an unknown impedance in terms of other impedances of known value. The circuits of a number of impedance bridges and amplifiers and detectors used for bridge measurements are described in Chap. 15.4. Transducer amplifying and stabilizing circuits are used in conjunction with measurement transducers to provide an electric signal of adequate amplitude, which is suitable for use in measurement and control systems. These circuits, which often have severe linearity, drift, and gain-stability requirements, are described in Chap. 15.3.

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CHAPTER 15.2

SUBSTITUTION AND ANALOG MEASUREMENTS Francis T. Thompson

VOLTAGE SUBSTITUTION The constant-current potentiometer, which is used for the precise measurement of unknown voltages below 1.5 V, is shown schematically in Fig. 15.2.1. For a constant current, the output voltage Vo is proportional to the resistance included between the sliding contacts. In this circuit all the current-carrying connections can be soldered, thereby minimizing contact-resistance errors. When the sliding contacts are adjusted to produce a null, Vo is equal to the unknown emf and no current flows in the sliding contacts. At null, no current is drawn from the unknown emf, and therefore the measured voltage is independent of the internal resistance of the source. The circuit of a multirange commercial potentiometer is shown in Fig. 15.2.2. The instrument is standardized with the range switch in the highest range position as shown and switch S connected to the standard cell. The calibrated standard-cell dial is adjusted to correspond to the known voltage of the standard cell, and the standardizing resistance is adjusted to obtain a null on the galvanometer. This procedure establishes a constant current of 20 mA through the potentiometer. The unknown emf is connected to the emf terminals, and switch S is thrown to the emf position. The unknown emf can be read to at least five significant figures by adjusting the tap slider and the 11-turn 5.5-Ω potentiometer for a null on the galvanometer. The range switch reduces the potentiometer current to 2 or 0.2 mA for the 0.1 and the 0.01 ranges, respectively, thereby permitting lower voltages to be measured accurately. Since the range switch does not alter the battery current (22 mA), the instrument remains standardized on the lower ranges. When making measurements, the current should be checked using the standard cell to ensure that the current has not drifted from the standardized value. The Leeds and Northrup Model 7556-B six-dial potentiometer operates in a similar manner and provides an accuracy of ±(0.001 percent of reading + 0.1 mV). The constant-resistance potentiometer of Fig. 15.2.3 uses a variable current through a fixed resistance to generate a voltage for obtaining a null with the unknown emf. The constant-resistance potentiometer is used primarily for measurements in the millivolt and microvolt range. The microvolt potentiometer, or low-range potentiometer, is designed to minimize the effect of contact resistance and thermal emfs. Thermal shielding is used to minimize temperature differences. The galvanometer is connected to the circuit through a special Wenner thermo-free reversing key of copper and gold construction to eliminate thermal effects in the galvanometer circuit. A typical microvolt potentiometer circuit consisting of two constant-current decades and a constant-resistance element is shown in Fig. 15.2.4. The constant-current decades use Diesselhorst rings, in which the constant current entering and leaving the ring divides two paths. The IR drop across the resistance in the isothermal shield increases in 10 equal increments as the dial switch is rotated. The switch contacts are in the constant-current 15.6 Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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supply circuit, and therefore the effects of their IR drops and thermal emfs are minimized. A 100-division milliameter associated with the constant-resistance element provides nearly three additional decades of resolution. Readings to 10 nV are possible with this type of potentiometer. The direct-current comparator potentiometer used for precise measurement of unknown voltages below 2.1 V is shown in Fig. 15.2.5. Feedback from the zero-flux detector winding is used to adjust the current supply for ampere-turn balance between the primary and secondary windings as in the dc-comparator ratio bridge of Chap. 15.4. Standardization on the 1X range is obtained in a two-step FIGURE 15.2.1 Constant-current potentiometer. procedure. First, the external standard cell and galvanometer are connected in series across resistor EH by the selector switch, and the constant current source is adjusted for zero galvanometer deflection. This transfers the standard cell voltage across resistor EH. Second, the seven measuring dials are set to the known standard voltage, and the selector switch is used to connect the galvanometer across the opposing voltages AD and EH. Trimmer turns ns are used to obtain zero galvanometer deflection. This results in the standard cell voltage being generated across resistor AD with the dials set to the known standard cell value, and therefore calibration of the 1X range. The unknown emf is measured on the 1X range by using the selector switch to connect the unknown emf and the voltage generated across resistor AD in series opposition across the galvanometer. The seven

FIGURE 15.2.2 K2 potentiometer. (Leeds and Northrup)

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measuring dials are adjusted to obtain zero deflection. Specified measurement accuracies are ±(0.5 ppm of reading + 0.05 mV) on the 1X range (2.111111 V full scale), ±(1 ppm of reading + 0.01 mV) on the 0.1X range, and ±(2 ppm of reading + 0.005 mV) on the 0.01X range.

DIVIDER CIRCUITS The volt box (Fig. 15.2.6) is used to extend the voltage range of a potentiometer. The unknown voltage is connected between 0 and an appropriate terminal, for example, ×100. The potentiometer is connected between the 0 and P output terminals. When the potentiometer is balanced, it draws no current, and therefore the current drawn from the source flows through the resistor between terminals 0 and P. The unknown voltage is equal to the potentiometer reading multiplied by the selected tap multiplier. Unlike the potentiometer, the volt box does load the voltage source. Typical resistances range from about 200 to 1000 Ω/V. The higher resistance values minimize self-heating and do not load the source as heavily. Errors due to leakage currents, which could flow through the insulators supporting the resistors, are minimized by using a guard circuit (see Chap. 15.4). Decade voltage dividers provide a wide range of precisely defined, and very accurate voltage ratios. The Kelvin-Varley vernier decade circuit is shown in Fig. 15.2.7. The slide arms FIGURE 15.2.3 Constant-resistance potentiometer. in the first three decades are arranged so that they always span two contacts. The shunting effect of the second gang resistance across the slide arms of the first decade is equal to 2R, thereby giving a net resistance of R between

FIGURE 15.2.4 Microvolt potentiometer.

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FIGURE 15.2.5 Direct-current comparator potentiometer.

the slide-arm contacts. With no current drawn from the output, the resistance loading on the input is equal to 10R and is independent of the slide-arm settings. In each of the first three decades, 11 resistors are used, while only 10 resistors are used in the final decade, which has a single sliding contact. Potentiometers with six decades have been constructed using the Kelvin-Varley circuit.

DECADE BOXES Decade resistor boxes contain an assembly of resistances and switches, as shown in Fig. 15.2.8. The power rating of each resistance step is approximately constant; therefore, each decade has a different maximum current rating, which should not be exceeded. Boxes having four to seven decades are available with accuracies of 0.02 percent. Two typical seven-decade boxes provide resistance values from 0 to 1,111,111 Ω in 0.1-Ω steps and values from 0 to 11,111,110 Ω in 1-Ω steps. The accuracy at higher frequencies is affected by skin effect, series inductance, and shunt capacitance. The equivalent circuit of a resistance decade is shown in Fig. 15.2.9, where ∆L is the undesired incremental inductance added with each resistance step ∆R. Silver contacts are used to obtain a zero resistance Ro, as low as 1 mΩ/decade at dc. Zero inductance values Lo as low as 0.1 mH/decade are obtainable. The shunt capacitance for the configuration of Fig. 15.2.8 is a function of the highest decade in use, i.e., not set at zero. The shunt capacitance with the low terminal connected to the shield is typically 10 to 15 pF for the highest decade in use plus an equal value for each higher decade not in use. FIGURE 15.2.6 Volt-box circuit. Some applications, e.g., the determination of small inductances at audio frequency and the determination of resistance at radio frequency by the substitution method, require that the equivalent series inductance of the resistance box remain constant, independent of the resistance setting. In the inductively compensated decade resistance box small copper-wound coils each having an inductance equal to the inductance of an individual resistance unit are selected by the decade switch so as to maintain a constant total inductance. Decade capacitor units generally consist of four capacitances which are selectively connected in parallel by a four-gang 11-position switch (Fig. 15.2.10). The individual capacitors and their associated switch are shielded to

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FIGURE 15.2.7 Decade voltage divider.

ensure that the selected steps add properly. Decade capacitor boxes are available with six-decade resolution, which provides a range of 0 to 1.11111 mF in increments of 1 pF and with an accuracy of 0.05 percent. Air capacitors are used in the 1- and 10-pF decades, and silver-mica capacitors in the higher ranges. Polystyrene capacitors are used in some less-precise decade capacitors. Decade inductance units can be constructed using four series-connected inductances of relative units 1, 2, 3, 4 or 1, 2, 2, 5. A four-gang 11-position switch is used to short-circuit the undesired inductances. Care must be

FIGURE 15.2.8 Decade resistance box.

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FIGURE 15.2.9 Equivalent circuit of a resistance decade. (General Radio Co.)

15.11

FIGURE 15.2.10 Capacitor decade.

taken to avoid mutual coupling between the inductances. Decade inductance boxes are available with individual decades ranging from 1 mH to 10 H total inductance. A commercial single-decade unit consists of an assembly of four inductors wound on molybdenum-Permalloy dust cores and a switch which enables consecutive values to be selected. Typical units have an accuracy of 1 percent at zero frequency. The effective series inductance of a typical decade unit increases with frequency. The inductance is also a function of the ac current and any dc bias current. The Q of the coils varies with frequency.

ANALOG MEASUREMENTS Ohmmeter circuits provide a convenient means of obtaining an approximate measurement of resistance. The basic series-type ohmmeter circuit of Fig. 15.2.11a consists of an emf source, series resistor R1 and d’Arsonval milliammeter. Resistor R2 is used to compensate for changes in battery emf and is adjusted to provide full-scale meter deflection (0-Ω indication) with terminals X1 and X2 short-circuited. No deflection (infinite resistance indication) is obtained with X1 and X2 open-circuited. When an unknown resistor Rx is connected

FIGURE 15.2.11 Series-type ohmmeters: (a) basic circuit; (b) commercial circuit (Simpson Electric Co.)

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SUBSTITUTION AND ANALOG MEASUREMENTS 15.12

MEASUREMENT SYSTEMS

across the terminals, the meter deflection varies inversely with the unknown resistance. With the range switch in the position shown, half-scale deflection is obtained when the external resistance is equal to R1 + R2RM / (R2 + RM). A multirange meter can be obtained using current-shunting resistors R3 and R4. A typical commercial ohmmeter circuit (Fig. 15.2.11b) having midscale readings of 12 Ω, 1200 Ω, and 120 kΩ uses an Ayrton shunt for range selection and a higher battery voltage for the highest resistance range. In the shunt-type ohmmeter the unknown resistor Rx is connected across the d’Arsonval milliammeter, as shown in Fig. 15.2.12a. The variable resistance R1 is adjusted for fullscale deflection (infinite-resistance indication) with terminals X1 and X2 open-circuited. The ohm scale, with 0 Ω corresponding to zero deflection, is the reverse of the series-type ohmmeter scale. The resistance range can be lowered by switching a shunt resistor across the meter. With the range switch selecting shunt resistor R2, half-scale deflection occurs when Rx is equal to the parallel combination of R1, RM, and R2. The shunt-type ohmmeter is therefore most suited to low-resistance measurements. The use of a high-input impedance amplifier between the circuit and the d’Arsonval meter permits the shunt-type FIGURE 15.2.12 Shunt-type ohmmeter. (Triplett ohmmeter to be used for high- as well as low-resistance meaElectrical Instrument Co.) surements. A commercial ohmmeter (Fig. 15.2.12b) uses a field-effect-amplifier input stage which draws negligible current. The amplifier gain is adjusted to provide full-scale deflection with terminals X1 and X2 open-circuited. Half-scale deflection occurs when Rx is equal to the total selected tap resistance. Voltage-drop (or fall-of-potential) methods for determining resistance involve measuring the current flowing through the resistor with an ammeter, measuring the voltage drop across the resistor with a voltmeter, and calculating the resistance using Ohm’s law. The circuit of Fig. 15.2.13a should be used for low-resistance measurements since the current drawn by the voltmeter V/Rv will be small with respect to the total current I. The circuit of Fig. 15.2.13b should be used for high-resistance measurements since the resistance of the ammeter RA will be small with respect to the unknown resistance Rx. An accuracy of 1 percent or better can be obtained using 0.5 percent accurate instruments if the voltage source and instrument ranges are selected to provide readings near full scale. Resonance methods can be used to measure the inductance, capacitance, and Q factor of components at radio frequencies. In Fig. 15.2.14, resistors R1 and R2 couple the oscillator voltage e to a series-connected known capacitance and an unknown inductance represented by effective inductance L′ and effective series resistance r′. Resistor R2 is chosen to be small with respect to resistance r′, thereby minimizing the effect of source resistance of the injected voltage.

FIGURE 15.2.13 Fall-of-potential method: (a) for low resistances; (b) for high resistances.

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15.13

FIGURE 15.2.14 Inductance measurement.

A circuit containing reactive components is in resonance when the supply current is in phase with the applied voltage. The series circuit of Fig. 15.2.14 is in resonance when the inductive reactance XL′ is equal to the capacitive XC, which occurs when

ω 2 = ω 02 = 1/L ′C where XL′ = wL′, XC = 1/wC, w = 2p f, w0 = 2p f0, f0 = resonant frequency (Hz), L′ = effective inductance (H), and C = capacitance (F). If L′, r′, C, and e are constant and the oscillator frequency w is adjusted until the voltage read across C by the FET input voltmeter is maximum, the frequency w will be slightly less than the resonant frequency w0:

ω2 =

(r ′ + Rs )2 1 − = ω 02 L ′C 2L′ 2

 1   1 − 2Q*2 

where Rs = R1R2/(R1 + R2) and Q* = w0L′/(r′ + Rs). If Q* ≥ 10, w and w0 will differ by less than 0.3 percent. The ratio m of the voltage across C to the voltage across R2 can be measured while operating at w. If Rs 10. If Rs is not small with respect to r′, its value affects the determination of Q′ only indirectly through its effect on w. If Rs = r and Q′ ≥ 10, the determination of Q′ by the above equation is in error by less than 1 percent. If w, L′, r′, and e are constant and the capacitance C is adjusted until the voltage across it is maximum, the capacitance value C will be slightly less than the capacitance value CR needed for resonance at the frequency w: C=

 1  1 1 = CR  2 *2  ω L ′  1 + 1/Q  1 + 1/Q*2

where w = w0, Q* = w0L′/(r′ + Rs), and Rs = R1R2/(R1 + R2). For Q* ≥ 10, C differs from CR by less than 1 percent. If Rs 100 dB

>120 dB

1000 V 200 mV 100 nV ±(0.0007% + 10) ≤ 20 V: 1 GΩ >20 V: 10 MΩ >120 dB

AC voltage Max. range Min. range Sensitivity Basic accuracy (60 dB

750 V 200 mV 10 mV ±(0.5% + 10) 10 MΩ/100 pF >60 dB

750 V 2V 1 mV ±(0.25% + 1000) 2 MΩ/50 pF >60 dB

Ohms Max. range Min. range Sensitivity Basic accuracy

200 Ω 20 mΩ 100 mΩ ±(0.2% + 1)

200 Ω 200 mΩ 10 mΩ ±(0.05% + 2)

200 Ω 200 mΩ 100 mΩ ±(0.01% + 2)

DC current Max. range Min. range Sensitivity Basic accuracy

2A 2 mA 1 mA ±(0.75% + 1)

2A 200 mA 10 nA ±(0.2% + 2)

2A 200 mA 1 nA ±(0.09% + 10)

AC current Max. range Min. range Sensitivity Basic accuracy

2A 2 mA 1 mA ±(1.5% + 2)

2A 200 mA 10 nA ±(1% + 20)

2A 200 mA 1 nA ±(0.6% + 300)

CMRR (1 kΩ unbalance)

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For example, if a meter having a 10-MΩ input resistance is used to measure an unknown emf having an equivalent resistance of 100 KΩ, the meter will read 99 percent of the correct value. Resistance measurements rely on the accuracy of an internal current reference, shown as Ir in Fig.15.2.19. For an ideal meter with infinite input resistance Rin, the unknown resistance Rx is equal to Vm/Ir and the meter is calibrated to read the resistance value directly. For finite values of Rin, the indicated resistance value of Rx is equal to the parallel resistance of Rx and Rin, which can introduce a significant error in the measurement of high-value unknown resistances. The resistance of the FIGURE 15.2.18 Effect of loading. leads connecting the unknown resistance to the meter of Fig. 15.2.19 can introduce an error in the measurement of low-value resistances. This problem is overcome in high-precision meters by using separate terminals and leads to connect the precision current reference to the unknown resistance. In this case the voltage measurement leads carry only the current drawn by the input resistance Rin. Digital electrometers are highly refined dc multimeters which provide exceptionally high input resistance and sensitivity. The block diagram of a typical microcomputer-controlled digital electrometer is shown in Fig. 15.2.20. Performance depends on the high-input-resistance, low-offset-current JFET preamp and operational amplifier as well as the A/D converter. A state-of-the-art 41/2-digit autoranging meter* provides voltage ranges from 200 mV to 200 V, current ranges from 2 pA (2 × 10–12 A) to 20 mA, resistance ranges from 2 kΩ to 200 GΩ (200 × 109 Ω), and Coulomb ranges from 200 pC to 200 nC. Specified accuracies for the most-sensitive ranges are ±(0.05 percent + 4 counts) for voltage, ±(1.6 percent + 66 counts) for current, ±(0.20 percent + 4 counts) for resistance, and ±(0.4 percent + 4 counts) for charge. The input impedance is greater than 200 × 1012 Ω in parallel with 20 pF, and the input bias current is less than 5 × 10–15 A at 23°C. A bipolar 100-V, 0.2 percent-accuracy voltage source programmable in 50-mV steps and a 1-nA to 100-mA decade current source are built into the meter. Two techniques may be used to measure resistance or generate I − V curves: The decade current source can be used to force a known current through the unknown impedance with the voltage measured by the high-input-impedance voltmeter, or the voltage source can be applied across the unknown with the resulting current measured by the current meter. The latter method is preferred for characterizing voltage-dependent materials.

FIGURE 15.2.19 Effect of loading.

*Keithley

Model 617 Electrometer.

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FIGURE 15.2.20 Typical digital electrometer.

A triaxial input cable, Fig. 15.2.21, is used with the electrometer to minimize input lead leakage and cable capacitance problems. The outer shield connected to the LO input can be grounded. The inner shield is driven by electrometer unity gain low-impedance output which maintains the guard voltage essentially equal to the high-impedance input signal HI. Insulator leakage through r becomes negligible since there is essentially no voltage difference between the center conductor and the guard. Digital nanovoltmeters are digital voltmeters that are optimized for nanovolt measurements. A state-of-the-art meter uses a JFET input amplifier to obtain an input resistance of 109 Ω and a 5-nF input capacitance. Voltage ranges of 2 mV to 1000 V are available. Specified accuracy for a 24-h period is ± (0.006 percent + 5 counts) when properly zeroed. A special connector having a low thermoelectric voltage is used for the 200-mV and lower ranges.

FIGURE 15.2.21 Guard shield minimizes input leakage.

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Source: STANDARD HANDBOOK OF ELECTRONIC ENGINEERING

CHAPTER 15.3

TRANSDUCER-INPUT MEASUREMENT SYSTEMS Francis T. Thompson

Transducers are used to convert the quantity to be measured into an electric signal. Transducer types and their input and output quantities are discussed in Sec. 8.

TRANSDUCER SIGNAL CIRCUITS Amplifiers are often required to increase the voltage and power levels of the transducer output and to prevent excessive loading of the transducer by the measurement system. The design of the amplifier is a function of the performance specifications, which include required amplification in terms of voltage gain or power gain, frequency response, distortion permissible at a given maximum signal level, dynamic range, residual noise permissible at the output, gain stability, permissible drift (for dc amplifiers), operating-temperature range, available supply voltage, permissible power consumption and dissipation, reliability, size, weight, and cost. Capacitive-coupled amplifiers (ac amplifiers) are used when it is not necessary to preserve the dc component of the signal. AC amplifiers are used with transducers that produce a modulated carrier signal. Low-level amplifiers increase the signal from millivolts to several volts. The two-stage class A capacitor-coupled transistor amplifier of Fig. 15.3.1 has a power gain of 64 dB and a voltage gain of approximately 1000. Design information, an explanation of biasing, and equations for calculating the input impedance and various gain values are given in Walston and Miller (see Chap. 15.5). An excellent ac amplifier can be obtained by connecting a coupling capacitor in series with resistor R1 of the operational amplifier of Fig. 15.3.4. The capacitor should be selected so that C > 1/2p fR1, where f is the lowest signal frequency to be amplified. Class B transformercoupled amplifiers, which are often used for higher power-output stages, are also discussed in Walston and Miller (see Chap. 15.5). Direct-coupled amplifiers are used when the dc component of the signal must be preserved. These designs are more difficult than those of capacitive-coupled amplifiers because changes in transistor leakage currents, gain, and base-emitter voltage drops can cause the output voltage to change for a fixed input voltage, i.e., cause a dc-stability problem. The dc stability of an amplifier is determined primarily by the input stage since the equivalent input drift introduced by subsequent stages is equal to their drift divided by the preceding gain. Balanced input stages, such as the differential amplifier of Fig. 15.3.2, are widely used because drift components tend to cancel. By selecting a pair of transistors, Q1 and Q2, which are matched for current gain within 10 percent and base-to-emitter voltage within 3 mV, the temperature drift referred to the input can be held to within 10 mV/°C. Transistor Q3 acts as a constant-current source and thereby increases the ability of the amplifier to reject common-mode input voltages. For applications where the generator resistance rg is 15.18 Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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FIGURE 15.3.1 Two-stage cascaded commonemitter capacitive audio amplifier.

15.19

FIGURE 15.3.2 Differential amplifier.

greater than 50 kΩ, current offset becomes dominant, and lower overall drift can be obtained by using fieldeffect transistors in place of the bipolar transistors Q1 and Q2. Voltage drifts as low as 0.4 mV/°C can be obtained using integrated-circuit operational amplifiers (see Table 15.3.1). Operational amplifiers are widely used for amplifying low-level ac and dc signals. They usually consist of a balanced input stage, a number of direct-coupled intermediate stages, and a low-impedance output stage. They provide high open-loop gain, which permits the use of a large amount of gain-stabilizing negative feedback. High-gain bipolar and JFET transistors are often used in the balanced input stage. The bipolar input provides lower voltage offset and offset voltage drift while the JFET input provides higher input impedance, lower bias current, and lower offset current as can be seen in Table 15.3.1 which compares the typical specifications of three high-performance operational amplifiers. The chopper-stabilized CMOS operational amplifier provides the low offset and bias currents of FET transistors while using internal chopper stabilization to achieve excellent offset voltage characteristics. With input voltages, e1, e2, and ecm equal to zero, the output of the amplifier of Fig. 15.3.3 will have an offset voltage Eos defined by Eos = Vos

R R ( R + R2 ) R1 + R2 + I b1R2 − I b 2 3 4 1 R1 R1 ( R3 + R4 )

TABLE 15.3.1 Operational Amplifier Comparison Typical parameter (except where noted) Input characteristics Offset voltage Maximum offset voltage Avg. offset voltage drift Bias current Bias current avg. drift Maximum offset current Offset current avg. drift Differential input resistance Transfer characteristics Voltage gain Common-mode rejection ratio

Temp.

Bipolar input (Harris 5130)

JFET input (Harris 5170)

Chopper-stabilized CMOS (Siliconix 7652)

25°C 25°C Full 25°C Full 25°C Full 25°C

10 mV 25 mV 0.4 mV/°C 1 nA 20 pA/°C 2 nA 20 pA/°C 30 × 106 Ω

100 mV 300 mV 2 mV/°C 0.02 nA 3 pA/°C 0.03 nA 0.3 pA/°C 6 × 1010 Ω

0.7 mV 5 mV 0.01 mV/°C 0.015 nA

25°C

140 dB

116 dB

150 dB

25°C

120 dB

100 dB

130 dB

0.06 nA 1012 Ω

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FIGURE 15.3.3 Operational amplifier.

where Ib1 and Ib2 are bias currents that flow into the amplifier when the output is zero and Vos is the input offset voltage that must be applied across the input terminals to achieve zero output. The input bias current specified for an operational amplifier is the average of Ib1 and Ib2. Since the bias currents are approximately equal, it is desirable to choose the parallel combination of R3 and R4 equal to the parallel combination of R1 and R2. For this case, Eos = Vos(R1 + R2)/R1 + Ios R2, where the offset current Ios = Ib1 – Ib2. In the ideal case, where Vos and Ios are zero, the output voltage E0 as a function of signal voltage e1 and e2 and common-mode voltage ecm is E0 = − e1

R ( R + R2 ) − R2 ( R3 + R4 ) R2 R ( R + R2 ) + e2 4 1 + ecm 4 1 R1 R1 ( R3 + R4 ) R1 ( R3 + R4 )

Maximum common-mode rejection can be obtained by choosing R4/R3 = R2/R1, which reduces the above equation to E0 = R2(e2 – e1)/R1. The common-mode signal is not entirely rejected in an actual amplifier but will be reduced relative to a differential signal by the common-mode rejection ratio of the amplifier. Minimum drift and maximum common-mode rejection, which are important when terminating the wires from a remote transducer, can be obtained by selecting R3 = R1 and R4 = R2. Where common-mode voltages are not a problem, the simple inverting amplifier (Fig. 15.3.4) is obtained by replacing ecm and e2 with short circuits and combining R3 and R4 into one resistor, which is equal to the parallel equivalent of R1 and R2. The input impedance of this circuit is equal to R1. Similarly, the simple noninverting amplifier (Fig. 15.3.5) is obtained by replacing ecm and e1 with short circuits. The voltage follower is a special case of the noninverting amplifier where R1 = ∞ and R2 = 0. The input impedance of the circuit of Fig. 15.3.5 is equal to the parallel combination of the common-mode input impedance of the amplifier and impedance Zid [1 + (AR1)/(R1 + R2)], where Zid is the differential-mode amplifier input impedance and A is the amplifier gain. Where very high input impedances are required, as in electrometer circuits, operational amplifiers having field-effect input transistors are used to provide input resistances up to 1012 Ω.

FIGURE 15.3.4 Inverting amplifier.

FIGURE 15.3.5 Noninverting amplifier.

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15.21

An ac-coupled amplifier can be obtained by connecting a coupling capacitor in series with the input resistor of Fig. 15.3.4. The capacitor value should be selected so that the capacitive reactance at the lowest frequency of interest is lower than the amplifier input impedance R1. Operational amplifiers are useful for realizing filter networks and integrators. Other applications include absolute-value circuits, logarithmic converters, nonlinear amplification, voltage-level detection, function generation, and analog multiplication and division. Care should be taken not to exceed the maximum supply voltage and maximum common-mode voltage ratings and also to be sure that the load resistance RL is not smaller than that permitted by the rated output. The charge amplifier is used to amplify the ac signals from variable-capacitance transducers and transducers having a capacitive impedance such as piezoelectric transducers. In the simplified circuit of Fig. 15.3.6a, the current through Cs is equal to the current through C1, and therefore Cs

∂es ∂C de + es s = −C1 o ∂t ∂t dt

For the piezoelectric transducer, Cs is assumed constant, and the gain deo/des = −Cs/C1. For the variablecapacitance transducer, es is constant, and the gain deo/ dCs = –es/C1. A practical circuit requires a resistance across C1 to limit output drift. The value of this resistance must be greater than the impedance of C1 at the lowest frequency of interest. A typical operational amplifier having field-effect input transistors has a specified maximum input current of 1 nA, which will result in an output offset of only 0.1 V if a 100-MΩ resistance is used across C1. It is preferable to provide a high effective resistance by using a network of resistors, each of which has a value of 1 MΩ or less. FIGURE 15.3.6 Charge amplifier. The effective feedback resistance R′ in the practical circuit of Fig. 15.3.6b is given by R′ = R3(R1 + R2)/R2, assuming that R3 > 10R1R2/(R1 + R2). Output drift is further reduced by selecting R4 = R3 + R1R2/(R1 + R2). Resistor R5 is used to provide an upper frequency rolloff at f = 1/2pR5Cs, which improves the signal-to-noise ratio. Amplifier-gain stability is enhanced by the use of feedback since the gain of the amplifier with feedback is relatively insensitive to changes in the open-loop amplifier gain G provided that the loop gain GH is high. For example, if the open-loop gain G changes by 10 percent from 100,000 to 90,000 and the feedback divider gain H remains constant at 0.01, the closed-loop gain G/(1 + GH) ≈ 99.9 changes only 0.011 percent. If a high closed-loop gain is required, simply decreasing the value of H will reduce the value of GH and thereby reduce the accuracy. The desired accuracy can be maintained by cascading two or more amplifiers, thereby reducing the closed-loop gain required from each amplifier. Each amplifier has its own individual feedback, and no feedback is applied around the cascaded amplifiers. In this case, it is unwise to cascade more stages than needed to achieve a reasonable value of GH in each individual amplifier, since excessive loop gain will make the individual stages more prone to oscillation and the overall system will exhibit increased sensitivity to noise transients. Chopper amplifiers are used for amplifying dc signals in applications requiring very low drift. The dc input signal is converted by a chopper to a switched ac signal having an amplitude proportional to the input signal and a phase of 0 or 180° with respect to the chopper reference frequency, depending on the polarity of the input signal. This ac signal is amplified by an ac amplifier, which eliminates the drift problem, and then is converted back into a proportional dc output voltage by a phase-sensitive demodulator. The frequency response of a chopper amplifier is theoretically limited to one-half the carrier frequency. In practice, however, the frequency response is much lower than the theoretical limit. High-frequency components in the input signal exceeding the theoretical limit are removed to avoid unwanted beat signals with the chopper frequency.

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FIGURE 15.3.7 Chopper amplifier.

The chopper amplifier of Fig. 15.3.7 consists of a low-pass filter to attenuate high frequencies, an input chopper, an ac amplifier, a phase-sensitive demodulator, and a low-pass output filter to attenuate the chopper ripple component in the output signal. The frequency response of this amplifier is limited to a small fraction of the chopper frequency. The frequency-response limitation of the chopper amplifier can be overcome by using the chopper amplifier for the dc and low-frequency signals and a separate ac amplifier for the higher-frequency signals, as shown in Fig. 15.3.8. Simple shunt field-effect-transistor choppers Q1 and Q2 are used for modulation and detection, respectively. Capacitor CT is used to minimize spikes at the input to the ac amplifier. A CMOS auto-zeroed operational amplifier, which contains a built-in chopper amplifier, has typical specifications of 0.7 mV input offset voltage, 0.01 mV/°C average offset voltage drift, and 15 pA input bias current (see Table 15.3.1). Modulator-demodulator systems avoid the drift problems of dc amplifiers by using a modulated carrier which can be amplified by ac amplifiers (Fig. 15.3.9). Inputs and outputs may be either electrical or mechanical. The varactor modulator (Fig. 15.3.10) takes advantage of the variation of diode-junction capacitance with voltage to modulate a sinusoidal carrier. The carrier and signal voltages applied to the diodes are small, and the diodes never reach a low-resistance condition. Input bias currents of the order of 0.01 pA are possible. For zero signal input, the capacitance values of the diodes are equal, and the carrier signals coupled by the diodes cancel. A dc-input signal will increase the capacitance of one diode while decreasing the capacitance of the other and thereby produce a carrier imbalance signal which is coupled to the ac amplifier by capacitor C2. A phasesensitive demodulator, such as field-effect transistor Q2 of Fig. 15.3.8, may be used to recover the dc signal. The magnetic amplifier and second-harmonic modulator can also be used to convert dc-input signals to modulation on a carrier, which is amplified and later demodulated. Mechanical-input modulators include acdriven potentiometers, linear variable differential transformers, and synchros. The amplified ac carrier can be converted directly into a mechanical output by a two-phase induction servomotor.

FIGURE 15.3.8 Chopper-stabilized dc amplifier.

FIGURE 15.3.9 Modulator-demodulator system.

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FIGURE 15.3.10 Basic varactor modulator.

15.23

FIGURE 15.3.11 Analog integrator.

Integrators are often required in systems where the transducer signal is a derivative of the desired output, e.g., when an accelerometer is used to measure the velocity of a vibrating object. The output of the analog integrator of Fig. 15.3.11 consists of an integrated signal term plus error terms caused by the offset voltage Vos and the bias currents Ib1 and Ib2 e0 =

1 1 e dt + (V + I R − I R ) dt R1C ∫ 1 R1C ∫ os b1 1 b 2 2

These error terms will cause the integrator to saturate unless the integrator is reset periodically or a feedback path exists, which tends to drive the output toward a given level within the linear range. In the accelerometer integrator, accurate integration may not be required below a given frequency, and the desired stabilizing feedback path can be introduced by incorporating a large effective resistance across the capacitor using the technique shown in Fig. 15.3.6b. Digital processing of analog quantities is frequently used because of the availability of high-performance analog-to-digital (A/D) converters, digital-to-analog (D/A) converters, microprocessors, and other special digital processors. The analog input signal (Fig. 15.3.12) is converted into a sequence of digital values by the A/D converter. The digital values are processed by the microprocessor (see “The microprocessor”) or other digital processor, which can be programmed to provide a wide variety of functions including linear or nonlinear gain characteristics, digital filtering, integration, differentiation, modulation, linearization of signals from nonlinear transducers, computation, and self-calibration. The Texas Instruments TMS 320 series of digital processors are specially designed for these applications. The digital output may be used directly or converted back into an analog signal by the D/A converter. Commercial A/D converter modules are available with 15-bit resolution and 17-ms conversion times using the successive-approximation technique (Analog Devices AD 376, Burr Brown ADC 76). Monolithic integratedcircuit A/D converters are available with 12-bit resolution and 6-ms conversion times (Harris HI-774A). An 18bit D/A converter with a full-scale current output of 100 mA and a compliance voltage range of ±12 V has been

FIGURE 15.3.12 Digital processing of analog signals.

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built at the National Bureau of Standards (Schoenwetter). It exhibits a settling a time to 1/2 least significant bit (2 ppm) of less than 20 ms. Commercial 16- and 18-bit D/A converters are available with 2-mA full-scale outputs (Analog Devices DAC1136/1138, Burr Brown DAC 70). The application of A/D converters, D/A converters, and sample-and-hold (S/H) circuits requires careful consideration of their static and dynamic characteristics. The microprocessor is revolutionizing instrumentation and control. The digital processing power that previously cost many thousands of dollars has been made available on a silicon integrated-circuit chip for only a few dollars. A microcomputer system (Fig. 15.3.13) consists of a microprocessor central processing unit (CPU), memory, and input-output ports. A typical microprocessorbased system consists of the 8051 microprocessor, which provides 4 kbytes of read-only memory (ROM), 128 bytes of random-access memory (RAM), 2 timers and 32 inputoutput lines, and a number of additional RAM and ROM memory chips as needed for a particular application. The microprocessor can provide a number of features at little FIGURE 15.3.13 Microcomputer system. incremental cost by means of software modification. Typical features include automatic ranging, self-calibration, self-diagnosis, data conversion, data processing, linearization, regulation, process monitoring, and control. Instruments using microprocessors are described in Chaps. 15.2 and 15.4. Instrument systems can be automated by connecting the instruments to a computer using the IEEE-448 general purpose interface bus (Santoni). The bus can connect as many as 14 individually addressable instruments to a host computer port. Full control capability requires the selection of instruments that permit bus control of front panel settings as well as bus data transfers. Voltage comparators are useful in a number of applications, including signal comparison with a reference, positive and negative signal-peak detection, zero-crossing detection, A/D successive-approximation converter systems, crystal oscillators, voltage-controlled oscillators, magnetic-transducer voltage detection, pulse generation, and square-wave generation. Comparators with input offset voltages of 2 mV and input offset currents of 5 nA are commercially available. Analog switches using field-effect-transistor (FET) technology are used in general-purpose high-level switching (±10 V), multiplexing, A/D conversion, chopper applications, set-point adjustment, and bridge circuits. Logic and schematic diagrams of a typical bilateral switch are shown in Fig. 15.3.14. The switch provides the required isolation between the data signal and the control signal. Typical switches provide zero offset voltage, on resistance of 35 Ω, and leakage current of 0.04 nA. Multiple-channel switches are commercially available in a single package. Output Indicators. A variety of analog and digital output indicators can be used to display and record the output from the signal-processing circuitry.

FIGURE 15.3.14 Bilateral analog switch.

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Source: STANDARD HANDBOOK OF ELECTRONIC ENGINEERING

CHAPTER 15.4

BRIDGE CIRCUITS, DETECTORS, AND AMPLIFIERS Francis T. Thompson

PRINCIPLES OF BRIDGE MEASUREMENTS Bridge circuits are used to determine the value of an unknown impedance in terms of other impedances of known value. Highly accurate measurements are possible because a null condition is used to compare ratios of impedances. The most common bridge arrangement (Fig. 15.4.1) contains four branch impedances, a voltage source, and a null detector. Galvanometers, alone or with chopper amplifiers, are used as null detectors for dc bridges; while telephone receivers, vibration galvanometers, and tuned amplifiers with suitable detectors and indicators are used for null detection in ac bridges. The voltage across an infinite-impedance detector is Vd =

( Z1Z 3 − Z 2 Z x ) E ( Z1 + Z 2 ) ( Z 3 + Z x )

If the detector has a finite impedance Z5, the current in the detector is Id =

( Z1Z 3 − Z 2 Z s ) E Z 5 ( Z1 + Z 2 ) ( Z3 + Z x ) + Z1Z 2 ( Z3 + Z x ) + Z 3Z x ( Z1 + Z 2 )

where E is the potential applied across the bridge terminals. A null or balance condition exists when there is no potential across the detector. This condition is satisfied, independent of the detector impedance, when Z1Z3 = Z2Zx. Therefore, at balance, the value of the unknown impedance Zx can be determined in terms of the known impedances Z1, Z2, and Z3: Zx = Z1Z3/Z2 Since the impedances are complex quantities, balance requires that both magnitude and phase angle conditions be met: |Zx| = |Z1| ⋅| Z3|/|Z2| and qx = q1 + q3 − q2. Two of the known impedances are usually fixed impedances, while the third impedance is adjusted in resistance and reactance until balance is attained.

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The sensitivity of the bridge can be expressed in terms of the incremental detector current ∆Id for a given small per-unit deviation d of the adjustable impedance from the balance value. If Z1 is adjusted, d = ∆Z1/Z1 and ∆ Id =

Z 3Z x Eδ ( Z 3 + Z x )2 [ Z 5 + Z1Z 2 /( Z1 + Z 2 ) + Z 3Z x /( Z 3 + Z x )]

when Z5 is the detector impedance. If a high-input-impedance amplifier is used for the detector and impedance Z5 can be considered infinite, the sensitivity can be expressed in terms of the incremental input voltage to the detector ∆Vd for a small deviation from balance ∆Vd = Z 3Z x Eδ /( Z 3 + Z x )2 = Z1Z 2 Eδ /( Z1 + Z 2 )2 where d = ∆Z1/Z1 and ∆Z1 is the deviation of impedance Z1 from its balance value Z1. Maximum sensitivity occurs when the magnitudes of Z3 and Zx are equal (which for balance implies that the magnitudes of Z1 and Z2 are equal). Under this condition, ∆Vd = Ed/4 when the phase angles q3 and qx are equal; ∆Vd = Ed/2 when the phase angles q3 and qx are in quadrature; and ∆Vd is infinite when q3 = −qx, as is the case with lossless reactive components of opposite sign. In practice, the value of the adjustable impedance must be sufficiently large to ensure that the resolution provided by the finest adjusting step permits the desired precision to be obtained. This value may not be compatible with the highest sensitivity, but adequate sensitivity can be obtained for an order-of-magnitude difference between Z3 and Zx or Z1 and Z2, especially if a tuned-amplifier detector is used. FIGURE 15.4.1 Basic impedance bridge.

Interchanging the source and detector can be shown to be equivalent to interchanging impedances Z1 and Z3. This interchange does not change the equation for balance but does change the sensitivity of the bridge. For a fixed applied voltage E higher sensitivity is obtained with the detector connected from the junction of the two high-impedance arms to the junction of the two low-impedance arms. The source voltage must be carefully selected to ensure that the allowable power dissipation and voltage ratings of the known and unknown impedances of the bridge are not exceeded. If the bridge impedances are low with respect to the source impedance Zs, the bridge-terminal voltage E will be lowered. This can adversely affect the sensitivity, which is proportional to E. The source for an ac bridge should provide a pure sinusoidal voltage since the harmonic voltages will usually not be nulled when balance is achieved at the fundamental frequency. A tuned detector is helpful in achieving an accurate balance. Balance Convergence. The process of balancing an ac bridge consists of making successive adjustments of two parameters until a null is obtained at the detector. It is desirable that these parameters do not interact and that convergence be rapid. The equation for balance can be written in terms of resistances and reactances as Rx + jX x = ( R1 + jX1 )( R3 + jX 3 )/( R2 + jX 2 ) Balance can be achieved by adjusting any or all of the six known parameters, but only two of them need be adjusted to achieve the required equality of both magnitude and phase (or real and imaginary components). In a ratio-type bridge, one of the arms adjacent to the unknown, either Z1 and Z3, is adjusted. Assuming that Z1 is adjusted, then to make the resistance adjustment independent of the change in the corresponding reactance, the ratio (R3 + jX3)/(R2 + jX2) must be either real or imaginary but not complex. If this ratio is equal to the real number k, then for balance Rx = kR1 and Xx = kX1. In a product-type bridge, the arm opposite the unknown Z2

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FIGURE 15.4.2 Linearized convergence locus.

is adjusted for balance, and the product of Z1Z3 must be either real or imaginary to make the resistance adjustment independent of the reactance adjustment. Near balance, the denominator of the equation giving the detector voltage (or current) changes little with the varied parameter, while the numerator changes considerably. The usual convergence loci, which consist of circular segments, can be simplified to obtain linear convergence loci by assuming that the detector voltage near balance is proportional to the numerator, Z1Z3 − Z2Zx. Values of this quantity can be plotted on the complex plane. When only a single adjustable parameter is varied, a straight-line locus will be produced as shown in Fig. 15.4.2. Varying the other adjustable parameter will produce a different straight-line locus. The rate of convergence to the origin (balance condition) will be most rapid if these two loci are perpendicular, slow if they intersect at a small angle, and zero if they are parallel. The cases of independent resistance and reactance adjustments described above correspond to perpendicular loci.

RESISTANCE BRIDGES The Wheatstone bridge is used for the precise measurement of two-terminal resistances. The lower limit for accurate measurement is about 1 Ω, because contact resistance is likely to be several milliohms. For simple galvanometer detectors, the upper limit is about 1 MΩ, which can be extended to 1012 by using a high-impedance high-sensitivity detector and a guard terminal to substantially eliminate the effects of stray leakage resistance to ground. The Wheatstone bridge (Fig. 15.4.3) although historically older, may be considered as a resistance version of the impedance bridge of Fig. 15.4.1, and therefore the sensitivity equations are applicable. At balance Rx = R1R3/R2 Known fixed resistors, having values of 1, 10, 100, or 1000 Ω, are generally used for two arms of the bridge, for example, R2 and R3. These arms provide a ratio R3/R2, which can be selected from 10–3 to 103. Resistor R1, typically adjustable to 10,000 Ω in 1- or 0.1-Ω steps, is adjusted to achieve balance. The ratio R3/R2 should be chosen so that R1 can be read to its full precision. The magnitudes of R2 and R3 should be chosen to maximize the sensitivity while taking care not to draw excessive current.

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FIGURE 15.4.4 Kelvin double bridge. A + B is typically 1000 Ω and a + b is typically 1000 Ω.

FIGURE 15.4.3 Wheatstone bridge.

An alternate arrangement using R1 and R2 for the ratio resistors and adjusting R3 for balance will generally provide a different sensitivity. The battery key B should be depressed first to allow any reactive transients to decay before the galvanometer key is depressed. The low-galvanometer-sensitivity key L should be used until the bridge is close to balance. The high-sensitivity key H is then used to achieve the final balance. Resistance RD provides critical damping between the galvanometer measurements. The battery connections to the bridge may be reversed and two separate resistance determinations made to eliminate any thermoelectric errors. The Kelvin double bridge (Fig. 15.4.4) is used for the precise measurement of low-value four-terminal resistors in the range 1 mΩ to 10 Ω. The resistance to be measured X and a standard resistance S are connected by means of their current terminals in a series loop containing a battery, an ammeter, an adjustable resistor, and a low-resistance link l. Ratio-arm resistances A and B and a and b are connected to the potential terminals of resistors X and S as shown. The equation for balance is X=S

βl  A α  A + − B α + β + l  B β 

If the ratio a/b is made equal to the ratio A/B, the equation reduces to X = S(A/B). The equality of the ratios should be verified after the bridge is balanced by removing the link. If a /b = A/B, the bridge will remain balanced. Lead resistances r1, r2, r3, and r4 between the bridge and the potential terminals of the resistors may contribute to ratio imbalance unless they have the same ratio as the arms to which they are connected. Ratio imbalance caused by lead resistance can be compensated by shunting a or b with a high resistance until balance is obtained with the link removed. In some bridges a fixed standard resistor S having a value of the same order of magnitude as resistor X is used. Fixed resistors of 10, 100, or 1000 Ω are used for two arms, for example, B and b, with B and b having equal values. Bridge balance is obtained by adjusting tap switches to select equal resistances for the other two arms, for example, A and a, from values adjustable up to 1000 Ω in 0.1-Ω steps. In other bridges, only decimal ratio resistors are provided for A, B, a, and b, and balance is obtained by means of an adjustable standard having nine steps of 0.001 Ω each and a Manganin slide bar of 0.0011 Ω.

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The battery connection should be reversed and two separate resistance determinations made to eliminate thermoelectric errors. The dc-comparator ratio bridge (Fig. 15.4.5) is used for very precise measurement of four-terminal resistors. Its accuracy and stability depend mainly on the turns ratio of a precision transformer. The master current supply is set at a convenient fixed value Ix. The zero-flux detector maintains an ampere-turn balance, IxNx = IsNs, by automatically adjusting the current Is from the slave supply as Nx is manually adjusted. A null reading on the galvanometer is obtained when IsRs = IxRx. Since the current ratio is precisely related to the turns ratio, the unknown resistance Rx = NxRs /Ns. Fractional turn FIGURE 15.4.5 Comparator ratio bridge. resolution for Nx can be obtained by diverting a fraction of the current Ix as obtained from a decade current divider through an additional winding on the transformer. Turns ratios have been achieved with an accuracy of better than 1 part in 107. The zero-flux detector operates by superimposing a modulating mmf on the core using modulation and detector windings in a second-harmonic modulator configuration. The limit sensitivity of the bridge is set by noise and is about 3 mA turns. Murray and Varley bridge circuits are used for locating faults in wire lines and cables. The faulted line is connected to a good line at one end by means of a jumper to form a loop. The resistance r of the loop is measured using a Wheatstone bridge. The loop is then connected as shown in Fig. 15.4.6 to form a bridge in which one arm contains the resistance Rx between the test set and the fault and the adjacent arm contains the remainder of the loop resistance. The galvanometer detector is connected across the open terminals of the loop, while the voltage supply is connected between the fault and the junction of fixed resistor R2 and variable resistor R3. When balance is attained Rx = rR3/(R2 + R3) where r is the resistance of the loop. Resistance Rx is proportional to the distance to the fault. In the Varley loop of Fig. 15.4.7, variable resistor R1 is adjusted to achieve balance and Rx =

rR3 − R1R2 R2 + R3

where r is the resistance of the loop.

FIGURE 15.4.6 Murray loop-bridge circuits.

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FIGURE 15.4.7 Varley loop circuit.

INDUCTANCE BRIDGES General. Many bridge types are possible since the impedance of each arm may be a combination of resistances, inductances, and capacitances. A number of popular inductance bridges are shown in Fig. 15.4.8. In the balance equations L and M are given in henrys, C in farads, and R in ohms; w is 2p times the frequency in hertz. The Q of an inductance is equal to wL/R, where R is the series resistance of the inductance. The symmetrical inductance bridge (Fig. 15.4.8a) is useful for comparing the impedance of an unknown inductance with that of a known inductance. An adjustable resistance is connected in series with the inductance having the higher Q, and the inductance and resistance values of this resistance are added to those of the associated inductance to obtain the impedance of that arm. If this series resistance is adjusted along with the known inductance to obtain balance, the resistance and reactance balances are independent and balance convergence is rapid. If only a fixed inductance is available, the series resistance is adjusted along with the ratio R3/R2 until balance is obtained. These adjustments are interacting, and the rate of convergence will be proportional to the Q of the unknown inductance. Care must be taken to avoid inductive coupling between the known and unknown inductances since it will cause a measurement error. The Maxwell-Wien bridge (Fig. 15.4.8b) is widely used for accurate inductance measurements. It has the advantage of using a capacitance standard which is more accurate and easier to shield and produces practically no external field. R2 and C2 are usually adjusted since they provide a noninteracting resistance and inductance balance. If C2 is fixed and R2 and R1 or R3 are adjusted, the balance adjustments interact and balancing may be tedious. Anderson’s bridge (Fig. 15.4.8c) is useful for measuring a wide range of inductances with reasonable values of fixed capacitance. The bridge is usually balanced by adjusting r and a resistance in series with the unknown inductance. Preferred values for good sensitivity are R1 = R2 = R3/2 = Rx /2 and L/C = 2R2x. This bridge is also used to measure the residuals of resistors using a substitution method to eliminate the effects of residuals in the bridge elements. Owen’s bridge (Fig. 15.4.8d ) is used to measure a wide range of inductance values in terms of resistance and capacitance. The inductance and resistance balances are independent if R3 and C3 are adjusted. The bridge can also be balanced by adjusting R1 and R3. This bridge is useful for finding the incremental inductance of iron-cored inductors to alternating current superimposed on a direct current. The direct current can be introduced by connecting a dc-voltage source with a large series inductance across the detector branch. Low-impedance blocking capacitors are placed in series with the detector and the ac source. Hay’s bridge (Fig. 15.4.8e) is similar to the Maxwell-Wien bridge and is used for measuring inductances having large values of Q. The series R2 C2 arrangement permits the use of smaller resistance values than the parallel arrangement. The frequency-dependent 1/Q 2x term in the inductance equation is inconvenient since the dials cannot be calibrated to indicate inductance directly unless the term is neglected, which causes a 1 percent error for Qx = 10.

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FIGURE 15.4.8 Inductance bridges: (a) symmetrical inductance bridge; (b) MaxwellWien bridge; (c) Anderson’s bridge; (d) Owen’s bridge; (e) Hay’s bridge; ( f ) Campbell’s bridge.

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This bridge is also used for determining the incremental inductance of iron-cored reactors, as discussed for Owen’s bridge. Campbell’s bridge (Fig. 15.4.8f ) for measuring mutual inductance makes possible the comparison of unknown and standard mutual inductances having different values. The resistances and self-inductances of the primaries are balanced with the detector switches to the right by adjusting L1 and R1. The switches are thrown to the left, and the mutual-inductance balance is made by adjusting Ms. Care must be taken to avoid coupling between the standard and unknown inductances.

CAPACITANCE BRIDGES Capacitance bridges are used to make precise measurements of capacitance and the associated loss resistance in terms of known capacitance and resistance values. Several different bridge circuits are shown in Fig. 15.4.9. In the balance equations R is given in ohms and C in farads, and w is 2p times the frequency in hertz. The loss angle d of a capacitor may be expressed either in terms of its series loss resistance rs, which gives tan d = w Crs, or in terms of the parallel loss resistance rp, in which case, tan d = 1/w Crp.

FIGURE 15.4.9 Capacitance bridges: (a) series-resistance-capacitance bridge; (b) Wien bridge; (c) Schering’s bridge; (d) transformer bridge.

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The Series RC bridge (Fig. 15.4.9a) is a resistance-ratio bridge used to compare a known capacitance with an unknown capacitance. The adjustable series resistance is added to the arm containing the capacitor having the smaller loss angle d. The Wien bridge (Fig. 15.4.9b) is useful for determining the equivalent capacitance Cx and parallel loss resistance Rx of an imperfect capacitor, e.g., a sample of insulation or a length of cable. An important application of the Wien bridge network is its use as the frequency-determining network in RC oscillators. Schering’s bridge (Fig. 15.4.9c) is widely used for measuring capacitance and dissipation factors. The unknown capacitance is directly proportional to known capacitance C1. The dissipation factor w CxRx can be measured with good accuracy using this bridge. The bridge is also used for measuring the loss angles of highvoltage power cables and insulators. In this application, the bridge is grounded at the R2 /R3 node, thereby keeping the adjustable elements R2, R3, and C2 at ground potential. The transformer bridge is used for the precise comparison of capacitors, especially for three-terminal shielded capacitors. A three-winding toroidal transformer having low leakage reactance is used to provide a stable ratio, known to better than 1 part in 107. In Fig. 15.4.9d capacitors C1 and C2 are being compared, and a balance scheme using inductive-voltage dividers a and b is shown. It is assumed that C1 > C2 and loss angle d2 > d1. In-phase current to balance any inequality in magnitude between C1 and C2 is injected through C5 while quadrature current is supplied by means of resistor R and current divider C3/(C3 + C4). The current divider permits the value of R to be kept below 1 MΩ. Fine adjustments are provided by dividers a and b. Na is the fraction of the voltage E1 that is applied to R, while Nb is the fraction of the voltage E2 applied to C5, d1 is the loss angle of capacitor C1 and tan d1 = w C1r1, where r1 is the series loss resistance associated with C1. The impedance of C3 and C4 in parallel must be small compared with the resistance of R. The substitution-bridge method is particularly valuable for determining the value of capacitance at radtio frequency. The shunt-substitution method is shown for the series RC bridge in Fig. 15.4.10. Calibrated adjustable standards Rs and Cs are connected as shown, and the bridge is balanced in the usual manner with the unknown capacitance disconnected. The unknown is then connected in parallel with Cs, and Cs and Rs are readjusted to obtain balance. The unknown capacitance Cx and its equivalent series resistance Rx are determined by the rebalancing changes ∆Cs and ∆Rs in Cs and Rs, respectively: Cx = ∆Cs and Rx = ∆Rs(Cs1/Cx)2, where Cs1 is the value of Cs in the initial balance. In series substitution the bridge arm is first balanced with the standard elements alone, the standard elements having an impedance of Zs1, and then the unknown is inserted in series with the standard elements. The standard elements are readjusted to an impedance Zs2 to restore balance. FIGURE 15.4.10 Substitution measurement. The unknown impedance Zx is equal to the change in the standard impedance, that is, Zx = Zs1 − Zs2. Measurement accuracy depends on the accuracy with which the changes in the standard values are known. The effects of residuals, stray capacitance, stray coupling, and inaccuracies in the impedances of the other three bridges arms are minimal, since these effects are the same with and without the unknown impedance. The proper handling of the leads used to connect the unknown impedance can be important.

FACTORS AFFECTING ACCURACY Stray Capacitance and Residuals. The bridge circuits of Figs. 15.4.8 and 15.4.9 are idealized since stray capacitances which are inevitably present and the residual inductances associated with resistances and connecting leads have been neglected. These spurious circuit elements can disturb the balance conditions and

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FIGURE 15.4.11 Stray capacitances in unshielded and ungrounded bridge.

FIGURE 15.4.12 Bridge with shields and ground.

result in serious measurement errors. Detailed discussions of the residuals associated with the various bridges are given in Souders. Shielding and grounding can be used to control errors caused by stray capacitance. Stray capacitances in an ungrounded, unshielded series RC bridge are shown schematically by C1 through C12 in Fig. 15.4.11. The elements of the bridge may be enclosed in the grounded metal shield, as shown schematically in Fig. 15.4.12. Shielding and grounding eliminate some capacitances and make the others definite localized capacitances which act in a known way as illustrated in Fig. 15.4.13. The capacitances associated with terminal D shunt the oscillator and have no adverse effect. The possible adverse effects of the capacitance associated with the output diagonal EF are overcome by using a shielded output transformer. If the shields are adjusted so that C22/C21 = Ra/Rb, the ratio of the bridge is independent of frequency. Capacitance C24 can be taken into account in the calibration of Cs, and capacitance C23 can be measured and its shunting effect across the unknown impedance can be calculated. Shielding, which is used at audio frequencies, becomes more necessary as the frequency and impedance levels are increased. Guard circuits (Fig. 15.4.14) are often used at critical circuit points to prevent leakage currents from causing measurement errors. In an unguarded circuit surface leakage current may bypass the resistor R and flow through the detector G, thereby giving an erroneous reading. If a guard ring surrounds the positive terminal

FIGURE 15.4.13 Schematic circuit of shielded and grounded bridge.

FIGURE 15.4.14 Leakage current in guarded circuit. (Leeds and Northrup)

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post (as in the circuit of Fig. 15.4.14), the surface leakage current flows through the guard ring and a noncritical return path to the voltage source. A true reading is obtained since only the resistor current flows through the detector. Coaxial leads and twisted-wire pairs may be used in connecting impedances to a bridge arm in order to minimize spurious-signal pickup from electrostatic and electromagnetic fields. It is important to keep lead lengths short, especially at high frequencies.

BRIDGE DETECTORS AND AMPLIFIERS Galvanometers are used for null decision in dc bridges. The permanent-magnet moving-coil d’Arsonval galvanometer is widely used. The suspension provides a restoring torque so that the coil seeks a zero position for zero current. A mirror is used in the sensitive suspension-type galvanometer to reflect light from a fixed source to a scale. This type of galvanometer is capable of sensitivities on the order of 0.001 mA per millimeter scale division but is delicate and subject to mechanical disturbances. Galvanometers for portable instruments generally have indicating pointers and use taut suspensions which are less sensitive but more rugged and less subject to disturbances. Sensitivities are typically in the range of 0.5 mA per millimeter scale division. Galvanometers exhibit a natural mechanical frequency which depends on the suspension stiffness and the moment of inertia. Overshoot and oscillatory behavior can be avoided without an excessive increase in response time if an external resistance of the proper value to produce critical damping is connected across the galvanometer terminals. Null-detector amplifiers incorporating choppers or modulators (see Chap. 15.3) are used to amplify the null output signal from dc bridges to provide higher sensitivity and permit the use of rugged, less-sensitive microammeter indicators. Null-detector systems such as the L&N 9838 are available with sensitivities of 10 nV per division for a 300-Ω input impedance. The Guideline 9460A nanovolt amplifier uses a light-beam-coupled amplifier that can provide 7.5-mm deflection per nV when used with a sensitive galvanometer. The input signal polarity to this amplifier may be reversed without introducing errors because of hysteresis or input offset currents. This reversal-capability is useful to balance out parasitic or thermal emfs in the measured circuit. Frequency-selective amplifiers are extensively used to increase the sensitivity of ac bridges. An ac amplifier with a twin-T network in the feedback loop provides full amplification at the selected frequency but falls off rapidly as the frequency is changed. Rectifiers or phase-sensitive detectors are used to convert the amplified ac signal into a direct current to drive a dc microammeter indicator. The General Radio 1232-A tuned amplifier and null detector, which is tunable from 20 Hz to 20 kHz with fixed-tuned frequencies of 50 and 100 kHz, provides a sensitivity better than 0.1 mV. Cathode-ray-tube displays using Lissajous patterns are also used to indicate the deviation from null conditions. Amplifier and detector circuits are described in Chap. 15.3.

MISCELLANEOUS MEASUREMENT CIRCUITS Multifrequency LCR meters incorporate microprocessor control of ranging and decimal-point positioning, which permits automated measurement of inductance, capacitance, and resistance in less than 1 s. Typical of the new generation of microprocessor instrumentations is the General Radio 1689 Digibridge, which automatically measures a wide range of L, C, R, D, and Q values from 12 Hz to 100 kHz with a basic accuracy of 0.02 percent. This instrument compares sequential measurements rather than obtaining a null condition and therefore is not actually a bridge. Similar performance is provided by the Hewlett-Packard microprocessor-based 4274A (100 Hz to 100 kHz) and 4275A (10 kHz to 10 MHz) multifrequency LCR meters, which measure the impedance of the device under test at a selected frequency and compute the value of L, C, R, D, and Q as well as the impedance, reactance, conductance, susceptance, and phase angle with a basic accuracy of 0.1 percent.

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MEASUREMENT SYSTEMS

FIGURE 15.4.15 Q meter. (Hewlett-Packard )

The Q meter is used to measure the quality factor Q of coils and the dissipation factor of capacitors; the dissipation factor is the reciprocal of Q. The Q meter provides a convenient method of measuring the effective values of inductors and capacitors at the frequency of interest over a range of 22 kHz to 70 MHz. The simplified circuit of a Q meter is shown in Fig. 15.4.15, where an unknown impedance of effective inductance L′ and effective resistance r′ is being measured. A sinusoidal voltage e is injected by the transformer secondary in series with the circuit containing the unknown impedance and the tuning capacitor C. The transformer secondary has an output impedance of approximately 1 mΩ. Unknown capacitors can be measured by connecting them between the HI and GND terminals while using a known standard inductor for L′. Either the oscillator frequency or the tuning-capacitor value is adjusted to bring the circuit to approximate resonance, as indicated by a maximum voltage across capacitor C. At resonance XL′ = Xc where XL′ = 2p f L′, Xc = 1/2p fC, L′ is the effective inductance in henrys, C is the capacitance in farads, and f is the frequency in hertz. The current at resonance is I = e/R, where R is the sum of the resistances of the unknown and the internal circuit. The voltage across the capacitor C is VC = IXC = eXC /R, and the indicated circuit Q is equal to VC /e. In practice, the injected voltage e is known for each Q-range attenuator setting and the meter is calibrated to indicate the value of Q. Corrections for residual resistances and reactances in the internal circuit become increasingly important at higher frequencies (see Chap. 15.2). For low values of Q, neglecting the difference between the resonance and the approximate resonance achieved by maximizing the capacitor voltage may result in an unacceptable error. Exact equations are given in Chap. 15.2. The rf impedance analyzer is a microprocessor-based instrument designed to measure impedance parameter values of devices and materials in the rf and UHF regions. The basic measurement circuit consists of a signal source, an rf directional bridge, and a vector voltage ratio detector as shown in Fig. 15.4.16. The measurement source produces a selectable 1-MHz to 1-GHz sinusoidal signal using frequency synthesizer techniques. The unknown impedance Zx is connected to a test port of an rf directional bridge having resistor values Z equal to the 50-Ω characteristic impedance of the measuring circuit. The test-channel and reference-channel signal frequencies are converted to 100 kHz by the sampling i.f. converters in order to improve the accuracy of vector ratio detection. The vector ratio of the test channel and reference channel i.f. signals is detected for both the real and imaginary component vectors. The vector ratio, which is equal to e2 /e1, is proportional to the reflection coefficient Γ, where Γ = (Z − Zx)/(Z + Zx). The microprocessor computes values of L, C, D, Q, R, X, q, G, and B from the real and imaginary components Γx and Γy of the reflection coefficient Γ. The basic accuracy of the magnitude of Γ is better than 1 percent, while that of other parameters is typically better than 2 percent. The twin-T measuring circuit of Fig. 15.4.17 is used for admittance measurements at radio frequencies. This circuit operates on a null principle similar to a bridge circuit, but it has an advantage in that one side of the oscillator and detector are common and therefore can be grounded. The substitution method is used with this circuit, and therefore the effect of stray capacitances is minimized. The circuit is first balanced to a null condition

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15.37

FIGURE 15.4.16 Rf impedance analyzer. (Hewlett-Packard)

with the unknown admittance Gx + jBx unconnected. GL = ω 2 RC1C2 (1 + Co /C3 ) L = 1 / [ω 2 (Cb + C1 + C2 + C1C2 /C3 )] The unknown admittance is connected to terminals a and b, and a null condition is obtained by readjusting the variable capacitors to values C′a and C′b The conductance Gx and the susceptance Bx of the unknown are proportional to the changes in the capacitance settings: Gx = ω 2 RC1C2 (Ca′ − Ca )/C3

Bx = ω (Cb − Cb′ )

Measurement of Coefficient of Coupling. Two coils are inductively coupled when their relative positions are such that lines of flux from each coil link with turns of the other coil. The mutual inductance M in henrys can be measured in terms of the voltage e induced in one coil by a rate of change of current di/dt in the other coil; M = −e1/(di2/dt) = −e2 /(di1/dt). The maximum coupling between two coils of self-inductance L1 and L2 exists when all the flux from each of the coils links all the turns of the other coil; this condition produces the maximum value of mutual inductance, Mmax = √L1L2. The coefficient of coupling k is defined as the ratio of the actual mutual inductance to its maximum value; k = M/√L1L2. The value of mutual inductance can be measured using Campbell’s mutual-inductance bridge. Alternately, the mutual inductance can be measured using a selfinductance bridge. When the coils are connected in series with the mutual-inductance emf aiding the selfinductance emf (Fig. 15.4.18a), the total inductance La = FIGURE 15.4.17 Twin-T measuring circuit. (General L1 + L2 + 2M is measured. With the coils connected with Radio Co.)

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MEASUREMENT SYSTEMS

FIGURE 15.4.18 Mutual inductance connected for self-inductance measurement: (a) aiding configuration; (b) opposing configuration.

the mutual-inductance emf opposing the self-inductance emf (Fig. 15.4.18b), inductance Lb = L1 + L2 − 2M is measured. The mutual inductance is M = (La − Lb)/4. Permeameters are used to test magnetic materials. By simulating the conditions of an infinite solenoid, the magnetizing force H can be computed from the ampere-turns per unit length. When H is reversed, the change in flux linkages in a test coil induces an emf whose time integral can be measured by a ballistic galvanometer. The Burrows permeameter (Fig. 15.4.19) uses two magnetic specimen bars, S1 and S2, usually 1 cm in diameter and

FIGURE 15.4.19 Burrows permeameter.

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15.39

30 cm long, joined by soft-iron yokes. High precision is obtainable for magnetizing forces up to 300 Oe. The currents in magnetizing windings M1 and M2 and in compensating windings A1, A2, A3, and A4 are adjusted independently to obtain uniform induction over the entire magnetic circuit. Windings A1, A2, A3, and A4 compensate for the reluctance of the joints. The reversing switches are mechanically coupled and operate simultaneously. Test coils a and c each have n turns, while each half of the test coil b has n/2 turns. Coils a and b are connected in opposing polarity to the galvanometer when the switch is in position b, while coils a and c are opposed across the galvanometer for switch position c. Potentiometer P1 is adjusted to obtain the desired magnetizing force, and potentiometers P2 and P3 are adjusted so that no galvanometer deflection is obtained on magnetizing current reversal with the switches in either position b or c. This establishes uniform flux density at each coil. The switch is now set at position a and the galvanometer deflection d is noted when the magnetizing current is reversed. The values of B in gauss and H in oersteds can be calculated from H= where N I l d k R a A n

0.4π NI l

B = 108

dkR A − a − H 2an a

= turns of coil M1 = current in coil M1 (A) = length of coil M1 (cm) = galvanometer deflection = galvanometer constant = total resistance of test coil a circuit = area of specimen (cm2) = area of test coil (cm2) = turns in test coil a

The term (A − a)H/a is a small correction term for the flux in the space between the surface of the specimen and the test coil. Other permeameters such as the Fahy permeameter, which requires only a single specimen, the SandfordWinter permeameter, which uses a single specimen of rectangular cross section, and Ewing’s isthmus permeameter, which is useful for magnetizing forces as high as 24,000 G, are discussed in Harris. The frequency standard of the National Institute of Standards and Technology (formerly the National Bureau of Standards) is based on atomic resonance of the cesium atom and is accurate to 1 part in 1013. The second is defined as the duration of 9,192,631,770 periods of the radiation corresponding to the transition between the two hyper-fine levels of the ground state of the atom of cesium 133. Reference frequency signals are transmitted by the NIST radio stations WWV and WWH at 2.5, 5, 10, and 15 MHz. Pulses are transmitted to mark the seconds of each minute. In alternate minutes during most of each hour, 500- or 600-Hz audio tones are broadcast. A binary-coded-decimal time code is transmitted continuously on a 100-Hz subcarrier. The carrier and modulation frequencies are accurate to better than 1 part in 1011. These frequencies are offset by a known and stable amount relative to the atomic-resonance frequency standard to provide “Coordinated Universal Time” (UTC), which is coordinated through international agreements by the International Time Bureau. UTC is maintained within ±0.9 s of the UT1 time scale used for astronomical measurements by adding leap seconds about once per year to UTC, depending on the behavior of the earth’s rotation. Quartz-crystal oscillators are used as secondary standards for frequency and time-interval measurement. They are periodically calibrated using the standard radio transmissions. Frequency measurements can be made by comparing the unknown frequency with a known frequency, by counting cycles over a known time interval, by balancing a frequency-sensitive bridge, or by using a calibrated resonant circuit. Frequency-comparison methods include using Lissajous patterns on an oscilloscope and heterodyne measurement methods. In Fig. 15.4.20, the frequency to be measured is compared with a harmonic of the 100-kHz reference oscillator. The difference frequency lying between 0 and 50 kHz is selected by the low-pass filter and

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MEASUREMENT SYSTEMS

FIGURE 15.4.20 Heterodyne frequency-comparison method.

compared with the output of a calibrated audio oscillator using Lissajous patterns. Alternately, the difference frequency and the audio oscillator frequency may be applied to another detector capable of providing a zero output frequency. Digital frequency meters provide a convenient and accurate means for measuring frequency. The unknown frequency is counted for a known time interval, usually 1 or 10 s, and displayed in digital form. The time interval is derived by counting pulses from a quartz-crystal oscillator reference. Frequencies as high as 50 MHz can be measured by using scalers (frequency dividers). Frequencies as high as 110 GHz are measured using heterodyne frequency-conversion techniques. At low frequencies, for example 60 Hz, better resolution is obtained by measuring the period T = 1/f . A counter with a built-in computer is available, which measures the period at low frequencies and automatically calculates and displays the frequency. A frequency-sensitive bridge can be used to measure frequency to an accuracy of about 0.5 percent if the impedance elements are known. The Wien bridge of Fig. 15.4.21 is commonly used, R3 and R4 being identical slide-wire resistors mounted on a common shaft. The equations for balance are f = 1/2π √R3R4C3C4 and R1/R2 = R4/R3 + C3/C4. In practice, the values are selected so that R3 = R4, C3 = C4, and R1 = 2R2. Slide wire r, which has a total resistance of R1/100, is used to correct any slight tracking errors in R3 and R4. Under these conditions f = 1/2pR4C4. A filter is needed to reject harmonics if a null indicator is used since the bridge is not balanced at harmonic frequencies. Time intervals can be measured accurately and conveniently by gating a reference frequency derived from a quartz-crystal oscillator standard to a counter during the time interval to be measured. Reference frequencies of 10, 1, and 0.1 MHz, derived from a 10-MHz oscillator, are commonly used. Analog frequency circuits that produce an analog output proportional to frequency are used in control systems and to drive frequency-indicating meters. In Fig. 15.4.22, a fixed amount of charge proportional to C1(E − 2d ), where d is the diode-voltage drop, is withdrawn through diode D1 during each cycle of the input. The current

FIGURE 15.4.21 Wien frequency bridge.

FIGURE 15.4.22 Frequency-to-voltage converter.

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15.41

FIGURE 15.4.23 Real-time analyzer using 30 attenuators and filters. (General Radio Co.)

through diode D1, which is proportional to frequency, is balanced by the current through resistor R, which is proportional to eout. Therefore, eout = fRC1(E − 2d). Temperature compensation is achieved by adjusting the voltage E with temperature so that the quantity E − 2d is constant. Frequency analyzers are used for measuring the frequency components and analyzing the spectra of acoustic noise, mechanical vibrations, and complex electric signals. They permit harmonic and intermodulation distortion components to be separated and measured. A simple analyzer consists of a narrow-bandwidth filter, which can be adjusted in frequency or swept over the frequency range of interest. The output amplitude in decibels is generally plotted as a function of frequency using a logarithmic frequency scale. Desirable characteristics include wide dynamic range, low distortion, and high stop-band attenuation. Analog filters that operate at the frequency of interest exhibit a constant bandwidth, for example, 10 Hz. The signal must be averaged over a period inversely proportional to the filter bandwidth if the reading is to be within given confidence limits of the long-time average value. Real-time frequency analyzers are available which perform 1/3-octave spectrum analysis on a continuous real-time basis. The analyzer of Fig. 15.4.23 uses 30 separate filters each having a bandwidth of 1/3 octave to achieve the required speed of response. The multiplexer sequentially samples the filter output of each channel at a high rate. These samples are converted into a binary number by the A/D converter. The true rms values for each channel are computed from these numbers during an integration period adjustable from 1/8 to 32 s and stored in the memory. The rms value for each channel is computed from 1,024 samples for integration periods of 1 to 32 s. Real-time analyzers are also available for analyzing narrow-bandwidth frequency components in real time. The required rapid response time is obtained by sampling the input waveform at 3 times the highest frequency of interest using an A/D converter and storing the values of a large number of samples in a digital memory. The frequency components can be calculated in real time by a microprocessor using fast Fourier transforms. Time-compression systems can be used to preprocess the input signal so that analog filters can be used to analyze narrow-bandwidth frequency components in real time. The time-compression system of Fig. 15.4.24 uses a recirculating digital memory and a D/A converter to provide an output signal having the same waveform as the input with a repetition rate which is k times faster. This multiplies the output-frequency spectrum by a factor of k and reduces the time required to analyze the signal by the same factor. The system operates as follows. A new sample is entered into the circulating memory through gate A during one of each k shifting periods. Information from the output of the memory recirculates through gate B during the remaining k − 1 periods. Since information experiences k shifts between the addition of new samples in a memory of length k − 1, each new sample p is entered directly behind the previous sample p − 1, and therefore the correct order is preserved. (k − 1)/n seconds is required to fill an empty memory, and thereafter the oldest sample is discarded when a new sample is entered.

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MEASUREMENT SYSTEMS

FIGURE 15.4.24 Time-compression system.

Frequency synthesizers/function generators provide sine wave, square wave, triangle, ramp, or pulse voltage outputs, which are selectable over a wide frequency range and yet have the frequency stability and accuracy of a crystal oscillator reference. They are useful for providing accurate reference frequencies and for making measurements on filter networks, tuned circuits, and communications equipment. High-precision units feature up to 11-decade digital frequency selection and programmable linear or logarithmic frequency sweep. A variety of units are available, which cover frequencies from a fraction of a hertz to tens of gigahertz. Many synthesizers use the indirect synthesis method shown in Fig. 15.4.25. The desired output frequency is obtained from a voltage-controlled oscillator, which is part of a phase-locked loop. The selectable frequency divider is set to provide the desired ratio between the output frequency and the crystal reference frequency. Fractional frequency division can be obtained by selecting division ratio R alternately equal to N and N + 1 for appropriate time intervals. Time-domain reflectometry is used to identify and locate cable faults. The cable-testing equipment is connected to a line in the cable and sends an electrical pulse that is reflected back to the equipment by a fault in the cable. The original and reflected signals are displayed on an oscilloscope. The type of fault is identified by the shape of the reflected pulse, and the distance is determined by the interval between the original and reflected pulses. Accuracies of 2 percent are typical. A low-frequency voltmeter using a microprocessor has been developed that is capable of measuring the true rms voltage of approximately sinusoidal inputs at voltages from 2 mV to 10 V and frequencies from 0.1 to 120 Hz. A combination of computer algorithms is used to implement the voltage- and harmonic-analysis functions. Harmonic distortion is calculated using a fast Fourier transform algorithm. The total autoranging, settling, and measurement time is only two signal periods for frequencies below 10 Hz.

FIGURE 15.4.25 Indirect frequency synthesis.

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Source: STANDARD HANDBOOK OF ELECTRONIC ENGINEERING

CHAPTER 15.5

AC IMPEDANCE MEASUREMENT Ramon C. Lebron

The generation of Impedance Gain and Phase versus frequency plots of an electrical circuit (passive or active) is extremely important to characterize small signal behavior and evaluate stability. In space dc power distribution systems, such as the International Space Station power system, each of the power system components and dc-to-dc converters has to meet strict input and output impedance requirements over a specific frequency range to ensure end-to-end system stability. Figures 15.5.1 and 15.5.2 show the technique used to measure ac impedance. This test can be performed with the device under test (DUT) operating at rated voltage and rated load. The network analyzer output provides a sinusoidal signal with a frequency that will vary over the desired range. The signal is amplified and fed into the primary of an audio isolation transformer. Figure 15.5.1 shows the method of ac voltage injection by connecting the transformer secondary in series with the power source. The voltage and current amplifiers are ac coupled and the network analyzer is set to generate the magnitude and phase plot of Channel 2 (ac voltage) divided by Channel 1 (ac). Therefore the impedance magnitude plot is |Z| = |Vac|/|Iac| and the impedance phase plot is qZ = qvac − qiac for the required frequency values. Figure 15.5.2 shows the method of ac injection where a capacitor and a resistor are connected in series with the secondary of the transformer. The transformer and RC series combination is connected in parallel with the terminals of the DUT to inject a small ac into the DUT. The network analyzer performs the same computations for |Z| and qz at the desired frequency range. The voltage injection method is used for high-impedance measurements such as the input impedance of a dc-to-dc converter, and the current injection method is better suited for low-impedance measurements such as the output impedance of a dc-to-dc converter.

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AC IMPEDANCE MEASUREMENT 15.44

MEASUREMENT SYSTEMS

FIGURE 15.5.1 Impedance measurement with voltage injection method.

FIGURE 15.5.2 Impedance measurement with current injection method.

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Page 16.1

Source: STANDARD HANDBOOK OF ELECTRONIC ENGINEERING

SECTION 16

ANTENNAS AND WAVE PROPAGATION An antenna can be thought of as the control unit between a source and some medium that will propagate an electromagnetic wave. In the case of a wire antenna, it can be seen as a natural extension of the two-wire transmission line, and, in a similar way, a horn antenna can be considered a natural extension of the waveguide that feeds the horn. The radiation properties of antennas are covered in Chap. 16.1. They include gain and directivity, beam efficiency, and radiation impedance. Depending on the antenna application, certain parameters may be more important. For example, in the case of receiving antennas that measure noise signals from an extended source, beam efficiency is an important measure of its performance. Chapter 16.2 examines the various types of antennas, including simple wire antennas, waveguide antennas useful in aircraft and spacecraft applications, and low-profile microstrip antennas. Finally, Chap. 16.3 treats the propagation of electromagnetic waves through or along the surface of the earth, through the atmosphere, and by reflection or scattering from the ionosphere or troposphere. More details of propagation over the earth through the nonionized atmosphere and propagation via the ionosphere are covered on the accompanying CD-ROM. D.C.

In This Section: CHAPTER 16.1 PROPERTIES OF ANTENNAS AND ARRAYS ANTENNA PRINCIPLES REFERENCES

16.3 16.3 16.16

CHAPTER 16.2 TYPES OF ANTENNAS WIRE ANTENNAS WAVEGUIDE ANTENNAS HORN ANTENNAS REFLECTOR ANTENNAS LOG-PERIODIC ANTENNAS SURFACE-WAVE ANTENNAS MICROSTRIP ANTENNAS REFERENCES

16.18 16.18 16.22 16.25 16.32 16.35 16.37 16.39 16.43

CHAPTER 16.3 FUNDAMENTALS OF WAVE PROPAGATION INTRODUCTION: MECHANISMS, MEDIA, AND FREQUENCY BANDS REFERENCES ON THE CD-ROM

16.47 16.47 16.64 16.66

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ANTENNAS AND WAVE PROPAGATION

On the CD-ROM: Kirby, R. C., and K. A. Hughes, Propagation over the Earth Through the Nonionized Atmosphere, reproduced from the 4th edition of this handbook. Kirby, R. C., and K. A. Hughes, Propagation via the Ionosphere, reproduced from the 4th edition of this handbook.

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Page 16.3

Source: STANDARD HANDBOOK OF ELECTRONIC ENGINEERING

CHAPTER 16.1

PROPERTIES OF ANTENNAS AND ARRAYS William F. Croswell

ANTENNA PRINCIPLES The radiation properties of antennas can be obtained from source currents or fields distributed along a line or about an area or volume, depending on the antenna type. The magnetic field H can be determined from the vector potential as H=

1 ∇× A µ

(1)

To determine the form of A first consider an infinitesimal dipole of length L and current I aligned with the z axis and placed at the center of the coordinate system given in Fig. 16.1.1. A = z[ µ IL exp(− jkr )]/4π r

(2)

where k = 2p/l, and r is the radial distance away from origin in Fig. 16.1.1. From Eqs. (1) and (2) and Maxwell’s equations, the fields of a short current element are Hφ =

jkIL sinθ  1  1+ exp ( − jkr )  4π r jkr  

Eθ =

1 1  jkLI η sinθ  1+ − 2 2  exp ( − jkr )  4π r jkr k r  

Er =

 ILη 1  cosθ  1 + exp(− jkr ) 2π r jkr  

(3)

when η = µ/e and e = permitivity of source medium. By superposition, these results can be generalized to the vector of an arbitrary oriented volume-current density J given by A( x , y, z ) =

µ 4π

∫r′ J(x ′, y′, z ′)

exp(− jkR) dx ′ dy ′ dz ′ R

(4)

For a surface current, the volume-current integral Eq. (4) reduces to a surface integral of Js[exp (−jkR)]/R, and for a line current reduces to a line integral of I [exp(−jkR)]/R. The fields of all physical antennas can be 16.3 Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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PROPERTIES OF ANTENNAS AND ARRAYS 16.4

ANTENNAS AND WAVE PROPAGATION

FIGURE 16.1.1 Spherical coordinate system with unit vectors.

FIGURE 16.1.2 Equivalent aperture plane for far-field calculations: M = 2Es × nˆ . J = 2ˆn × Hs′, and J = n × H′s, M = E′s × nˆ .

obtained from the knowledge of J alone. However, in the synthesis of antenna fields the concept of a magnetic volume current M is useful, even though the magnetic current is physically unrealizable. In a homogeneous medium the electric field can be determined by E=

1 ∇×F e

F=

e 4π

∫ r′ M (x ′, y′, z ′)

exp (− jkR) dx ′ dy′ dz ′ R

(5)

Examples of antennas that have a dual property are the thin dipole in free space and the thin slot in an infinite ground plane. The fields of an electric source J can be determined using Eqs. (1) and (5) and Maxwell’s equations. From the far-field conditions and the relationships between the unit vectors in the rectangular and spherical coordinate systems, the far fields of an electric source J are

η HθJ =

− jnk exp ( − jkr ) ∫ v (J x′ cosθ cos φ 4π r + J y′ cosθ sin φ − J z ′ sin θ ) exp[ jk ( x ′ sin θ cos φ

(6)

+ y ′ sin θ sin φ + z ′ cosθ )] dx ′ dy ′ dz ′ jηk exp(− jkr ) ∫v′ (Jx′ sin φ 4ηr − J y′ cos φ ) exp [ jk ( x ′ sinθ cos φ

−ηHθJ = EφJ =

(7)

+ y′ sin θ sin φ + z ′ cosθ ] dx ′ dy′ dz ′ In a similar manner the radiated far fields from a magnetic current M are − jk exp(− jkr ) ∫ v′ ( M y′ cos φ 4π r − M x ′ sin φ ) exp[ jk ( x ′ sin θ cos φ

ηHφM = EθM =

+ y′ sin θ sin φ + z ′ cosθ ] dx ′ dy′ dz ′

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(8)

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PROPERTIES OF ANTENNAS AND ARRAYS PROPERTIES OF ANTENNAS AND ARRAYS

− jk exp (− jkr ) ∫v′ ( M x′ cos φ cosθ 4π r + M y′ sin φ cosθ − M z ′ sin θ ) exp [ jk ( x ′ sin θ cos φ

16.5

ηHθM = EφM =

(9)

+ y′ sin θ sin φ + z cosθ ] dx ′ dy′ dz ′ Currents and Fields in an Aperture For aperture antennas such as horns, slots, waveguides, and reflector antennas, it is sometimes more convenient or analytically simpler to calculate patterns by integrating the currents or fields over a fictitious plane parallel to the physical aperture than to integrate the source currents. Obviously, the fictitious plane can be chosen to be arbitrarily close to the aperture plane. If the integration is chosen to be an infinitesimal distance away from the aperture plane, the fields to the right of s′ in Fig. 16.1.2 can be found using either of the equivalent currents M s′ = 2Es′ × nˆ

(10a)

J s′ = 2 ˆn × H s′

(10b)

J s′ = nˆ × H s′

and M s′ = −nˆ × Es′

(10c)

The combined electric and magnetic current given in Eq. (10c) is the general Huygens’ source and is generally useful for aperture problems where the electric and magnetic fields are small outside the aperture: In limited cases, the waveguide without a ground plane, a small horn, and a large tapered aperture can be approximated this way. Far Fields of Particular Antennas From the field equations stated previously or coordinate transformations of these equations, the far-field pattern of antennas can be determined when the near-field or source currents are known. Approximate forms of these fields or currents can often be estimated, giving good pattern predictions for practical purposes. Electric Line Source Consider an electric line source (current filament) of length L centered on the z′ axis of Fig. 16.1.1 with a time harmonic-current I(z′)e jwt. The fields of this antenna are, from Eq. (6), Eθ =

jnk sinθ exp( − jkr ) 4π r

L/2

∫ −L/2

I ( z ′) exp[− jkz ′ cosθ )]dz ′ Eφ = 0

For the short dipole where kL 15 to 55

>55 to 160

>160 to 3500

2000 to 8000 4% 0.2%

2000 to 8000 5% 0.2%

4000 to 20,000 7.5% 0.2%

6000 to 20,000 16% 0.2%

15,000 to 30,000 not specified 0.2%

0.03%

0.02%

0.02%

0.02%

0.01%

An errored block is a block in which 1 or more bits are in error. An errored second is a 1-s period with one or more errored blocks. A severely errored second is a 1-s period which contains 30 percent or more errored blocks, or four contiguous blocks each of which has more than 1 percent of its bits in error, or a period of loss of signal. A background errored block is an errored block not occurring as part of a severely errored second.

*An

additional requirement based on a one-minute interval will likely be deleted as redundant in practice.

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enough (perhaps 2 s), the channel bank causes the trunks it serves to be declared “busy,” lights a red alarm light, and sounds an office alarm. It also transmits a special code that causes the other channel bank to take the trunks out of service, light a yellow alarm light, and sound an alarm. Maintenance personnel then clear the trouble, perhaps by patching in a spare T1 line, and proceed with fault location and repair. Channel banks can be checked by looping, i.e., connecting digital output and input. Repeatered line-fault location techniques were discussed earlier. In higher-speed systems, automatic line and multiplex protection switching is often provided. A typical line-protection switch monitors and removes violations of the redundancy rules of the line signal on the working line at the receiving (tail) end. When violations in excess of the threshold are detected, a spare line is bridged on at the transmitting (head) end and if a violation-free signal is received on this line, the tail-end switch to spare is completed. If the spare line also has violations, there is probably an upstream failure and no switch is performed. A multiplex-protection switch is typically based on a time-shared monitor that evaluates each of several multiplexers and demultiplexers in turn by pulse-by-pulse comparison of the actual output with correct output based on current input. Multiplex monitors also usually check the incoming high- and low-speed signals using the line-code redundancy. As the digital network has grown, there has been an increasing use of maintenance centers, to which all alarms in a geographic region are remoted, and which are responsible for dispatching and supervising maintenance personnel, directing restoration of failed facilities over other facilities or routes, and rearrangements for other purposes as well. There is also increasing provision, in network design, of alternative routes, sometimes by routing lines to form a ring, so that there are two physically separate paths between any two offices. Synchronous Digital Hierarchy and SONET. The existing plesiochronous digital network has grown piecemeal over decades, with the parameters of new systems reflecting the technology and needs at the time of their development. In the late 1980s, a worldwide effort brought forth a new hierarchy for higher rate systems to provide capabilities not possible in the existing network. In this new hierarchy, multiplexing is by interleaving of 8-b bytes, as in the primary rate multiplexes, as opposed to the bit interleaving used elsewhere in the existing network. Further, similar formats are used for multiplexing at all levels, and it is intended that new transmission systems will be at hierarchical levels. Another important feature of the new hierarchy is an overall plan for monitoring and controlling a complex network, and the inclusion of enough overhead in the formats to support it. In spite of the name, the new hierarchy allows nonsynchronous signals based on the existing hierarchy to enter, and multiplexing throughout includes enough justification capability to accommodate the small frequency deviations characteristics of reference clocks. The new hierarchy starts at 51.84 Mb/s, and all higher rates are an integral multiple of this lowest rate. Multiples up to 255 have been envisioned, and structures for several rates have been standardized within the United States. The rates of most interest are shown in Table 17.1.8. A single frame of the STS-1 signal consists of 810 bytes, as shown in Fig. 17.1.10. The bytes appear on the transmission line read from left to right, starting with the first row. The transported signal occupies 774 bytes of the frame, with the remainder of the frame dedicated to overhead. The transported signal plus the path overhead, the payload, are intended to be transported across the network without alteration as the signal is multiplexed to, and recovered from, higher levels. In order to accommodate frequency and phase variations in the network, the 783 bytes of payload can start anywhere within the 783 byte locations allocated to the payload, and continue into the next frame. The starting point is signaled by a payload pointer included in the line overhead, so the proper alignment can be recovered at the receiving end. This pointer, as well

TABLE 17.1.8

Major Rates in the Synchronous Digital Hierarchy

Line Rate Mb/s

Designation US (SONET)

Designation CCITT

51.84 155.52 622.08 2488.32

STS-1 STS-3 STS-12 STS-48

STM-1 STM-4 STM-16

Comment Used to carry one 44.736 Mb/s (DS-3) signal Used to carry one 139.254 Mb/s signal Used for fiber optic systems Used for fiber optic systems

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FIGURE 17.1.10 An STS-1 frame: (1) Section overhead (9 bytes); (2) line overhead (18 bytes); (3) path overhead (9 bytes); (4) transported signal (774 bytes). Each square represents 1 byte.

as the remainder of the line and section overhead bytes, are provided for the use of multiplex and line equipment, and will normally be changed several times as the frame passes through the network. The path overhead is placed on the signal at the path terminating equipment, where the transported signal is assembled and embedded in the frame. It is not intentionally modified as the STS-1 frame passes through subsequent multiplexes and line systems, but can be read and used at intermediate points. This overhead is, from the point of view of the hierarchy, end-to-end information. It contains signals identifying the structure of the frame to aid in retrieving the embedded signal, status of maintenance indications, such as loss of signal for the opposite direction of transmission, a parity check on the previous frame, as well as provision for a message channel for use by the path terminating equipment. Line overhead information may be inserted or modified when the STS-1 signal is multiplexed to a higher rate, or transferred between higher rate signals. Normally the capability to switch the higher rate signal to a standby facility in case of failure will be provided at such points, so the line overhead includes signaling for coordinating the operation of this protection switching, as well as functionality similar to the path overhead, but for use over the shorter “line.” The section overhead includes the framing alignment pattern by which the frame is located, and functionality similar to that of the path overhead, but for use and modification within individual sections, which end at regenerators or multiplexes.

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TABLE 17.1.9

Representative North American Digital Systems for Paired Cable

Line rate, Mb/s

64-kb/s voice channel capacity

1.544

24

T1 T10S (T1-outstate)

Bipolar with 1-in-8 1s density, 15 0s maximum

3.152

48

T1C, T1D, T148

Bipolar, 4B3T; duobinary; modified duobinary

6.443

96

T1G

Widely used designation

Line formats

Quaternary

Usual medium Wire pairs in single cable (but two directions in different units) As for T1, but also with shielded (screened) units As for T1C

Typical repeater spacing, mi

Typical section loss, dB

1 (on 22 gauge)

32

1 (on 22 gauge)

48

48

Frames for higher rate signals are generally similar. An STM-N frame has nine rows, and N × 270 columns of which N × 3 are for section overhead. The rather complex structure is based on virtual containers, tributary units, and administrative units, which are combinations of user signal with the overheads defined above appropriate to the administration of various types of paths. Line Systems for Transmission Systems on Wire Cable. Systems providing trunks on wire pair are generally designed to operate on the same cable types used for voice trunks, and to share such cables with voice trunks. Large numbers of such systems that have characteristics indicated in Table 17.1.9 are in service in North America and Japan, although the fiber systems are increasingly being used in new installations. Wire pair systems at 2.048 Mb/s are common in Europe. All the above are four-wire systems, using one pair for each direction of transmission. Two-wire systems providing 144 kb/s in both directions on a single pair have been specified and developed for use as ISDN loops, but little deployed as yet. These two-wire systems use echo cancelers, or time compression multiplexing in which the pair is used alternately in each direction (at about twice the average bit rate) with buffering at the ends. Systems on Fiber Optic Cable. Fiber-optic systems, operating digitally, and using one fiber for each direction of transmission have developed extremely rapidly since their introduction in 1977, with steadily increasing capacity and, correspondingly, decreased per-channel cost. Systems for trunks and loops have been installed at many of the hierarchical rates (Table 17.1.1), but systems at even higher rates are most prevalent. The characteristics of such systems are summarized in Table 17.1.10, and some specific systems are shown on in Table 17.1.11. A branching unit, including 296 Mb/s regenerative repeaters, used in TAT-8 (Trans ATlantic cable 8) is shown in Fig. 17.1.11. Similar branching units in TAT-9 operate at 591 Mb/s, and include some multiplexing functions as well. All terrestrial and submarine systems have customarily used intermediate regenerators when the system length requires gain between the terminals. Systems using optical amplifiers instead of regenerators have recently appeared, and the characteristics of one of these is also included in Table 17.1.10. In such systems, erbium doped optical amplifiers are used at intermediate points to overcome loss of the dispersion-shifted fiber with regeneration only at the ends. Figure 7.1.12 shows an amplifier designed for the system shown in the table. Typical output power of such amplifiers is +1 to +3 dBm. Even these systems do not come close to exploiting the theoretical capacity of the fibers, and further developments are to be expected. Wavelength-division multiplexing, in which two or more transmitter-receiver pairs operate over a single fiber but at different wavelengths, is one way of tapping this capacity, and has seen limited use. The use of solitrons is being explored, and the record as of early 1993 for simulated long-distance transmission in the laboratory, 20 Gb/s over 13,000 km, used this technology. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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TABLE 17.1.10

Fiber type

850 1300 1300 1550

Graded index Graded index Single mode Single mode

TABLE 17.1.11

Name TAT-10 FT-2000

TAT-12

Parameters of Fiber-Optic Systems

Wavelength, nm

*Lower

17.29

Bit rate, Mb/s

Maximum regenerator spacing, km*

2–140 2–140 140–1700 1.5–2500

15–20 45–60 25–60 50–150

spacings generally correspond to higher bit rates.

Some Fiber-Optic Systems

Primary application

Bit rate per fiber

Wavelength, nm

Repeater spacing, km

Long undersea routes Short and long terrestrial routes Long undersea routes

591.2 Mb/s

1550

110

2488.32 Mb/s

1310 or 1550

60 at 1310 nm 84 at 1550 nm

5 Gb/s

1550

33–45

Comment

A variety of terminals is available Uses optical amplifiers

FIGURE 17.1.11 TAT-8 (transatlantic telephone cable no. 8) branching repeater with cable-laying ship in background. (From AT&T. Used with permission)

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FIGURE 17.1.12 Amplifier pair for TAT-12 (AT&T section).

Terrestrial Radio. Frequencies allocated to telecommunications in the United States are shown in Table 17.1.2. Typical systems for analog signals modulate a carrier using low index FM with a signal consisting of one or more multiplexed mastergroups, and occupy a bandwidth of two or more times 4 kHz for each voice channel. Systems with very linear amplifiers have also used single-sideband AM, with a resulting bandwidth of closet to 4 kHz per voice channel. While analog microwave radio once carried the bulk of long-haul telecommunications in the United States and many other countries, it has been mostly displaced in long-haul applications by optical fiber, particularly in the United States, and in short-haul applications by digital radio, owing to the need to interconnect with digital switches and other digital transmission systems. A block diagram of a digital radio regenerator is shown in Fig. 17.1.8. The regenerator operates at i.f., and a complete station involves frequency conversion to and from rf, as well as receiving and transmitting antennas. An end station uses the transmitting and receiving portions of the regenerator separately to create and demodulate the transmitted and received signals. Communications Satellite Systems. While the first experimental communications satellites were in low earth orbit, commercial satellites have almost uniformly been in a geostationary orbit, 22,300 miles above the equator. (The exceptions were in polar orbits, for better visibility from the northern polar regions.) In such an orbit, the satellite appears stationary from the earth, so a permanent communication link can be established using a single satellite, and earth stations with very directive stationary (or almost stationary) antennas. The disadvantages of this orbit are the high loss and delay resulting from the long distance the signal must travel. Table 17.1.12 lists representative applications of communication satellites, including current proposals for new low earth orbit systems. Communications satellites receive signals from an earth station, and include transponders, which amplify and translate the signal in frequency and retransmit it to the receiving earth station, thus making effective use of the line-of-sight microwave bands without requiring erection of relay towers. The transponders are powered from solar cells, with batteries for periods of eclipse. Spin-stabilized satellites are roughly cylindrical and spin at about 60 r/min, except for a “despun” portion, including the antennas, that is pointed at the earth. Three-axis-stabilized satellites have internal high-speed rotating wheels for stability, and solar cells on appendages which unfold after they are in orbit. Adjustments in the position and orientation of a satellite in orbit are accomplished under control of the telemetry tracking and control (TTC) station on the earth, and the exhaustion of fuel for this purpose is the normal cause of end of life of the satellite, typically 10 to 12 years. (At end of life, the TTC moves the satellites to an unused portion of the orbit, where it remains, an archeological resource for future generations.) High reliability is necessary, and on-board spares for the electronics, switchable from the TTC, at a ratio of 50 to 100 percent, are typically provided. Table 17.1.13 gives the characteristics of two current satellites. Most civilian communication satellites have used the common-carrier bands of 5925 to 6425 MHz in the uplinks, and the 3700 to 4200-MHz band in the downlinks. Now, direct broadcast satellites (DBS) use the 11and 14-GHz bands for down- and uplinks, respectively. Since these bands are not so widely used in terrestrial

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TABLE 17.1.12

17.31

Representative Applications of Communication Satellites

Application

Type of Service

Technical Characteristics

Status

Intercontinental telephone trunking

Point-to-point, 2-way

Earth station antennas to 30 m. FDMA, TDMA, and FM with a single channel per transponder used

The Intelsat system. Widely used where fiber optic cables are not available, also for handling peak loads on cables, and during repair of failed cables

Intercontinental TV transmission

Point-to-point, 1-way

Analog TV signals using FM with a single channel per transponder

Carried along with voice on the Intelsat satellites. Primary way of providing this service

National telephone trunks

Point-to-point, 2-way

Wide variety of antenna sizes, access methods have been used

No longer used in the United States, primarily because voice users don’t like delay. Still used in countries with difficult terrain, long distances between population centers, or sparse networks

Distribution of TV signals to local broadcast stations or CATV distribution centers

Point-to-multipoint, 1-way

Smaller receiving antennas. Analog TV signals using FM with a single channel per transponder

Major provider of this service. Economics generally favorable compared to cable and microwave radio

Business and educational TV distribution, typically directly to viewing site

Point-to-multipoint, 1-way

Originally analog TV using FM, but increasingly digital, using coders, which, by removing redundancy encode the signal into 6 Mb/s or less, allowing multiple channels per transponder

Major provider of this comparatively new service

Data links, international and domestic

Point-to-point, 2-way

Low rate data channels can be multiplexed to a high rate to fill a transponder, or FDMA or TDMA can be used

Has seen considerable use, as with proper protocols, delay is not a problem in most applications. Fiber optic cables are eroding market

Maritime Mobile telephone

Fixed-point to mobile, 2-way

Operates at 1.5 GHz, with geosynchronous satellite

Via the INMARSAT system, the major modality for ship-to-shore telephony

Paging, short message

Fixed-point to mobile, 1-way

Would operate at 150 MHz with a total bandwidth of 1 MHz,using low-earthorbit satellite

Proposal. Intent is to provide paging and limited message capability to personal receivers

Terrestrial mobile

Fixed-point to mobile, 2-way

Would operate at about 1.5 GHz, with a total bandwidth of about 20 MHz. Would use from 12 to 30 satellites in low earth orbit, using circular polarization and low directivity antennas on the mobile stations

Proposal. Intent is to provide mobile service roughly comparable to cellular, but available without the necessity for local terrestrial construction and network access

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TABLE 17.1.13

Representative Communications Satellites

microwave relay, interference problems are less although rain attenuation is much higher. All frequencies are subject to sun-transit outage when the satellite is directly between the sun and the receiving earth station, so that the receiving antenna is pointing directly at the noisy sun. This occurs for periods of up to 1/2 h/d for several days around the equinoxes. The effect can be avoided by switching to another distant satellite during the suntransit period. The propagation delay between earth stations is about 0.25 s in each direction for geostationary

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17.33

FIGURE 17.1.13 Satellite transponder.

satellites. This delay is of no consequence for one-way television transmission, but is disturbing to telephone users. Some satellites use each frequency band twice, once in each polarization. Earth antenna directivity permits reuse of the same frequencies by different satellites as long as satellites are not too close in orbit (2° is the limit for domestic U.S. satellites in the 4- to 6-GHz band). Further frequency reuse is possible in a single satellite by using more directive satellite antennas which direct separate beams to different earth areas. Although Intelsat has made use of spot beams, most present satellite antennas have beam widths covering upward of 1000 mi on earth. A simplified transponder block diagram is given in Fig. 17.1.13. Transponder utilization and multiple access. A transponder can be used for a single signal (single carrier operation) which may be either frequency- or time-division-multiplexed. Such signals have included a single TV signal, two or three 600-channel analog master groups multiplexed together and used to frequency modulate a carrier, thirteen 600-channel master groups using compounders and single-sideband amplitude modulation, and a digital signal with rates up to 14.0 Mb/s used to modulate a carrier using quaternary phaseshift keying (QPSK), or coded octal phase-shift keying. Single-carrier operation can be either point-to-point (as for normal telecommunication) or broadcast (as for distributing TV programs). Transponders can also be used in either of two multiple-access modes in which the same transponder carries (simultaneously) signals from several different earth stations. In frequency-division multiplex access (FDMA) the frequency band of each transponder is subdivided and portions assigned to different earth stations. Each station can then transmit continuously in its assigned frequency band without interfering with the other signals. All earth stations receive all signals but demodulate only signals directed to that station. In the limit of subdivision, one voice channel can be placed on a single carrier (single channel per carrier or SCPC). As the high-power amplifiers (HPA) in the earth station and the satellite are highly nonlinear, power levels must be reduced considerably (“backed off”) below the saturation level to reduce intermodulation distortion between the several carriers. It is also possible to use demand assignment in which a given frequency slot can be reassigned among several earth stations as traffic demands change. In TDMA (time-division multiple access) each earth station uses the entire bandwidth of a transponder for a portion of the time, as illustrated in Fig. 17.1.14. This arrangement implies digital transmission (such as QPSK) with buffer memories at the earth stations to form the bursts. A synchronization arrangement that controls the time of transmission of each station is also required. As at any given time only a single carrier is involved, less backoff is required than with FDMA, allowing an improved signal-to-noise ratio. Demand assignment can be realized by reassigning burst times among the stations in the network. Satellite-switched TDMA (SSTDMA) in which a switch in the satellite routes bursts among spot beams covering different terrestrial areas is a feature of Intelsat VI. Transmission considerations. The free-space loss between a geostationary satellite and the earth is about 200 dB. To overcome this large loss, earth stations for telecommunications trunks have traditionally used large parabolic antennas (10 to 30 m in diameter), high output power (up to several kilowatts), and low-noise receiving amplifiers (cryogenically cooled in some cases). Transponder output power is limited to the power available from the solar cells, and therefore, downlink thermal noise often accounts for most of the system noise with intermodulation in the transponder power amplifier a significant limiting factor. Consequently, the capacity of

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FIGURE 17.1.14 Satellite time-division multiplex access (TDMA). From Digital Communications Corporation; used by permission.

a satellite channel is often limited by the received signal-to-noise ratio (power-limited) rather than by the bandwidth of the channel. For applications other than high-capacity trunking, the cost of large antennas at the earth stations is often prohibitive, so lower capacity is accepted, and received power may be increased by dedicating more power to the transponder or by use of spot beams, as the economics of the application dictate. Smaller antennas are less directive, possibly causing interference to adjacent satellites, unless the station is receive-only. Therefore VSATs (very small aperture terminals), which may have antennas as small as 1 m, typically operate in the higher frequency bands where directivity of smaller antennas may be adequate. Some applications, including the proposals included in Table 17.1.12, use much lower frequencies, and accept, or even exploit, the lesser directivity.

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Source: STANDARD HANDBOOK OF ELECTRONIC ENGINEERING

CHAPTER 17.2

SWITCHING SYSTEMS Amos E. Joel, Jr.

A telecommunication service that includes directing a message from any input to one or more selected outputs requires a switching system. The terminals are connected to the switching system by loops, which together with the terminals are known as lines. The switching systems at nodes of a network are connected to each other by channels called trunks. This section deals primarily with systems that provide circuit switching, i.e., provision of a channel that is assigned for the duration of a call. Other forms of switching are noted later. Switching systems find application throughout a communication network. They range from small and simple manual key telephone systems or PBXs to the largest automatic local and toll switching systems.

SWITCHING FUNCTIONS Introduction A switching system performs certain basic functions plus others that depend on the type of services being rendered. Generally switching systems are designed to act on each message or call, although there are some switches that perform less often, e.g., to switch spare or alternate facilities. Each function is described briefly here and in greater detail in specific paragraphs devoted to each function. A basic function of a circuit telecommunication switching system is connected by the switching fabric,* the transfer of communication from a source to a selected destination. Vital to this basic function are the additional functions of signaling and control (call processing) (Fig. 17.2.1). Other functions are required to operate, administer, and maintain the system.

Signaling Automatic switching is remote-controlled switching. Transfer of control information from the user to the switching office and between offices requires electrical technology and a format. This is known as signaling, and it is usually a special form of data communication. Voice recognition is also used.

*The term switching fabric will be used in these paragraphs to identify the implementation of the connection function within a switching system. The term communications or switched network will refer to the collection of switching systems and transmission systems that constitute a communications system.

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FIGURE 17.2.1 Basic switching functions in circuit switching.

Originally, signaling was developed to accommodate the type of switching technology used for local switching. Most of these systems used dc electric signals. Later, with the advent of longer distances, signaling using single- and multiple-frequency tones in the voice band was developed. Most recently, signaling between offices using digital signals has been introduced over dedicated networks, distinct from the talking channels. As dialing between more distant countries became feasible, specific international signaling standards were set. These standards were necessarily different from national signaling standards since it was necessary to provide for differences in calling devices (dials) and call handling such as requests for language assistance or restrictions in routing.

Control Control of switching systems and their application is called system control, the overall technique by which a system receives and interprets signals to take the required actions and to direct the switching fabric to carry them out. In the past, the control of switching systems was accomplished by logic circuits. Virtually all systems now employ stored-program control (SPC). By changing and adding to a program one can modify the behavior of a switching system faster and more efficiently than with wired logic control. Switching Fabrics The switching fabric provides the function of connecting channels within a circuit-switching system. Storeand-forward or packet-switching systems do not need complex switching fabrics but do require connecting networks such as a bus structure. Switching systems have generally derived their names or titles from the type of switching technology used in the switching fabric, e.g., step-by-step, panel, and crossbar. These devices constitute the principal connective elements of switching fabrics. Two-state devices that change in electrical impedance are known as crosspoints. Typically electromechanical crosspoints are metallic and go from almost infinite to zero impedance; electronic crosspoints change impedance by several orders of magnitude. The off-to-on impedance ratio must be great enough to keep intelligible signals from passing into other paths in the network (crosstalk). A plurality of crosspoints accessible to or from a common path or link is known as a switch or, for a rectangular array, a switch matrix. A crosspoint may contain more than one gate or contact. The number depends on the information switched and the technology. Generally a number of stages of switches are used to provide a network in order to conserve the total number of crosspoints required. For connecting 100 inputs to 100 outputs, a single switch matrix requires 100 × 100 = 10,000 crosspoints. A two-stage fabric requires only 2000 crosspoints when formed with twenty 10 × 10 matrices. In a two-stage fabric, an output of each first-stage switch is connected to an input of a second-stage switch via a link. There is a connectable path for each and every input to each and every output. Since each input has access to every output, the network is characterized as having full access. However, two paths may not simultaneously exist between two inputs on the same first-stage switch and two outputs of a single-output-stage switch. (There is only one link between any first- and second-stage switch.) A second call cannot be placed, and this network is said to be a blocking network. By making the switches larger and adding links to provide parallel paths, the chance of incurring a blocking condition is reduced or eliminated. A three-stage Clos nonblocking fabric can be designed requiring only 5700 crosspoints. Even fewer crosspoints are needed if existing internal paths can be rearranged to accommodate a new connection that would otherwise encounter blocking. The design of most practical switching fabrics includes a modest degree of blocking in order to provide an economical design. Large central-office switching networks may have more than 100,000 lines and trunks to be interconnected and provide tens of thousands of simultaneous connections. Such networks typically require six to eight stages of switches and are built to carry loads, which result in less than 2 percent of call attempts in the peak traffic period being blocked. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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SWITCHING SYSTEMS SWITCHING SYSTEMS

17.37

Network Control While the switching system as a whole requires a control, the control required for a switching fabric may be separated in part or in its entirety from the system control function. The most general network control accepts the address of the input(s) and output(s) for which an interconnection is required and performs all the logic and decision functions associated with the process of establishing (and later releasing) connections. The control for some networks may be common to many switches or individual to each switch. Self-routing is also used in fabrics where terminal addresses are transmitted through and acted on by the switches. Some form of memory is involved with all networks. It may be intimately associated with the crosspoint device employed, e.g., to hold it operated, or it may be separated in a bulk memory. The memory keeps a record of the device in use and of the associated switch path. (In some electronic switching systems it may also designate a path reserved for future use.) Operation, Administration, and Maintenance (OAM) When switching systems are to be used by the public, a high-quality continuous service day in and day out over every 24-h period is required. A system providing such reliable service requires additional functions and features. Examples are continuity of service in the presence of device or component failure and capability for growth while the system is in service. Separate maintenance and administrative functions are introduced into systems to monitor, test, and record and to provide human control of the service-affecting conditions of the system. These functions together with a human input/output (I/O) interface constitute the basic maintenance functions needed to detect, locate, and repair system and component faults. In addition to specific maintenance functions, redundancy in the switching system is usually necessary to provide the desired quality of service. Complete duplication of an active system with a standby system will protect against one or more failures in one system but presents severe recovery problems in the event of a simultaneous failure of both systems. Judicious subdivision of the system into parts that can be reconfigured (e.g., either of a pair of central processors may work with either of a pair of program memories) can greatly increase the ability of the system to continue operation in the presence of multiple faults. Where there are many switching entities in a telecommunications network and as systems have become more reliable and training more expensive, the centralization of maintenance has become a more efficient technique. It ensures better and more continuous use of training and can also provide access to more extensive automated data bases that benefit from more numerous experiences. For public operation, a basic subset of administration and operation features has become accepted as required features. These include the collecting of traffic data, service-evaluation data, and data for call billing.

SWITCHING FABRICS Three different aspects will be considered in the design of switching fabrics: (1) the types of switching fabrics, (2) the technology of the devices, and (3) the topology of their interconnection. Types of Switching Fabrics The three types of switching fabrics are known by the manner in which the message passes through the network. In space-division fabrics analog or digital signals representing messages pass through a succession of operated crosspoints that are assigned to the call for all or most of its duration. In virtual circuit-switching systems previously assigned crosspoints are reoperated and released during successive message segments. In time-division fabrics analog or digital signals representing periodically sampled message segments from a plurality of time multiplexed inputs are switched to the same number of outputs. Using equal length segments assigned in time to time slots identifies them for address purposes in the system control. There are two kinds of time-division switching elements, referred to as space switches and time switches (or time-slot interchanges, TSI). The space switch (also known as a time-multiplexed switch, TMS), shown in Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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FIGURE 17.2.2 Time-multiplex switch (TMS): space switch.

Fig. 17.2.2, operates like the normal space-switch matrix but with each new time slot the electronic gates are reconfigured to provide a new set of input and output connections. The two-dimensional space switch now has an added third dimension of time. The time-slot interchange uses a buffer memory, into which one frame of input information is stored. Under direction of the contents of the control memory, transfer logic recorders the sequence of information stored in the buffer, as shown in Fig. 17.2.3. To ensure the timely progression of signals through the TSI, two memories are used, one being loaded while the other is being read. The TSI necessarily creates delays in handling the information stream. Also with storage of message (voice) samples in T-stages, delay of at least one frame (e.g., 125 ms) is introduced into transmission by each switch through which the message passes. Channels arriving at the switch in time-multiplexed form can be further multiplexed (and demultiplexed) into frames of greater (or lesser) capacity, i.e., at a higher rate and with more time slots. This function is generally used before using TSI so that channels from different input multiplexes can be interchanged. Time-division switch fabrics are designated by the sequence of time and space stages through which the samples pass, e.g., TSST. The most popular general form of fabric is TST. The choice of others, e.g., STS, is dependent on the size of the fabric and growth patterns. Analog samples can be switched in both directions through bilateral gates. An efficient and accurate transfer of the pulse is effected by a technique known as resonant transfer. For most analog and all digital timedivision networks, however, the two directions of signals to be switched are separated. Therefore two reciprocal connections or what is known as four-wire connections (the equivalent of two wires in each direction) must be established in the network. When connections transmit in only one direction, amplification and other forms of signal processing can more readily be switched into the network.

FIGURE 17.2.3 Time-slot interchange (TSI): time switch.

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If multiplexing is performed in such a way that samples from an incoming circuit can be assigned arbitrarily to any of a number of time slots on an outgoing circuit, time-slot interchange and multiplexing are effectively achieved in a single operation. With the application of digital facilities throughout telecommunications and in particular with the digitalization of speech, digital time-division fabrics are currently the most popular form of switching found in public networks. Digital voice communication exists throughout the public network. The ISDN (see Chap. 17.4) becomes a reality with digital access line interfaces in the local central offices, completing the end-to-end digital capability. As a result, switched 64,000 b/s clear digital channels are now available not only for voice but also for data. The number of time slots provided for in a time-division fabric depends on the speed employed. Typically in a voice-band fabric there may be from 32 to 1024 time slots. The coded information in digitized samples may be sent serially (typically 8 b per sample for voice signals), in parallel, or combinations. Extra bits are sometimes added as they pass through the switch for checking parity, for other signals, or to allow for timing adjustments. For digital transmission, the crosspoints used in S stages of a switching fabric need not be linear. Figure 17.2.4 shows the block diagram of the switching fabric for a no. 4 ESS, a large digital time-division switching system presently being deployed mainly in North America. Incoming digital T carrier streams (five T1 lines with 24 channels each) are further multiplexed to frames of 120 (DS120). The information is buffered in registers to permit synchronization of all inputs. The TSIs on the right side of the figure reverse the order of selecting and buffering; selected input sequences driven by a control memory (not shown) and sequentially gated out of the buffer attain the desired interchange in time. Note that the fabric shown is unilateral (left to right); the complete fabric includes a second unilateral fabric to carry the right-to-left portion of the conversation. This fabric has a maximum of 107,000 input channels, which can accommodate over 47,000 simultaneous conversations with essentially no blocking. When digital time division fabrics are designed to work with digital carrier (T carrier in the United States) systems either in the loop as pair gain systems, line concentrators, or as interoffice trunks, carrier multiplexed bit streams can be synchronized and applied directly to the switch fabrics requiring no demultiplexing. This represents a cost advantage synergy between switching and transmission. Frequency Division. Since frequency-multiplex carrier has been used successfully for transmission, its use for switching has been proposed. Connections are established by assigning the same carrier frequency to the two terminals to be connected. Generally to achieve this requires a tunable modulator and a tunable demodulator to be associated with each terminal, and therefore frequency-division switching has had little practical application. Wave Division switching is a version of frequency division used in optical or photonic transmission and switching. Other forms of photonic switching use true space division to switch optical paths en masse in free space (see Hinton and Miller, 1992).

Switching Fabric Technology Broadly speaking, basically three types of technology have been used to implement switching networks. (1) From the distant past comes the manually operated switch, where wires, generally with plug ends, can be moved within the reach of the operator. (2) Electromechanical switches can be remotely controlled. They may be electromagnetically operated or power-driven. Another classification is by the contact movement distance, gross motion and fine motion. Gross-motion switches inherently have limitations in their operating speeds and tend to provide noisy transmission paths. Consequently, they have seen little recent development. (3) The electronic switch is prevalent in modern design. Electronic Crosspoints. Gross- and fine-motion switches can be used only in space-division systems. Electronic crosspoints achieve much higher operating speeds. Although they can be used in space-, time-, and frequency-division systems, they have the disadvantage of not having as high an open-to-closed impedance ratio as metallic contacts. Steps must therefore be taken to ensure that excessive transmission loss or crosstalk is not introduced into connections. The crosspoint devices are either externally triggered or are self-latching diodes of the four-layer pnpn type. The external trigger may be an electric or optical pulse. The devices have a negative resistance characteristic

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FIGURE 17.2.4 Block diagram of no. 4 ESS digital time-division fabric.

SWITCHING SYSTEMS

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and are operated in a linear region if they are to pass analog voice or wideband signals. For fixed-amplitude pulse transmission, as in PCM, the devices need not be operated over a linear region. Electronic crosspoints are generally designed to pass low-level signals at high speed. Recently a new class of high-energy integrated-circuit crosspoints has been developed, which can pass signals used in telephone circuit switching such as ringing and coin control. Switching Fabric Topology Of all the switching functions, the topology and traffic aspects of fabrics have been most amenable to normal analytical treatment, although many less precise engineering and technology considerations are also involved. The simplest fabric is one provided by a single-stage rectangular switch (or, equivalently, a TSI) so that any idle input can reach any idle output. If some of the contacts are omitted, grading has been introduced and not every input can reach every output. With the advent of electronic crosspoints and time division, grading has become less important and will not be pursued further here. When inputs to a rectangular switch exceed the outputs, concentration is achieved; the converse is expansion. A switching fabric is usually arranged in stages. Input lines connect to a concentration stage, several stages of distribution follow, and a last expansion stage connects to trunks or other lines. Within the design of a switching system, provision is usually made for installation of switches in only the quantity required by the traffic and number of inputs and outputs of each particular application. To achieve this, the size of each stage and sometimes the number of stages is made adjustable. Consideration of control, wiring expense, transition methods (for rearranging the system during growth without stopping service), and technology leads to the configurations selected for each system. In order to achieve acceptable blocking in networks that are smaller than their maximum designed size, more parallel paths are provided from one stage to the next. In this case, because the distribution need is also reduced, the connections between stages are rewired so that those switch inputs and outputs which are required for distribution in a large network are used for additional parallel paths instead. It is convenient to divide the fabric into groups of stages or subfabrics according to the direction of the connection. (Calls are considered as flowing from an originating circuit, associated with the request for a connection, to a terminating circuit.) Local interoffice telephone trunks, for example, are usually designed to carry traffic in only one direction. The trunk circuit appearances at a tandem office are then either originating (incoming) or terminating (outgoing). Figure 17.2.5a illustrates such an arrangement where the whole network is unidirectional. Telephone lines are usually bidirectional: they can originate or terminate calls. For control or other design purposes, however, they can be served by unidirectional stages, as shown in Fig. 17.2.5b. Concentration and expansion are normally used with line switching to increase the internal network occupancy above that of lines. In smaller systems a bidirectional network can serve all terminal needs: lines, trunks, service circuits, and so forth (Fig. 17.2.5c). When interconnection between trunks, as in a combined local-tandem office, is required, line stages can be kept bidirectional while trunk stages are unidirectional (Fig. 17.2.5d ). When the majority of trunks are bidirectional, as may occur in a toll office, a bidirectional switching fabric is used (Fig. 17.2.5e). Many other configurations are possible.

SYSTEM CONTROLS Stored Program Control As discussed earlier, most modern systems use some form of general-purpose stored-program control (SPC). Full SPC implies a flexibility of features, within the capability of existing hardware, by changes in the program. SPC system controls generally include two memory sets, one for the program and other semipermanent memory requirements and one for information that changes on a real-time basis, such as progress of telephone calls, or the busy-idle status of lines, trunks, or paths in the switching network. These latter writable memories are call stores or scratch-pad memories. The two memories may be in the same storage medium, in which case there is a need for a nonvolatile backup store such as disc or tape. Sometimes the less frequently used programs are also retrieved from this type of bulk storage when needed.

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FIGURE 17.2.5 Switching fabrics: (a) unidirectional network (tandem); (b) unidirectional network (local); (c) bidirectional network (local); (d) combined network (local-toll); (e) bidirectional network; line stages: C = concentration, E = expansion, D = distribution; trunk stages: O = outgoing, I = incoming. Arrows indicate direction of progress of setup of call.

Nonprogram semipermanent memory is required for such data as parameters and translations. A switching system is generally designed to cover a range of applications; memory, fabric, and other equipment modules are provided in quantities needed for each particular switching office. Parameters define for the program the actual number of these modules in a particular installation. The translation data base provides relations between signal addresses and physical addresses as well as other service and feature class identification information. Central Control Single Active. The simplest system control in concept is the common or centralized control. Before the advent of electronics, the control of a large telephone switching system generally required up to 10 or more central controls. The application of electronics has made it possible for a system to be fully serviced by a single control. This has the advantage of greatly simplifying the access circuits between the control and the remainder of a switching system. It also presents a single point in the system for introducing additional service capabilities. It has the disadvantage that a complete control must be provided regardless of system size, and complete redundancy is often required so that the system can continue to operate in the presence of a single trouble or while changes are being made in the control.

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Redundancy is usually provided by a duplicate central control that is idle and available as a standby to replace the active unit (the unit actually in control) if it has a hardware failure. The duplicate may carry out each program step in synchronism with the active unit; matching circuits observe both units and almost instantaneously detect the occurrence of a fault in either unit. Otherwise central-control faults can be detected by additional redundant self-checking logic built into each central control unit or by software checks. In these latter modes of operation the central controls may be designed to operate independently and share the workload. Load sharing allows the two (or more) central controls to handle more calls per unit time than would be possible with a single unit. However, in the event of a failure of one unit, the remaining unit(s) must carry on with reduced system capacity. Load-sharing represents independent multiprocessing where two or more processors may have full capability of handling calls and do not depend on each other. At least part of the call store memory (containing, for example, the busy-idle indications of lines) must be accessible, either directly or through another processor, to more than one processor in order to avoid conflicting actions among processors. A small office would require less than the maximum number of processors, so that the control cost is lower for that office; as the office grows, more processors can be added. Increasing the number of processors results in decreasing added capacity per processor. Conflicts on processor access to memory and other equipment modules, with accompanying delays, accelerate with the number of processors. Independent multiprocessing or load sharing rapidly reaches its practical limit. Functional Multiprocessing. Another way to allocate central-control workload is to assign different functions to different processors. Each carries out its task; together they are responsible for total capability of the switching system. This functional or dependent multiprocessing arrangement can also evolve from a single central control. A small office can start with the entire program in one processor. When one or more functional processing units are added, the software is modified and apportioned on a functional basis. As in load sharing, the mutually dependent processors must communicate with each other directly or through common memory stores. In handling calls, each processor may process a portion and hand the next step to a succeeding processor, as in a factory assembly line. This sequential multiprocessing has been used in wired-logic switching systems. Virtually all SPC-dependent multiprocessing arrangements are hierarchical. A master processor assigns the more routine tasks to subsidiary processors and maintains control of system. The one or more subsidiary processors may be centralized or distributed. If the subsidiary processors are centralized, they have full access to network and other peripheral equipment. Distributed controls are dedicated to segments of the switching network and associated signaling circuits. As network and associated signaling equipment modules are added, the control capability is correspondingly enlarged. Most newer switching systems use distributed controls.

TYPES OF SWITCHING SYSTEMS In the preceding paragraphs the various switching functions were described. A variety of switching systems can be assembled using these functions. The choice of system type depends on the environment and the quantity of the services the system is required to provide. Combining the various types of systems within one embodiment is also possible. Circuit Switching Circuit switching is generally used where visual, data, or voice messages must be delivered with imperceptible delay (2d 2/l, where d is the largest dimension of either antenna. Thus, Friis equation applies only when the two antennas are in the far-field of each other. It also shows that the received power falls off as the square or the separation distance r. The power decay as 1/r 2 in wireless systems as exhibited in Eq. (1) is better than the exponential decay in power in a wired link. In actual practice, the value of the received power given in Eq. (1) should be taken as the maximum possible because some factors can serve to reduce the received power in a real wireless system. From Eq. (1), we notice that the received power depends on the product PtGt. The product is defined as the effective isotropic radiated power (EIRP), i.e. EIRP = PtGt

(2)

The EIRP represents the maximum radiated power available from a transmitter in the direction of maximum antenna gain relative to an isotropic antenna. Empirical Path Loss Formula In addition to the theoretical model presented in the preceding section, there are empirical models for finding path loss. Of the several models in the literature, Okumura et al.’s model is the most popular choice for analyzing mobile-radio propagation because of its simplicity and accuracy. The model is based on extensive measurements in and around Tokyo between 200 MHz and 2 GHz, compiled into charts, which can be applied to VHF and UHF mobile-radio propagation. The medium path loss is given by  A + B log10 (r ), for urban area  L p =  A + B log10 (r ) − C , for suburban area   A + B log10 (r ) − D, for open areea

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(3)

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FIGURE 17.5.2 Radio propagation over a flat surface.

where r (in kilometers) is the distance between the base and mobile stations, as illustrated in Fig. 17.5.2. The values of A, B, C, and D are given in terms of the carrier frequency f, the base station antenna height hb (in meters), and the mobile station antenna height hm (in meters) as A = 69.55 + 26.16 log10( f ) − 13.82 log10(hb) − a(hm) B = 44.9 − 6.55 log10(hb)

(4a) (4b)

2

  f  C = 5.4 + 2  log10     28    D = 40.94 − 19.33 log10 ( f ) + 4.78[log10( f )]2

(4c) (4d)

where 0.8 − 1.56 log10 ( f ) + [1.1 log10 ( f ) − 0.7]hm , for medium/small city  a(hm ) =  8.28[log10 (1.54 hm )]2 − 1.1, for f ≥ 200 MHz  2 3.2[log10 (11.75hm )] − 4.97, for f < 400 MHz  for large city

(5)

The following conditions must be satisfied before Eq. (3) is used: 150 < f < 1500 MHz; 1 < r < 80 km, 30 < hb < 400 m; 1 < hm < 10 m. Okumura’s model has been found to be fairly good in urban and suburban areas, but not as good in rural areas.

CORDLESS TELEPHONY Cordless telephones first became widespread in the mid-1980s as products became available at an affordable price. The earliest cordless telephone used narrow band technology and used separate channels for frequency channel for transmission to/from the base station. They had limited range, poor sound quality, and poor security—people could easily intercept signals from another cordless phone because of the limited number of channels. The Federal Communications Commission (FCC) granted the frequency range of 47 to 49 MHz for cordless phones in 1986 and the frequency range of 900 MHz in 1990. This improved their interference problem, reduced the power needed to run them, and allowed cordless phones to be clearer, broadcast a longer distance, and choose from more channels. However, cordless phones were still quite expensive.

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The use of digital technology transformed the cordless phone. Digital technology represents the voice as a series of 0s and 1s, just as a CD stores music. Digital cordless phones in the 900-MHz frequency range were introduced in 1994. Digital signals allowed the phones to be more secure and decreased eavesdropping. With the introduction of digital spread spectrum (DSS) in 1995, eavesdropping on the cordless conversations was practically made impossible. The opening up of the 2.4-GHz range by the FCC in 1988 increased the distance over which a cordless phone can operate and further increased security. With the cordless phone components getting smaller, more and more features and functions can be placed in phones without making them any bigger. Such functions may include voice mail, call screening, and placing outside calls. With many appealing features, there continues to be a strong market interest in cordless telephones for residential and private office use. As shown in Fig. 17.5.3, the cordless telephone has gone through an evolution. This started with the 46/49 MHz telephones. Although earlier cordless telephones existed, the 46/49 MHz cordless telephones were the first to be produced in substantial quantities. The second generation used 900-MHz frequency range resulting in longer range. The third generation introduced the spread spectrum telephones in the 900 MHz band. The fourth generation changed from 900-MHz to 2.4-GHz band, which is accepted worldwide. The fifth generation of cordless telephones is emerging now and employs time division multiple access (TDMA).

FIGURE 17.5.3 Evolution of cordless phone.

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FIGURE 17.5.4 Cordless telephone system configuration.

Basic Features A cordless phone basically combines the features of telephone and radio transmitter/receiver. As shown in Fig. 17.5.4, it consists of two major units: base and handset. The base unit interfaces with the public telephone network through the phone jack. It receives the incoming call through the phone line, converts it to an FM radio signal, and then broadcasts that signal. The handset receives the radio signal from the base, converts it to an electrical signal, and sends that signal to the speaker, where it is converted into the sound wave. When someone talks, the handset broadcasts the voice through a second FM radio signal back to the base. The base receives the voice signal, converts it to an electrical signal, and sends that signal through the phone line to the other party. The base and handset operate on a frequency pair (duplex frequency) that allows one to talk and listen simultaneously.

Types of Cordless Telephone Over the years, several types of cordless have been developed. These include:

• CT1: This first generation cordless telephone was introduced in 1983. It provides a maximum range of about 200 m between handset and base station. It is an analog phone that is primarily designed for domestic use. It employs analog radio and uses eight RF channel and frequency division multiple access (FDMA) scheme.

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TABLE 17.5.1 CT1 Cordless Telephone Duplex Frequencies

• •

•

•

Channel number

Base unit transmission frequency (kHz)

Handset transmission frequency (MHz)

1 2 3 4 5 6 7

1642.00 1662.00 1682.00 1702.00 1722.00 1742.00 1762.00

8

1782.00

47.45625 47.46875 47.48125 47.49375 47.50625 47.51875 47.53125 or 47.44375 47.54375

Operation has to be on not more than one of the pair of frequencies shown in Table 17.5.1 at any one time. As the number of users grew, so did the co-channel interference levels, while the quality of the service (customer satisfaction) deteriorated. CT2: This second generation cordless telephone uses digitized speech and digital transmission, thereby offering a clearer voice signal than analog CT1. Another advantage is that CT2 does not suffer from the inherent interference problems associated with CT1. DECT: DECT stands for digital enhanced cordless telecommunications. The DECT specification was developed by European Telecommunications Standards Institute (ETSI) and operates throughout Europe in the frequency band 1880 to 1900 MHz. DECT provides cordless telephones with the greater range, up to several hundred meters, allows encryption, provides for greater number of handsets, and even allows data communication. It uses high-frequency signals (1.88 to 1.9 GHz) and also employs time division multiple access (TDMA), which allows several conversations to share the same frequency. Although CT1, CT2, and DECT are European standards, the US PCS standards have followed these models too. DECT is being adopted increasingly worldwide. PHS: The personal hand-phone system (PHS) was introduced in Japan in 1995 for private use as well as for PCS. Unlike conventional cellular telephone systems, the PHS system employs ISDN technology. With PHS, a subscriber can have two separate telephone numbers: one for the home and the other for outside the home. The PHS system uses TDMA format because of the flexibility for call control and economy—characteristics common to the cellular system. To allow for two-way communication, forward and reverse channels are located on the same frequency by employing time-division duplex (TDD). It employs carrier spaced 300 kHz apart over a 23-MHz band from 1895 to 1918 MHz. Each carrier supports four channels—one control channel broadcast on a carrier, while three speech channels broadcast on other carrier waves. PHS is attracting attention around the world, particularly in Asian nations. ISM: The 900-MHz digital spread spectrum (DSS) cordless telephone operates in the 902 to 928 MHz industrial-scientific-medical (ISM) band. The spread spectrum systems have the additional advantage of enhanced security. The channel spacing is 1.2 MHz and there are 21 nonoverlapping channels in the band. The system is operated using TDD at a frame rate of 250 Hz. It provides clear sound, superb range, and security. It has a greater output power than other cordless phones. This increased power dramatically boosts range. The 2.4GHz DSS cordless telephone is an upgrade of this.

Cordless telephones are categorized by the radio frequency used and whether transmission between the handset and base unit is in the form of analog or digital signals. Generally speaking, the clarity of a cordless telephone improves with the use of higher frequencies and digital technology. Regulatory authorities in each country also specify and allocate the frequencies that may be used by cordless telephones in their respective countries and all telephones intended for use in their countries must receive their approvals. All cordless telephones are approved in the respective markets in which they are sold. Table 17.5.2 shows the common cordless telephone standards and their respective frequency range. In common with all areas of communications, the trend is away from analog systems to digital systems.

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TABLE 17.5.2 Comparison of Cordless Telephone Standards Analog cordless telephone Standard Region Frequency (MHz) Range (km)

Digital cordless telephone

CT1 Europe 914/960

JCT Japan 254/380

900 MHz worldwide 900

DECT Europe 1880–1990

PHS Japan 1895–1918

ISM USA 2400–2485

Up to 7

0.3

0.25

0.4

0.2

0.5

JCT—Japanese cordless telephone; PHS—Personal Hand-phone System.

PAGING Paging started as early as 1921 when the concept of one-way information broadcasting was introduced. The 1930s saw the widespread use of radio paging by government agencies, police departments, and the armed forces in the United States. Paging systems have undergone dramatic development. Radio transmission technology has advanced and so are the computer hardware and firmware (computer program) used in radio-paging systems.

One-Way Pagers A paging system is a one-way wireless messaging system that allows continuous accessibility to someone away from the wired communications network. In its most basic form, the person on-the-move carries a palm-sized device (the pager) that has an identification number. The calling party inputs this number, usually through the public telephone network, to the paging system which then signals the pager to alert the called party. Early paging systems were nonselective and operator assisted. Not only did it waste airtime, the system was inconvenient, labor-intensive, and offered no privacy. With automatic paging, a telephone number is assigned to each pager and the paging terminal can automatically signal for voice input from the calling party. The basic paging system consists of the following components:

• Input Source: A caller enters a page from a phone or through an operator. Once it is entered, the page is sent through the public switched telephone network (PSTN) to the paging terminal for encoding and transmission through the paging system. • Encoder: The encoder typically accepts the incoming page, checks the validity of the pager number, looks up the database for the subscriber’s pager address, and converts it into the appropriate paging signaling protocol. The encoded paging signal is then sent to the transmitters (base stations). • Base Station: This transmits page codes on an assigned radio frequency. Most base stations are designed specifically for paging but some of those designed for two-way voice can also be used. • Page Receivers: These are the pagers, which are basically FM receivers turned to the same RF frequency as the paging base station in the system. A decoder in each pager recognizes the unique code assigned to the pager and rejects all other codes for selective alerting. The most basic function of the pager is alerting. On receiving its own paging code, the receiver sets off an alert that can be audible (tone), visual (flashing indicator), or silent (vibrating). Messaging functions can also include voice and/or display (numeric/alphanumeric) messaging. Today’s paging systems offer much more than the basic system described above. A paging system subscriber can be alerted anytime and at almost any place as coverage can be easily extended, even across national borders. Paging systems are increasingly migrating from tone and numeric paging, to alphanumeric paging. Alphanumeric pagers display alphabetic or numeric messages entered by the calling party. The introduction of alphanumeric pagers also enables important information/data (e.g., business, financial news) to be constantly updated and monitored. Pagers that can display different ideographic languages, e.g., Chinese and Japanese, are now available in the market. The specific language supported is determined by the computer program installed in the pager.

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Two-Way Pagers The conventional paging systems are designed for one-way communication—from network toward pagers. Such systems provide the users one or more of the following services: beep, voice messaging, numeric messaging, and alphanumeric messages. With the recent development in paging systems, it is possible to supply a reverse link and thus allow two-way paging services. Two-way paging offers some significant capabilities with distinct advantages. Two-way paging is essentially alphanumeric paging that lets the pager send messages, either to respond to received messages or to originate its own messages. The pagers come in various shapes and sizes. Some look almost like today’s alphanumeric pagers, while some add small keyboards and larger displays. Two-way paging networks employ the 900-MHz band, a small fraction of the spectrum originally meant for PCS. Networks are built around protocols. Two-way messaging network is based on Reflex, which is basically an extension of Motorola’s Flex protocol for one-way paging. Reflex is a new generation of paging protocols. But reflex is a proprietary protocol. In view of the fact that two-way paging is the dominant application for wide area wireless networks and that a set of open, nonproprietary protocols is required to enable the convergence of the two-way paging and the Internet, efficient mail submission and delivery (EMSD) has been designed. EMSD is an open, efficient, Internet messaging protocol that is highly optimized for short messages. Devices that provide two-way paging capabilities should use this protocol (e.g., dedicated pagers, cell phones, palm PCs, handheld PCs, laptops, and desktops). The majority of pagers are used for the purpose of contacting someone on the move. The most popular type of pager used for this application is the alphanumeric pager that displays the telephone number to call back after alerting the paging subscriber. Although they are not common or cheap, the trend toward alphanumeric paging is inevitable with improved speed and better pagers. There will be more varied applications of paging such as the sending of e-mail, voice mail, faxes, or other useful information to a pager, which will also take on more attractive and innovative forms. Future pagers may compete more aggressively with other twoway technologies, such as cellular and PCS. Although paging does not provide real-time interactive communications between the caller and the called party, it has some advantages over other forms of PCS, such as cellular telephone. These include less bandwidth requirement, larger coverage area, lower cost, and lighter weight. Owing to these advantages, paging service is bound to be in a strong competitive PCS services in years to come. With more than 51 million paging subscribers worldwide, major paging markets in the world, especially in Asia, continue to expand rapidly. With the use of pagers getting more and more integrated into our daily lives, we will be seeing a host of new and exciting applications. There will emerge satellite pagers, which will send and receive messages through satellite systems such as Iridium, ICO, and Globalstar. With the help of such pagers, it is possible to supply paging services in global scale.

CELLULAR NETWORKS The conventional approach to mobile radio involved setting up a high-power transmitter on top of the highest point in the coverage area. The mobile telephone must have a line-of-sight to the base station for proper coverage. Line-of-sight transmission is limited to as much as 40 to 50 miles on the horizon. Also, if a mobile travels too far from its base station, the quality of the communications link becomes unacceptable. These and other limitations of conventional mobile telephone systems are overcome by cellular technology. Areas of coverage are divided into small hexagonal radio coverage units known as cells. A cell is the basic geographic unit of a cellular system. A cellular communications system employs a large number of low-power wireless transmitters to create the cells. These cells overlap at the outer boundaries, as shown in Fig. 17.5.5. Cells are base stations transmitting over small geographic areas that are represented as hexagons. Each cell size varies depending on the landscape and tele-density. Those stick towers one sees on hilltops with triangular structures at the top are cellular telephone sites. Each site typically covers an area of 15 miles across, depending on the local terrain. The cell sites are spaced over the area to provide a slightly overlapping blanket of coverage. Like the early mobile systems, the base station communicates with mobiles via a channel. The channel is made of two frequencies—one frequency (the forward link) for transmitting information to the base station and the other frequency (the reverse link) to receive from the base station.

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FIGURE 17.5.5 A typical wireless seven-cell pattern; cells overlap to provide greater coverage.

Fundamental Features Besides the idea of cells, the essential principles of cellular systems include cell splitting, frequency reuse, handover, capacity, spectral efficiency, mobility, and roaming.

• Cell Splitting: As a service area becomes full of users, the single area is split into smaller ones. This way, urban regions with heavy traffic can be split into as many areas as necessary to provide acceptable service, while large cell can be used to cover remote rural regions. Cell splitting increases the capacity of the system. • Frequency Reuse: This is the core concept that defines the cellular system. The cellular-telephone industry is faced with a dilemma: services are growing rapidly and users are demanding more sophisticated call-handling features, but the amount of the EM spectrum allocation for cellular service is fixed. This dilemma is overcome by the ability to reuse the same frequency (channel) many times. Several frequency-reuse patterns are in use in the cellular industry, each with its advantages and disadvantages. A typical example is shown in Fig. 17.5.6, where all the available channels are divided into 21 frequency groups numbered 1 to 21. Each cell is assigned three frequency groups. For example, the same frequencies are reused in cell designated 1 and adjacent locations do not reuse the same frequencies. A cluster is a group of cells; frequency reuse does not apply to clusters. • Handoff: This is another fundamental feature of the cellular technology. When a call is in progress and the switch from one cell to another becomes necessary, a handoff takes place. Handoff is important because as a mobile user travels from one cell to another during a call, as adjacent cells do not use the same radio channels, a call must be either dropped or transferred from one channel to another. Dropping the call is not acceptable. Handoff was created to solve the problem. A number of algorithms are used to generate and process a handoff request and eventual handoff order. Handing off from cell to cell is the process of transferring the mobile unit that has a call on a voice channel to another voice channel, all done without interfering with the call. The need for handoff is determined by the quality of the signal, whether it is weak or strong. A handoff threshold is predefined. When the received signal level is weak and reaches the threshold, the system provides

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FIGURE 17.5.6 Frequency reuse in a seven-cell pattern cellular system.

a stronger channel from an adjacent cell. This handoff process continues as the mobile moves from one cell to another as long as the mobile is in the coverage area. • Mobility and Roaming: Mobility implies that a mobile user while in motion will be able to maintain the same call without service interruption. This is made possible by the built-in-handoff mechanism that assigns a new frequency when the mobile moves to another cell. Because of several cellular operators within the same region using different equipment and a subscriber is only registered with one operator, some form of agreement is necessary to provide services to subscribers. Roaming is the process whereby a mobile moves out of its own territory and establishes a call from another territory. If we consider a cell (an area) with a perimeter L where r mobile units per unit area are located, the average number of users M crossing the cell boundaries per unit time is M=

ρVL π

where V is the average velocity of the mobile units.

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• Capacity: This is the number of subscribers that can use the cellular system. For an FDMA system, the capacity is determined by the loading (no. of calls and the average time per call) and system layout (size of cells and amount of frequency reuse utilized). Capacity expansion is required because cellular systems must serve more subscribers. It takes place through frequency reuse, cell splitting, planning, and redesigning of the system. • Spectral Efficiency: This a performance measure of the efficient use of the frequency spectrum. It is the most desirable feature of a mobile communication system. It produces a measure of how efficiently space, frequency, and time are used. Expressed in channels/MHz/km2, channel efficiency is given by

η=

total no. of channels available in the sysstem bandwidth × total coverage area

Bw N c × Bc N 1 η= = Bw × N c × Ac Bc × N × Ac

(7)

where Bw = bandwidth of the system in MHz Bc = channel spacing in MHz Nc = number of cells in a cluster N = frequency reuse factor of the system Ac = area covered by a cell in km2

Cellular System A typical cellular network is shown in Fig. 17.5.7. It consists of the following three major hardware components [3]:

• Cell Site (Base Stations): The cell site acts as the user-to-MTSO interface, as shown in Fig. 17.5.7. It consists of a transmitter and two receivers per channel, an antenna, a controller, and data links to the cellular office. Up to 12 channels can operate within a cell depending on the coverage area. • Mobile Telephone Switching Office (MTSO): This is the physical provider of connections between the base stations and the local exchange carrier. MTSO is also known as mobile switching center (MSC) or digital multiplex switch-mobile telephone exchange (DMS-MTX) depending on the manufacturer. It manages and controls cell site equipment and connections. It supports multiple-access technologies such as AMPS, TDMA, CDMA, and CDPD. As a mobile moves from one cell to another, it must continually send messages to the MTSO to verify its location. • Cellular (Mobile) Handset: This provides the interface between the user and the cellular system. It is essentially a transceiver with an antenna and is capable of tuning to all channels (666 frequencies) within a service area. It also has a handset and a number assignment module (NAM), which is a unique address given to each cellular phone.

Cellular Standards Because of the rapid development of cellular technology, different standards have resulted. These include:

• Advanced Mobile Phone System (AMPS): This is the standard introduced in 1979. Although it was developed and used in North America, it has also been used in over 72 countries. It operates in the 800-MHz frequency band. It is based on FDMA. The mobile transmit channels are in the 825- to 845-MHz range, while the mobile receive channels are in the 870- to 890-MHz range. There is also the digital AMPS, which is also known as TDMA (or IS-54). FDMA systems allow for a single mobile telephone to call on a radio channel;

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FIGURE 17.5.7 A typical cellular network.

each voice channel can communicate with only one mobile telephone at a time. TDMA systems allow several mobile telephones to communicate all the same time on a single radio carrier frequency. This is achieved by dividing their signal into time slots. • IS-54 and IS-95: The IS-54 is a North American standard developed by the Electronic Industries Association (EIA) and the Telecommunications Industry Association (TIA) to meet the growing demand for cellular capacity in high-density areas. It is based on TDMA and it retains the 30-kHz channel spacing of AMPS to facilitate evolution from analog to digital systems. The IS-95 standard was also adopted by EIA/TIA. It is based on CDMA, a spread-spectrum technique that allows many users to access the same band by assigning a unique orthogonal code to each user. • Global System for Mobile Communications (GSM): This is a digital cellular standard developed in Europe and designed to operate in the 900-MHz band. It is a globally accepted standard for digital cellular communication. It uses a 200-kHz channel divided into eight time slots with frequency division multiplexing (FDM). The technology allows international roaming and provides integrated cellular systems across different national borders. GSM is the most successful digital cellular system in the world. It is estimated that many countries outside Europe will join the GSM partnership. • Personal Digital Cellular (PDC): This is a digital cellular standard developed in Japan. It was designed to operate in 800-MHz and 1.5-GHz bands.

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• Future Public Land Mobile Telecommunication Systems (FPLMTS): This is a new standard being developed in ITU to form the basis for third-generation wireless systems. It will consolidate today’s increasingly diverse and incompatible mobile environments into a seamless infrastructure that will offer a diverse portfolio of telecommunication services to an exponentially growing number of mobile users on a global scale. It is a digital system based on 1.8- to 2.2-GHz band. It is being tested to gain valuable user and operator experience. In many European countries, the use of GSM has allowed cross-country roaming. However, global roaming has not been realized because there are too many of these incompatible standards.

PERSONAL COMMUNICATION SYSTEMS The GSM digital network has pervaded Europe and Asia. A comparable technology known as PCS is beginning to make inroads in the United States. According to FCC, “PCS is the system by which every user can exchange information with anyone, at anytime, in any place, through any type of device, using a single personal telecommunication number (PTN).” PCS is an advanced phone service that combines the freedom and convenience of wireless communications with the reliability of the legacy telephone service. Both GSM and PCS promise clear transmissions, digital capabilities, and sophisticated encryption algorithms to prevent eavesdropping. PCS is a new concept that will expand the horizon of wireless communications beyond the limitations of current cellular systems to provide users with the means to communicate with anyone, anywhere, anytime. It is called PCS by the FCC or personal communications networks (PCN) by the rest of the world. Its goal is to provide integrated communications (such as voice, data, and video) between nomadic subscribers irrespective of time, location, and mobility patterns. It promises near-universal access to mobile telephony, messaging, paging, and data transfer. PCS/PCN networks and the existing cellular networks should be regarded as complimentary rather than competitive. One may view PCS as an extension of the cellular to the 1900-MHz band, using identical standards. Major factors that separate cellular networks from PCS networks are speech quality, complexity, flexibility of radio-link architecture, economics of serving high-user-density or low-user-density areas, and power consumption of the handsets. Table 17.5.3 summarizes the differences between the two technologies and services. PCS offers a number of advantages over traditional cellular communications:

• A truly personal service, combining lightweight phones with advanced features such as paging and voice • • • • •

mail that can be tailored to each individual customer. Less background noise and fewer dropped calls An affordable fully integrated voice and text messaging that works just about anywhere, anytime A more secure all-digital network that minimizes chances of eavesdropping or number cloning An advanced radio network that uses smaller cell sites A state-of-the-art billing and operational support system

TABLE 17.5.3

Comparison of Cellular and PCS Technologies

Cellular Fewer sites required to provide coverage More expensive equipment Higher costs for airtime High antenna and more space needed for site Higher power output

PCS More sites required to provide coverage (e.g., a 20:1 ratio) Less expensive cells Airtime costs dropping rapidly Smaller space for the microcell Lower power output

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FIGURE 17.5.8 Various cell sizes.

Basic Features PCS refers to digital wireless communications and services operating at broadband (1900 MHz) or narrowband (900 MHz) frequencies. Thus there are three categories of PCS: broadband, narrowband, and unlicensed. Broadband PCS addresses both cellular and cordless handset services, while narrowband PCS focuses on enhanced paging functions. Unlicensed service is allocated from 1890 to 1930 MHz and is designed to allow unlicensed short-distance operation. The salient features that enable PCS to provide communications with anyone, anywhere, anytime include:

• Roaming Capability: The roaming service should be greatly expanded to provide universal accessibility. PCS • •

• •

will have the capability to support global roaming. Diverse Environment: Users must be able to use the PCS in all types of environments, e.g., urban, rural, commercial, residential, mountains, and recreational area. Various Cell Size: With PCS, there will be a mix of broad types of cell sizes: the picocell for low power indoor applications, the microcell for lower power outdoor pedestrian application, macrocell for high power vehicular applications, and supermacrocell with satellites, as shown in Fig. 17.5.8. For example, a picocell of a PCS will be in the 10 to 30 m range; a microcell may have a radius of 50 to 150 m; and a macrocell may have a radius of 1 km. Portable Handset: PCS provides a low-power radio, switched access connection to the PSTN. The user should be able to carry a single, small, universal handset outside without having to recharge its batter. Single PTN: The user can be reached through a single PTN regardless of the location and the type of service used.

The FCC frequency allocation for PCS usage is significant. FCC allocated 120 MHz for licensed operation and another 20 MHz for unlicensed operation, amounting to a total of 140 MHz for PCS, which is three times the spectrum currently allocated for cellular network. The FCC’s frequency allocation for PCS is shown in Tables 17.5.4 and 17.5.5 for licensed and unlicensed operators. To use the PCS licensed frequency band, a company must obtain a license from FCC. To use the unlicensed (or unregulated) PCS spectrum, a company must use equipment that will conform with the FCC unlicensed requirements that include low power transmission to prevent interference with other users in the same frequency band. PCS Architecture A PCS network is a wireless network that provides communication services to PCS subscribers. The service area of the PCS network is populated with base stations, which are connected to a fixed wireline network

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TABLE 17.5.4 The PCS Frequency Bands for Licensed Operation

Block

Spectrum low side (MHz)

Spectrum high side (MHz)

1850–1865 1865–1870 1870–1885 1885–1890 1890–1895 1895–1910

1930–1945 1945–1950 1950–1965 1965–1970 1970–1975 1975–1990

A D B E F C Total

Bandwidth (MHz) 30 10 30 10 10 30 120

through mobile switch centers (MSCs). Like a cellular network, the radio coverage of a base station is called a cell. The base station locates a subscriber or mobile unit and delivers calls to and from the mobile unit by means of paging within the cell it serves. PCS architecture resembles that of a cellular network with some differences. The structure of the local portion of a PCS network is shown in Fig. 17.5.9. It basically consists of five major components:

• • • • •

Terminals installed in the mobile unit or carried by pedestrians Cellular base stations to relay signals Wireless switching offices that handle switching and routing calls Connections to PSTN central office Database of customers and other network-related information

Since the goal of PCS is to provide anytime-anywhere communication, the end device must be portable and both real-time interactive communication (e.g., voice) and data services must be available. PCS should be able to integrator or accommodate the current PSTN, ISDN, the paging system, the cordless system, the wireless PBX, the terrestrial mobile system, and the satellite system. The range of applications associated with PCS is depicted in Fig. 17.5.10.

PCS Standards The Joint Technical Committee (JTC) has been responsible for developing standards for PCS in the United States. The JTC committee worked cooperatively with the TIA committee working on the TR-46 reference model and ATIS committee working on the T1P1 reference model. Unlike GSM, PCS is unfortunately not a single standard but a mosaic consisting of several incompatible versions coexisting rather uneasily with one another. One major obstacle to PCS adoption in the United States has been the industry’s failure to sufficiently convince customers on the advantages of PCS over AMPS, which already offers a single standard. This places the onus on manufacturers to inundate phones with features that attract market attention without compromising the benefits inherent in cellular phones. However, digital cellular technology enjoys distinct advantages. Perhaps the most significant advantage involves security because one cannot adequately encrypt AMPS signals.

TABLE 17.5.5 The PCS Frequency Bands for Unlicensed Operation Block

Spectrum (MHz)

Bandwidth (MHz)

Isochronous Asynchronous Total

1910–1920 1920–1930

10 10 20

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FIGURE 17.5.9 Structure of PCS network.

Satellites are instrumental in achieving global coverage and providing PCS services. Mobile satellite communications for commercial users is evolving rapidly toward PCS systems to provide basic telephone, fax, and data services virtually anywhere on the globe. Satellite orbits are being moved closed to the earth, improving communication speed and enabling PCS services. Global satellite systems are being built for personal communications. In the United States, the FCC licensed five such systems: Iridium, Globalstar,

FIGURE 17.5.10 Range of applications associated with PCS.

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Odyssey, Ellipso, and Aries. In Europe, ICO-Global is building ICO. Japan, Australia, Mexico, and India are making similar effort. Future growth and success of PCS services cannot be taken for granted. Like any new technology, the success of PCS system will depend on a number of factors. These include initial system overall cost, quality, and convenience of the service provided,