Application Note AN 33: Initialization and operation of the NET2280 with target only PCI devices

1. General Description This document details the initialization and operation of the NET2280 in PCI host mode with target only PCI devices. In this system, the NET2280 is connected to a USB Host on one end and a PCI target only device on the other. There is no RAM or other devices on the PCI bus. For this system, the NET2280 will have to be placed in PCI host mode. It will be the one to setup and configure the PCI device. Once configured, the built in DMA controllers will be used to transfer data to and from the PCI device. As there is no RAM on the PCI bus, DMA scatter gather and valid mode functions cannot be used. Therefore, the on-chip 8051 CPU or the USB Host will have to actively manage the DMA controllers.

2. Suggested Pin Settings To place the NET2280 in the correct mode for proper operation, the following pins must be connected to specific values. Pins not listed should be set normally (i.e. USB pins to USB, PCI pins to PCI, etc.).

Pin Name HOST

Pin Number 112

Description

CLK

41

RST# EXTARB REQ# GNT#

40 113 44 43

IDSEL

63

AD17

71

INTA# SERR# PME# PWRDOWN #

39 83 45

Set to 1 to place NET2280 in PCI Host Mode Connect to central PCI Clock resource and clock input of target PCI device Connect to RESET input on PCI device Connect to 0 to use the internal PCI Arbiter Connect to 1, as target devices never need to master the PCI bus No connect, as target devices never need to master the PCI bus Connect to 0, as the Host will not be configured by other PCI devices Connect to IDSEL of the PCI device, this allows the NET2280 to configure it using 17 as its device number Connect to INTA# output of PCI device Connect to SERR# output of PCI device Connect to PME# output of PCI device

4

Set to 1 to keep the PCI clock active at all times

Table #1: Suggested Pin Settings for Host Mode

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3. Suggested Configuration Settings To set up the NET2280 for hosting the PCI bus, the following registers must be set to specific values. Configuration registers can be set by an external EEPROM, the internal 8051 CPU, or by the USB Host. Registers not listed should be set normally (i.e. max packet sizes, interrupt enables, vender and device IDs, etc.). Register Name PCICMD PCICMD PCICMD

Bits

Value

Interrupt Disable SERR# Enable Bus Master Enable

1 0 1

PCISTAT

Capability Valid

0

DEVINIT DEVINIT

Force PCI RST PCI Enable

Varies 1

DEVINIT CPUIRQENB1 CPUIRQENB1

8051 Reset CPU Interrupt Enable PCI Master Abort Received Interrupt Enable

0 1 1

PCIMSTCTL EP_CFG

PCI Arbiter Park Select Endpoint Enable

0 1

Description Disable PCI Interrupt Out Disable PCI SERR# Out This enables the NET2280 to initiate PCI bus cycles Do not use Power Management Capabilities This bit toggles the PCI Reset pin This enables PCI transactions on the NET2280 Enable internal 8051 CPU Enable Interrupts to the 8051 CPU This allows PCI Master Aborts to generate an interrupt (only needed if an undetermined number of slots are filled) Set arbiter to park on last grantee Enable USB Endpoints

Table #2: Suggested Internal Configuration Register Values

4. Configuring the PCI Bus In this system, the NET2280 is the Host of the PCI bus. As a Host, the NET2280 must properly configure all the PCI devices. This means enabling features, setting timer values, and building a memory map of the PCI bus. This configuration process can be directed by the internal 8051 CPU or by the USB Host. Generally, the PCI Host first determines which PCI slots have cards plugged in. If a slot is empty, an access to it by the Host will result in a Master Abort. Once it knows which cards are present, the Host then goes on to determine which base addresses are implemented in each of the cards, and how much memory each one requires. The Host will then build a memory map for the entire system. It will assign addresses to each of the base address requests in each card. The Host then sets latency timers, cache line sizes, etc. to optimize the cards for this system. On a PC, these settings can often be found in the BIOS setup as options. Finally, the Host will enable each card to start up and pass the device and vender information to the device driver for further action. The Host will also be the destination of any PCI interrupts and error messages. See section 8 for sample source code of the 8051’s initialization of a PCI device

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Figure #1: PCI Initialization Flow

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5. USB IN Data transfers using DMA In an IN transfer, the USB host is requesting data from the PCI side. The PCI side has the data and knows how much of it is available to go to the USB host. The USB host starts by requesting IN data from the PCI side. Initially, there is no data in the FIFOs, so the NET2280 will return a NAK to the USB Host. The NET2280 will also send an IN Token Interrupt to the 8051 CPU. Upon this interrupt, the 8051 should disable the IN Token Interrupt and then program the DMA engine to transfer the available amount of data to the USB host. The DMA (initiating PCI reads) will then occur automatically, transparently responding to FIFO status, PCI and USB retries, wait states, etc., until all data transfer is complete. Meanwhile, the USB host will be retrying that initial NAK. The NET2280 will respond with the IN data (or NAK again if the FIFO doesn’t have a max packet-full of data yet). The USB host will continue to read one packet of data at a time until it gets a short packet (DMA would have completed). This short packet indicates to the USB host that there is no more data to transfer. A zero-length packet is also defined as a short packet. A Short Packet Transferred Interrupt will be sent to the 8051 when that packet transfer has completed. The 8051 should then clear all interrupts and re-enable the IN Token Interrupt. It is also possible not to wait for the initial IN Token Interrupt. If the PCI data for the IN transfer is already available, the DMA could be used to prefetch some of that data into the internal FIFOs. This prefetched data will sit there waiting for the next IN request from the USB host. The DMA engine is aware of the internal FIFO status and will always attempt to keep it full, yet never overflow it. In this case, the initial NAK would not occur, and data transfer begins immediately. Instead of using the built in 8051 CPU, the DMA engines could also be programmed by a PCI Master, or directly by the USB host itself. The USB host can access the internal registers via the CFGIN and CFGOUT dedicated endpoints (section 7.6.5.1 in the NET2280 databook). Interrupts would not have to be deployed if the USB host were programming the DMAs itself. Register Name EP_IRQENB EP_IRQENB CPUIRQENB1 CPUIRQENB0 DMACTL DMACTL DMACTL DMACTL DMACTL DMACTL

Bits 5 0 31 4:1 21 17 16 2 1 0

Value 1 1 1 Varies 0 0 0 1 1 Varies

DMACOUNT DMACOUNT DMACOUNT

30 29 23:0

1 0 Varies

DMAADDR

31:0

Varies

DMASTAT

0

1

Description Short Packet Transferred Interrupt Enable IN Token Interrupt Enable Enable Interrupts to the 8051 CPU Enable appropriate Endpoint interrupt to 8051 CPU No clear count used in this application No valid bit used in this application No DMA scatter gather used in this application Automatic short packet validation DMA enable Set to 1 if the DMA is to generate a constant PCI address for FIFOs (rather than an incrementing address for memories) Set DMA direction for IN transfers DMA done interrupt not needed Number of bytes to transfer (does not need to be in increment of 4 bytes) PCI address where IN data is being held at (does not have to be aligned to any byte counts) Writing a 1 to this bit starts the DMA controller

Table #3: Register Configuration for USB IN Transfers © PLX Technology, Inc., 2004 870 Maude Avenue, Sunnyvale, California 94085 TEL (650) 526-1490 FAX (650) 526-1494 http://www.plxtech.com/netchip

5.1 IN Transfer Example Assume max packet sizes are set to 512 bytes (default for high speed bulk endpoints), and there are 1025 bytes of data to be sent to the USB host (the NET2280’s internal FIFO is set to 1024 bytes deep). Step 1: The USB host requests IN data from the NET2280. Step 2: The NET2280 responses with a NAK as the internal FIFO is initially empty. Step 3: The 8051 receives an IN Token Interrupt. Step 4: The 8051 disables the IN Token Interrupt Step 5: The 8051 programs the DMA to transfer 1025 bytes. Step 6: The DMA transfers the first bytes to the internal FIFO (attempting to fill it up). Step 7: The USB host is constantly retrying the IN request, waiting for the first 512 bytes of data in the FIFO. Step 8: The NET2280 sends the first 512 byte packet to the USB host. Step 9: The DMA transfers the last byte (number 1025) to the internal FIFO (space is available once the USB host has read out the first 512 bytes). Step 10: The USB host is constantly returning for more data with further IN requests. Step 11: The NET2280 sends the second 512 byte packet to the USB host (sending NAKs if the data was not yet available in the FIFO). Step 12: The USB host is constantly returning for more data with further IN requests. Step 13: The NET2280 sends the last byte (number 1025) to the USB host. This is a short packet so the USB host will know that there is no more data to be received in this transfer. (If the DMA was programmed to only transfer 1024 bytes, the USB host would receive a zero-length packet instead.) Step 14: The 8051 receives a Short Packet Transferred Interrupt. Step 15: The 8051 clears the Short Packet Transferred and IN Token Interrupts and re-enables the IN Token Interrupt (If the USB host requests a new IN transfer before the IN Token Interrupt has been re-enabled by the 8051, the NET2280 would simply respond with a NAK. This causes the USB host to retry the IN transfer at a later time – resulting in an IN Token Interrupt at that time.) Step 16: The NET2280 is now ready for another IN transfer.

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6. USB OUT Data Transfers using DMA In an OUT transfer, the USB host has data to send to a PCI target. While USB will send a max packetfull of data at a time, the PCI side generally does not know in advance how many bytes the USB host intends to send in a complete transfer. The 8051 CPU starts the process by programming the DMA engine to transfer an arbitrary large amount of data to the PCI bus. However, as the FIFOs are initially empty, the DMA engine would simply wait there, not initiating any PCI cycles. Once the USB host sends OUT data to the Internal FIFOs, the DMA engine will kick in and start PCI write cycles to the PCI Target automatically. The DMA engine will transparently respond to FIFO status, PCI disconnects, USB retries, wait states, etc. The USB host will continue sending OUT packets until there is no more data to transfer. The last packet sent will be a short packet. A zero length packet is also considered a short packet. This short packet will trigger NAK OUT Packets, blocking any further OUT transfers on this endpoint until cleared. When the DMA engine has finished transferring the last data of that short packet to PCI, it will trigger a Short Packet OUT Done Interrupt to the 8051. The 8051 should then abort the DMA transfer and clear the interrupt and NAK OUT Packet Status. It may also want to prep the DMA for the next OUT transfer. Instead of using the built in 8051 CPU, the DMA engines could also be programmed by a PCI Master, or directly by the USB host itself. The USB host can access the internal registers via the CFGIN and CFGOUT dedicated endpoints (section 7.6.5.1 in the NET2280 databook). In this case, rather than programming the DMA count to an arbitrary big value, the USB host would program the DMA count to the actual expected count, so DMA aborts would not be needed. The Short Packet OUT Done Interrupt would still have to be monitored so that the USB host would not inadvertently re-program an on-going DMA cycle. Register Name EP_IRQENB EP_RSP CPUIRQENB1 CPUIRQENB0 DMACTL DMACTL DMACTL DMACTL

Bits 6 2 31 4:1 21 17 16 4

Value 1 1 1 Varies 0 0 0 1

1 0

1 Varies

DMACOUNT DMACOUNT DMACOUNT

30 29 23:0

0 0 999999

DMAADDR

31:0

Varies

DMASTAT

1

1

DMASTAT

0

1

DMACTL DMACTL

Description Short Packet OUT Done Interrupt Enable NAK OUT Packets Mode Enable Interrupts to the 8051 CPU Enable appropriate Endpoint interrupt to 8051 CPU No clear count used in this application No valid bit used in this application No DMA scatter gather used in this application Automatically start the DMA transfer when an OUT packet is received DMA enable Set to 1 if the DMA is to generate a constant PCI address for FIFOs (rather than an incrementing address for memories) Set DMA direction for OUT transfers DMA done interrupt not needed Set number of bytes to transfer to a value higher than any complete OUT transfer PCI address where OUT data is to be stored at (does not have to be aligned to any byte counts) Abort the DMA after receiving a Short Packet OUT Done Interrupt Writing a 1 to this bit starts the DMA controller

Table #4: Register Configuration for USB OUT Transfers © PLX Technology, Inc., 2004 870 Maude Avenue, Sunnyvale, California 94085 TEL (650) 526-1490 FAX (650) 526-1494 http://www.plxtech.com/netchip

6.1 OUT Transfer Example Assume max packet sizes are set to 512 bytes (default for high speed bulk endpoints), and there are 1025 bytes of data to be sent to the PCI target (the NET2280’s internal FIFO is set to 1024 bytes deep). Step 1: The 8051 programs the DMA to transfer an arbitrary large amount of OUT data to the PCI Target (the DMA doesn’t actually do anything as there is no data in the internal FIFO yet). Step 2: The USB host sends the first 512 byte packet to the NET2280. Step 3: The DMA automatically starts transferring data to the PCI target, taking into account internal FIFO and PCI Bus status. Step 4: The USB host sends the second 512 byte packet to the NET2280. Step 5: The DMA continues to send OUT data to the PCI target. Step 6: The USB host send the last packet (1 byte long short packet) to the NET2280. If the internal FIFO is full, the NET2280 will respond with a NAK, forcing the USB host to retry the OUT transfer at a later time. Step 7: NAK OUT Packets ars activated by the USB host sending out the short packet. This blocks any further OUT transfers on this endpoint until it is cleared. Step 8: The DMA sends the last byte (number 1025) to the PCI Target. (If the USB host only transferred 1024 bytes, followed by a zero length packet, the DMA will stop.) Step 9: A Short Packet OUT Done Interrupt is sent to the 8051 by the DMA engine. Step 10: The 8051 aborts the DMA transfer. Step 11: The 8051 clears the Short Packet OUT Done Interrupt and the NAK OUT Packets Status. Step 12: The 8051 reprograms and restarts the DMA. The NET2280 is now ready for another OUT transfer.

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7. Summary Two steps are required to use the NET2280 for transferring data to and from a target only PCI device. The first step is for the NET2280 to initialize and configure the PCI bus / device. The second step is to utilize the built in DMA engines to transfer the data. While the DMA engines are flexible and will automatically respond to internal FIFO status and PCI bus events, they still require some intelligence to periodically set up and start them. This intelligence could be the programmed in the 8051 CPU or the USB host itself. While this application note deals with a PCI bus with target only devices and no memory, the NET2880 can also be used with other options. The addition of memory on the PCI bus would enable the use of the Scatter Gather / Valid Mode options of the DMA engines. This will reduce the burden on the 8051 / USB host to manage the data transfers. The NET2280 can also be used with bus mastering PCI devices. In this situation, the internal DMAs, and the need to manage them, would not be needed at all.

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8. Sample Source Code for Internal 8051 CPU Initialization of a PCI Device The following source code has the Internal 8051 CPU accessing the PCI bus to configure a device there. It calls routines MasterRead and MasterWrite, for the 8051 to access the NET2280’s internal registers. The code uses them to perform configuration accesses to the PCI bus (through the PCI Master Control Registers). The 8051 first determines what resources are required, allocates memory for those resources, then it enables PCI features and timers for efficient PCI operation. In this case, the code knows exactly which device is attached (NET2270 RDK with a PLX PCI bridge) and how many base addresses are needed. This code would have to be modified so that it can recover from PCI Master Aborts in order to work with a non-predetermined number of devices and requested resources. (PCI Aborts occur when a device attempts to access a non-existent PCI device or non-allocated memory location.) EnumeratePCI( void ) { #if PCI_CYCLES_NEEDED DWORD tmp; BYTE ii; MASTER_CYCLE_RESULT result; PCIMasterControlRead = CONFIG_READ; PCIMasterControlWrite = CONFIG_WRITE; //////////////////////////////////////////////// // Write to PCICMD to enable 2280 as the bus master CFGADDR0 = PCICMD; CFGADDR1 = 0; CFGDATA3 = 0; CFGDATA2 = 0; CFGDATA1 = 0; CFGDATA0 = 1