GAL26V12 High Performance E2CMOS PLD Generic Array LogicTM FEATURES

FUNCTIONAL BLOCK DIAGRAM ®

• HIGH PERFORMANCE E CMOS TECHNOLOGY — 7.5 ns Maximum Propagation Delay — Fmax = 142.8 MHz — 4.5 ns Maximum from Clock Input to Data Output — TTL Compatible 16 mA Outputs — UltraMOS® Advanced CMOS Technology

I/CLK 1 8

8 INPUT

I/O/Q

OLMC 2

I/O/Q

12 INPUT

INPUT

INPUT

• PRELOAD AND POWER-ON RESET OF REGISTERS — 100% Functional Testability

INPUT

• APPLICATIONS INCLUDE: — DMA Control — State Machine Control — High Speed Graphics Processing — Standard Logic Speed Upgrade

I/O/Q

OLMC 3 14

OLMC 4

I/O/Q

OLMC 5

I/O/Q

16

16

I/O/Q

OLMC 6 14

I/O/Q

OLMC 7

INPUT 12

I/O/Q

OLMC 8

INPUT 10

I/O/Q

OLMC 9

INPUT

• ELECTRONIC SIGNATURE FOR IDENTIFICATION

8

I/O/Q

OLMC 10

INPUT

DESCRIPTION

8

I/O/Q

OLMC 11

INPUT

RESET

PACKAGE DIAGRAMS

DIP

The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. The GAL26V12 is fully function/fuse map/parametric compatible with other 26V12 devices.

I/CLK1

I

I I/O/Q

II/CLK1

2

28

I/O/Q 7

GAL26V12

I I

Top View

9

23

21

I 11

I/O/Q

I/O/Q

I/O/Q

19 18

16

I/O/Q

I

14

I

12

I

I

I/O/Q

26

I VCC

I I/O/Q

I

I/O/Q

28

I I/CLK2

25

5

1

I

I/O/Q

4

I

I

PLCC I I/CLK2

Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, LATTICE is able to guarantee 100% field programmability and functionality of all GAL® products. LATTICE also guarantees 100 erase/rewrite cycles.

OLMC 1 10

INPUT/CLK 2

• TWELVE OUTPUT LOGIC MACROCELLS — Maximum Flexibility for Complex Logic Designs

The GAL26V12, at 7.5ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 26V12 device on the market. E2 technology offers high speed (