FPGA Development Techniques

Wednesday November 3, 2004 Polytech’ Orléans

Agenda • Static Timing Analysis – Constraining an FPGA design and ensuring it meets performance requirements

• On-Chip Debugging – Using a logic analyzer implemented inside the FPGA to quickly debug at full system speed

• Power Estimation & Analysis – Obtaining an initial power estimate before starting your design & analyzing detailed results after implementation FPGA Development Techniques 2

Outline • Static Timing Analysis – – – – – –

Introduction Review of Basic Constraints When to Use Advanced Constraints Handling Multiple Clock Domains Analyzing Design Results Demonstration of Constraints Editor & Timing Analyzer to Floorplanner Cross-Probing

• On-Chip Debugging • Power Estimation & Analysis FPGA Development Techniques 3

What are Timing Constraints for ? • The implementation tools do not try to find the placement & routing that will obtain the fastest speed – Instead, the implementation tools try to meet your performance expectations

• Performance expectations are communicated with timing constraints – Timing constraints cause the tools to improve the design performance by placing logic closer together so shorter routing resources can be used FPGA Development Techniques 4

Without Timing Constraints • This design had no timing constraints or pin assignments entered with the design when it was implemented • Note the logical structure of the placement and pins • Xilinx recommends that you verify that your timing constraints are realistic before completing the functional verification of your design • This design has a maximum system clock frequency of 50 MHz FPGA Development Techniques 5

With Timing Constraints • This is the same design with three global timing constraints entered with the Constraints Editor • It has a maximum system clock frequency of 60 MHz • Note how most of the logic is placed closer to the edge of the device, where the pins have been placed

FPGA Development Techniques 6

How do I add Constraints? • Start the Constraints Editor GUI from the Process window – will create a new “Implementation Constrains” source file and run the TRANSLATE step

• Can also be invoked at the command line – by typing “constraints_editor”

• Or edit the constraints file – a text file which contains constraints – identified by a “.ucf” suffix FPGA Development Techniques 7

Constraints in the Design Flow TextEditor Editor Text

TextEditor Editor Text

EDIFor orNGC NGC EDIF

Synthesis Synthesis

VHDL VHDL

1. Enter Timing Constraints here... 2. … and Physical Constraints here (not covered today) 3. Used by the implementation tools 4. Analyze results here

FPGA Development Techniques 8

Specifying Constraints • Usually written (automatically or by hand) in a separate file, one per project • Documented in the “Constraints Guide” – see doc\usenglish\books\docs\cgd\cgd.pdf or – www.support.xilinx.com

• Constraints can also be directly embedded in source code or IP core netlists FPGA Development Techniques 9

Outline • Static Timing Analysis – – – – – –

Introduction Review of Basic Constraints When to Use Advanced Constraints Handling Multiple Clock Domains Analyzing Design Results Demonstration of Constraints Editor & Timing Analyzer to Floorplanner Cross-Probing

• On-Chip Debugging • Power Estimation & Analysis FPGA Development Techniques 10

The PERIOD Constraint NET “CLK” PERIOD = 10 nS ; FPGA

CLK

This says, Data has 10nS to get from this flip-flop, to another flip-flop, here All synchronous elements (RAMs, FFs, MULTS) are identified by forward propagation of the CLK net. Note that I/O Pads are not covered by the PERIOD constraint!

FPGA Development Techniques 11

The OFFSET IN - ‘BEFORE’ Constraint OFFSET = IN 3nS BEFORE “CLK”; UPSTREAM DEVICE

FPGA Din

CLK

CLK

This says, Data will be valid here, 3 nS BEFORE the clock arrives here The tools attempt to control internal data and clock delays for all flip-flops’ setup requirement (TsuFF).

FPGA Development Techniques 12

The OFFSET OUT - ‘AFTER’ Constraint OFFSET = OUT 4nS AFTER “CLK”; FPGA

CLK

DOWNSTREAM DEVICE

This says, Data will be valid here, 4 nS AFTER the clock arrives here The tools attempt to control internal data and clock delays to meet this clock-toout requirement. The downstream device’s setup time and the board delay will help you set this value. Using a DLL or DCM can help improve this number!

FPGA Development Techniques 13

The PADS to PADS Constraint TIMESPEC "TS_P2P" = FROM PADS TO PADS 15 ns; UPSTREAM DEVICE

FPGA

DOWNSTREAM DEVICE

This says, from the input pad, Data has 15 nS to get to the output pad This constraint is required to constrain combinatorial logic paths (ie, don’t contain any synchronous elements) within the FPGA. Purely combinatorial paths, while easily implemented with consistent timing in CPLDs, should be used with caution in FPGAs. FPGA Development Techniques 14

Outline • Static Timing Analysis – – – – – –

Introduction Review of Basic Constraints When to Use Advanced Constraints Handling Multiple Clock Domains Analyzing Design Results Demonstration of Constraints Editor & Timing Analyzer to Floorplanner Cross-Probing

• On-Chip Debugging • Power Estimation & Analysis FPGA Development Techniques 15

Using Advanced Constraints • Review of Basic Constraints showed how to fully constraint a simple, synchronous, single clock design • Most real designs are more complicated than this! • Many designs may require some of the following: – Specifying different setup and clk-to-out values for different I/O pins on the same clock domain (ie microprocessor I/F) – Defining multi-cycle paths (useful for clock enables) – Ignoring some paths which aren’t timing critical – Clocks on non-global routing – Forwarding clocks off-chip FPGA Development Techniques 16

OFFSET IN & OUT Revisited • For certain interfaces, I/O pins in the same clock domain may have different setup & hold requirements • Continue to use general OFFSET IN & OUT for entire clock domain, but add exceptions: – OFFSET = IN 3 nS BEFORE “CLK”; – NET “FAST_IN” OFFSET = IN 1.8 ns BEFORE “CLK”; – NET “SLOW_IN” OFFSET = IN 4.2 ns BEFORE “CLK”;

• Specific exceptions will take precedence over general constraint, without duplication in the timing report • Wildcards, for example ADDR_BUS[*] can be used... FPGA Development Techniques 17

Creating Timing Groups • To allow for more complex timing constraints, the notion of groups of elements is required • Since logic paths start and stop at synchronous elements, the following keywords can be used: FFS All flip-flops LATCHES All latches RAMS All RAM elements

• Input & outputs can also be grouped: PADS

All I/O pads

• Can be used globally and/or to create sub-groups FPGA Development Techniques 18

Slow Exceptions • Slow Exceptions are FROM:TOs that define a different delay for portion of the design. The majority of the design is covered by a PERIOD constraint. Example 1: Using FROM:TO’s only -- OK, but not best method 60 ns

30 ns IN

D

Q

FROM:flop1:TO:flop2:30

D

Q

FROM:flop2:TO:flop3:60

D

Q

OUT

CLK

Example 2: Using PERIOD with a FROM:TO Slow Exception -- BEST, faster par & trce 60 ns

30 ns IN

D

Q

D

NET CLK PERIOD=30 CLK

FPGA Development Techniques 19

Q

FROM:flop2:TO:flop3:60

D

Q

OUT

Multi-Cycle Delays • Use INST to create groups by matching the symbol name NET “CLK” PERIOD = 10 ; INST “CNT16/U1” TNM = CNT50 ; INST “reg0” TNM = MYREGS ; TIMESPEC TS_MYBUS = FROM : CNT50 : TO : MYREGS : 20 ns ; D

TS_MYBUS

Q

MY_REG_0

reg0 MY_REG_1 D

Q

D

Q

reg1

CNT16

reg2 D

Q

reg3

FPGA Development Techniques 20

MY_REG_2

MY_REG_3

FROM : TO Syntax Details TIMESPEC TS_name = FROM:group1:TO:group2:value; • TIMESPEC defines the type of specification • TS_name must always start with “TS”. Any alphanumeric character or underscore may follow • Group1 designates the origin of the path • Group2 designates the destination of the path • Value is in ns by default. Other possible values are MHz or another time spec like TS_C2S/2 or TS_C2S*2 FPGA Development Techniques 21

Ignoring Selected Paths • Why use Timing IGnore (TIG) ? – Not all paths in designs require timing specifications – Decreases competition for routing resources – When non-critical timing paths are included in time specifications, more important paths may be slower and may not meet time specifications

• The TIG constraint ignores all nets that fan forward from the specified element • The TIG constraint prevents any constraints from being applied to the specified path FPGA Development Techniques 22

TIG Example • UCF Syntax:

NET “NETC” TIG ;

NETA NETB NETC NETD

• NETC shown in the diagram is ignored. – This will remove all constraints on 3 different paths

• NETA, NETB and NETD which overlap some parts of NETC’s path will not be ignored FPGA Development Techniques 23

TIG Attribute • Syntax: {NET|PIN|INST} “name” TIG = group1 [ group2, … ];

• name : element, net, or instance that is to be ignored • group_name : optional field which ignores the net, instance, or pin in the listed group • All paths that fan forward from the net or instance will not have any timing constraints applied to them – The paths will be treated as if they don’t exist

• Paths can be specified between & through groups, ie: TIMESPEC ts_ignr = FROM groupA THRU groupB TO groupC TIG ; FPGA Development Techniques 24

Clocks on non-global Routing • Clocks which don’t use BUFGs can be skewed INPUT

3.1

D Q_A

CLOCK 3.0

3.1 D Q_B

3.3 D Q_C 3.0

4.5

A

B

C

• This shift register will not work because of clock skew! 2 cycles 3 cycles

A&C Clock

Clock

B Clock

Q_A Q_B

Q_A

Expected operation

Q_C

FPGA Development Techniques 25

Q_B Q_C

Clock skewed version

Minimizing Clock Skew • Global Clock networks, using GCK pin and BUFG, distribute clocks with minimal skew • In the case of clocks on non-global routing, two constraints can help minimize skew: – NET “net_name” USELOWSKEWLINES ; – NET “net_name” MAXSKEW = 1 ns ;

• USELOWSKEWLINES will instruct the tools to use backbone local clock routing resources • MAXSKEW will try to balance the clock delay FPGA Development Techniques 26

Forwarding Clocks off-chip • When sending a clock off-chip, general purpose routing will be used, even if the clock is on BUFG • To properly constrain this path, use the following: – NET “net_name” MAXDELAY = 3 ns ;

• MAXDELAY can be used for any timing critical nets, not just clocks • The Virtex-II/-II Pro/-4 & Spartan-3 IOB with its integrated DDR register provides a very effective way to send clock(s) off-chip with very little skew FPGA Development Techniques 27

Timing Constraint Priority • Within a particular source: – Highest Priority

– Lowest Priority

FPGA Development Techniques 28

Tool Runtime Reduction Tips • Limit number of time constraints – –

Add PERIOD and OFFSET constraints through Xilinx Constraints Editor, instead of doing Advanced Analysis Consolidate similar timespecs to limit the number of time constraints • •

– – – –

Especially slow exceptions (TIG) Individual OFFSETs for every net with the same requirement

Be aware of duplicate constraints created by synthesis tools (.ncf files) Remove FROM:TO constraints between related clocks Use Global constraints, then grouped or net constraints Limit analysis of unconstrained paths

• Group related I/O pads together and place early on • Use higher placement effort, lower router effort FPGA Development Techniques 29

Outline • Static Timing Analysis – – – – – –

Introduction Review of Basic Constraints When to Use Advanced Constraints Handling Multiple Clock Domains Analyzing Design Results Demonstration of Constraints Editor & Timing Analyzer to Floorplanner Cross-Probing

• On-Chip Debugging • Power Estimation & Analysis FPGA Development Techniques 30

Constraining Between Multiple Clock Domains • By default, different clock domains are assumed to be unrelated (ie, no constraint applied between domains) • Define clock groups: – NET CLK_A TNM = A_GRP; – NET CLK_B TNM = B_GRP;

• Define timing constraints:

– TIMESPEC TS_CLKA = PERIOD A_GRP 20; – TIMESPEC TS_CLKB = PERIOD B_GRP TS_CLKA*2; – TIMESPEC TS_CLKA2B = FROM: A_GRP: TO: B_GRP: 20; D

CLK_A CLK_B

FPGA Development Techniques 31

Q

D

Q

D

Q D

Q

OUT1

Constraining Between Multiple Clock Domains • When generating clocks using a DLL or DCM, the phase & frequency relation will be determined automatically and handle the clock domain crossing • To constrain clocks which have a phase relation but which enter using separate pins, use the following constraints: TIMESPEC “TS01” = PERIOD “clk0” 10 ns; TIMESPEC “TS02” = PERIOD “clk180” TS01 PHASE + 5 ns;

FPGA Development Techniques 32

Outline • Static Timing Analysis – – – – – –

Introduction Review of Basic Constraints When to Use Advanced Constraints Handling Multiple Clock Domains Analyzing Design Results Demonstration of Constraints Editor & Timing Analyzer to Floorplanner Cross-Probing

• On-Chip Debugging • Power Estimation & Analysis FPGA Development Techniques 33

Analyzing Design Results • Place & Route Report lists all constraints and the obtained results: Timing Score: 90071 WARNING:Par:62 - Timing constraints have not been met. Asterisk (*) preceding a constraint indicates it was not met. -------------------------------------------------------------------------------Constraint | Requested | Actual | Logic | | | Levels -------------------------------------------------------------------------------* TS_clk = PERIOD TIMEGRP "clk" 6.450 nS | 6.450ns | 10.772ns | 7 HIGH 50.000000 % | | | -------------------------------------------------------------------------------1 constraint not met. All signals are completely routed. Total REAL time to par completion: 2 mins 44 secs Total CPU time to par completion: 2 mins 39 secs Placement: Completed - No errors found. Routing: Completed - No errors found. Timing: Completed - 52 errors found.

• For more detail on why a constraint wasn’t met, view the static timing analysis reports

Generating Timing Reports • Post-Map Static Timing

Report can be created after Map process • May be useful for checking logic only delays early in the design process

• Post-Place & Route Static

Timing Report created after Place & Route process • Best way to get timing information on fully implemented design

Post-Map Versus Post-Place & Route Static Timing Reports • The Post-Map Static Timing Report indicates whether or not your constraints are reasonable – Contains actual block delays and minimum net delays – What is “reasonable”? • If less than 50 percent of the timing budget is used for logic delays, the Place & Route tools should be able to meet the constraint easily • Between 50 - 80 percent, software runtime will increase • Greater than 80 percent, the tools may have trouble meeting your goals

• The Post-Place & Route Static Timing Report indicates whether or not your constraints were actually met – Contains actual block delays and actual net delays calculated from Place & Route FPGA Development Techniques 36

Viewing Timing Reports • Timing Reports are best viewed using the Timing Analyzer – Provides index into report greatly facilitating navigation – The Timing Analyzer can create custom reports for selected paths

• Note: Timing Reports can be created for designs without constraints – Advanced Analysis option (trce -a) – Useful for finding paths that may have not been constrained and obtaining their timing

Timing Report Example Clock Clock edge edge and and time time added added to to clock clock name name

Link Link to to “Timing “Timing Improvement Improvement Wizard” Wizard” (failing (failing paths paths only) only)

FPGA Development Techniques 38

Cross Cross probing probing to to Floorplanner Floorplanner and and synthesis synthesis RTL RTL and and Technology Technology views views

Timing Reports Contents • Command line options for the trce program • Timing Constraints section • Summary of each timing constraint • Details on paths that fail to meet constraints

• Data Sheet section • Setup/hold, clock to pad, timing between clock domains, and pad-to-pad delay information • Organized in easy-to-read table format

• Timing Summary section • Number of errors and Timing Score • Constraint coverage

Post-Place & Route Static Timing Report Properties • Report Type – Error (failing) or Verbose (all)

• Number of Items in Error/Verbose Timing Report • Analyze Skew for All Clocks – Only necessary for clocks routed on general routing as others are skew checked automatically

• Stamp Timing Model Filename • Timing Specification Interaction Report file

FPGA Development Techniques 40

ProActive Timing Closure Cross-Probing to the Xilinx Floorplanner

Link Linkfrom fromthe theXilinx Xilinxtiming timingreport reporttotothe theFloorplanner Floorplanner AAgraphical graphicalview viewprovides providespowerful powerfulinsights insightsfor fortiming timingdebug debugstrategies strategies

FPGA Development Techniques 41

Outline • Static Timing Analysis – – – – – –

Introduction Review of Basic Constraints When to Use Advanced Constraints Handling Multiple Clock Domains Analyzing Design Results Demonstration of Constraints Editor & Timing Analyzer to Floorplanner Cross-Probing

• On-Chip Debugging • Power Estimation & Analysis FPGA Development Techniques 42

Cross-Probing to Floorplanner Example

Click on Path OR Click on Net FPGA Development Techniques 43

Reference Material • The Answers Database: support.xilinx.com – latest information on advanced constaints: using the DCM with phase offset, DDR I/O, etc...

• The “Constraints Guide” – syntax and examples for PERIOD, OFFSET, MAXDELAY, etc…

• The “Development Systems Reference Guide” – command line options for par, trce, etc…

• On-line documentation: http://www.xilinx.com/support/sw_manuals/xilinx6/index.htm FPGA Development Techniques 44

Outline • Static Timing Analysis • On-Chip Debugging – – – –

Traditional Debugging Techniques Introduction to On-Chip Debugging On-Chip Debugging Features Demonstration of On-Chip Debugging

• Power Estimation & Analysis

FPGA Development Techniques 45

System Debug and Verification is Critical • Pressure of Time-to-Market deadlines • Design milestones need to be met • The debug phase is typically the largest variable in the development cycle

FPGA Development Techniques 46

Typical Board Debug Setup Download Cable Scope Probe

Logic Analyzer 40-Pin Pod

FPGA Development Techniques 47

FPGA Debug Issues • FPGAs are getting bigger and faster • Packages getting smaller with more pins, and pin pitches are smaller • Number of board layers is increasing • Test point headers are consuming valuable board space • Access to logic analyzers

FPGA Development Techniques 48

Existing Solution: FPGA Editor and Probe • • • • • •

Bring internal nodes out to a pin All nets available Use any available pin Additional routing delay is given No need to re-run Place and Route !!! Run Bitgen and download

FPGA Development Techniques 49

FPGA Editor and Probe

FPGA Development Techniques 50

The Need for On-Chip Debug • Traditional board level testing methods are not enough – Need internal access to signals, nodes and system buses • Integrated IP means wider, faster busses = more I/O pins dedicated to debug • No direct access to IP within the FPGA

– Difficult to drive high speed clocks and signals off chip without introducing new problems – High pin count, fine pitch packaging makes accessing pins nearly impossible FPGA Development Techniques 51

Outline • Static Timing Analysis • On-Chip Debugging – – – –

Traditional Debugging Techniques Introduction to On-Chip Debugging On-Chip Debugging Features Demonstration of On-Chip Debugging

• Power Estimation & Analysis

FPGA Development Techniques 52

The ChipScope Pro Solution Logic analysis core integrated in the FPGA – – – –

Software interface to monitor and analyze results Access to all internal design nodes Many flexible trigger options Operates at the full system speed synchronous to the design clock up to 350 MHz – Available for Virtex, Spartan-II and later FPGA families

FPGA Development Techniques 53

Debugging with Chipscope Pro JTAG Connections

USB port

-or-

Serial Port

Simple ! FPGA Development Techniques 54

The ChipScope Pro System • FPGA fabric provides full internal visibility

Pads IOIO Pads

ILA

ILA IBA Custom

IP Core

Logic

PPC405 Core

Custom ILA Core

Memory Array

ILA

ICON Boundary Scan TAP Controller

IO Pads

IO Pads

Embedded System Bus

– Access all the internal signals and nodes within the FPGA – Access system busses implemented in the FPGA

• Debug occurs at or near system speeds – Debug on-chip using the system clock

Target Connection

FPGA Development Techniques 55

• Minimize pins needed for debug – Access via the existing JTAG interface

ChipScope Pro Components • ChipScope Pro Soft Cores – – – – –

ICON – Integrated Control Core communication to BSCAN ILA – Integrated Logic Analysis Core ATC2 – ILA core with Agilent ATC2 support for off-chip data capture & pin reduction IBA – Integrated Bus Analysis Core for CoreConnect OPB and PLB VIO – Virtual Input Output cores for internal stimulus

• ChipScope Pro Software

– ChipScope Pro Core Generator – ChipScope Pro Core Inserter

• ChipScope Pro Analyzer

– Support for logic and bus analysis – Project-centric interface

• ChipScope Pro Communication

– Parallel Cable III and IV, MultiLINX, and Agilent FPGA Trace Port Analyzer via JTAG and Trace Port

• ChipScope Pro Device Support

– Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro & Virtex-4

FPGA Development Techniques 56

ChipScope Pro Analyzer • ChipScope Pro Logic and Bus Analysis Interface Makes Debug and Verification Easy – Multiple windows • Bus Plotting (Data vs. Time, Data vs. Data)

– Windows Capture Mode

• Enables User to Compare Data Captured After Multiple Trigger Events

– New Listing Viewer

• Import Bus Token Files and View Instructions As They Occurred

– Core Polling Disable

• Eliminate Conflicts with Software Debugger and Other JTAG Tools

– VIO Console

• Assign Inputs, Pulse Trains and View Signal Activity

– New Print Support

FPGA Development Techniques 57

Xilinx On-Chip Debugging Strategy Design with Debug and Verification in Mind •

Adopt an On-Chip Verification and Debug Strategy – Define the ChipScope Pro Cores Needed to Debug and Verify Design

•

Allocate Resources for ChipScope Pro Cores

•

Include Connectors in PCB Design

•

Define Target Connection Cable

– BlockRAM – Slice Logic – BSCAN USER1 or USER2

– JTAG – Optional High-Speed Trace Port – JTAG (PCIV or MultiLinx) – Agilent FPGA Dynamic Probing

FPGA Development Techniques 58

Outline • Static Timing Analysis • On-Chip Debugging – – – –

Traditional Debugging Techniques Introduction to On-Chip Debugging On-Chip Debugging Features Demonstration of On-Chip Debugging

• Power Estimation & Analysis

FPGA Development Techniques 59

ChipScope Pro ILA Core

• User Selectable 1 to 4 Trigger Ports – Up to 256 Channels Per Trigger Port – Multiple Match Units on Same Trigger Port • Up to 16 Match Units

• Trigger Condition Sequencer – Define Complex Trigger Sequences that Include up to 16 States or Levels

• Over 300Mhz performance

FPGA Development Techniques 60

ChipScope Pro IBA Cores • ChipScope IBA Pro Cores – IBA Core Supports CoreConnect OPB and PLB • Supports Both PPC and MicroBlaze OPB/PLB Buses

– Automatic Mapping of Bus Signals to Trigger/Data Ports – CoreConnect OPB Protocol Violation Detection

FPGA Development Techniques 61

ChipScope Pro VIO Core • ChipScope Pro VIO Core – Insert virtual pins into your design • Input or Output • Synchronous or Asynchronous – System Clock or JTAG clock

• Up to 256 bits each

– Inputs are Virtual LEDs • Different Refresh Rates Available

– Outputs are Virtual DIP Switches • Force Value or Pulse Train into FPGA

FPGA Development Techniques 62

ChipScope Pro Core Generator Adding ChipScope Pro Cores During Design Entry

• ChipScope Pro Core Generator – Specify ILA, ATC2, IBA and VIO Cores – Generate Synthesizable HDL to Add to Design HDL – Access any Signal or Node with the FPGA Under Test – Define Internal or External Memory Sample Storage Requirements

FPGA Development Techniques 63

ChipScope Pro ILA Core Generator Features

Define the number of Trigger Ports, Width and Number of Match Units Used

Expanded Bit Values and Functions Based on Match Type

Enable and Define Trigger Sequence

FPGA Development Techniques 64

ChipScope Pro IBA Core Generator Features • Target CoreConnect Processor Local Bus (PLB) or On-Chip Peripheral Bus (OPB) – Embedded PowerPC or Soft Core MicroBlaze

• Trigger Input/Output Logic – Detects PLB and OPB Bus Activity – Drive External Equipment or Additional Cores

• Optional OPB Protocol Bus Monitor – Detect 32 IBM CoreConnect OPB Protocol Violations

FPGA Development Techniques 65

ChipScope Pro Core Inserter • Insert ChipScope Pro ILA/ATC2 Cores – No changes to source code required, modifications are performed on postsynthesis netlist – Support All Available Trigger Options • Same Options as Core Generator

– Easy to Use Core Configuration • Trigger Options Tab • Capture Settings Tab • Net Connections Tab

– Easy to Remove ChipScope Pro Cores • Remove .CDC This File from Project – Available for HDL or EDIF Flows – Core Inserter doesn’t currently support for IBA or VIO Cores FPGA Development Techniques 66

ChipScope Pro Core Inserter Add ChipScope Pro Cores to an Existing Design

• ChipScope Pro Core Inserter

Set ChipScope Pro Core Parameters and Connections Via This Source

– Add ILA and ATC2 Cores to an Existing Design Netlist – ChipScope Pro and ISE Integration Inserter Called Automatically During Translate Stage

• ChipScope File (.CDC) Added to Project as a Source, Associated With the Top Level Design Source • User Double-Clicks .CDC to Set Parameters and Connections

– Versions of ISE and ChipScope Pro Must Match FPGA Development Techniques 67

Automatically Launch the ChipScope Pro Analyzer

ChipScope Pro Analyzer Features – Multiple windows – Bus Plotting • data vs. time • data vs. data – New listing viewer – More trigger options – Core polling disable • Eliminate conflicts with software debuggers or other tools using the JTAG chain

FPGA Development Techniques 68

Storage Qualification Improves On-Chip Data Storage • Define Boolean storage qualification conditions – Determine whether to capture and store individual data samples – Use trigger and storage qualification together • When to start and stop capture • To specify data to capture

• Reduces required storage while maintaining full visibility FPGA Development Techniques 69

VIO Console in Analyzer • VIO Console gives you control over Virtual I/O ports

View activity Assign internal inputs to FPGA

FPGA Development Techniques 70

ChipScope CLB Resource Utilization • Single basic ILA with ICON core for Virtex / -E or Spartan-II / -IIE: Trigger/Data Percentage Flops LUTs Slices Width of XCV1000

FPGA Development Techniques 71

2 4

125 128

143 151

72 76

0.58 % 0.62 %

8

134

167

84

0.68 %

16 32

146

199

100

0.81 %

173

265

133

1.08 %

64

222

395

198

1.61 %

ChipScope Block RAM Resource Utilization • Single basic ILA with ICON core for Virtex / -E or Spartan-II / -IIE Trigger/Data 256 512 1024 2048 4096 Width samples samples samples samples samples 2 4

1 unit 1 unit

1 unit 1 unit

1 unit 1 unit

1 unit 2 units

2 units 4 units

8

1 unit

1 unit

2 units

4 units

8 units

16 32

1 unit

2 units

4 units

8 units

16 units

2 units

4 units

8 units

16 units

32 units

64

4 units

8 units

16 units

32 units

64 units

• Spartan-3 & Virtex-II / -II Pro / -4 BRAMs are four times larger FPGA Development Techniques 72

Integration with FPGA Editor • Change data and/or trigger nets connected to ILA... ...without re-running PAR !

Insert ILA and ICON into synthesized design Connect Clock, Control and Data Points to Cores Place and Route Design Download Design

Change Data Capture Points With FPGA Editor Run BitGen

Set Triggers Run ILA Chipscope

FPGA Development Techniques 73

ILA in FPGA Editor

Select new net to analyze

FPGA Development Techniques 74

FPGA Dynamic Probe Measures new groups of internal FPGA signals in seconds without: – Recompiling the design – Impacting the timing of the design Save 15 min to 10 hours per new measurement

Achieves wider internal visibility over a fixed number of pins – 64 internal probe points for every pin conserves FPGA resources Save 8 hours per problem by not having to create a testbench

Eliminates error prone & time consuming tasks – Automates signal/bus labeling from FPGA design to logic analyzer – Maps FPGA pins from board layout to logic analysis channels Save 2 to 30 minutes per new measurement FPGA Development Techniques 75

Agilent FPGA Dynamic Probe FPGA Dynamic Probe SW application supported by 1680/1690/16900 Probe MUX outputs of ATC2 core and PCB Signals

Xilinx JTAG Cable

PC Board FPGA

Works with Xilinx Virtex-4, Spartan-3, Virtex-II Pro and Virtex-II FPGAs FPGA Development Techniques 76

ATC2

Insert ATC2 core with ChipScope Pro

Dynamic control of ATC2 with your regular Xilinx Cable JTAG Header

Agilent Trace Core (ATC2) 2nd Generation Trace Core • 2, 4, 8, 16, or 32 input banks

4 - 128

Improved Signal Visibility

4 - 128

Output to FPGA pins for debug

Select

• • Using Usingoptional optional2X 2X TDM TDMininstate statemode mode each eachpin pin corresponds correspondstoto22 signalsper perbank bank signals

4 - 128

2X TDM

• Bank width determined by # of pins - each pin corresponds to 1 signal per bank

4 - 128 4 - 128

Selection MUX

• All banks have identical width (4 to 128 signals wide)

ATC2

JTAG Change input bank selection dynamically via JTAG

FPGA Development Techniques 77

Number

Maximum

of Debug

Internal

Pins

Signals 4

256

8

512

16

1024

32

2048

. . 128 .

8192

Outline • Static Timing Analysis • On-Chip Debugging – – – –

Traditional Debugging Techniques Introduction to On-Chip Debugging On-Chip Debugging Features Demonstration of On-Chip Debugging

• Power Estimation & Analysis

FPGA Development Techniques 78

ChipScope Demonstration Block Diagram *RAM address [17:0] Port 01

Rx_Data

UART Rx

FIFO 16 Byte

Port 00

Rx_status

KCPSM3

Tx_status PROMstatus

Program (BRAM)

[15:8]

Ain[15:0] [7:0]

PROMin[7:0]

[15:8]

RAM_Data

LBa

Bin[15:0] [7:0]

[17:16]

Port 12

[15:8]

Port 11

[7:0]

* Common to both RAM devices

RAM enables

Port 80

Port 04 BUTTONS [3:0]

CEa

Port 05

Port 14

*WE *OE CE UB LB CE UB LB

Port 03

SWITCHES [7:0] Port 02 LBb

IC10 IC11

8

LED [7:0] Port A0 Ports E0-E3

Port 60

Port 40 PROM Reader

16×8 Dual Port RAM

7-Segment Display

DIN

20-bit counter

decode

2 MSBs

D

ChipScope Probe Points FPGA Development Techniques 79

AN3 AN2 AN1 AN0

Data [15:0]

[7:0]

Ain[15:0]

PROMstatus

*OE [15:8]

Port C0

FIFO 16 Byte

IC10

16

PROMin[7:0]

dp,g,f,e,d,c,b,a A

OE CCLK

*OE [15:8]

UART Tx Tx_status

16

IC11 Data [15:0]

[7:0]

Bin[15:0]

Four-Character, 7-Segment Drive anode LED Display Details control Low to

Control an individual character

select character

• 8 control lines light a specific segment on LED • 4 anode control lines define which character responds FPGA Development Techniques 80

Outline • Static Timing Analysis • On-Chip Debugging • Power Estimation & Analysis – Initial Estimation – Post-Implementation Analysis

FPGA Development Techniques 81

Initial Power Estimation • Online Estimation Tool:

• Available at: http://www.xilinx.com/products/design_resources/design_tool/grouping/power_tools.htm FPGA Development Techniques 82

Initial Power Estimation Tool Features

• Provide Resource Estimates:

• Save & Reload Data if required:

FPGA Development Techniques 83

Outline • Static Timing Analysis • On-Chip Debugging • Power Estimation & Analysis – Initial Estimation – Post-Implementation Analysis

FPGA Development Techniques 84

Power Estimation with XPower • Integrated in ISE’s Project Navigator • Operates on post-PAR netlist (NCD file) • Generate stimuli manually or from timing simulation • New Design Wizard: – Load Design & Simulation Data Files FPGA Development Techniques 85

Power Estimation with XPower • Step 1: Set / Verify Voltage, Ambient temperature, and Airflow • Step 2: Set / Verify clock & input frequencies, and activity rates • Step 3: Set / Verify Capacitive Loads for the outputs • Step 4: Set / Verify DC loads for the outputs • Step 5: Set / Verify enable rate for the bi-directional IO

FPGA Development Techniques 86