Eastman Kodak Company

Technical Data

Kodak Digital Science KAC-0310 Image Sensor Features •

1/3” Color VGA Digital Image Sensor

•

640 x 480 pixel progressive/interlace scan

•

7.8µm pitch square pixels with patented pinned photodiode architecture

•

Bayer-RGB CFA with optional micro lenses

•

High sensitivity, quantum efficiency, and charge conversion efficiency

•

Low fixed pattern noise / Wide dynamic range

•

Antiblooming and continuous variable speed shutter

•

Single master clock operation

•

Digitally programmable via I C interface

•

Integrated on-chip timing/logic circuitry

•

CDS sample and hold for suppression of low frequency and correlated reset noise

•

Typical Key Specifications •

Image Size: 5.0mm x 3.7mm (1/3”)

•

Responsivity: 3.0 V/Lux-sec

•

Min Light: 5 Lux at 30FPS/F2 lens

•

Scan Modes: Progressive/Interlace

•

Shutter Modes: Continuous & Single

•

Readout Rate: 20 MSPS

27x linear programmable gain

•

Frame Rate: 0-60 frames per second

•

10-bit, pipelined algorithmic RSD ADC

•

System Dynamic Range: 50dB

•

User selectable digital output formats: • 8-bit companded data • 10-bit linear data

•

Programmable gain: -2.7dB to 27dB

•

ADC: 10-bit, RSD ADC (DNL +/-0.5 LSB, INL +/-1.0 LSB)

•

Automatic column offset correction

•

•

Pixel addressability to support ‘Window of Interest’ windowing, resolution, and sub-sampling

Power Dissipation: 215mW (dynamic) / 25mW (standby)

•

30fps full VGA at 10Mhz Master Clock Rate

•

Single 3.3V power supply

•

48 pin CLCC package

•

Dark reference pixels with automatic Frame Rate Clamp

•

Patented Electronic Shutter Operation

2

Eastman Kodak Company - Image Sensor Solutions For the most current information regarding this product: Web: www.kodak.com/go/ccd Phone: (716) 722-4385 Email: [email protected]

Rev C Page 1 of 56 04/18/00

Eastman Kodak Company

Technical Data

Kodak Digital Science KAC-0310 Image Sensor Pin Pin No. Name

Pin No.

Pin Name

Description 2

Pin Type

Power

1

ADC6

Output Bit 6=64 10 Weight

O

D

25 SCLK

I C Serial Clock Line

I/O

D

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 DVDD DVSS BLANK AVDD AVSS EXTRES Unused Unused AVDD AVSS CVREFM CVREFP CLRCB CLRCA AVDD AVSS MCLK

Output Bit 5=32 10 Weight Output Bit 4=16 10 Weight Output Bit 3=8 10 Weight Output Bit 2=4 10 Weight Output Bit 1=2 10 Weight Output Bit 0=1 10 Weight Digital Power Digital Ground Pixel Invalid Analog Power Analog Ground External Bias Resistor

O O O O O O P G O P G I

Analog Power Analog Ground ADC Bottom Bias Ref Capacitor ADC Top Bias Ref Capacitor Frame Rate Clamp Capacitor Frame Rate Clamp Capacitor Analog Power Analog Ground Master Clock = Pixel Rate

P G O O O O P G I

D D D D D D D D D A A A A A A A A A A A A A D

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

I 2 C Serial Data Line Power Down Standby Enable Sensor Initialize Dig Output Tri-State Enable Sensor Sync Signal Digital Power Post Chip Test Input 9 MSB Post Chip Test Input 8 Post Chip Test Input 7 Post Chip Test Input 6 Post Chip Test Input 5 Post Chip Test Input 4 Post Chip Test Input 3 Post Chip Test Input 2 Post Chip Test Input 1 Post Chip Test Input 0 LSB Digital Ground Pixel Sync Line Sync Start of Frame Sync Output Bit 9=512 10 W eight Output Bit 8=256 10 W eight Output Bit 7=128 10 W eight

I/O I I I I P I I I I I I I I I I G O O O O O O

D D D D D D D D D D D D D D D D D D D D D D D

DVDD

TEST_IN9

TEST_IN8

TEST_IN7

TEST_IN6

TEST_IN5

TEST_IN4

TEST_IN3

TEST_IN2

TEST_IN1

Note: pins 14,15,27,19-30,32-41 should be pulled down to ground when not in use.

42 41 40 39 38 37 36 35 34 33 32 31 HCLK VCLK

43

30

44

29

SYNC TS INIT

SOF

45

28

ADC9

46

27

STBY

ADC8

47

26

SDATA

ADC7

47

ADC6 ADC5

1 2

ADC4

3

ADC3

4

ADC2 ADC1

25

SCLK

24 23

MCLK AVSS

22

AVDD

21

CLRCA

5

20

CLRCB

6

19

CVREFP

Top View

CVREFM

AVSS

AVDD

Unused

Unused

EXTRES

AVSS

AVDD

9 10 11 12 13 14 15 16 17 18 DVSS

8

ADC0 DVDD

7

BLANK

VDD VSS Input Output Digital Analog

DVSS TEST_IN0

= = = = = =

SDATA STBY INIT TS SYNC DVDD TEST_IN9 TEST_IN8 TEST_IN7 TEST_IN6 TEST_IN5 TEST_IN4 TEST_IN3 TEST_IN2 TEST_IN1 TEST_IN0 DVSS HCLK VCLK SOF ADC9 ADC8 ADC7

Table 1: KAC-0310 Pin Definitions

Legend: P G I O D A

Pin Power Type

Description

Figure 1 : Pinout Diagram

Eastman Kodak Company - Image Sensor Solutions For the most current information regarding this product: Web: www.kodak.com/go/ccd Phone: (716) 722-4385 Email: [email protected]

Rev C Page 2 of 56 04/18/00

Eastman Kodak Company

Technical Data

Kodak Digital Science KAC-0310 Image Sensor

MCLK INIT STBY SYNC SCLK SDATA

Sensor Interface Block

640 x 480 pixels (704 x 512 total including dark and isolation)

I2C Serial Interface CDS

FRC

Column Offset

White Balance Gain

Global Gain

Global Offset

10 Bit ADC

Post ADC

ADC(9:0) HCLK VCLK SOF

Figure 2: Simplified Block Diagram

1

General Description

The KAC-0310 is a fully integrated, high performance CMOS image sensor with features such as integrated timing, control, and analog signal processing for digital imaging applications. The part provides designers a complete imaging solution with a monolithic image capture and processing engine thus making it a true “camera on a chip”. System benefits enable design of smaller, portable, low cost and low power systems. Thereby making the product suitable for a variety of consumer applications including still/full motion imaging, security/surveillance, and automotive among others. The imaging pixels are based on active CMOS pixels using pinned photodiodes that are realized using a patented Kodak and Motorola sub-micron ImageMOSTM technology. The frame rate is completely adjustable from 0 to 60 frames per second without adjusting the system clock. The sensor is run by supplying a single Master Clock. The sensor output is 8 or 10 digital bits depending on output mode selected. The image sensor comprises a 1/3” format pixel array with 640x480 (VGA) active elements. The image size is fully programmable to user defined windows of interest. The pixels are on a 7.8µm pitch. High sensitivity and low noise are a characteristic of the pinned photodiode architecture utilized in the pixels. Optional microlenses are available to further enhance the sensitivity. The sensor is available with Bayer patterned Color Filter Array (CFA) for color output or as a monochrome imager. Integrated timing and programming controls allow video (CFCM) or still (SFCM) image capture modes supporting progressive or interlace scan modes. Frame rates are programmable while keeping Master Clock frequency constant. User programmable row and column start/stop allow movable windowing down a 1x1 pixel window. The Window of Interest(WOI) can further be sub-sampled to reduce resolution while maintaining field of view. A high performance analog signal processing chain establishes a new benchmark for digital image capture. The sensor has an unprecedented level of integration. The analog video output of the pixel array is processed by an on-chip processing pipeline. Correlated Double Sampling (CDS) eliminates low frequency correlated noise. The Frame Rate Clamp (FRC) enables real time optical black level calibration and offset correction. Digitally Programmable Amplifiers (DPGAs) allow real time color gain correction for Auto White Balance (AWB) as well as global gain adjustment. Offset calibration can be performed on a per column basis and globally. This per-column offset correction can be auto-calibrated or user programmed to the on-chip SRAM. A 10-bit Redundant Signed Digit(RSD) ADC converts the analog data to a 10-bit digital word stream. The fully

Eastman Kodak Company - Image Sensor Solutions For the most current information regarding this product: Web: www.kodak.com/go/ccd Phone: (716) 722-4385 Email: [email protected]

Rev C Page 3 of 56 04/18/00

Eastman Kodak Company

Technical Data

Kodak Digital Science KAC-0310 Image Sensor differential analog signal processing pipeline serves to improve noise immunity, signal to noise ratio, and system dynamic range. A digital signal post-processing block includes programmable features for output data companding or other mapping. Data companding can be done by loading any one of eight hard coded compression curves which performs a 10 to 8 bit transformation on the data. The sensor uses an industry standard two line I2C serial interface. It operates with a single 3.3V power supply with no additional biases and requires only a single Master Clock for operation up to 20 MHz. It is housed in a 48 pin ceramic LCC package. The KAC-0310 is designed taking into consideration interfacing requirements to standard video encoders. In addition to the 10 bit Bayer encoded data stream, the sensor outputs the valid frame, line and pixel sync signals needed for encoding. The sensor interfaces with a variety of commercially available video image processors to allow encoding into various standard video formats. The KAC-0310 is an elegant and extremely flexible single chip solution that simplifies a system designer’s tasks of image sensing, processing, digital conversion, and digital signal processing to a high performance, low cost, low power IC. One that supports among others a wide range of low power portable consumer digital imaging applications.

Eastman Kodak Company - Image Sensor Solutions For the most current information regarding this product: Web: www.kodak.com/go/ccd Phone: (716) 722-4385 Email: [email protected]

Rev C Page 4 of 56 04/18/00

Eastman Kodak Company

Technical Data

Kodak Digital Science KAC-0310 Image Sensor 2

Specifications

Image Size: 5.0mm x 3.7mm (1/3”) Resolution: 640 x 480 pixels, available digital zoom and region of interest (ROI) windowing Pixel Size: 7.8µm x 7.8µm Monochrome Sensitivity: 3.0 V/Lux-sec Min. Detectable Light Level: 5 Lux at 30FPS/F2 lens Scan Modes: Progressive/Interlace Shutter Modes: Continuous (Video)/ Single (Still) Readout Rate: 20 MSPS Frame Rate: 0-60 frames per second Max Master Clock Frequency: 20 MHz System Dynamic Range: 50dB On Chip programmable gain: -2.7dB to 27dB On Chip Image Correction: Column offset calibration, data companding Analog to Digital Converter: 10-bit, RSD ADC (DNL +/-0.5 LSB, INL +/-1.0 LSB) Power Dissipation: 215mW (dynamic) / 25mW (standby) Package: 48 pin ceramic LCC Temperature Operating Range: 0
70 οC

Eastman Kodak Company - Image Sensor Solutions For the most current information regarding this product: Web: www.kodak.com/go/ccd Phone: (716) 722-4385 Email: [email protected]

Rev C Page 5 of 56 04/18/00

Eastman Kodak Company

Technical Data

Kodak Digital Science KAC-0310 Image Sensor Table Of Contents 1 2 3

General Description............................................................................................................................................................. 3 Specifications ...................................................................................................................................................................... 5 KAC-0310 Theory of Operation ....................................................................................................................................... 10 3.1 Sensor Interface......................................................................................................................................................... 10 3.1.1 Pixel Architecture.............................................................................................................................................. 10 3.1.2 Color Separation and Fill Factor Enhancement ................................................................................................. 11 3.1.3 Frame Capture Modes ....................................................................................................................................... 12 3.1.4 Image Scan Modes ............................................................................................................................................ 12 3.1.5 Window of Interest Control............................................................................................................................... 12 3.1.6 WOI Sub-Sampling Control(Resolution) .......................................................................................................... 13 3.1.7 CFCM Virtual Frame ........................................................................................................................................ 13 3.1.8 CFCM Frame Rate ............................................................................................................................................ 14 3.1.9 SFCM Integration Time Control ....................................................................................................................... 14 3.2 Analog Signal Processing Chain Overview............................................................................................................... 15 3.2.1 Frame Rate Clamp (FRC).................................................................................................................................. 15 3.2.2 Per-Column Digital Offset Voltage Adjust (DOVA)......................................................................................... 16 3.2.3 Digitally Programmable Gain Amplifiers (DPGA) ........................................................................................... 16 3.2.3.1 White Balance Control PGA ......................................................................................................................... 16 3.2.3.2 Global Gain PGA .......................................................................................................................................... 17 3.2.4 Global Digital Offset Voltage Adjust (DOVA) ................................................................................................. 17 3.2.5 Analog to Digital Converter (ADC) .................................................................................................................. 17 3.3 Digital Signal Post Processing Data Compander....................................................................................................... 17 3.4 Additional Operational Conditions............................................................................................................................ 18 3.4.1 Initialization ...................................................................................................................................................... 18 3.4.2 Standby Mode ................................................................................................................................................... 18 3.4.3 References CVREFP, CVREFM ....................................................................................................................... 18 3.4.4 Internal Timing Control Register....................................................................................................................... 18 3.4.5 Internal Bias Current Control ............................................................................................................................ 18 4 KAC-0310 Waveform Diagrams....................................................................................................................................... 19 4.1 CFCM Data Waveforms............................................................................................................................................ 19 4.2 SFCM Data Waveforms ............................................................................................................................................ 21 5 KAC-0310 Register Reference Map.................................................................................................................................. 22 6 Detailed Register Block Assignments ............................................................................................................................... 25 6.1 Color Gain Registers 00h
03h ................................................................................................................................ 25 6.2 Color Tile Register (05h
09h) ................................................................................................................................ 27 6.3 Reference Voltage Adjust Registers (0Ah, 0Bh) ........................................................................................................ 29 6.4 Power Configuration Registers (0Ch) ........................................................................................................................ 30 6.5 Reset Control Register (0Eh) ..................................................................................................................................... 31 6.6 Global Gain Register (10h) ........................................................................................................................................ 32 6.7 Column DOVA DC Register (20h) ............................................................................................................................ 32 6.8 Column DOVA Control (21h).................................................................................................................................... 33 6.9 Column DOVA RAM (22h)....................................................................................................................................... 34 6.10 Global DOVA (23h) .................................................................................................................................................. 35 6.11 Post ADC Control (32h) ............................................................................................................................................ 36 6.12 Capture Mode Control (40h)...................................................................................................................................... 37 6.13 Sub-sample Control (41h) .......................................................................................................................................... 38

Eastman Kodak Company - Image Sensor Solutions For the most current information regarding this product: Web: www.kodak.com/go/ccd Phone: (716) 722-4385 Email: [email protected]

Rev C Page 6 of 56 04/18/00

Eastman Kodak Company

Technical Data

Kodak Digital Science KAC-0310 Image Sensor 6.14 Programmable Window of Interest (WOI) (45h-4Ch) ................................................................................................ 39 6.15 Integration Time Control (4Dh
4Fh)...................................................................................................................... 42 6.16 Programmable Virtual Frame (50h
53h) ................................................................................................................ 43 6.17 SOF Control Register (54h) ....................................................................................................................................... 45 6.18 VCLK Control Register (55h).................................................................................................................................... 45 7 I2C Serial Interface ............................................................................................................................................................ 46 7.1 KAC-0310 I2C Bus Protocol ..................................................................................................................................... 46 7.2 START Signal ........................................................................................................................................................... 47 7.3 Slave Address Transmission...................................................................................................................................... 47 7.4 Acknowledgment....................................................................................................................................................... 47 7.5 Data Transfer............................................................................................................................................................. 47 7.6 Stop Signal ................................................................................................................................................................ 47 7.7 Repeated START Signal ........................................................................................................................................... 48 7.8 I2C Bus Clocking and Synchronization ..................................................................................................................... 48 7.9 Register Write ........................................................................................................................................................... 48 7.10 Register Read ............................................................................................................................................................ 48 8 Electrical Characteristics................................................................................................................................................... 50

Table Of Figures Figure 1 : Pinout Diagram ........................................................................................................................................................... 2 Figure 2: Simplified Block Diagram ........................................................................................................................................... 3 Figure 3: KAC-0310 Detailed Block Diagram............................................................................................................................ 9 Figure 4: KAC-0310 Spectral Response ................................................................................................................................... 11 Figure 5: Optional Bayer Pattern CFA...................................................................................................................................... 11 Figure 6: Increase of sensitivity due to microlensles................................................................................................................. 12 Figure 7: WOI Definition .......................................................................................................................................................... 13 Figure 8: Bayer ½ x ½ Sub-sample Example. Sub-sample Control Register(41h) = x01x0101b .............................................. 13 Figure 9: Virtual Frame Definition............................................................................................................................................ 14 Figure 10: Conceptual block diagram of CDS .......................................................................................................................... 15 Figure 11: FRC Conceptual Block Diagram ............................................................................................................................. 15 Figure 12: Color Gain Register Selection.................................................................................................................................. 16 Figure 13: Available Companding Curves ................................................................................................................................ 17 Figure 14: Power Consumption dependence on External Resistor............................................................................................ 18 Figure 15: CFCM Default Frame Sync Waveforms .................................................................................................................. 19 Figure 16: CFCM Default Row Syncs Waveforms ................................................................................................................... 19 Figure 17: CFCM Single Frame Mode Sync Waveforms.......................................................................................................... 20 Figure 18: CFCM Interlaced Scan Mode Sync Waveforms ...................................................................................................... 20 Figure 19: Frame View of CFCM Sync Waveforms ................................................................................................................. 21 Figure 20: One row view of SFCM Sync Waveforms............................................................................................................... 21 Figure 21: I2C Bus WRITE Cycle ............................................................................................................................................. 46 Figure 22: I2C Bus READ Cycle............................................................................................................................................... 49

Eastman Kodak Company - Image Sensor Solutions For the most current information regarding this product: Web: www.kodak.com/go/ccd Phone: (716) 722-4385 Email: [email protected]

Rev C Page 7 of 56 04/18/00

Eastman Kodak Company

Technical Data

Kodak Digital Science KAC-0310 Image Sensor List Of Tables Table 1: KAC-0310 Pin Definitions............................................................................................................................................ 2 Table 2: I2C Address Ranges..................................................................................................................................................... 22 Table 3: I2C Address Assignments (0h- 3Fh) ............................................................................................................................. 23 Table 4: I2C Address Assignments (40h - FFh) .......................................................................................................................... 24 Table 5: DPGA Color 1 Gain Register (00h)............................................................................................................................. 25 Table 6: DPGA Color 2 Gain Register (01h)............................................................................................................................. 25 Table 7: DPGA Color 3 Gain Register (02h)............................................................................................................................. 26 Table 8: DPGA Color 4 Gain Register (03h)............................................................................................................................. 26 Table 9: Color Tile Register (05h)............................................................................................................................................. 27 Table 10: Color Tile Row 1 Definition Register (06h) .............................................................................................................. 27 Table 11: Color Tile Row 2 Definition Register (07h) .............................................................................................................. 28 Table 12: Color Tile Row 3 Definition Register (08h) .............................................................................................................. 28 Table 13: Color Tile Row 4 Definition Register (09h) .............................................................................................................. 28 Table 14: Negative Voltage Reference Register (0Ah).............................................................................................................. 29 Table 15: Positive Voltage Reference Register (0Bh) ............................................................................................................... 29 Table 16: Power Configuration Register (0Ch) ......................................................................................................................... 30 Table 17: Reset Control Register (0Eh) ..................................................................................................................................... 31 Table 18: DPGA Global Gain Register (10h) ............................................................................................................................ 32 Table 19: Column DOVA DC Offset (20h) ............................................................................................................................... 32 Table 20: Column DOVA Control (21h) ................................................................................................................................... 33 Table 21: Column DOVA RAM (22h) ...................................................................................................................................... 34 Table 22: Global DOVA Register (23h) .................................................................................................................................... 35 Table 23: Post ADC Control Register (32h) .............................................................................................................................. 36 Table 24: Capture Mode Register (40h) .................................................................................................................................... 37 Table 25: Sub-Sample Control Register (41h)........................................................................................................................... 38 Table 26: WOI Row Pointer MSB Register (45h) ..................................................................................................................... 39 Table 27: WOI Row Pointer LSB Register (46h) ...................................................................................................................... 39 Table 28: WOI Column Pointer MSB Register (49h)................................................................................................................ 39 Table 29: WOI Column Pointer LSB Register (4Ah) ................................................................................................................ 40 Table 30: WOI Row Depth MSB Register (47h)....................................................................................................................... 40 Table 31: WOI Row Depth LSB Register (48h) ........................................................................................................................ 40 Table 32: WOI Column Depth MSB Register (4Bh) ................................................................................................................. 41 Table 33: WOI Column Depth LSB Register (4Ch) .................................................................................................................. 41 Table 34: Integration Time MSB Register (4Dh) ...................................................................................................................... 42 Table 35: Integration Time ISB Register (4Eh) ......................................................................................................................... 42 Table 36: Integration Time LSB Register (4Fh) ........................................................................................................................ 42 Table 37: SFCM Virtual Frame Row Depth MSB (50h) ........................................................................................................... 43 Table 38: SFCM Virtual Frame Row Depth LSB (51h) ............................................................................................................ 43 Table 39: Virtual Frame Column Width MSB (52h) ................................................................................................................. 44 Table 40: Virtual Frame Column Width LSB (53h) .................................................................................................................. 44 Table 41: SOF Control Register (54h)....................................................................................................................................... 45 Table 42: VCLK Control Register (55h) ................................................................................................................................... 45

Eastman Kodak Company - Image Sensor Solutions For the most current information regarding this product: Web: www.kodak.com/go/ccd Phone: (716) 722-4385 Email: [email protected]

Rev C Page 8 of 56 04/18/00

Eastman Kodak Company

Technical Data

DVSS

TEST_IN_0

TEST_IN_1

TEST_IN_2

TEST_IN_3

TEST_IN_4

TEST_IN_5

TEST_IN_6

TEST_IN_7

TEST_IN_8

TEST_IN_9

Kodak Digital Science KAC-0310 Image Sensor

DVDD1

42

41

40

39

38

37

36

35

34

33

32

31

704

30

2 1

VGA CMOS Image Sensor Array

512

10

SYNC

8Dark + 8Isolation

45

BLANK

480

44

SOF

40Dark + 8Isolation

43

VCLK

Row Decoder and Drivers

HCLK

Master Row Sequencer, Integration Control, and Timing Generator

4Dark + 8Isolation

640

12Dark + 8Isolation 1 2

Column Sequencer & Drivers

29 TS

Column Decode, Sensing, and Muxing

28 INIT 27 STDBY

Color Sequencer Analog Switch 6

6

6

26 SDATA

I2C Serial Interface

25 SCLK

24 MCLK

6

I2C Register Decode

Column Offset Calibration

23 AVSS1 22 AVDD1

6

Frame Rate Clamp

6

6

Column DOVA

1.0x 0dB

6

WB PGA 0.9 - 4.8x

Global PGA 1.0 - 8.9x

-0.8 - 13.6 dB

0 - 19 dB

Global Dova

10 Bit RSD Pipelined ADC

1.0x 0dB

10

CLRCB 21

Post ADC Processing

CLRCA 20

CVREFM 18

ADC0

6

ADC1

5

ADC2

4

ADC3

3

ADC4

2

ADC5

1

ADC6

48 ADC7 47 ADC8 46 ADC9

Vrefp

Bandgap Reference and Bias Generation

CVREFP 19

Test Monitor Logic

7

Vrefm

Analog Circuits

Vcm Ibias

Digital Logic

10

8

9

11

12

13

16

17

DVDD2

DVSS2

AVDD4

AVSS3

EXTRES

AVDD2

AVSS2

Figure 3: KAC-0310 Detailed Block Diagram

Eastman Kodak Company - Image Sensor Solutions For the most current information regarding this product: Web: www.kodak.com/go/ccd Phone: (716) 722-4385 Email: [email protected]

Rev C Page 9 of 56 04/18/00

Eastman Kodak Company

Technical Data

Kodak Digital Science KAC-0310 Image Sensor 3

KAC-0310 Theory of Operation

This section reviews the concepts behind the operation of the image sensing and capture mechanisms employed in the KAC0310.

3.1 Sensor Interface 3.1.1 Pixel Architecture

The KAC-0310 ImageMOS TM1 sensor comprises a 640x480 active pixel array and supports both progressive and interlaced scan readout modes. The basic operation of the pixel relies on the photoelectric effect where, due to its physical properties, silicon is able to detect photons of light. The photons generate electron-hole pairs in direct proportion to the intensity and wavelength of the incident illumination. The application of an appropriate bias allows the user to collect the electrons and meter the charge in the form of a useful parameter such as voltage. 2

The pixel architecture is based on a four transistor (4T) Advanced CMOS Imager TM pixel which requires all pixels in a row to have common Reset, Transfer, and Row Select controls. In addition all pixels have common supply (VDD ) and ground (VSS ) connections. An optimized cell architecture provides enhancements such as noise reduction, fill factor maximization, and anti-blooming. The use of pinned photodiodes3 and proprietary transfer gate devices in the photoelements enables enhanced sensitivity in the entire visual spectral range and a low lag operation. The nominal photoresponse of the KAC-0310 is shown in Figure 3. In addition to the imaging pixels, there are additional pixels called dark and dummy pixels at the periphery of the imaging section (see Figure 2). The dark pixels are covered by a light blocking shield rendering the pixels underneath insensitive to photons. These pixels provide the sensor means to measure the dark level offset which is used downstream in the signal processing chain to perform auto black level calibration. The dummy pixels are provided at the array’s periphery to eliminate inexact measurements due to light piping into the dark pixels adjacent to active pixels and for extra pixels needed for some color interpolation algorithms. Electronic shuttering, also known as electronic exposure timing in photographic terms, is a standard feature. The pixel integration time can be widely varied from a small fraction of a given frame readout time to the entire frame time. This feature can be especially useful in situations such as imaging of fast moving objects where normal integration times cause smear, blurring, or image tear.

1

ImageMOS is a Motorola trademark Advanced CMOS Imager is a Kodak trademark 3 Patents held jointly by Kodak and Motorola 2

Eastman Kodak Company - Image Sensor Solutions For the most current information regarding this product: Web: www.kodak.com/go/ccd Phone: (716) 722-4385 Email: [email protected]

Rev C Page 10 of 56 04/18/00

Eastman Kodak Company

Technical Data

Kodak Digital Science KAC-0310 Image Sensor KAC-0310 Spectral Response Bayer No lenslets 25 Monochrome

Absolute Quantum Efficiency (%)

20

15 Green1 Green2 Red

10

Blue 5

0 400

450

500

550

600

650

700

750

Wavelength (nm)

Figure 4: KAC-0310 Spectral Response

3.1.2

Color Separation and Fill Factor Enhancement

The KAC-0310 family is offered with the option of monolithic polymer color filter arrays (CFAs). The combination of an extremely planarized process and proprietary color filter technology results in CFAs with superior spectral and transmission properties. The standard option (Part # KAC-0310C-x-A) is a primary (RGB) “Bayer” pattern (see Figure 5), however, facility to produce customized CFAs including complementary (CMYG) mosaics also exists. Depending on the application, the choice between primary or complementary filter mosaics should be made. In general, primary mosaics are used in still video while complementary are used in real time video applications.

G1

R

G1

R

B

G2

B

G2

G1

R

G1

R

B

G2

B

G2

Figure 5: Optional Bayer Pattern CFA Applications requiring higher sensitivity can benefit from the optional microlens arrays shown in Figure 6. The lenslet arrays can improve the fill factor (aperture ratio) of the sensor by approximately 1.5x depending on the Fnumber of the main lens used in the camera system. Microlenses yield greatest benefits when the main lens has a high F-number. As a caution, unoptimized F-numbers can

Eastman Kodak Company - Image Sensor Solutions For the most current information regarding this product: Web: www.kodak.com/go/ccd Phone: (716) 722-4385 Email: [email protected]

Rev C Page 11 of 56 04/18/00

Eastman Kodak Company

Technical Data

Kodak Digital Science KAC-0310 Image Sensor lead to optical aberrations hence; care should be taken when incorporating microlens equipped imagers into camera systems/heads. The fill factor of the pixels without microlenses is ~35%.

Incident Light

when the ambient lighting will not cause the pixels to saturate during the readout time. The Capture Mode is controlled by the Capture Mode Register, (Table 24), on page 37.

3.1.4 Microlenses

Active Photodiode Area Figure 6: Increase of sensitivity due to microlensles

3.1.3

Frame Capture Modes

Depending on the application the user may choose between the two available Frame Capture Modes (FCMs). The default mode of image capture is the Continuous Frame Capture Mode (CFCM). This mode is most suitable for full motion video capture and will yield VGA sized frame rates up to 60fps at 20 MHz MCLK. In this mode the image integration and row readout take place in parallel. While a row of pixels is being integrated, another row is being readout. Since the integration time (Tint) must be equal for all rows, the start of integration for rows is staggered. The net effect is very similar to an SLR shutter in a film camera. As in any SLR camera system, long integration times can cause blur for fast moving objects. And short integration times cause image tear where the moving object’s horizontal image is distorted at the bottom of the image relative to the top of the image. Rapidly varying illumination (ex. Flickering lights) can also cause distortion of the image. For these cases special consideration must be applied to the capture sequence or SFCM can be used. The second available capture mode is called Single Frame Capture Mode (SFCM). This mode consists of global integration of all pixels, next a simultaneous transfer to the Floating Diffusion (FD) node of all pixels followed by a sequential read out of all rows. This mode is best suited for still or “single snap shot” capture of an image where a flash illumination is utilized. SFCM should only be used

Image Scan Modes

The KAC-0310 has two available image scanning modes: interlaced and progressive. Interlacing is a technique used in TV systems that is used to enhance the vertical resolution of the picture without increasing the bandwidth of the transmission system. A spatial offset is introduced on the display system between the odd and even fields. An odd field consists of rows 1,3,5,7,9.... while an even field comprises rows 2,4,6,8..... Since the spatial offset is exactly half the vertical pitch of the sensor, the even and odd fields appear interdigitated when displayed on top of one another, thus appearing to improve the sensor’s vertical resolution. By definition two interlaced fields comprise a frame. It should be noted that at high frame rates, motion between fields in interlaced video can cause smear and/or serrations to appear in the image. Progressive scanning refers to non-interlaced or sequential row by row scanning of the entire sensor in a single pass. The image capture happens at one instant of time. This mode is primarily used in applications where vertical resolution is of prime importance and available bandwidth of the transmission system does not impose any limitations. The scan mode is controlled via the Sub-Sample Control Register, (Table 25), on page 38.

3.1.5

Window of Interest Control

The pixel data to be read out of the device is defined as a ‘Window of Interest’ (WOI). The window of interest can be defined anywhere on the pixel array at any size. The user provides the upper-left pixel location and the size in both rows and columns to define the WOI. The WOI is defined using the WOI Pointer, WOI Depth, and WOI Width registers, (Table 26 on page 39 through Table 33 on page 41). Please refer to Figure 7 for a pictorial representation of the WOI within the active pixel array.

Eastman Kodak Company - Image Sensor Solutions For the most current information regarding this product: Web: www.kodak.com/go/ccd Phone: (716) 722-4385 Email: [email protected]

Rev C Page 12 of 56 04/18/00

Eastman Kodak Company

Technical Data

Kodak Digital Science KAC-0310 Image Sensor

0

ACTIVE PIXEL ARRAY WOI Pointer (wcp,wrp)

Window of Interest (WOI)

WOI Row Depth (wrd)

0

703

WOI Column Depth (wcd)

511

Figure 7: WOI Definition

G

R

G

R

G

R

G

R

G

R

G

R

B

G

B

G

B

G

B

G

B

G

B

G

G

R

G

R

G

R

G

R

G

R

G

R

B

G

B

G

B

G

B

G

B

G

B

G

G

R

G

R

G

R

G

R

G

R

G

R

B

G

B

G

B

G

B

G

B

G

B

G

G

R

G

R

G

R

G

R

G

R

G

R

B

G

B

G

B

G

B

G

B

G

B

G

G

R

G

R

G

R

G

R

G

R

G

R

B

G

B

G

B

G

B

G

B

G

B

G

G

R

G

R

G

R

G

R

G

R

G

R

B

G

B

G

B

G

B

G

B

G

B

G

Figure 8: Bayer ½ x ½ Sub-sample Example. Subsample Control Register(41h) = x01x0101b

3.1.6

WOI Sub-Sampling Control(Resolution)

The WOI can be sub-sampled in either monochrome or Bayer pixel space in four different sampling rates in each direction: full, ½, ¼, or 1/8. Sub-sampling the imager by 1 /8 in both horizontal and vertical directions results in only 1 /16 of the pixel being readout. The frame readout rate is therefore increased by 16x. The user controls the subsampling via the Sub-sample Control Register, (Table 25), on page 38. An example of Bayer space sub-sampling is shown in Figure 8.

3.1.7

CFCM Virtual Frame

Changing the WOI does not change the frame rate of the imager. The user has the ability to control the frame rates while operating in CFCM. This is done by varying the size of a Virtual Frame surrounding the WOI. Refer to Figure 9 for a pictorial description of the Virtual Frame and its relationship to the WOI. The virtual frame can be shrunk to the size of the WOI. If the virtual Frame is greater than the WOI then the readout is padded with invalid dark pixels. The WOI and the virtual frame may both be larger than the actual imager size. In this case the WOI is also padded with invalid dark pixels. Figure 9 illustrates a WOI larger than the Virtual Frame. The Virtual frame is always larger than the WOI. If you attempt to set the WOI larger than the virtual window then the Virtual frame is automatically grown to fit the WOI. Similarly the WOI is auto-shrunk if the virtual frame is set smaller than the WOI.

Eastman Kodak Company - Image Sensor Solutions For the most current information regarding this product: Web: www.kodak.com/go/ccd Phone: (716) 722-4385 Email: [email protected]

Rev C Page 13 of 56 04/18/00

Eastman Kodak Company

Technical Data

Kodak Digital Science KAC-0310 Image Sensor 0

vcw[13:0]

WOI Pointer (wcp,wrp)

Window of Interest (WOI)

WOI Row Depth (wrd)

0

WOI Column Depth (wcd)

Virtual Frame

Tfc is the minimum amount of time required to perform a frame clamp with timing overhead and is defined as: Tfc = (719 + shsd + shrd + 19) * MCLK period The Integration Time for CFCM is defined by a combination of the width of the WOI and the integration time register, (Table 35 on page 42 and Table 36 on page 42); and can be expressed as: Integration Time = (cintd + 1) * Trow

vrd[13:0]

Figure 9: Virtual Frame Definition

3.1.8

CFCM Frame Rate

The frame rate (time required to readout an entire frame of data plus the required boundary timing) is completely defined by the size of the Virtual Frame and can be expressed as: Frame Time = vrdd* Trow + Tfc for T row < T lim Frame Time = (vrdd + 1) * Trow for T row > T lim where vrdd defines the number of rows in the virtual frame. The user controls vrdd via the CFCM Virtual Frame Row Depth registers (Table 37on page 43 and Table 38 on page 43). Row Time (T row ) is the length of time required to read one row of the virtual frame and can be defined as: Trow = (vcwd + shsd + shrd + 19) * MCLK period where vcwd defines the number of columns in the virtual frame and shsd and shrd are internal timing control registers. The user controls vcwd via the CFCM Virtual Frame Column Width registers (Table 39 on page 44 and Table 40 on page 44). The user controls the shsd and shrd values via the Internal Timing Control Register; Table 28 and is strongly encouraged to write an 00h to this register. Tlim is the minimum amount of time required for the internally generated frame clamp signal and is defined as:

where cintd is the number of virtual frame row times desired for integration time. Therefore, the integration time in CFCM mode can be adjusted in steps of virtual frame row times. This equation for Integration Time is valid only for Trow > (Tlim * MCLK period ). For virtual frames where Trow < (Tlim * MCLK period ), the integration time is different for the first cintd rows and is defined as: Integration Time cintdrows = Tfc + (cintd * Trow) By using the default values in the Virtual Frame definition and Integration Time registers, an FFh loaded into the Internal Timing Control Register, and assuming a standard video square pixel clock rate of 12.27Mhz, we can calculate the frame rate and integration time as: Row Time = (749 + 16 + 16 + 19) / 12.27e6 = 65.2 µs Frame Time = (524 + 1) * 65.2 µs = 34.23ms which results in a Frame Rate of 29.21 frames per second. Integration Time = (524 + 1) * 65.2 µs = 34.23ms. Sum the above off with references back to the actual registers.

3.1.9

SFCM Integration Time Control

The Integration Time for the SFCM is defined by the integration time register (Table 34 on page 42 through Table 36 on page 42) and can be expressed as:

Tlim = 719 * MCLK period

Eastman Kodak Company - Image Sensor Solutions For the most current information regarding this product: Web: www.kodak.com/go/ccd Phone: (716) 722-4385 Email: [email protected]

Rev C Page 14 of 56 04/18/00

Eastman Kodak Company

Technical Data

Kodak Digital Science KAC-0310 Image Sensor Integration Time = sintd * 16 * MCLK period where sintd is a number. Therefore, the user can adjust integration time in steps of 16 MCLK periods.

3.2

Analog Signal Processing Chain Overview

The KAC-0310’s analog signal processing (ASP) chain incorporates Correlated Double Sampling (CDS), Frame Rate Clamp (FRC), two Digitally Programmable Gain Amplifiers (DPGA), Offset Correction (DOVA), and a 10-bit Analog to Digital Converter (ADC). 2.2.1 Correlated Double Sampling (CDS) The uncertainty associated with the reset action of a capacitive node results in a reset noise which is proportional to kTC; ‘C’ being the capacitance of the node, ‘T’ the temperature, and ‘k’ the Boltzmann constant. A common way of eliminating this noise source in all image sensors is to use Correlated Double Sampling. The output signal is sampled twice, once for its reset (reference) level and once for the actual video signal. These values are sampled and held while a difference amplifier subtracts the reference level from the signal output. Double sampling of the signal eliminates correlated noise sources.

frame. The KAC-0310 uses optical black (dark) pixels to aid in establishing this reference. On the KAC-0310, dark pixel input signals should be sampled for a minimum of 137µs to allow the two 0.1µF capacitors at the CLRCA and CLRCB pins sufficient time to charge for 10-bit accuracy. This guarantees that the FRC’s “droop” will be maintained at