Differences between STMP3700 and STMP3780 registers Amaury Pouly January 6, 2012

Contents 1

Summary of differences

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AHB-to-APBH Bridge with DMA 2.1 Summary . . . . . . . . . . . . 2.2 Programmable Registers . . . . 2.2.1 HW_APBH_CTRL0 . . 2.2.2 HW_APBH_CTRL1 . . 2.2.3 HW_APBH_CTRL2 . . 2.2.4 HW_APBH_DEVSEL . 2.2.5 HW_APBH_VERSION

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18 18 19 19 19 19 20 20

AHB-to-APBX Bridge with DMA 3.1 Summary . . . . . . . . . . . . . . . . 3.2 Programmable Registers . . . . . . . . 3.2.1 HW_APBX_CTRL0 . . . . . . 3.2.2 HW_APBX_CTRL1 . . . . . . 3.2.3 HW_APBX_CTRL2 . . . . . . 3.2.4 HW_APBX_CHANNEL_CTRL 3.2.5 HW_APBX_DEVSEL . . . . . 3.2.6 HW_APBX_VERSION . . . .

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20 20 21 21 21 22 22 23 23

AUDIOIN/ADC 4.1 Summary . . . . . . . . . . . . . . . . . 4.2 Programmable Registers . . . . . . . . . 4.2.1 HW_AUDIOIN_CTRL . . . . . . 4.2.2 HW_AUDIOIN_STAT . . . . . . 4.2.3 HW_AUDIOIN_ADCSRR . . . . 4.2.4 HW_AUDIOIN_ADCVOLUME . 4.2.5 HW_AUDIOIN_ADCDEBUG . . 4.2.6 HW_AUDIOIN_ADCVOL . . . 4.2.7 HW_AUDIOIN_MICLINE . . . 4.2.8 HW_AUDIOIN_ANACLKCTRL 4.2.9 HW_AUDIOIN_DATA . . . . . .

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23 23 24 24 24 25 25 26 26 27 27 28

AUDIOOUT/DAC 5.1 Summary . . . . . . . . . . . . . . . . . . 5.2 Programmable Registers . . . . . . . . . . 5.2.1 HW_AUDIOOUT_CTRL . . . . . 5.2.2 HW_AUDIOOUT_STAT . . . . . . 5.2.3 HW_AUDIOOUT_DACSRR . . . 5.2.4 HW_AUDIOOUT_DACVOLUME 5.2.5 HW_AUDIOOUT_DACDEBUG . 5.2.6 HW_AUDIOOUT_HPVOL . . . . 5.2.7 HW_AUDIOOUT_RESERVED . .

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28 28 29 29 30 30 30 31 32 32

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5.2.8 5.2.9 5.2.10 5.2.11 5.2.12 5.2.13 5.2.14 5.2.15 5.2.16 5.2.17 5.2.18 5.2.19 6

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HW_AUDIOOUT_PWRDN . . . . . HW_AUDIOOUT_REFCTRL . . . . HW_AUDIOOUT_ANACTRL . . . HW_AUDIOOUT_TEST . . . . . . HW_AUDIOOUT_BISTCTRL . . . HW_AUDIOOUT_BISTSTAT0 . . . HW_AUDIOOUT_BISTSTAT1 . . . HW_AUDIOOUT_ANACLKCTRL . HW_AUDIOOUT_DATA . . . . . . HW_AUDIOOUT_SPEAKERCTRL HW_AUDIOOUT_LINEOUTCTRL HW_AUDIOOUT_VERSION . . . .

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32 33 33 34 34 34 34 35 35 35 36 36

20-BIT Correcting ECC Accelerator (BCH) 6.1 Summary . . . . . . . . . . . . . . . . . . 6.2 Programmable Registers . . . . . . . . . . 6.2.1 HW_BCH_CTRL . . . . . . . . . 6.2.2 HW_BCH_STATUS0 . . . . . . . 6.2.3 HW_BCH_MODE . . . . . . . . . 6.2.4 HW_BCH_ENCODEPTR . . . . . 6.2.5 HW_BCH_DATAPTR . . . . . . . 6.2.6 HW_BCH_METAPTR . . . . . . . 6.2.7 HW_BCH_LAYOUTSELECT . . . 6.2.8 HW_BCH_FLASH0LAYOUT0 . . 6.2.9 HW_BCH_FLASH0LAYOUT1 . . 6.2.10 HW_BCH_FLASH1LAYOUT0 . . 6.2.11 HW_BCH_FLASH1LAYOUT1 . . 6.2.12 HW_BCH_FLASH2LAYOUT0 . . 6.2.13 HW_BCH_FLASH2LAYOUT1 . . 6.2.14 HW_BCH_FLASH3LAYOUT0 . . 6.2.15 HW_BCH_FLASH3LAYOUT1 . . 6.2.16 HW_BCH_DEBUG0 . . . . . . . . 6.2.17 HW_BCH_DBGKESREAD . . . . 6.2.18 HW_BCH_DBGCSFEREAD . . . 6.2.19 HW_BCH_DBGSYNDGENREAD 6.2.20 HW_BCH_DBGAHBMREAD . . 6.2.21 HW_BCH_BLOCKNAME . . . . 6.2.22 HW_BCH_VERSION . . . . . . .

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37 37 38 38 38 38 39 39 39 40 40 40 41 41 41 42 42 42 43 43 44 44 44 44 45

Clock Generation and Control 7.1 Summary . . . . . . . . . . . . . . . 7.2 Programmable Registers . . . . . . . 7.2.1 HW_CLKCTRL_PLLCTRL0 7.2.2 HW_CLKCTRL_PLLCTRL1 7.2.3 HW_CLKCTRL_CPU . . . . 7.2.4 HW_CLKCTRL_HBUS . . . 7.2.5 HW_CLKCTRL_XBUS . . . 7.2.6 HW_CLKCTRL_XTAL . . . 7.2.7 HW_CLKCTRL_PIX . . . . 7.2.8 HW_CLKCTRL_SSP . . . . 7.2.9 HW_CLKCTRL_GPMI . . . 7.2.10 HW_CLKCTRL_SPDIF . . . 7.2.11 HW_CLKCTRL_EMI . . . . 7.2.12 HW_CLKCTRL_IR . . . . . 7.2.13 HW_CLKCTRL_SAIF . . . . 7.2.14 HW_CLKCTRL_TV . . . . . 7.2.15 HW_CLKCTRL_ETM . . . .

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45 45 46 46 46 47 47 48 48 49 49 50 50 50 51 51 51 52

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HW_CLKCTRL_FRAC . . HW_CLKCTRL_FRAC1 . HW_CLKCTRL_CLKSEQ HW_CLKCTRL_RESET . HW_CLKCTRL_STATUS . HW_CLKCTRL_VERSION

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52 52 53 53 53 53

Data Co-Processor (DCP) 8.1 Summary . . . . . . . . . . . . . . . . . . 8.2 Programmable Registers . . . . . . . . . . 8.2.1 HW_DCP_CTRL . . . . . . . . . . 8.2.2 HW_DCP_STAT . . . . . . . . . . 8.2.3 HW_DCP_CHANNELCTRL . . . 8.2.4 HW_DCP_CAPABILITY0 . . . . . 8.2.5 HW_DCP_CAPABILITY1 . . . . . 8.2.6 HW_DCP_CONTEXT . . . . . . . 8.2.7 HW_DCP_KEY . . . . . . . . . . 8.2.8 HW_DCP_KEYDATA . . . . . . . 8.2.9 HW_DCP_PACKET0 . . . . . . . 8.2.10 HW_DCP_PACKET1 . . . . . . . 8.2.11 HW_DCP_PACKET2 . . . . . . . 8.2.12 HW_DCP_PACKET3 . . . . . . . 8.2.13 HW_DCP_PACKET4 . . . . . . . 8.2.14 HW_DCP_PACKET5 . . . . . . . 8.2.15 HW_DCP_PACKET6 . . . . . . . 8.2.16 HW_DCP_CSCCTRL0 . . . . . . 8.2.17 HW_DCP_CSCSTAT . . . . . . . 8.2.18 HW_DCP_CSCOUTBUFPARAM . 8.2.19 HW_DCP_CSCINBUFPARAM . . 8.2.20 HW_DCP_CSCRGB . . . . . . . . 8.2.21 HW_DCP_CSCLUMA . . . . . . . 8.2.22 HW_DCP_CSCCHROMAU . . . . 8.2.23 HW_DCP_CSCCHROMAV . . . . 8.2.24 HW_DCP_CSCCOEFF0 . . . . . . 8.2.25 HW_DCP_CSCCOEFF1 . . . . . . 8.2.26 HW_DCP_CSCCOEFF2 . . . . . . 8.2.27 HW_DCP_CSCCLIP . . . . . . . . 8.2.28 HW_DCP_CSCXSCALE . . . . . 8.2.29 HW_DCP_CSCYSCALE . . . . . 8.2.30 HW_DCP_DBGSELECT . . . . . 8.2.31 HW_DCP_DBGDATA . . . . . . . 8.2.32 HW_DCP_PAGETABLE . . . . . . 8.2.33 HW_DCP_VERSION . . . . . . .

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54 54 55 55 56 56 57 57 58 58 58 59 59 59 60 60 60 61 61 61 62 62 62 63 63 63 64 64 64 65 65 65 66 66 66 67

Digital Control and On-Chip RAM 9.1 Summary . . . . . . . . . . . . . . . . . . . . 9.2 Programmable Registers . . . . . . . . . . . . 9.2.1 HW_DIGCTL_CTRL . . . . . . . . . 9.2.2 HW_DIGCTL_STATUS . . . . . . . . 9.2.3 HW_DIGCTL_HCLKCOUNT . . . . . 9.2.4 HW_DIGCTL_RAMCTRL . . . . . . 9.2.5 HW_DIGCTL_RAMREPAIR . . . . . 9.2.6 HW_DIGCTL_ROMCTRL . . . . . . 9.2.7 HW_DIGCTL_WRITEONCE . . . . . 9.2.8 HW_DIGCTL_ENTROPY . . . . . . . 9.2.9 HW_DIGCTL_ENTROPY_LATCHED 9.2.10 HW_DIGCTL_SJTAGDBG . . . . . .

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67 67 69 69 69 70 70 71 71 71 71 72 72

3

9.2.11 9.2.12 9.2.13 9.2.14 9.2.15 9.2.16 9.2.17 9.2.18 9.2.19 9.2.20 9.2.21 9.2.22 9.2.23 9.2.24 9.2.25 9.2.26 9.2.27 9.2.28 9.2.29 9.2.30 9.2.31 9.2.32 9.2.33 9.2.34 9.2.35 9.2.36 9.2.37 9.2.38 9.2.39 9.2.40 9.2.41 9.2.42 9.2.43 9.2.44 9.2.45 9.2.46 9.2.47 9.2.48

HW_DIGCTL_MICROSECONDS . . . . . . HW_DIGCTL_DBGRD . . . . . . . . . . . . HW_DIGCTL_DBG . . . . . . . . . . . . . . HW_DIGCTL_OCRAM_BIST_CSR . . . . . HW_DIGCTL_OCRAM_STATUS0 . . . . . . HW_DIGCTL_OCRAM_STATUS1 . . . . . . HW_DIGCTL_OCRAM_STATUS2 . . . . . . HW_DIGCTL_OCRAM_STATUS3 . . . . . . HW_DIGCTL_OCRAM_STATUS4 . . . . . . HW_DIGCTL_OCRAM_STATUS5 . . . . . . HW_DIGCTL_OCRAM_STATUS6 . . . . . . HW_DIGCTL_OCRAM_STATUS7 . . . . . . HW_DIGCTL_OCRAM_STATUS8 . . . . . . HW_DIGCTL_OCRAM_STATUS9 . . . . . . HW_DIGCTL_OCRAM_STATUS10 . . . . . HW_DIGCTL_OCRAM_STATUS11 . . . . . HW_DIGCTL_OCRAM_STATUS12 . . . . . HW_DIGCTL_OCRAM_STATUS13 . . . . . HW_DIGCTL_SCRATCH0 . . . . . . . . . . HW_DIGCTL_SCRATCH1 . . . . . . . . . . HW_DIGCTL_ARMCACHE . . . . . . . . . HW_DIGCTL_DEBUG_TRAP . . . . . . . . HW_DIGCTL_SGTL . . . . . . . . . . . . . HW_DIGCTL_CHIPID . . . . . . . . . . . . HW_DIGCTL_AHB_STATS_SELECT . . . . HW_DIGCTL_L0_AHB_ACTIVE_CYCLES HW_DIGCTL_L0_AHB_DATA_STALLED . HW_DIGCTL_L0_AHB_DATA_CYCLES . . HW_DIGCTL_L1_AHB_ACTIVE_CYCLES HW_DIGCTL_L1_AHB_DATA_STALLED . HW_DIGCTL_L1_AHB_DATA_CYCLES . . HW_DIGCTL_L2_AHB_ACTIVE_CYCLES HW_DIGCTL_L2_AHB_DATA_STALLED . HW_DIGCTL_L2_AHB_DATA_CYCLES . . HW_DIGCTL_L3_AHB_ACTIVE_CYCLES HW_DIGCTL_L3_AHB_DATA_STALLED . HW_DIGCTL_L3_AHB_DATA_CYCLES . . HW_DIGCTL_EMICLK_DELAY . . . . . . .

10 DRAM Registers 10.1 Summary . . . . . . . . . . 10.2 Programmable Registers . . 10.2.1 HW_DRAM_CTL00 10.2.2 HW_DRAM_CTL01 10.2.3 HW_DRAM_CTL02 10.2.4 HW_DRAM_CTL03 10.2.5 HW_DRAM_CTL04 10.2.6 HW_DRAM_CTL05 10.2.7 HW_DRAM_CTL06 10.2.8 HW_DRAM_CTL07 10.2.9 HW_DRAM_CTL08 10.2.10 HW_DRAM_CTL09 10.2.11 HW_DRAM_CTL10 10.2.12 HW_DRAM_CTL11 10.2.13 HW_DRAM_CTL12 10.2.14 HW_DRAM_CTL13 10.2.15 HW_DRAM_CTL14

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73 73 73 73 74 74 74 75 75 75 76 76 76 77 77 77 78 78 78 79 79 79 80 80 81 81 81 82 82 82 82 83 83 83 84 84 84 85

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85 85 87 87 87 88 88 89 89 90 90 91 91 92 92 93 93 94

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10.2.16 HW_DRAM_CTL15 10.2.17 HW_DRAM_CTL16 10.2.18 HW_DRAM_CTL17 10.2.19 HW_DRAM_CTL18 10.2.20 HW_DRAM_CTL19 10.2.21 HW_DRAM_CTL20 10.2.22 HW_DRAM_CTL21 10.2.23 HW_DRAM_CTL22 10.2.24 HW_DRAM_CTL23 10.2.25 HW_DRAM_CTL24 10.2.26 HW_DRAM_CTL25 10.2.27 HW_DRAM_CTL26 10.2.28 HW_DRAM_CTL27 10.2.29 HW_DRAM_CTL28 10.2.30 HW_DRAM_CTL29 10.2.31 HW_DRAM_CTL30 10.2.32 HW_DRAM_CTL31 10.2.33 HW_DRAM_CTL32 10.2.34 HW_DRAM_CTL33 10.2.35 HW_DRAM_CTL34 10.2.36 HW_DRAM_CTL35 10.2.37 HW_DRAM_CTL36 10.2.38 HW_DRAM_CTL37 10.2.39 HW_DRAM_CTL38 10.2.40 HW_DRAM_CTL39 10.2.41 HW_DRAM_CTL40

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94 95 95 96 96 97 97 98 98 99 99 99 100 100 100 101 102 103 103 104 104 104 105 105 106 106

11 Digital Radio Interface (DRI) 11.1 Summary . . . . . . . . . . . 11.2 Programmable Registers . . . 11.2.1 HW_DRI_CTRL . . . 11.2.2 HW_DRI_TIMING . . 11.2.3 HW_DRI_STAT . . . 11.2.4 HW_DRI_DATA . . . 11.2.5 HW_DRI_DEBUG0 . 11.2.6 HW_DRI_DEBUG1 . 11.2.7 HW_DRI_VERSION .

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107 107 107 107 107 108 109 109 110 110

12 8-Symbol Correcting ECC Accelerator (ECC8) 12.1 Summary . . . . . . . . . . . . . . . . . . . 12.2 Programmable Registers . . . . . . . . . . . 12.2.1 HW_ECC8_CTRL . . . . . . . . . . 12.2.2 HW_ECC8_STATUS0 . . . . . . . . 12.2.3 HW_ECC8_STATUS1 . . . . . . . . 12.2.4 HW_ECC8_DEBUG0 . . . . . . . . 12.2.5 HW_ECC8_DBGKESREAD . . . . 12.2.6 HW_ECC8_DBGCSFEREAD . . . . 12.2.7 HW_ECC8_DBGSYNDGENREAD . 12.2.8 HW_ECC8_DBGAHBMREAD . . . 12.2.9 HW_ECC8_BLOCKNAME . . . . . 12.2.10 HW_ECC8_VERSION . . . . . . . .

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111 111 111 111 112 112 112 113 113 114 114 114 115

5

13 External Memory Interface (EMI) 13.1 Summary . . . . . . . . . . . . . . . . . . . . . . 13.2 Programmable Registers . . . . . . . . . . . . . . 13.2.1 HW_EMI_CTRL . . . . . . . . . . . . . . 13.2.2 HW_EMI_STAT . . . . . . . . . . . . . . 13.2.3 HW_EMI_TIME . . . . . . . . . . . . . . 13.2.4 HW_EMI_DDR_TEST_MODE_CSR . . . 13.2.5 HW_EMI_DEBUG . . . . . . . . . . . . . 13.2.6 HW_EMI_DDR_TEST_MODE_STATUS0 13.2.7 HW_EMI_DDR_TEST_MODE_STATUS1 13.2.8 HW_EMI_DDR_TEST_MODE_STATUS2 13.2.9 HW_EMI_DDR_TEST_MODE_STATUS3 13.2.10 HW_EMI_VERSION . . . . . . . . . . .

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115 115 116 116 116 117 117 117 117 118 118 118 119

14 GPIOMON 14.1 Summary . . . . . . . . . . . . . . . . . . . . . . . 14.2 Programmable Registers . . . . . . . . . . . . . . . 14.2.1 HW_GPIOMON_BANK0_DATAIN . . . . . 14.2.2 HW_GPIOMON_BANK1_DATAIN . . . . . 14.2.3 HW_GPIOMON_BANK2_DATAIN . . . . . 14.2.4 HW_GPIOMON_BANK3_DATAIN . . . . . 14.2.5 HW_GPIOMON_BANK0_DATAOUT . . . 14.2.6 HW_GPIOMON_BANK1_DATAOUT . . . 14.2.7 HW_GPIOMON_BANK2_DATAOUT . . . 14.2.8 HW_GPIOMON_BANK3_DATAOUT . . . 14.2.9 HW_GPIOMON_BANK0_DATAOEN . . . 14.2.10 HW_GPIOMON_BANK1_DATAOEN . . . 14.2.11 HW_GPIOMON_BANK2_DATAOEN . . . 14.2.12 HW_GPIOMON_BANK3_DATAOEN . . . 14.2.13 HW_GPIOMON_CTRL . . . . . . . . . . . 14.2.14 HW_GPIOMON_ALT1_PINMUX_BANK0 14.2.15 HW_GPIOMON_ALT1_PINMUX_BANK1 14.2.16 HW_GPIOMON_ALT1_PINMUX_BANK2 14.2.17 HW_GPIOMON_ALT1_PINMUX_BANK3 14.2.18 HW_GPIOMON_ALT2_PINMUX_BANK0 14.2.19 HW_GPIOMON_ALT2_PINMUX_BANK1 14.2.20 HW_GPIOMON_ALT2_PINMUX_BANK2 14.2.21 HW_GPIOMON_ALT2_PINMUX_BANK3 14.2.22 HW_GPIOMON_ALT3_PINMUX_BANK0 14.2.23 HW_GPIOMON_ALT3_PINMUX_BANK1 14.2.24 HW_GPIOMON_ALT3_PINMUX_BANK2 14.2.25 HW_GPIOMON_ALT3_PINMUX_BANK3

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119 119 120 120 120 121 121 121 122 122 122 123 123 123 124 124 125 125 125 125 126 126 126 127 127 127 128 128

15 General Purpose Media Interface 15.1 Summary . . . . . . . . . . . . . 15.2 Programmable Registers . . . . . 15.2.1 HW_GPMI_CTRL0 . . . 15.2.2 HW_GPMI_COMPARE . 15.2.3 HW_GPMI_ECCCTRL . 15.2.4 HW_GPMI_ECCCOUNT 15.2.5 HW_GPMI_PAYLOAD . 15.2.6 HW_GPMI_AUXILIARY 15.2.7 HW_GPMI_CTRL1 . . . 15.2.8 HW_GPMI_TIMING0 . . 15.2.9 HW_GPMI_TIMING1 . . 15.2.10 HW_GPMI_TIMING2 . . 15.2.11 HW_GPMI_DATA . . . .

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128 128 129 129 130 130 131 131 131 131 132 132 133 133

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6

15.2.12 HW_GPMI_STAT . . . 15.2.13 HW_GPMI_DEBUG . . 15.2.14 HW_GPMI_VERSION . 15.2.15 HW_GPMI_DEBUG2 . 15.2.16 HW_GPMI_DEBUG3 .

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134 134 134 135 135

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136 136 136 136 137 137 138 138 139 140 140 141 141

17 Interrupt Collector 17.1 Summary . . . . . . . . . . . . . 17.2 Programmable Registers . . . . . 17.2.1 HW_ICOLL_VECTOR . 17.2.2 HW_ICOLL_LEVELACK 17.2.3 HW_ICOLL_CTRL . . . 17.2.4 HW_ICOLL_VBASE . . 17.2.5 HW_ICOLL_STAT . . . . 17.2.6 HW_ICOLL_DEBUG . . 17.2.7 HW_ICOLL_DBGREAD0 17.2.8 HW_ICOLL_DBGREAD1 17.2.9 HW_ICOLL_DBGFLAG 17.2.10 HW_ICOLL_VERSION .

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142 142 142 142 142 143 143 144 144 145 145 146 146

18 IrDA Controller 18.1 Summary . . . . . . . . . . 18.2 Programmable Registers . . 18.2.1 HW_IR_CTRL . . . 18.2.2 HW_IR_TXDMA . 18.2.3 HW_IR_RXDMA . 18.2.4 HW_IR_DBGCTRL 18.2.5 HW_IR_INTR . . . 18.2.6 HW_IR_DATA . . . 18.2.7 HW_IR_STAT . . . 18.2.8 HW_IR_TCCTRL . 18.2.9 HW_IR_SI_READ . 18.2.10 HW_IR_DEBUG . . 18.2.11 HW_IR_VERSION .

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146 146 147 147 147 147 148 148 149 149 149 150 150 150

19 LCD Interface (LCDIF) 19.1 Summary . . . . . . . . . . . . . . . . . . 19.2 Programmable Registers . . . . . . . . . . 19.2.1 HW_LCDIF_CTRL . . . . . . . . 19.2.2 HW_LCDIF_CTRL1 . . . . . . . . 19.2.3 HW_LCDIF_TRANSFER_COUNT 19.2.4 HW_LCDIF_CUR_BUF . . . . . . 19.2.5 HW_LCDIF_NEXT_BUF . . . . .

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150 150 152 152 152 153 153 154

16 I2 C Interface 16.1 Summary . . . . . . . . . . 16.2 Programmable Registers . . 16.2.1 HW_I2C_CTRL0 . . 16.2.2 HW_I2C_TIMING0 16.2.3 HW_I2C_TIMING1 16.2.4 HW_I2C_TIMING2 16.2.5 HW_I2C_CTRL1 . . 16.2.6 HW_I2C_STAT . . . 16.2.7 HW_I2C_DATA . . 16.2.8 HW_I2C_DEBUG0 16.2.9 HW_I2C_DEBUG1 16.2.10 HW_I2C_VERSION

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7

19.2.6 HW_LCDIF_PAGETABLE . . . . . . 19.2.7 HW_LCDIF_TIMING . . . . . . . . . 19.2.8 HW_LCDIF_VDCTRL0 . . . . . . . . 19.2.9 HW_LCDIF_VDCTRL1 . . . . . . . . 19.2.10 HW_LCDIF_VDCTRL2 . . . . . . . . 19.2.11 HW_LCDIF_VDCTRL3 . . . . . . . . 19.2.12 HW_LCDIF_VDCTRL4 . . . . . . . . 19.2.13 HW_LCDIF_DVICTRL0 . . . . . . . 19.2.14 HW_LCDIF_DVICTRL1 . . . . . . . 19.2.15 HW_LCDIF_DVICTRL2 . . . . . . . 19.2.16 HW_LCDIF_DVICTRL3 . . . . . . . 19.2.17 HW_LCDIF_DVICTRL4 . . . . . . . 19.2.18 HW_LCDIF_CSC_COEFF0 . . . . . . 19.2.19 HW_LCDIF_CSC_COEFF1 . . . . . . 19.2.20 HW_LCDIF_CSC_COEFF2 . . . . . . 19.2.21 HW_LCDIF_CSC_COEFF3 . . . . . . 19.2.22 HW_LCDIF_CSC_COEFF4 . . . . . . 19.2.23 HW_LCDIF_CSC_OFFSET . . . . . . 19.2.24 HW_LCDIF_CSC_LIMIT . . . . . . . 19.2.25 HW_LCDIF_PIN_SHARING_CTRL0 19.2.26 HW_LCDIF_PIN_SHARING_CTRL1 19.2.27 HW_LCDIF_PIN_SHARING_CTRL2 19.2.28 HW_LCDIF_DATA . . . . . . . . . . 19.2.29 HW_LCDIF_BM_ERROR_STAT . . . 19.2.30 HW_LCDIF_STAT . . . . . . . . . . . 19.2.31 HW_LCDIF_VERSION . . . . . . . . 19.2.32 HW_LCDIF_DEBUG0 . . . . . . . . . 19.2.33 HW_LCDIF_DEBUG1 . . . . . . . . .

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154 154 155 155 156 156 157 157 158 158 159 159 160 160 161 161 161 161 162 162 162 163 163 163 164 164 165 165

20 Low-Resolution ADC and Touch-Screen Interface 20.1 Summary . . . . . . . . . . . . . . . . . . . . 20.2 Programmable Registers . . . . . . . . . . . . 20.2.1 HW_LRADC_CTRL0 . . . . . . . . . 20.2.2 HW_LRADC_CTRL1 . . . . . . . . . 20.2.3 HW_LRADC_CTRL2 . . . . . . . . . 20.2.4 HW_LRADC_CTRL3 . . . . . . . . . 20.2.5 HW_LRADC_STATUS . . . . . . . . 20.2.6 HW_LRADC_CH6 . . . . . . . . . . . 20.2.7 HW_LRADC_CH7 . . . . . . . . . . . 20.2.8 HW_LRADC_DEBUG0 . . . . . . . . 20.2.9 HW_LRADC_DEBUG1 . . . . . . . . 20.2.10 HW_LRADC_CONVERSION . . . . . 20.2.11 HW_LRADC_CTRL4 . . . . . . . . . 20.2.12 HW_LRADC_VERSION . . . . . . .

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165 165 166 166 167 167 167 168 168 169 169 170 170 170 171

21 Memory Copy Device 21.1 Summary . . . . . . . . . . . . . 21.2 Programmable Registers . . . . . 21.2.1 HW_MEMCPY_CTRL . 21.2.2 HW_MEMCPY_DATA . 21.2.3 HW_MEMCPY_DEBUG

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171 171 171 171 172 172

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8

22 On-Chip OTP (OCOTP) Controller 22.1 Summary . . . . . . . . . . . . . 22.2 Programmable Registers . . . . . 22.2.1 HW_OCOTP_CTRL . . . 22.2.2 HW_OCOTP_DATA . . . 22.2.3 HW_OCOTP_SWCAP . . 22.2.4 HW_OCOTP_CUSTCAP 22.2.5 HW_OCOTP_LOCK . . . 22.2.6 HW_OCOTP_ROM0 . . . 22.2.7 HW_OCOTP_ROM1 . . . 22.2.8 HW_OCOTP_ROM2 . . . 22.2.9 HW_OCOTP_ROM3 . . . 22.2.10 HW_OCOTP_ROM4 . . . 22.2.11 HW_OCOTP_ROM5 . . . 22.2.12 HW_OCOTP_ROM6 . . . 22.2.13 HW_OCOTP_ROM7 . . . 22.2.14 HW_OCOTP_VERSION .

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172 172 173 173 174 174 174 175 175 175 176 176 177 177 177 177 178

23 Pin Control and GPIO 23.1 Summary . . . . . . . . . . . . . . 23.2 Programmable Registers . . . . . . 23.2.1 HW_PINCTRL_CTRL . . . 23.2.2 HW_PINCTRL_MUXSEL0 23.2.3 HW_PINCTRL_MUXSEL1 23.2.4 HW_PINCTRL_MUXSEL2 23.2.5 HW_PINCTRL_MUXSEL3 23.2.6 HW_PINCTRL_MUXSEL4 23.2.7 HW_PINCTRL_MUXSEL5 23.2.8 HW_PINCTRL_MUXSEL6 23.2.9 HW_PINCTRL_MUXSEL7 23.2.10 HW_PINCTRL_DRIVE0 . 23.2.11 HW_PINCTRL_DRIVE1 . 23.2.12 HW_PINCTRL_DRIVE2 . 23.2.13 HW_PINCTRL_DRIVE3 . 23.2.14 HW_PINCTRL_DRIVE4 . 23.2.15 HW_PINCTRL_DRIVE5 . 23.2.16 HW_PINCTRL_DRIVE6 . 23.2.17 HW_PINCTRL_DRIVE7 . 23.2.18 HW_PINCTRL_DRIVE8 . 23.2.19 HW_PINCTRL_DRIVE9 . 23.2.20 HW_PINCTRL_DRIVE10 . 23.2.21 HW_PINCTRL_DRIVE11 . 23.2.22 HW_PINCTRL_DRIVE12 . 23.2.23 HW_PINCTRL_DRIVE13 . 23.2.24 HW_PINCTRL_DRIVE14 . 23.2.25 HW_PINCTRL_PULL0 . . 23.2.26 HW_PINCTRL_PULL1 . . 23.2.27 HW_PINCTRL_PULL2 . . 23.2.28 HW_PINCTRL_PULL3 . . 23.2.29 HW_PINCTRL_DOUT0 . . 23.2.30 HW_PINCTRL_DOUT1 . . 23.2.31 HW_PINCTRL_DOUT2 . . 23.2.32 HW_PINCTRL_DIN0 . . . 23.2.33 HW_PINCTRL_DIN1 . . . 23.2.34 HW_PINCTRL_DIN2 . . . 23.2.35 HW_PINCTRL_DOE0 . . . 23.2.36 HW_PINCTRL_DOE1 . . .

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178 178 180 180 180 181 181 181 182 182 182 183 183 183 184 184 185 185 186 186 187 187 188 188 189 189 190 190 191 191 191 192 192 192 192 193 193 193 194

9

23.2.37 HW_PINCTRL_DOE2 . . . . 23.2.38 HW_PINCTRL_PIN2IRQ0 . 23.2.39 HW_PINCTRL_PIN2IRQ1 . 23.2.40 HW_PINCTRL_PIN2IRQ2 . 23.2.41 HW_PINCTRL_IRQEN0 . . 23.2.42 HW_PINCTRL_IRQEN1 . . 23.2.43 HW_PINCTRL_IRQEN2 . . 23.2.44 HW_PINCTRL_IRQLEVEL0 23.2.45 HW_PINCTRL_IRQLEVEL1 23.2.46 HW_PINCTRL_IRQLEVEL2 23.2.47 HW_PINCTRL_IRQPOL0 . . 23.2.48 HW_PINCTRL_IRQPOL1 . . 23.2.49 HW_PINCTRL_IRQPOL2 . . 23.2.50 HW_PINCTRL_IRQSTAT0 . 23.2.51 HW_PINCTRL_IRQSTAT1 . 23.2.52 HW_PINCTRL_IRQSTAT2 .

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194 194 195 195 195 196 196 196 197 197 197 198 198 198 199 199

24 Power Supply 24.1 Summary . . . . . . . . . . . . . . . . . 24.2 Programmable Registers . . . . . . . . . 24.2.1 HW_POWER_CTRL . . . . . . . 24.2.2 HW_POWER_5VCTRL . . . . . 24.2.3 HW_POWER_MINPWR . . . . . 24.2.4 HW_POWER_CHARGE . . . . . 24.2.5 HW_POWER_VDDDCTRL . . . 24.2.6 HW_POWER_VDDACTRL . . . 24.2.7 HW_POWER_VDDIOCTRL . . 24.2.8 HW_POWER_VDDMEMCTRL . 24.2.9 HW_POWER_DCFUNCV . . . . 24.2.10 HW_POWER_DCDC4P2 . . . . 24.2.11 HW_POWER_MISC . . . . . . . 24.2.12 HW_POWER_DCLIMITS . . . . 24.2.13 HW_POWER_LOOPCTRL . . . 24.2.14 HW_POWER_STS . . . . . . . . 24.2.15 HW_POWER_SPEED . . . . . . 24.2.16 HW_POWER_BATTMONITOR . 24.2.17 HW_POWER_RESET . . . . . . 24.2.18 HW_POWER_DEBUG . . . . . 24.2.19 HW_POWER_SPECIAL . . . . . 24.2.20 HW_POWER_VERSION . . . .

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199 199 200 200 201 201 202 202 203 203 204 204 205 205 205 206 206 207 207 208 208 209 209

25 Pulse-Width Modulator (PWM) Controller 25.1 Summary . . . . . . . . . . . . . . . . 25.2 Programmable Registers . . . . . . . . 25.2.1 HW_PWM_CTRL . . . . . . . 25.2.2 HW_PWM_VERSION . . . . .

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210 210 210 210 210

26 Pixel Pipeline (PXP) 26.1 Summary . . . . . . . . . . . 26.2 Programmable Registers . . . 26.2.1 HW_PXP_CTRL . . . 26.2.2 HW_PXP_STAT . . . 26.2.3 HW_PXP_RGBBUF . 26.2.4 HW_PXP_RGBBUF2 26.2.5 HW_PXP_RGBSIZE . 26.2.6 HW_PXP_S0BUF . . 26.2.7 HW_PXP_S0UBUF .

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211 211 212 212 212 213 213 213 214 214

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26.2.8 HW_PXP_S0VBUF . . . . . . . 26.2.9 HW_PXP_S0PARAM . . . . . . 26.2.10 HW_PXP_S0BACKGROUND . . 26.2.11 HW_PXP_S0CROP . . . . . . . 26.2.12 HW_PXP_S0SCALE . . . . . . . 26.2.13 HW_PXP_S0OFFSET . . . . . . 26.2.14 HW_PXP_CSCCOEFF0 . . . . . 26.2.15 HW_PXP_CSCCOEFF1 . . . . . 26.2.16 HW_PXP_CSCCOEFF2 . . . . . 26.2.17 HW_PXP_NEXT . . . . . . . . . 26.2.18 HW_PXP_PAGETABLE . . . . . 26.2.19 HW_PXP_S0COLORKEYLOW . 26.2.20 HW_PXP_S0COLORKEYHIGH 26.2.21 HW_PXP_OLCOLORKEYLOW 26.2.22 HW_PXP_OLCOLORKEYHIGH 26.2.23 HW_PXP_DEBUGCTRL . . . . 26.2.24 HW_PXP_DEBUG . . . . . . . . 26.2.25 HW_PXP_VERSION . . . . . .

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214 215 215 215 216 216 216 217 217 217 218 218 218 219 219 219 220 220

27 Real-Time Clock, Alarm, Watchdog, Persistent Bits 27.1 Summary . . . . . . . . . . . . . . . . . . . . . 27.2 Programmable Registers . . . . . . . . . . . . . 27.2.1 HW_RTC_CTRL . . . . . . . . . . . . . 27.2.2 HW_RTC_STAT . . . . . . . . . . . . . 27.2.3 HW_RTC_MILLISECONDS . . . . . . 27.2.4 HW_RTC_SECONDS . . . . . . . . . . 27.2.5 HW_RTC_ALARM . . . . . . . . . . . 27.2.6 HW_RTC_WATCHDOG . . . . . . . . . 27.2.7 HW_RTC_PERSISTENT0 . . . . . . . . 27.2.8 HW_RTC_PERSISTENT1 . . . . . . . . 27.2.9 HW_RTC_PERSISTENT2 . . . . . . . . 27.2.10 HW_RTC_PERSISTENT3 . . . . . . . . 27.2.11 HW_RTC_PERSISTENT4 . . . . . . . . 27.2.12 HW_RTC_PERSISTENT5 . . . . . . . . 27.2.13 HW_RTC_DEBUG . . . . . . . . . . . . 27.2.14 HW_RTC_VERSION . . . . . . . . . .

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220 220 221 221 222 222 223 223 223 224 224 224 225 225 225 226 226

28 Serial Audio Interface (SAIF) 28.1 Summary . . . . . . . . . . . 28.2 Programmable Registers . . . 28.2.1 HW_SAIF_CTRL . . 28.2.2 HW_SAIF_STAT . . . 28.2.3 HW_SAIF_DATA . . 28.2.4 HW_SAIF_VERSION

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227 227 227 227 227 228 228

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29 Serial Audio Interface 1 (SAIF1) 229 29.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 29.2 Programmable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 30 Serial Audio Interface 2 (SAIF2) 229 30.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 30.2 Programmable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

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31 SPDIF Transmitter 31.1 Summary . . . . . . . . . . . . . . 31.2 Programmable Registers . . . . . . 31.2.1 HW_SPDIF_CTRL . . . . . 31.2.2 HW_SPDIF_STAT . . . . . 31.2.3 HW_SPDIF_FRAMECTRL 31.2.4 HW_SPDIF_SRR . . . . . 31.2.5 HW_SPDIF_DEBUG . . . 31.2.6 HW_SPDIF_DATA . . . . . 31.2.7 HW_SPDIF_VERSION . .

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229 229 229 229 230 230 231 231 231 231

32 Synchronous Serial Ports (SSP) 32.1 Summary . . . . . . . . . . . . 32.2 Programmable Registers . . . . 32.2.1 HW_SSP_CTRL0 . . . 32.2.2 HW_SSP_CMD0 . . . . 32.2.3 HW_SSP_CMD1 . . . . 32.2.4 HW_SSP_COMPREF . 32.2.5 HW_SSP_COMPMASK 32.2.6 HW_SSP_TIMING . . . 32.2.7 HW_SSP_CTRL1 . . . 32.2.8 HW_SSP_DATA . . . . 32.2.9 HW_SSP_SDRESP0 . . 32.2.10 HW_SSP_SDRESP1 . . 32.2.11 HW_SSP_SDRESP2 . . 32.2.12 HW_SSP_SDRESP3 . . 32.2.13 HW_SSP_STATUS . . . 32.2.14 HW_SSP_DEBUG . . . 32.2.15 HW_SSP_VERSION . .

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232 232 233 233 233 233 234 234 234 234 235 235 235 236 236 236 237 237

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33 Synchronous Serial Port 1 (SSP1) 238 33.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 33.2 Programmable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 34 Synchronous Serial Port 2 (SSP2) 238 34.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 34.2 Programmable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 35 SYDMA 35.1 Summary . . . . . . . . . . . . . . . . 35.2 Programmable Registers . . . . . . . . 35.2.1 HW_SYDMA_CTRL . . . . . 35.2.2 HW_SYDMA_RADDR . . . . 35.2.3 HW_SYDMA_WADDR . . . . 35.2.4 HW_SYDMA_XFER_COUNT 35.2.5 HW_SYDMA_BURST . . . . . 35.2.6 HW_SYDMA_DACK . . . . . 35.2.7 HW_SYDMA_DEBUG0 . . . . 35.2.8 HW_SYDMA_DEBUG1 . . . . 35.2.9 HW_SYDMA_DEBUG2 . . . . 35.2.10 HW_SYDMA_VERSION . . .

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238 238 239 239 239 239 240 240 240 240 241 241 241

36 Timers and Rotary Decoder 36.1 Summary . . . . . . . . . . . . . . . 36.2 Programmable Registers . . . . . . . 36.2.1 HW_TIMROT_ROTCTRL . . 36.2.2 HW_TIMROT_ROTCOUNT 36.2.3 HW_TIMROT_TIMCTRL3 . 36.2.4 HW_TIMROT_TIMCOUNT3 36.2.5 HW_TIMROT_VERSION . .

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242 242 242 242 243 243 243 244

37 Video DAC 37.1 Summary . . . . . . . . . . . . . . . . . . 37.2 Programmable Registers . . . . . . . . . . 37.2.1 HW_TVENC_CTRL . . . . . . . . 37.2.2 HW_TVENC_CONFIG . . . . . . 37.2.3 HW_TVENC_FILTCTRL . . . . . 37.2.4 HW_TVENC_SYNCOFFSET . . . 37.2.5 HW_TVENC_HTIMINGSYNC0 . 37.2.6 HW_TVENC_HTIMINGSYNC1 . 37.2.7 HW_TVENC_HTIMINGACTIVE . 37.2.8 HW_TVENC_HTIMINGBURST0 37.2.9 HW_TVENC_HTIMINGBURST1 37.2.10 HW_TVENC_VTIMING0 . . . . . 37.2.11 HW_TVENC_VTIMING1 . . . . . 37.2.12 HW_TVENC_MISC . . . . . . . . 37.2.13 HW_TVENC_COLORSUB0 . . . 37.2.14 HW_TVENC_COLORSUB1 . . . 37.2.15 HW_TVENC_COPYPROTECT . . 37.2.16 HW_TVENC_CLOSEDCAPTION 37.2.17 HW_TVENC_COLORBURST . . 37.2.18 HW_TVENC_MACROVISION0 . 37.2.19 HW_TVENC_MACROVISION1 . 37.2.20 HW_TVENC_MACROVISION2 . 37.2.21 HW_TVENC_MACROVISION3 . 37.2.22 HW_TVENC_MACROVISION4 . 37.2.23 HW_TVENC_DACCTRL . . . . . 37.2.24 HW_TVENC_DACSTATUS . . . . 37.2.25 HW_TVENC_VDACTEST . . . . 37.2.26 HW_TVENC_VERSION . . . . .

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244 244 245 245 246 246 247 247 247 248 248 248 249 249 249 250 250 250 251 251 251 252 252 252 253 253 253 254 254

38 Application UART 38.1 Summary . . . . . . . . . . . . . . . 38.2 Programmable Registers . . . . . . . 38.2.1 HW_UARTAPP_CTRL0 . . . 38.2.2 HW_UARTAPP_CTRL1 . . . 38.2.3 HW_UARTAPP_CTRL2 . . . 38.2.4 HW_UARTAPP_LINECTRL 38.2.5 HW_UARTAPP_LINECTRL2 38.2.6 HW_UARTAPP_INTR . . . . 38.2.7 HW_UARTAPP_DATA . . . 38.2.8 HW_UARTAPP_STAT . . . . 38.2.9 HW_UARTAPP_DEBUG . . 38.2.10 HW_UARTAPP_VERSION .

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255 255 255 255 255 256 256 256 257 257 257 258 258

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39 Application UART 1 258 39.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 39.2 Programmable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

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40 Application UART 2 259 40.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 40.2 Programmable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 41 Debug UART 41.1 Summary . . . . . . . . . . . . . . 41.2 Programmable Registers . . . . . . 41.2.1 HW_UARTDBGDR . . . . 41.2.2 HW_UARTDBGRSR_ECR 41.2.3 HW_UARTDBGFR . . . . 41.2.4 HW_UARTDBGILPR . . . 41.2.5 HW_UARTDBGIBRD . . . 41.2.6 HW_UARTDBGFBRD . . 41.2.7 HW_UARTDBGLCR_H . . 41.2.8 HW_UARTDBGCR . . . . 41.2.9 HW_UARTDBGIFLS . . . 41.2.10 HW_UARTDBGIMSC . . . 41.2.11 HW_UARTDBGRIS . . . . 41.2.12 HW_UARTDBGMIS . . . . 41.2.13 HW_UARTDBGICR . . . . 41.2.14 HW_UARTDBGDMACR .

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259 259 260 260 260 260 261 261 261 262 262 262 263 263 263 264 264

42 USB High-Speed Host/Device Controller 42.1 Summary . . . . . . . . . . . . . . . . . . . . . . 42.2 Programmable Registers . . . . . . . . . . . . . . 42.2.1 HW_USBCTRL_ID . . . . . . . . . . . . 42.2.2 HW_USBCTRL_HWGENERAL . . . . . 42.2.3 HW_USBCTRL_GENERAL . . . . . . . 42.2.4 HW_USBCTRL_HWHOST . . . . . . . . 42.2.5 HW_USBCTRL_HOST . . . . . . . . . . 42.2.6 HW_USBCTRL_DEVICE . . . . . . . . . 42.2.7 HW_USBCTRL_HWDEVICE . . . . . . . 42.2.8 HW_USBCTRL_TXBUF . . . . . . . . . 42.2.9 HW_USBCTRL_HWTXBUF . . . . . . . 42.2.10 HW_USBCTRL_RXBUF . . . . . . . . . 42.2.11 HW_USBCTRL_HWRXBUF . . . . . . . 42.2.12 HW_USBCTRL_TTTXBUF . . . . . . . . 42.2.13 HW_USBCTRL_TTRXBUF . . . . . . . . 42.2.14 HW_USBCTRL_GPTIMER0LD . . . . . 42.2.15 HW_USBCTRL_GPTIMER0CTRL . . . . 42.2.16 HW_USBCTRL_GPTIMER1LD . . . . . 42.2.17 HW_USBCTRL_GPTIMER1CTRL . . . . 42.2.18 HW_USBCTRL_SBUSCFG . . . . . . . . 42.2.19 HW_USBCTRL_CAPLENGTH . . . . . . 42.2.20 HW_USBCTRL_HCSPARAMS . . . . . . 42.2.21 HW_USBCTRL_HCCPARAMS . . . . . . 42.2.22 HW_USBCTRL_DCIVERSION . . . . . . 42.2.23 HW_USBCTRL_DCCPARAMS . . . . . . 42.2.24 HW_USBCTRL_USBCMD . . . . . . . . 42.2.25 HW_USBCTRL_USBSTS . . . . . . . . . 42.2.26 HW_USBCTRL_USBINTR . . . . . . . . 42.2.27 HW_USBCTRL_FRINDEX . . . . . . . . 42.2.28 HW_USBCTRL_CTRLDSSEGMENT . . 42.2.29 HW_USBCTRL_PERIODICLISTBASE . 42.2.30 HW_USBCTRL_DEVICEADDR . . . . . 42.2.31 HW_USBCTRL_ASYNCLISTADDR . . . 42.2.32 HW_USBCTRL_ENDPOINTLISTADDR

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264 264 266 266 267 267 267 268 268 268 269 269 269 270 270 270 271 271 271 272 272 272 273 273 273 274 274 274 275 275 275 276 276 276 277

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42.2.33 HW_USBCTRL_TTCTRL . . . . . . . 42.2.34 HW_USBCTRL_BURSTSIZE . . . . . 42.2.35 HW_USBCTRL_TXFILLTUNING . . 42.2.36 HW_USBCTRL_TXTTFILLTUNING 42.2.37 HW_USBCTRL_IC_USB . . . . . . . 42.2.38 HW_USBCTRL_ULPI . . . . . . . . . 42.2.39 HW_USBCTRL_VFRAME . . . . . . 42.2.40 HW_USBCTRL_ENDPTNAK . . . . 42.2.41 HW_USBCTRL_EPNAK . . . . . . . 42.2.42 HW_USBCTRL_ENDPTNAKEN . . . 42.2.43 HW_USBCTRL_EPNAKEN . . . . . 42.2.44 HW_USBCTRL_CONFIGFLAG . . . 42.2.45 HW_USBCTRL_PORTSC1 . . . . . . 42.2.46 HW_USBCTRL_OTGSC . . . . . . . 42.2.47 HW_USBCTRL_USBMODE . . . . . 42.2.48 HW_USBCTRL_ENDPTSETUPSTAT 42.2.49 HW_USBCTRL_ENDPTPRIME . . . 42.2.50 HW_USBCTRL_ENDPTFLUSH . . . 42.2.51 HW_USBCTRL_ENDPTSTAT . . . . 42.2.52 HW_USBCTRL_ENDPTSTATUS . . . 42.2.53 HW_USBCTRL_ENDPTCOMPLETE 42.2.54 HW_USBCTRL_ENDPTCTRL0 . . . 43 Integrated USB 2.0 PHY 43.1 Summary . . . . . . . . . . . . . . . . . . 43.2 Programmable Registers . . . . . . . . . . 43.2.1 HW_USBPHY_PWD . . . . . . . 43.2.2 HW_USBPHY_TX . . . . . . . . . 43.2.3 HW_USBPHY_RX . . . . . . . . 43.2.4 HW_USBPHY_CTRL . . . . . . . 43.2.5 HW_USBPHY_STATUS . . . . . . 43.2.6 HW_USBPHY_DEBUG . . . . . . 43.2.7 HW_USBPHY_DEBUG0_STATUS 43.2.8 HW_USBPHY_DEBUG1 . . . . . 43.2.9 HW_USBPHY_VERSION . . . . . 43.2.10 HW_USBPHY_IP . . . . . . . . .

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. . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . .

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. . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . .

277 277 278 278 278 279 279 279 280 280 280 281 281 281 282 282 282 283 283 283 284 284

. . . . . . . . . . . .

. . . . . . . . . . . .

. . . . . . . . . . . .

. . . . . . . . . . . .

. . . . . . . . . . . .

. . . . . . . . . . . .

. . . . . . . . . . . .

. . . . . . . . . . . .

. . . . . . . . . . . .

. . . . . . . . . . . .

. . . . . . . . . . . .

. . . . . . . . . . . .

. . . . . . . . . . . .

. . . . . . . . . . . .

. . . . . . . . . . . .

. . . . . . . . . . . .

. . . . . . . . . . . .

. . . . . . . . . . . .

. . . . . . . . . . . .

. . . . . . . . . . . .

. . . . . . . . . . . .

. . . . . . . . . . . .

. . . . . . . . . . . .

. . . . . . . . . . . .

. . . . . . . . . . . .

. . . . . . . . . . . .

. . . . . . . . . . . .

. . . . . . . . . . . .

. . . . . . . . . . . .

. . . . . . . . . . . .

. . . . . . . . . . . .

. . . . . . . . . . . .

. . . . . . . . . . . .

. . . . . . . . . . . .

. . . . . . . . . . . .

. . . . . . . . . . . .

. . . . . . . . . . . .

. . . . . . . . . . . .

. . . . . . . . . . . .

. . . . . . . . . . . .

. . . . . . . . . . . .

284 284 285 285 285 286 286 287 287 288 288 289 289

Summary of differences

The next table summarizes the differences between the STMP 3700 and the STMP 3780. The following differences are reported: • Non-Existent: this device block does not exist in one of the chip • Different Base Address: this device block exists in both chip but with a different base address • New Register(s): this device block contains at least one register not present in the other chip • Different Register Address(es): this device block contains at least one register with different addresses in each chip DEVICE

MNEMONIC

APHB DMA

APBH

REPORT LEVEL Block Register Field

15

STMP 3700 Different Register Address(es) Incompatible Field(s)

STMP 3780 New Register(s) Incompatible Field(s)

DEVICE

MNEMONIC

APHX DMA

APBX

Digital Audio Filter Input

AUDIOIN

Digital Audio Filter Output

AUDIOOUT

BCH ECC

BCH

Clock Controller

CLKCTRL

REPORT LEVEL Block Register Field Block Register Field Block Register Field Block

Register

DCP

Register

Incompatible Field(s)

Incompatible Field(s)

Incompatible Field(s)

New Register(s) New Field(s)

New Register(s) New Field(s) Different Base Address New Register(s) New Field(s)

Non-Existent

Different Register Address(es) Incompatible Field(s) Different Register Address(es)

Field Block Digital Control

DRAM Registers

DIGCTL

DRAM

Digital Radio Interface

DRI

Reed-Solomon ECC

ECC8

External Memory Interface

EMI

Register Field Block Register Field Block Register Field Block Register Field Block Register Field Block

GPIOMON

GPIOMON

General Purpose Media Interface

GPMI

I2 C

I2C

Interrupt Collector

IrDA

ICOLL

IR

Register Field Block Register Field Block Register Field Block Register Field Block Register Field

16

STMP 3780

Different Register Address(es) Incompatible Field(s)

Register Field Block

Field Block Data CoProcessor

STMP 3700

New Register(s)

New Register(s) Incompatible Field(s) New Register(s) New Field(s)

Different Register Address(es) Incompatible Field(s)

Different Register Address(es) Incompatible Field(s)

New Field(s)

Incompatible Field(s)

Incompatible Field(s)

New Field(s) Different Base Address New Register(s) New Field(s)

Non-Existent

New Field(s)

New Register(s) New Field(s)

Incompatible Field(s)

Incompatible Field(s)

Different Register Address(es) Incompatible Field(s)

Different Register Address(es) Incompatible Field(s)

DEVICE

MNEMONIC

LCD Interface

LCDIF

Low Resolution ADC

LRADC

REPORT LEVEL Block Register Field Block Register Field Block

Memory Copy Device

MEMCPY

One-time Programmable Array Controller

OCOTP

Pin Control

PINCTRL

Power Control

POWER

Pulse width Modulation

PWM

Pixel Pipeline

PXP

Real Time Clock

RTC

Sync Audio Interface

SAIF

Sync Audio Interface 1

SAIF1

Sync Audio Interface 2

SAIF2

Sony/Phillips Digital Audio Interface

SPDIF

Sync Serial Port

SSP

Sync Serial Port 1

SSP1

Register Field Block Register Field Block Register Field Block Register Field Block Register Field

SSP2

Different Register Address(es) Incompatible Field(s)

Different Base Address New Register(s) New Field(s)

STMP 3780 New Register(s) Incompatible Field(s)

Non-Existent

Incompatible Field(s)

New Register(s) Incompatible Field(s)

Different Register Address(es) Incompatible Field(s)

Different Register Address(es) Incompatible Field(s)

New Register(s) Incompatible Field(s)

New Register(s) Incompatible Field(s)

New Field(s) Different Base Address New Register(s) New Field(s)

Block

Non-Existent

Register Field Block Register Field Block Register Field

New Register(s) New Field(s)

Block

Non-Existent

Different Base Address

Block

Non-Existent

Different Base Address

Register Field Block Register Field Block Register Field

New Register(s) New Field(s)

Block

Non-Existent

Different Base Address

Non-Existent

Different Base Address

Register Field

Register Field Block

Sync Serial Port 2

STMP 3700

Register

17

DEVICE

MNEMONIC

SYDMA

SYDMA

Timers/Rotary Interface

TIMROT

TV Encoder

TVENC

Application UART

UARTAPP

Application UART 1

UARTAPP1

REPORT LEVEL Field

STMP 3700

Block

Non-Existent

Register Field Block Register Field

2 2.1

UARTAPP2

Debug UART

UARTDBG

USB Controller

USBCTRL

USB Physical Interface

USBPHY

Different Base Address New Register(s) New Field(s)

Different Base Address New Register(s) New Field(s)

Block

Non-Existent

Register Field Block Register Field

New Register(s) New Field(s)

Block

Non-Existent

Different Base Address

Non-Existent

Different Base Address

New Register(s) Incompatible Field(s)

New Register(s) Incompatible Field(s)

Incompatible Field(s)

New Register(s) Incompatible Field(s)

Register Field Block

Application UART 2

STMP 3780

Register Field Block Register Field Block Register Field Block Register Field

AHB-to-APBH Bridge with DMA Summary

The next table summarizes the important aspects of the APHB DMA device block and the main differences between the STMP 3700 and the STMP 3780. Name APHB DMA HW_APBH_CTRL0 HW_APBH_CTRL1 HW_APBH_CTRL2 HW_APBH_DEVSEL HW_APBH_VERSION

Property Base Address Address Fields Address Fields Address Fields Address Fields Address Fields

STMP 3700 STMP 3780 0x80004000 0x0 New Field(s) 0x10 Incompatible Field(s) Incompatible Field(s) Non-Existent 0x20 New Field(s) 0x20 0x30 0x3f0

18

2.2.3 3 3 2 2 1 0 9 8 2 2 2 2 7 6 5 4 2 2 2 2 3 2 1 0 1 1 1 1 9 8 7 6

HW_APBH_CTRL2

HW_APBH_CTRL1 HW_APBH_CTRL1

19

CLKGATE_CHANNEL CLKGATE_CHANNEL

1 1 0 0 1 0 9 8 0 0 0 0 7 6 5 4

STMP 3700 Non-Existent

HW_APBH_CTRL2

STMP 3780 0x20 CH0_CMDCMPLT_IRQ

CH0_CMDCMPLT_IRQ

CH3_CMDCMPLT_IRQ

CH3_CMDCMPLT_IRQ

CH1_CMDCMPLT_IRQ

CH4_CMDCMPLT_IRQ

CH4_CMDCMPLT_IRQ

CH2_CMDCMPLT_IRQ

CH5_CMDCMPLT_IRQ

CH5_CMDCMPLT_IRQ

CH2_CMDCMPLT_IRQ

CH6_CMDCMPLT_IRQ

CH6_CMDCMPLT_IRQ

CH1_CMDCMPLT_IRQ

CH7_CMDCMPLT_IRQ

CH7_CMDCMPLT_IRQ

CH0_CMDCMPLT_IRQ_EN

CH1_CMDCMPLT_IRQ_EN

CH2_CMDCMPLT_IRQ_EN

CH4_CMDCMPLT_IRQ_EN

1 1 1 1 5 4 3 2 FREEZE_CHANNEL

1 1 1 1 5 4 3 2

CH5_CMDCMPLT_IRQ_EN

HW_APBH_CTRL0

FREEZE_CHANNEL

0 0 0 0 7 6 5 4

CH6_CMDCMPLT_IRQ_EN

1 1 0 0 1 0 9 8

CH3_CMDCMPLT_IRQ_EN

1 1 1 1 9 8 7 6

CH7_CMDCMPLT_IRQ_EN

CH0_CMDCMPLT_IRQ_EN CH0_AHB_ERROR_IRQ

CH1_CMDCMPLT_IRQ_EN CH1_AHB_ERROR_IRQ

RESET_CHANNEL

2 2 2 2 3 2 1 0

CH2_CMDCMPLT_IRQ_EN CH2_AHB_ERROR_IRQ

RESET_CHANNEL

2 2 2 2 7 6 5 4

CH4_CMDCMPLT_IRQ_EN CH4_AHB_ERROR_IRQ

3 3 2 2 1 0 9 8

CH5_CMDCMPLT_IRQ_EN CH5_AHB_ERROR_IRQ

APB_BURST4_EN

AHB_BURST8_EN

CLKGATE

SFTRST

SFTRST CLKGATE

STMP 3700

HW_APBH_CTRL0

CH6_CMDCMPLT_IRQ_EN CH6_AHB_ERROR_IRQ

2.2.2 STMP 3780

2.2.1

CH3_CMDCMPLT_IRQ_EN CH3_AHB_ERROR_IRQ

STMP 3700

Programmable Registers

CH7_CMDCMPLT_IRQ_EN CH7_AHB_ERROR_IRQ

STMP 3780

2.2

0x0 0 0 0 0 3 2 1 0

0x10

0 0 0 0 3 2 1 0

CH3_ERROR_STATUS

1 1 1 1 5 4 3 2

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

CH3_ERROR_IRQ

1 1 1 1 9 8 7 6

CH7_ERROR_IRQ

2 2 2 2 3 2 1 0

CH7_ERROR_STATUS

2 2 2 2 7 6 5 4

1 1 0 0 1 0 9 8

CH0_ERROR_IRQ

CH1_ERROR_IRQ

CH2_ERROR_IRQ

CH4_ERROR_IRQ

CH5_ERROR_IRQ

CH6_ERROR_IRQ

CH0

CH0

0 0 0 0 3 2 1 0

CH1

CH1

0 0 0 0 7 6 5 4

CH2

CH5 CH5

CH3

CH6 CH6

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0x3f0

STEP

1 1 1 1 5 4 3 2

STEP

MINOR

1 1 1 1 9 8 7 6

MINOR

2 2 2 2 3 2 1 0

MAJOR

2 2 2 2 7 6 5 4

MAJOR

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

3.1

1 1 0 0 1 0 9 8

HW_APBH_VERSION HW_APBH_VERSION

3

STMP 3780 0x30

1 1 1 1 5 4 3 2

CH3

CH7

1 1 1 1 9 8 7 6

CH4

2 2 2 2 3 2 1 0

STMP 3700 0x20

CH4

2 2 2 2 7 6 5 4

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

CH7

HW_APBH_DEVSEL

2.2.5

CH0_ERROR_STATUS

CH1_ERROR_STATUS

CH2_ERROR_STATUS

CH4_ERROR_STATUS

CH5_ERROR_STATUS

HW_APBH_DEVSEL

CH2

2.2.4

CH6_ERROR_STATUS

STMP 3780

STMP 3700

3 3 2 2 1 0 9 8

AHB-to-APBX Bridge with DMA Summary

The next table summarizes the important aspects of the APHX DMA device block and the main differences between the STMP 3700 and the STMP 3780.

20

Name APHX DMA

Property Base Address Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields

HW_APBX_CTRL0 HW_APBX_CTRL1 HW_APBX_CTRL2 HW_APBX_CHANNEL_CTRL HW_APBX_DEVSEL HW_APBX_VERSION

3.2

Programmable Registers

3.2.1

HW_APBX_CTRL0

STMP 3700 STMP 3780 0x80024000 0x0 New Field(s) 0x10 Incompatible Field(s) Incompatible Field(s) Non-Existent 0x20 New Field(s) Non-Existent 0x30 New Field(s) 0x20 0x40 Incompatible Field(s) Incompatible Field(s) 0x3f0 0x800

HW_APBX_CTRL0

3.2.2

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0 FREEZE_CHANNEL

CLKGATE CLKGATE

2 2 2 2 7 6 5 4

RESET_CHANNEL

SFTRST SFTRST

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

0x0

HW_APBX_CTRL1 HW_APBX_CTRL1

21

0x10

3.2.4 2 2 2 2 3 2 1 0 1 1 1 1 9 8 7 6

CH3_ERROR_STATUS

HW_APBX_CHANNEL_CTRL

22

STMP 3700 Non-Existent 1 1 0 0 1 0 9 8 0 0 0 0 7 6 5 4

CH7_ERROR_IRQ

1 1 1 1 5 4 3 2

HW_APBX_CHANNEL_CTRL

STMP 3780 0x30 CH2_ERROR_IRQ CH0_ERROR_IRQ

CH1_ERROR_IRQ

CH7_CMDCMPLT_IRQ CH6_CMDCMPLT_IRQ CH5_CMDCMPLT_IRQ CH4_CMDCMPLT_IRQ CH3_CMDCMPLT_IRQ CH2_CMDCMPLT_IRQ

CH7_CMDCMPLT_IRQ CH6_CMDCMPLT_IRQ CH5_CMDCMPLT_IRQ CH4_CMDCMPLT_IRQ CH3_CMDCMPLT_IRQ CH2_CMDCMPLT_IRQ CH0_CMDCMPLT_IRQ

CH0_CMDCMPLT_IRQ

CH1_CMDCMPLT_IRQ

CH0_CMDCMPLT_IRQ_EN

CH8_CMDCMPLT_IRQ

CH1_CMDCMPLT_IRQ

CH1_CMDCMPLT_IRQ_EN

CH9_CMDCMPLT_IRQ

0 0 0 0 7 6 5 4

CH3_ERROR_IRQ

CH4_ERROR_IRQ

CH5_ERROR_IRQ

CH2_CMDCMPLT_IRQ_EN

CH10_CMDCMPLT_IRQ

1 1 0 0 1 0 9 8

CH6_ERROR_IRQ

CH8_ERROR_IRQ

CH9_ERROR_IRQ

CH3_CMDCMPLT_IRQ_EN

CH11_CMDCMPLT_IRQ

1 1 1 1 5 4 3 2

CH10_ERROR_IRQ

CH4_CMDCMPLT_IRQ_EN

CH12_CMDCMPLT_IRQ

CH5_CMDCMPLT_IRQ_EN

CH0_AHB_ERROR_IRQ

CH0_CMDCMPLT_IRQ_EN

CH13_CMDCMPLT_IRQ

CH1_AHB_ERROR_IRQ

CH1_CMDCMPLT_IRQ_EN

CH7_CMDCMPLT_IRQ_EN

CH2_AHB_ERROR_IRQ

CH2_CMDCMPLT_IRQ_EN

CH6_CMDCMPLT_IRQ_EN

CH3_AHB_ERROR_IRQ

CH3_CMDCMPLT_IRQ_EN

CH15_CMDCMPLT_IRQ

CH4_AHB_ERROR_IRQ

CH4_CMDCMPLT_IRQ_EN

CH14_CMDCMPLT_IRQ

CH5_AHB_ERROR_IRQ

CH5_CMDCMPLT_IRQ_EN

1 1 1 1 9 8 7 6

CH11_ERROR_IRQ

STMP 3700 Non-Existent

CH12_ERROR_IRQ

CH13_ERROR_IRQ

CH14_ERROR_IRQ

CH15_ERROR_IRQ

CH0_ERROR_STATUS

HW_APBX_CTRL2

CH1_ERROR_STATUS

CH6_AHB_ERROR_IRQ

CH6_CMDCMPLT_IRQ_EN

2 2 2 2 3 2 1 0

CH2_ERROR_STATUS

CH4_ERROR_STATUS

CH5_ERROR_STATUS

CH7_AHB_ERROR_IRQ

STMP 3700

CH7_CMDCMPLT_IRQ_EN

CH8_CMDCMPLT_IRQ_EN

CH9_CMDCMPLT_IRQ_EN

CH10_CMDCMPLT_IRQ_EN

CH11_CMDCMPLT_IRQ_EN

CH12_CMDCMPLT_IRQ_EN

CH13_CMDCMPLT_IRQ_EN

CH14_CMDCMPLT_IRQ_EN

CH15_CMDCMPLT_IRQ_EN

STMP 3780

2 2 2 2 7 6 5 4

CH6_ERROR_STATUS

CH8_ERROR_STATUS

CH9_ERROR_STATUS

CH10_ERROR_STATUS

2 2 2 2 7 6 5 4

CH7_ERROR_STATUS

3 3 2 2 1 0 9 8

CH11_ERROR_STATUS

CH12_ERROR_STATUS

CH13_ERROR_STATUS

CH14_ERROR_STATUS

STMP 3700

3.2.3

CH15_ERROR_STATUS

STMP 3780

3 3 2 2 1 0 9 8 0 0 0 0 3 2 1 0

HW_APBX_CTRL2 STMP 3780 0x20

0 0 0 0 3 2 1 0

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

RESET_CHANNEL

STMP 3780 HW_APBX_DEVSEL

CH0 CH0

CH1

CH2

CH1 CH3

CH4

CH2 CH5

CH7

CH4 CH9

CH10

CH12

CH11

STMP 3700 0x3f0

STMP 3780 0x800

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

STEP

MINOR

1 1 1 1 9 8 7 6

MINOR

2 2 2 2 3 2 1 0

MAJOR

2 2 2 2 7 6 5 4

MAJOR

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

4.1

1 1 0 0 1 0 9 8

HW_APBX_VERSION HW_APBX_VERSION

4

1 1 1 1 5 4 3 2

CH3

1 1 1 1 9 8 7 6

CH5

2 2 2 2 3 2 1 0

CH6 CH14

CH13

CH7

2 2 2 2 7 6 5 4

STMP 3780 0x40

STEP

3.2.6

CH15

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

STMP 3700 0x20

CH6

HW_APBX_DEVSEL

CH8

3.2.5

FREEZE_CHANNEL

STMP 3700

3 3 2 2 1 0 9 8

AUDIOIN/ADC Summary

The next table summarizes the important aspects of the Digital Audio Filter Input device block and the main differences between the STMP 3700 and the STMP 3780.

23

Property

4.2.2

HW_AUDIOIN_STAT HW_AUDIOIN_STAT

24

0x10

RUN

0 0 0 0 3 2 1 0

RUN

0 0 0 0 7 6 5 4

FIFO_ERROR_IRQ_EN

1 1 0 0 1 0 9 8

FIFO_OVERFLOW_IRQ

1 1 1 1 5 4 3 2

FIFO_ERROR_IRQ_EN

1 1 1 1 9 8 7 6

FIFO_OVERFLOW_IRQ

CLKGATE CLKGATE

2 2 2 2 3 2 1 0

DMAWAIT_COUNT

SFTRST SFTRST

2 2 2 2 7 6 5 4

DMAWAIT_COUNT

STMP 3700 STMP 3780

3 3 2 2 1 0 9 8

0x0

FIFO_UNDERFLOW_IRQ FIFO_UNDERFLOW_IRQ

HW_AUDIOIN_CTRL

LOOPBACK

HW_AUDIOIN_CTRL

0x70 Incompatible Field(s) Incompatible Field(s) 0x80

WORD_LENGTH

4.2.1

0x60

LOOPBACK

Programmable Registers

0x50

WORD_LENGTH

4.2

0x40

HPF_ENABLE

HW_AUDIOIN_DATA

0x30

HPF_ENABLE

HW_AUDIOIN_ANACLKCTRL

0x20

OFFSET_ENABLE

HW_AUDIOIN_MICLINE

0x10

INVERT_1BIT

HW_AUDIOIN_ADCVOL

0x0

OFFSET_ENABLE

HW_AUDIOIN_ADCDEBUG

Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields

INVERT_1BIT

HW_AUDIOIN_ADCVOLUME

0x8004c000

EDGE_SYNC

HW_AUDIOIN_ADCSRR

Base Address

EDGE_SYNC

HW_AUDIOIN_STAT

STMP 3780

LR_SWAP

HW_AUDIOIN_CTRL

STMP 3700

LR_SWAP

Name Digital Audio Filter Input

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

HW_AUDIOIN_ADCSRR HW_AUDIOIN_ADCSRR

1 1 0 0 1 0 9 8

SRC_FRAC

1 1 1 1 5 4 3 2

SRC_FRAC

SRC_HOLD SRC_HOLD

1 1 1 1 9 8 7 6 SRC_INT

BASEMULT BASEMULT

2 2 2 2 3 2 1 0

0x20

SRC_INT

OSR

2 2 2 2 7 6 5 4

OSR

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_AUDIOIN_ADCVOLUME

VOLUME_LEFT VOLUME_LEFT

1 1 1 1 5 4 3 2 VOLUME_UPDATE_RIGHT VOLUME_UPDATE_RIGHT

EN_ZCD EN_ZCD

1 1 1 1 9 8 7 6

VOLUME_UPDATE_LEFT

2 2 2 2 3 2 1 0

VOLUME_UPDATE_LEFT

2 2 2 2 7 6 5 4

STMP 3700

3 3 2 2 1 0 9 8

0x30

25

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

VOLUME_RIGHT

HW_AUDIOIN_ADCVOLUME

STMP 3780

4.2.4

1 1 0 0 1 0 9 8

VOLUME_RIGHT

4.2.3

2 2 2 2 7 6 5 4

ADC_PRESENT ADC_PRESENT

STMP 3780

STMP 3700

3 3 2 2 1 0 9 8

HW_AUDIOIN_ADCDEBUG

4.2.6

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

HW_AUDIOIN_ADCVOL HW_AUDIOIN_ADCVOL

26

0x50

FIFO_STATUS

1 1 1 1 5 4 3 2

FIFO_STATUS

1 1 1 1 9 8 7 6

DMA_PREQ

2 2 2 2 3 2 1 0

SET_INTERRUPT3_HAND_SHAKE

ENABLE_ADCDMA ENABLE_ADCDMA

2 2 2 2 7 6 5 4

ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS

STMP 3700 STMP 3780

3 3 2 2 1 0 9 8

0x40

DMA_PREQ

HW_AUDIOIN_ADCDEBUG

SET_INTERRUPT3_HAND_SHAKE

4.2.5

4.2.8 DIVIDE_LINE1 DIVIDE_LINE2

MIC_SELECT

DIVIDE_LINE1 DIVIDE_LINE2

MIC_SELECT

1 1 1 1 9 8 7 6

27

HW_AUDIOIN_MICLINE

1 1 1 1 5 4 3 2

HW_AUDIOIN_ANACLKCTRL 1 1 0 0 1 0 9 8

HW_AUDIOIN_ANACLKCTRL

0x70 0 0 0 0 7 6 5 4

GAIN_RIGHT

0 0 0 0 7 6 5 4

GAIN_RIGHT

SELECT_RIGHT

GAIN_LEFT

1 1 0 0 1 0 9 8

SELECT_RIGHT

GAIN_LEFT

SELECT_LEFT

MUTE

MUTE

SELECT_LEFT

EN_ADC_ZCD

EN_ADC_ZCD

1 1 1 1 5 4 3 2

MIC_GAIN

STMP 3700

VOLUME_UPDATE_PENDING VOLUME_UPDATE_PENDING

STMP 3780

1 1 1 1 9 8 7 6

MIC_GAIN

MIC_CHOPCLK MIC_CHOPCLK

2 2 2 2 3 2 1 0

MIC_BIAS

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

MIC_BIAS

3 3 2 2 1 0 9 8

2 2 2 2 7 6 5 4

MIC_RESISTOR MIC_RESISTOR

STMP 3700

4.2.7

STMP 3780

3 3 2 2 1 0 9 8 0 0 0 0 3 2 1 0

HW_AUDIOIN_MICLINE 0x60

0 0 0 0 3 2 1 0

4.2.9

2 2 2 2 7 6 5 4

ADCDIV ADCDIV

ADCCLK_SHIFT

INVERT_ADCCLK

0 0 0 0 3 2 1 0

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

0x80

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

LOW

HIGH

LOW

HIGH

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

5.1

0 0 0 0 7 6 5 4

HW_AUDIOIN_DATA HW_AUDIOIN_DATA

5

1 1 0 0 1 0 9 8

INVERT_ADCCLK

1 1 1 1 5 4 3 2

SLOW_DITHER

1 1 1 1 9 8 7 6

DITHER_OFF

2 2 2 2 3 2 1 0

SLOW_DITHER

CLKGATE CLKGATE

2 2 2 2 7 6 5 4

DITHER_OFF

STMP 3700 STMP 3780

3 3 2 2 1 0 9 8

AUDIOOUT/DAC Summary

The next table summarizes the important aspects of the Digital Audio Filter Output device block and the main differences between the STMP 3700 and the STMP 3780. Name Digital Audio Filter Output HW_AUDIOOUT_CTRL HW_AUDIOOUT_STAT HW_AUDIOOUT_DACSRR HW_AUDIOOUT_DACVOLUME HW_AUDIOOUT_DACDEBUG HW_AUDIOOUT_HPVOL

Property

STMP 3700

STMP 3780

Base Address

0x80048000

Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields

0x0

28

0x10 0x20 0x30 0x40 0x50

HW_AUDIOOUT_BISTSTAT0 HW_AUDIOOUT_BISTSTAT1 HW_AUDIOOUT_ANACLKCTRL HW_AUDIOOUT_DATA HW_AUDIOOUT_SPEAKERCTRL HW_AUDIOOUT_LINEOUTCTRL HW_AUDIOOUT_VERSION

5.2

Programmable Registers

5.2.1

HW_AUDIOOUT_CTRL

0xc0 0xd0 0xe0 0xf0 Non-Existent

0x100 New Field(s) 0x200

HW_AUDIOOUT_CTRL

29

INVERT_1BIT

SS3D_EFFECT

WORD_LENGTH

DAC_ZERO_ENABLE

LOOPBACK

INVERT_1BIT

SS3D_EFFECT

WORD_LENGTH

DAC_ZERO_ENABLE

LOOPBACK

0 0 0 0 7 6 5 4

EDGE_SYNC

1 1 0 0 1 0 9 8

EDGE_SYNC

DMAWAIT_COUNT DMAWAIT_COUNT

1 1 1 1 5 4 3 2

LR_SWAP

CLKGATE CLKGATE

0x0

LR_SWAP

SFTRST

1 1 1 1 9 8 7 6

SFTRST

2 2 2 2 3 2 1 0

STMP 3700

2 2 2 2 7 6 5 4

STMP 3780

3 3 2 2 1 0 9 8

0x100 New Field(s) Non-Existent

0 0 0 0 3 2 1 0

RUN

HW_AUDIOOUT_BISTCTRL

0xa0 New Field(s) New Field(s) 0xb0

RUN

HW_AUDIOOUT_TEST

0x90

FIFO_OVERFLOW_IRQ

HW_AUDIOOUT_ANACTRL

FIFO_ERROR_IRQ_EN

HW_AUDIOOUT_REFCTRL

0x70 New Field(s) New Field(s) 0x80

FIFO_OVERFLOW_IRQ

HW_AUDIOOUT_PWRDN

STMP 3700 STMP 3780 0x60

FIFO_ERROR_IRQ_EN

HW_AUDIOOUT_RESERVED

Property Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields

FIFO_UNDERFLOW_IRQ FIFO_UNDERFLOW_IRQ

Name

5.2.2

HW_AUDIOOUT_STAT HW_AUDIOOUT_STAT

5.2.3

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

HW_AUDIOOUT_DACSRR HW_AUDIOOUT_DACSRR

1 1 0 0 1 0 9 8

SRC_FRAC

1 1 1 1 5 4 3 2

SRC_FRAC

SRC_HOLD SRC_HOLD

1 1 1 1 9 8 7 6 SRC_INT

BASEMULT BASEMULT

2 2 2 2 3 2 1 0

0x20

SRC_INT

OSR

2 2 2 2 7 6 5 4

OSR

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

5.2.4

1 1 0 0 1 0 9 8

DAC_PRESENT DAC_PRESENT

STMP 3780

STMP 3700

3 3 2 2 1 0 9 8

0x10

HW_AUDIOOUT_DACVOLUME HW_AUDIOOUT_DACVOLUME

30

0x30

31 DMA_PREQ FIFO_STATUS

FIFO_STATUS

0 0 0 0 7 6 5 4

DMA_PREQ

1 1 0 0 1 0 9 8

MUTE_LEFT

MUTE_LEFT

VOLUME_RIGHT

MUTE_RIGHT

VOLUME_RIGHT

MUTE_RIGHT

VOLUME_UPDATE_RIGHT VOLUME_UPDATE_RIGHT

0 0 0 0 7 6 5 4

SET_INTERRUPT0_HAND_SHAKE SET_INTERRUPT0_HAND_SHAKE

EN_ZCD

EN_ZCD

VOLUME_LEFT

VOLUME_UPDATE_LEFT

VOLUME_UPDATE_LEFT

VOLUME_LEFT

STMP 3700

STMP 3780

1 1 0 0 1 0 9 8

SET_INTERRUPT1_HAND_SHAKE SET_INTERRUPT1_HAND_SHAKE

1 1 1 1 5 4 3 2 SET_INTERRUPT0_CLK_CROSS

HW_AUDIOOUT_DACDEBUG

SET_INTERRUPT1_CLK_CROSS

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

SET_INTERRUPT0_CLK_CROSS

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

SET_INTERRUPT1_CLK_CROSS

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

RAM_SS

ENABLE_DACDMA

ENABLE_DACDMA

3 3 2 2 1 0 9 8

2 2 2 2 7 6 5 4

RAM_SS

STMP 3700

5.2.5

STMP 3780

3 3 2 2 1 0 9 8 0 0 0 0 3 2 1 0

HW_AUDIOOUT_DACDEBUG 0x40

0 0 0 0 3 2 1 0

HW_AUDIOOUT_HPVOL

5.2.7

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 3 2 1 0

VOL_LEFT

HW_AUDIOOUT_RESERVED HW_AUDIOOUT_RESERVED 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

0x60

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

5.2.8

0 0 0 0 7 6 5 4

VOL_LEFT

1 1 1 1 9 8 7 6

SELECT

MUTE MUTE

2 2 2 2 3 2 1 0

SELECT

EN_MSTR_ZCD

2 2 2 2 7 6 5 4

EN_MSTR_ZCD

VOLUME_UPDATE_PENDING VOLUME_UPDATE_PENDING

STMP 3780

STMP 3700

3 3 2 2 1 0 9 8

0x50

VOL_RIGHT

HW_AUDIOOUT_HPVOL

VOL_RIGHT

5.2.6

HW_AUDIOOUT_PWRDN HW_AUDIOOUT_PWRDN

32

0x70

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

SHORT_LR_STS

SHORT_LR_STS

33

SHORT_LVLADJR

HP_HOLD_GND

HP_CLASSAB

SHORT_LVLADJR

HP_HOLD_GND

HP_CLASSAB

1 1 1 1 9 8 7 6

SHORT_LVLADJL

LW_REF BIAS_CTRL

LW_REF BIAS_CTRL

HW_AUDIOOUT_ANACTRL

1 1 1 1 5 4 3 2

HW_AUDIOOUT_ANACTRL 0x90

1 1 0 0 1 0 9 8 0 0 0 0 7 6 5 4 DAC_ADJ

DAC_ADJ

1 1 0 0 1 0 9 8

CAPLESS

0 0 0 0 7 6 5 4

0 0 0 0 7 6 5 4

HEADPHONE HEADPHONE

CAPLESS

ADC

DAC

DAC

ADC

RIGHT_ADC

RIGHT_ADC

1 1 0 0 1 0 9 8

VAG_VAL

1 1 1 1 5 4 3 2

VAG_VAL

HW_AUDIOOUT_REFCTRL

ADC_REFVAL

ADJ_VAG

ADJ_VAG

SELFBIAS

LINEOUT

SPEAKER

SELFBIAS

STMP 3700

STMP 3780

1 1 1 1 5 4 3 2

ADC_REFVAL

ADJ_ADC

ADJ_ADC

1 1 1 1 9 8 7 6

SHORT_LVLADJL

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

VDDXTAL_TO_VDDD VDDXTAL_TO_VDDD

LOW_PWR

XTAL_BGR_BIAS

XTAL_BGR_BIAS

LOW_PWR

RAISE_REF

RAISE_REF

VBG_ADJ

FASTSETTLING

FASTSETTLING

2 2 2 2 3 2 1 0

SHORTMODE_LR

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

SHORTMODE_LR

3 3 2 2 1 0 9 8 2 2 2 2 7 6 5 4

VBG_ADJ

STMP 3700

STMP 3780 3 3 2 2 1 0 9 8

2 2 2 2 7 6 5 4

SHORTMODE_CM SHORTMODE_CM

SHORT_CM_STS

SHORT_CM_STS

5.2.10

STMP 3700

5.2.9

STMP 3780

3 3 2 2 1 0 9 8 0 0 0 0 3 2 1 0

HW_AUDIOOUT_REFCTRL 0x80

0 0 0 0 3 2 1 0

0 0 0 0 3 2 1 0

HW_AUDIOOUT_TEST

DAC_DOUBLE_I

DAC_DIS_RTZ DAC_DIS_RTZ

0 0 0 0 3 2 1 0

START

0 0 0 0 7 6 5 4

START

1 1 0 0 1 0 9 8

DONE

1 1 1 1 5 4 3 2

PASS

1 1 1 1 9 8 7 6

DONE

2 2 2 2 3 2 1 0

PASS

2 2 2 2 7 6 5 4

0xb0

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_AUDIOOUT_BISTSTAT0 HW_AUDIOOUT_BISTSTAT0 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

0xc0

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

DATA

DATA

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

5.2.14

DAC_CLASSA

HW_AUDIOOUT_BISTCTRL HW_AUDIOOUT_BISTCTRL

5.2.13

0 0 0 0 3 2 1 0

DAC_DOUBLE_I

0 0 0 0 7 6 5 4

DAC_CLASSA

VAG_DOUBLE_I

HP_I1_ADJ HP_I1_ADJ

VAG_DOUBLE_I

TM_HPCOMMON TM_HPCOMMON

VAG_CLASSA

TM_LINEOUT TM_LOOP

1 1 0 0 1 0 9 8

VAG_CLASSA

TM_ADCIN_TOHP TM_ADCIN_TOHP

1 1 1 1 5 4 3 2

HP_IALL_ADJ

HP_ANTIPOP HP_ANTIPOP

1 1 1 1 9 8 7 6

HP_IALL_ADJ

STMP 3700

2 2 2 2 3 2 1 0

FAIL

5.2.12

2 2 2 2 7 6 5 4

STMP 3780

3 3 2 2 1 0 9 8

0xa0

ADCTODAC_LOOP

HW_AUDIOOUT_TEST

FAIL

5.2.11

HW_AUDIOOUT_BISTSTAT1 HW_AUDIOOUT_BISTSTAT1

34

0xd0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

ADDR

0 0 0 0 3 2 1 0

ADDR

STATE

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

DACDIV

CLKGATE CLKGATE

2 2 2 2 7 6 5 4

0xe0

INVERT_DACCLK INVERT_DACCLK

STMP 3700 STMP 3780

3 3 2 2 1 0 9 8

HW_AUDIOOUT_DATA HW_AUDIOOUT_DATA 2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

LOW

HIGH

2 2 2 2 7 6 5 4

0xf0

LOW

HIGH

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

5.2.17

0 0 0 0 7 6 5 4

HW_AUDIOOUT_ANACLKCTRL HW_AUDIOOUT_ANACLKCTRL

5.2.16

1 1 0 0 1 0 9 8

DACDIV

5.2.15

2 2 2 2 7 6 5 4

STATE

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_AUDIOOUT_SPEAKERCTRL HW_AUDIOOUT_SPEAKERCTRL

35

STMP 3700 Non-Existent

STMP 3780 0x100

0 0 0 0 3 2 1 0

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

1 1 1 1 5 4 3 2

STMP 3780 Non-Existent 1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

VOLUME_RIGHT

1 1 1 1 9 8 7 6

STMP 3700 0x100

CHARGE_CAP

2 2 2 2 3 2 1 0

OUT_CURRENT

EN_LINEOUT_ZCD

MUTE

2 2 2 2 7 6 5 4

VOLUME_UPDATE_PENDING

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

VAG_CTRL

HW_AUDIOOUT_LINEOUTCTRL

HW_AUDIOOUT_VERSION HW_AUDIOOUT_VERSION

0x200 1 1 0 0 1 0 9 8

STEP

1 1 1 1 5 4 3 2

STEP

MINOR

1 1 1 1 9 8 7 6

MINOR

2 2 2 2 3 2 1 0

MAJOR

2 2 2 2 7 6 5 4

MAJOR

3 3 2 2 1 0 9 8 STMP 3780 STMP 3700

5.2.19

NEGDRIVER

POSDRIVER

IALL_ADJ

I1_ADJ

HW_AUDIOOUT_LINEOUTCTRL

VOLUME_LEFT

5.2.18

MUTE

STMP 3780

STMP 3700

3 3 2 2 1 0 9 8

36

6 6.1

20-BIT Correcting ECC Accelerator (BCH) Summary

The next table summarizes the important aspects of the BCH ECC device block and the main differences between the STMP 3700 and the STMP 3780. Name BCH ECC HW_BCH_CTRL HW_BCH_STATUS0 HW_BCH_MODE HW_BCH_ENCODEPTR HW_BCH_DATAPTR HW_BCH_METAPTR HW_BCH_LAYOUTSELECT HW_BCH_FLASH0LAYOUT0 HW_BCH_FLASH0LAYOUT1 HW_BCH_FLASH1LAYOUT0 HW_BCH_FLASH1LAYOUT1 HW_BCH_FLASH2LAYOUT0 HW_BCH_FLASH2LAYOUT1 HW_BCH_FLASH3LAYOUT0 HW_BCH_FLASH3LAYOUT1 HW_BCH_DEBUG0 HW_BCH_DBGKESREAD HW_BCH_DBGCSFEREAD HW_BCH_DBGSYNDGENREAD HW_BCH_DBGAHBMREAD HW_BCH_BLOCKNAME HW_BCH_VERSION

Property Base Address Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields

37

STMP 3700 Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent

STMP 3780 0x8000a000 0x0 New Field(s) 0x10 New Field(s) 0x20 New Field(s) 0x30 New Field(s) 0x40 New Field(s) 0x50 New Field(s) 0x70 New Field(s) 0x80 New Field(s) 0x90 New Field(s) 0xa0 New Field(s) 0xb0 New Field(s) 0xc0 New Field(s) 0xd0 New Field(s) 0xe0 New Field(s) 0xf0 New Field(s) 0x100 New Field(s) 0x110 New Field(s) 0x120 New Field(s) 0x130 New Field(s) 0x140 New Field(s) 0x150 New Field(s) 0x160 New Field(s)

6.2

Programmable Registers

6.2.1

HW_BCH_CTRL STMP 3700 Non-Existent

HW_BCH_CTRL 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

6.2.2

HW_BCH_STATUS0 HW_BCH_STATUS0 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

STMP 3700 Non-Existent

1 1 1 1 9 8 7 6

STMP 3780 0x10

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

HW_BCH_MODE HW_BCH_MODE

STMP 3700 Non-Existent

38

STMP 3780 0x20

UNCORRECTABLE

CORRECTED

ALLONES

STATUS_BLK0

COMPLETED_CE

HANDLE

STMP 3780

STMP 3700

3 3 2 2 1 0 9 8

6.2.3

COMPLETE_IRQ

DEBUG_STALL_IRQ

BM_ERROR_IRQ

COMPLETE_IRQ_EN

DEBUG_STALL_IRQ_EN

M2M_ENABLE

M2M_ENCODE

M2M_LAYOUT

DEBUGSYNDROME

CLKGATE

SFTRST

STMP 3780

STMP 3700

3 3 2 2 1 0 9 8

STMP 3780 0x0

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

STMP 3780

ERASE_THRESHOLD

STMP 3700

3 3 2 2 1 0 9 8

6.2.4

HW_BCH_ENCODEPTR HW_BCH_ENCODEPTR 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

6.2.5

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

HW_BCH_DATAPTR HW_BCH_DATAPTR 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

STMP 3700 Non-Existent

1 1 1 1 9 8 7 6

STMP 3780 0x40

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

ADDR

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

6.2.6

STMP 3780 0x30

ADDR

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

STMP 3700 Non-Existent

HW_BCH_METAPTR HW_BCH_METAPTR

STMP 3700 Non-Existent

39

STMP 3780 0x50

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

6.2.7

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

STMP 3700 Non-Existent

STMP 3780 0x70

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

ADDR

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_BCH_LAYOUTSELECT HW_BCH_LAYOUTSELECT 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

6.2.8

CS0_SELECT

HW_BCH_FLASH0LAYOUT0 HW_BCH_FLASH0LAYOUT0 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

STMP 3700 Non-Existent 1 1 1 1 5 4 3 2

STMP 3780 0x80 1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

DATA0_SIZE

ECC0

META_SIZE

NBLOCKS

STMP 3780

STMP 3700

3 3 2 2 1 0 9 8

6.2.9

CS1_SELECT

CS2_SELECT

CS3_SELECT

CS4_SELECT

CS5_SELECT

CS6_SELECT

CS7_SELECT

CS8_SELECT

CS9_SELECT

CS10_SELECT

CS11_SELECT

CS12_SELECT

CS13_SELECT

CS14_SELECT

CS15_SELECT

STMP 3780

STMP 3700

3 3 2 2 1 0 9 8

HW_BCH_FLASH0LAYOUT1 HW_BCH_FLASH0LAYOUT1

40

STMP 3700 Non-Existent

STMP 3780 0x90

0 0 0 0 3 2 1 0

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

6.2.10

DATAN_SIZE

ECCN

PAGE_SIZE

STMP 3780

STMP 3700

3 3 2 2 1 0 9 8

HW_BCH_FLASH1LAYOUT0 HW_BCH_FLASH1LAYOUT0 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

STMP 3780 0xa0 1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

6.2.11

DATA0_SIZE

ECC0

META_SIZE

NBLOCKS

STMP 3780

STMP 3700

3 3 2 2 1 0 9 8

STMP 3700 Non-Existent

HW_BCH_FLASH1LAYOUT1 HW_BCH_FLASH1LAYOUT1 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

STMP 3780 0xb0 1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

6.2.12

DATAN_SIZE

ECCN

PAGE_SIZE

STMP 3780

STMP 3700

3 3 2 2 1 0 9 8

STMP 3700 Non-Existent

HW_BCH_FLASH2LAYOUT0 HW_BCH_FLASH2LAYOUT0

41

STMP 3700 Non-Existent

STMP 3780 0xc0

0 0 0 0 3 2 1 0

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

6.2.13

DATA0_SIZE

ECC0

META_SIZE

NBLOCKS

STMP 3780

STMP 3700

3 3 2 2 1 0 9 8

HW_BCH_FLASH2LAYOUT1 HW_BCH_FLASH2LAYOUT1 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

STMP 3780 0xd0 1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

6.2.14

DATAN_SIZE

ECCN

PAGE_SIZE

STMP 3780

STMP 3700

3 3 2 2 1 0 9 8

STMP 3700 Non-Existent

HW_BCH_FLASH3LAYOUT0 HW_BCH_FLASH3LAYOUT0 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

STMP 3780 0xe0 1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

6.2.15

DATA0_SIZE

ECC0

META_SIZE

NBLOCKS

STMP 3780

STMP 3700

3 3 2 2 1 0 9 8

STMP 3700 Non-Existent

HW_BCH_FLASH3LAYOUT1 HW_BCH_FLASH3LAYOUT1

42

STMP 3700 Non-Existent

STMP 3780 0xf0

0 0 0 0 3 2 1 0

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

6.2.16

DATAN_SIZE

ECCN

PAGE_SIZE

STMP 3780

STMP 3700

3 3 2 2 1 0 9 8

HW_BCH_DEBUG0 HW_BCH_DEBUG0 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

STMP 3780 0x100

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

DEBUG_REG_SELECT

BM_KES_TEST_BYPASS

KES_DEBUG_STALL

KES_DEBUG_STEP

KES_STANDALONE

KES_DEBUG_KICK

KES_DEBUG_MODE4K

KES_DEBUG_PAYLOAD_FLAG

KES_DEBUG_SHIFT_SYND

KES_DEBUG_SYNDROME_SYMBOL

HW_BCH_DBGKESREAD STMP 3700 Non-Existent

HW_BCH_DBGKESREAD 3 3 2 2 1 0 9 8

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

VALUES

STMP 3780 STMP 3700

6.2.17

ROM_BIST_COMPLETE

STMP 3780

ROM_BIST_ENABLE

STMP 3700

3 3 2 2 1 0 9 8

STMP 3700 Non-Existent

43

STMP 3780 0x110 1 1 0 0 1 0 9 8

6.2.18

HW_BCH_DBGCSFEREAD HW_BCH_DBGCSFEREAD 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

6.2.19

STMP 3780 0x120

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

1 1 1 1 9 8 7 6

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

STMP 3700 Non-Existent

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

STMP 3780 0x130 1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

VALUES

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_BCH_DBGAHBMREAD STMP 3700 Non-Existent

HW_BCH_DBGAHBMREAD 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

STMP 3780 0x140 1 1 0 0 1 0 9 8

VALUES

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

6.2.21

0 0 0 0 3 2 1 0

HW_BCH_DBGSYNDGENREAD HW_BCH_DBGSYNDGENREAD

6.2.20

0 0 0 0 7 6 5 4

VALUES

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

STMP 3700 Non-Existent

HW_BCH_BLOCKNAME HW_BCH_BLOCKNAME

STMP 3700 Non-Existent

44

STMP 3780 0x150

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

2 2 2 2 3 2 1 0

STMP 3700 Non-Existent

0 0 0 0 3 2 1 0

1 1 1 1 9 8 7 6

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

STMP 3780 0x160

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

MINOR

2 2 2 2 7 6 5 4

MAJOR

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

7.1

0 0 0 0 7 6 5 4

HW_BCH_VERSION HW_BCH_VERSION

7

1 1 0 0 1 0 9 8

STEP

6.2.22

1 1 1 1 5 4 3 2

NAME

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

Clock Generation and Control Summary

The next table summarizes the important aspects of the Clock Controller device block and the main differences between the STMP 3700 and the STMP 3780. Name Clock Controller HW_CLKCTRL_PLLCTRL0 HW_CLKCTRL_PLLCTRL1 HW_CLKCTRL_CPU HW_CLKCTRL_HBUS HW_CLKCTRL_XBUS HW_CLKCTRL_XTAL HW_CLKCTRL_PIX HW_CLKCTRL_SSP HW_CLKCTRL_GPMI

Property Base Address Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields 45

STMP 3700 STMP 3780 0x80040000 0x0 0x10 0x20 Incompatible Field(s) Incompatible Field(s) 0x30 New Field(s) 0x40 0x50 0x60 Incompatible Field(s) Incompatible Field(s) 0x70 0x80

Name

Property Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields

HW_CLKCTRL_SPDIF HW_CLKCTRL_EMI HW_CLKCTRL_IR HW_CLKCTRL_SAIF HW_CLKCTRL_TV HW_CLKCTRL_ETM HW_CLKCTRL_FRAC HW_CLKCTRL_FRAC1 HW_CLKCTRL_CLKSEQ HW_CLKCTRL_RESET HW_CLKCTRL_STATUS HW_CLKCTRL_VERSION

7.2

Programmable Registers

7.2.1

HW_CLKCTRL_PLLCTRL0

STMP 3700

0xa0 New Field(s) 0xb0 0xc0 Non-Existent Non-Existent 0xd0 Non-Existent 0xe0 0xf0 Non-Existent 0x100

HW_CLKCTRL_PLLCTRL0

7.2.2

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

POWER

HW_CLKCTRL_PLLCTRL1 HW_CLKCTRL_PLLCTRL1

46

0xd0 New Field(s) 0xe0 New Field(s) 0xf0 0x100 New Field(s) 0x110 New Field(s) 0x120 0x130 New Field(s) 0x140

0x0

POWER

1 1 1 1 9 8 7 6 EN_USB_CLKS EN_USB_CLKS

CP_SEL CP_SEL

DIV_SEL

LFR_SEL LFR_SEL

2 2 2 2 3 2 1 0

DIV_SEL

STMP 3700

2 2 2 2 7 6 5 4

STMP 3780

3 3 2 2 1 0 9 8

STMP 3780 0x90

0x10

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

FORCE_LOCK

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

HW_CLKCTRL_CPU

47

0x30

DIV_CPU

DIV_CPU_FRAC_EN

HW_CLKCTRL_HBUS HW_CLKCTRL_HBUS

1 1 0 0 1 0 9 8

DIV_CPU_FRAC_EN

1 1 1 1 5 4 3 2 INTERRUPT_WAIT

1 1 1 1 9 8 7 6

DIV_XTAL

BUSY_REF_CPU BUSY_REF_CPU

2 2 2 2 3 2 1 0

DIV_XTAL

BUSY_REF_XTAL BUSY_REF_XTAL

2 2 2 2 7 6 5 4 DIV_XTAL_FRAC_EN DIV_XTAL_FRAC_EN

STMP 3700 STMP 3780

3 3 2 2 1 0 9 8

0x20

DIV_CPU

HW_CLKCTRL_CPU

7.2.4

1 1 0 0 1 0 9 8 LOCK_COUNT LOCK_COUNT

LOCK LOCK

2 2 2 2 7 6 5 4

INTERRUPT_WAIT

7.2.3

FORCE_LOCK

STMP 3780

STMP 3700

3 3 2 2 1 0 9 8

7.2.6 BUSY

BUSY

2 2 2 2 3 2 1 0

BUSY

BUSY

APBXDMA_AS_ENABLE

APBXDMA_AS_ENABLE

CPU_INSTR_AS_ENABLE AUTO_SLOW_MODE

SLOW_DIV

CPU_INSTR_AS_ENABLE AUTO_SLOW_MODE

SLOW_DIV

DIV_FRAC_EN

CPU_DATA_AS_ENABLE

CPU_DATA_AS_ENABLE

DIV_FRAC_EN

TRAFFIC_AS_ENABLE

TRAFFIC_AS_ENABLE

TRAFFIC_JAM_AS_ENABLE TRAFFIC_JAM_AS_ENABLE

APBHDMA_AS_ENABLE

APBHDMA_AS_ENABLE

PXP_AS_ENABLE

DCP_AS_ENABLE

STMP 3700

STMP 3780

1 1 1 1 9 8 7 6

1 1 1 1 9 8 7 6

48

1 1 1 1 5 4 3 2

HW_CLKCTRL_XBUS

1 1 1 1 5 4 3 2

HW_CLKCTRL_XTAL HW_CLKCTRL_XTAL 0x50 DIV

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

DIV

3 3 2 2 1 0 9 8

2 2 2 2 7 6 5 4

DIV_FRAC_EN DIV_FRAC_EN

STMP 3700

7.2.5

STMP 3780

3 3 2 2 1 0 9 8

HW_CLKCTRL_XBUS 0x40

1 1 0 0 1 0 9 8 0 0 0 0 7 6 5 4

DIV

0 0 0 0 7 6 5 4

DIV

1 1 0 0 1 0 9 8 0 0 0 0 3 2 1 0

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

HW_CLKCTRL_PIX HW_CLKCTRL_PIX 1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

DIV

BUSY BUSY

2 2 2 2 3 2 1 0

DIV_FRAC_EN

CLKGATE CLKGATE

2 2 2 2 7 6 5 4

0x60

DIV_FRAC_EN

STMP 3700 STMP 3780

3 3 2 2 1 0 9 8

HW_CLKCTRL_SSP

BUSY BUSY

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

49

0 0 0 0 7 6 5 4

DIV

CLKGATE CLKGATE

2 2 2 2 7 6 5 4

DIV_FRAC_EN DIV_FRAC_EN

STMP 3700

3 3 2 2 1 0 9 8

0x70

DIV

HW_CLKCTRL_SSP

STMP 3780

7.2.8

1 1 0 0 1 0 9 8

DIV_UART

DRI_CLK24M_GATE DRI_CLK24M_GATE

1 1 1 1 5 4 3 2

DIV_UART

PWM_CLK24M_GATE PWM_CLK24M_GATE

1 1 1 1 9 8 7 6

TIMROT_CLK32K_GATE

FILT_CLK24M_GATE FILT_CLK24M_GATE

2 2 2 2 3 2 1 0

TIMROT_CLK32K_GATE

UART_CLK_GATE UART_CLK_GATE

DIGCTRL_CLK1M_GATE DIGCTRL_CLK1M_GATE

STMP 3700

2 2 2 2 7 6 5 4

DIV

7.2.7

STMP 3780

3 3 2 2 1 0 9 8

0 0 0 0 3 2 1 0

HW_CLKCTRL_GPMI

BUSY BUSY

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

HW_CLKCTRL_SPDIF HW_CLKCTRL_SPDIF 2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

CLKGATE

2 2 2 2 7 6 5 4

0x90

CLKGATE

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_CLKCTRL_EMI

50

1 1 1 1 5 4 3 2

DIV_EMI

DCC_RESYNC_ENABLE DCC_RESYNC_ENABLE

1 1 1 1 9 8 7 6 BUSY_DCC_RESYNC

2 2 2 2 3 2 1 0

BUSY_DCC_RESYNC

BUSY_SYNC_MODE

BUSY_REF_EMI BUSY_REF_EMI

2 2 2 2 7 6 5 4

BUSY_REF_CPU

BUSY_REF_XTAL BUSY_REF_XTAL

CLKGATE CLKGATE

SYNC_MODE_EN

STMP 3700

3 3 2 2 1 0 9 8

0xa0

DIV_EMI

HW_CLKCTRL_EMI

STMP 3780

7.2.11

1 1 0 0 1 0 9 8

DIV

CLKGATE CLKGATE

2 2 2 2 3 2 1 0

DIV_FRAC_EN DIV_FRAC_EN

STMP 3700

2 2 2 2 7 6 5 4

DIV_XTAL

7.2.10

STMP 3780

3 3 2 2 1 0 9 8

0x80

DIV

HW_CLKCTRL_GPMI

DIV_XTAL

7.2.9

7.2.12

HW_CLKCTRL_IR HW_CLKCTRL_IR

7.2.13

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

0 0 0 0 7 6 5 4

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

IR_DIV

0 0 0 0 3 2 1 0

IR_DIV

HW_CLKCTRL_SAIF HW_CLKCTRL_SAIF 1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

DIV

BUSY BUSY

2 2 2 2 3 2 1 0

DIV

CLKGATE CLKGATE

2 2 2 2 7 6 5 4

0xc0

DIV_FRAC_EN DIV_FRAC_EN

STMP 3700 STMP 3780

3 3 2 2 1 0 9 8

HW_CLKCTRL_TV HW_CLKCTRL_TV 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

STMP 3700 Non-Existent

1 1 1 1 9 8 7 6

CLK_TV_GATE

CLK_TV108M_GATE

STMP 3700

3 3 2 2 1 0 9 8

STMP 3780

7.2.14

1 1 0 0 1 0 9 8

IROV_DIV

IR_BUSY IR_BUSY

2 2 2 2 3 2 1 0

IROV_DIV

AUTO_DIV AUTO_DIV

2 2 2 2 7 6 5 4 IROV_BUSY IROV_BUSY

CLKGATE CLKGATE

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

0xb0

51

STMP 3780 0xd0

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

7.2.15

HW_CLKCTRL_ETM HW_CLKCTRL_ETM 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

STMP 3780 0xe0

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

CPUFRAC

0 0 0 0 3 2 1 0

CPUFRAC

CPU_STABLE

CPU_STABLE

0 0 0 0 7 6 5 4 CLKGATECPU CLKGATECPU

1 1 0 0 1 0 9 8

EMIFRAC

1 1 1 1 5 4 3 2

EMIFRAC

PIXFRAC PIXFRAC

STMP 3780 0xf0

EMI_STABLE

CLKGATEPIX

PIX_STABLE

1 1 1 1 9 8 7 6

PIX_STABLE

IOFRAC IOFRAC

2 2 2 2 3 2 1 0

CLKGATEPIX

CLKGATEIO

IO_STABLE IO_STABLE

2 2 2 2 7 6 5 4

CLKGATEIO

STMP 3700 STMP 3780

3 3 2 2 1 0 9 8

STMP 3700 0xd0

EMI_STABLE

HW_CLKCTRL_FRAC

HW_CLKCTRL_FRAC1 HW_CLKCTRL_FRAC1 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

STMP 3700 Non-Existent

1 1 1 1 9 8 7 6

VID_STABLE

CLKGATEVID

STMP 3700

3 3 2 2 1 0 9 8

STMP 3780

7.2.17

DIV

DIV_FRAC_EN

BUSY

HW_CLKCTRL_FRAC

CLKGATEEMI CLKGATEEMI

7.2.16

CLKGATE

STMP 3780

STMP 3700

3 3 2 2 1 0 9 8

STMP 3700 Non-Existent

52

1 1 1 1 5 4 3 2

STMP 3780 0x100 1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

HW_CLKCTRL_CLKSEQ

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

BYPASS_PIX

BYPASS_SAIF

BYPASS_PIX

BYPASS_SAIF

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

DIG

1 1 1 1 9 8 7 6

DIG

2 2 2 2 3 2 1 0

CHIP

2 2 2 2 7 6 5 4

STMP 3780 0x120

CHIP

STMP 3700 0xf0

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_CLKCTRL_STATUS STMP 3700 Non-Existent

HW_CLKCTRL_STATUS 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

STMP 3780 0x130 1 1 0 0 1 0 9 8

CPU_LIMIT

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

7.2.21

BYPASS_IR

HW_CLKCTRL_RESET HW_CLKCTRL_RESET

7.2.20

0 0 0 0 3 2 1 0

BYPASS_IR

BYPASS_ETM

STMP 3780 7.2.19

0 0 0 0 7 6 5 4 BYPASS_SSP

1 1 0 0 1 0 9 8

BYPASS_GPMI BYPASS_GPMI

1 1 1 1 5 4 3 2

BYPASS_SSP

1 1 1 1 9 8 7 6

BYPASS_EMI

2 2 2 2 3 2 1 0

BYPASS_EMI

2 2 2 2 7 6 5 4

STMP 3700

3 3 2 2 1 0 9 8

STMP 3780 0x110

BYPASS_CPU

STMP 3700 0xe0

HW_CLKCTRL_CLKSEQ

BYPASS_CPU

7.2.18

HW_CLKCTRL_VERSION HW_CLKCTRL_VERSION 53

STMP 3700 0x100

STMP 3780 0x140

8 8.1

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

STEP

MINOR

STEP

MINOR

MAJOR

2 2 2 2 7 6 5 4

MAJOR

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

Data Co-Processor (DCP) Summary

The next table summarizes the important aspects of the Data CoProcessor device block and the main differences between the STMP 3700 and the STMP 3780. Name Data CoProcessor HW_DCP_CTRL HW_DCP_STAT HW_DCP_CHANNELCTRL HW_DCP_CAPABILITY0 HW_DCP_CAPABILITY1 HW_DCP_CONTEXT HW_DCP_KEY HW_DCP_KEYDATA HW_DCP_PACKET0 HW_DCP_PACKET1 HW_DCP_PACKET2 HW_DCP_PACKET3 HW_DCP_PACKET4 HW_DCP_PACKET5 HW_DCP_PACKET6 HW_DCP_CSCCTRL0 HW_DCP_CSCSTAT

Property Base Address Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields

54

STMP 3700 STMP 3780 0x80028000 0x0 0x10 0x20 0x30 New Field(s) 0x40 0x50 0x60 0x70 0x80 0x90 0xa0 0xb0 0xc0 0xd0 0xe0 0x300 New Field(s) 0x310 New Field(s)

Name HW_DCP_CSCOUTBUFPARAM HW_DCP_CSCINBUFPARAM HW_DCP_CSCRGB HW_DCP_CSCLUMA HW_DCP_CSCCHROMAU HW_DCP_CSCCHROMAV HW_DCP_CSCCOEFF0 HW_DCP_CSCCOEFF1 HW_DCP_CSCCOEFF2 HW_DCP_CSCCLIP HW_DCP_CSCXSCALE HW_DCP_CSCYSCALE HW_DCP_DBGSELECT HW_DCP_DBGDATA HW_DCP_PAGETABLE HW_DCP_VERSION

8.2

Programmable Registers

8.2.1

HW_DCP_CTRL

Property Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields

HW_DCP_CTRL

55

STMP 3700 STMP 3780 0x320 0x330 0x340 0x350 0x360 0x370 0x380 0x390 0x3a0 Non-Existent

0x3d0 New Field(s) 0x3e0 0x3f0

0x400 0x410 Non-Existent 0x420

0x0

0x420 New Field(s) 0x430

8.2.3 OTP_KEY_READY

CUR_CHANNEL

OTP_KEY_READY

CUR_CHANNEL

HW_DCP_STAT

1 1 1 1 9 8 7 6

56 1 1 1 1 5 4 3 2

HW_DCP_CHANNELCTRL

HW_DCP_CHANNELCTRL

0x20 IRQ

2 2 2 2 3 2 1 0

CLKGATE PRESENT_CRYPTO PRESENT_CSC

GATHER_RESIDUAL_WRITES ENABLE_CONTEXT_CACHING

CLKGATE PRESENT_CRYPTO PRESENT_CSC

GATHER_RESIDUAL_WRITES ENABLE_CONTEXT_CACHING

CSC_INTERRUPT_ENABLE

1 1 0 0 1 0 9 8

1 1 0 0 1 0 9 8

CHANNEL_INTERRUPT_ENABLE CHANNEL_INTERRUPT_ENABLE

CSC_INTERRUPT_ENABLE

1 1 1 1 5 4 3 2

IRQ

SFTRST

SFTRST

ENABLE_CONTEXT_SWITCHING ENABLE_CONTEXT_SWITCHING

STMP 3700

STMP 3780

1 1 1 1 9 8 7 6

CSCIRQ

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

CSCIRQ

3 3 2 2 1 0 9 8

2 2 2 2 7 6 5 4

READY_CHANNELS READY_CHANNELS

STMP 3700

8.2.2

STMP 3780

3 3 2 2 1 0 9 8 0 0 0 0 7 6 5 4

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

HW_DCP_STAT 0x10

0 0 0 0 3 2 1 0

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

ENABLE_CHANNEL

ENABLE_CHANNEL

0 0 0 0 3 2 1 0

HW_DCP_CAPABILITY0

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

ENABLE_TZONE

DISABLE_DECRYPT

STMP 3780

HW_DCP_CAPABILITY1 HW_DCP_CAPABILITY1

57

0x40

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

NUM_KEYS

1 1 1 1 9 8 7 6

NUM_KEYS

2 2 2 2 3 2 1 0

NUM_CHANNELS

2 2 2 2 7 6 5 4

STMP 3700

3 3 2 2 1 0 9 8

0x30

NUM_CHANNELS

HW_DCP_CAPABILITY0

8.2.5

0 0 0 0 7 6 5 4

HIGH_PRIORITY_CHANNEL HIGH_PRIORITY_CHANNEL

CH0_IRQ_MERGED CH0_IRQ_MERGED

STMP 3780 8.2.4

1 1 1 1 9 8 7 6

CSC_PRIORITY

2 2 2 2 3 2 1 0

CSC_PRIORITY

2 2 2 2 7 6 5 4

STMP 3700

3 3 2 2 1 0 9 8

HASH_ALGORITHMS HASH_ALGORITHMS

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

0 0 0 0 3 2 1 0

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0x50

1 1 1 1 5 4 3 2

ADDR

ADDR

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_DCP_KEY

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

HW_DCP_KEYDATA HW_DCP_KEYDATA

58

0x70

SUBWORD

2 2 2 2 3 2 1 0

SUBWORD

2 2 2 2 7 6 5 4

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

0x60

INDEX

HW_DCP_KEY

8.2.8

0 0 0 0 7 6 5 4

HW_DCP_CONTEXT HW_DCP_CONTEXT

8.2.7

1 1 0 0 1 0 9 8 CIPHER_ALGORITHMS CIPHER_ALGORITHMS

STMP 3700

2 2 2 2 3 2 1 0

INDEX

8.2.6

2 2 2 2 7 6 5 4

STMP 3780

3 3 2 2 1 0 9 8

8.2.11 3 3 2 2 1 0 9 8 INPUT_BYTESWAP KEY_WORDSWAP

KEY_WORDSWAP

59

HW_DCP_PACKET2

HW_DCP_PACKET2

0xa0 ENABLE_BLIT ENABLE_HASH ENABLE_CIPHER ENABLE_MEMCOPY

ENABLE_HASH

ENABLE_CIPHER

ENABLE_MEMCOPY CHAIN DECR_SEMAPHORE INTERRUPT

CHAIN

DECR_SEMAPHORE

INTERRUPT

CHAIN_CONTIGUOUS CHAIN_CONTIGUOUS

CIPHER_ENCRYPT

ENABLE_BLIT

1 1 1 1 5 4 3 2

CIPHER_ENCRYPT

HW_DCP_PACKET1

CIPHER_INIT

HASH_INIT

HASH_INIT

1 1 1 1 5 4 3 2

CIPHER_INIT

HASH_TERM

HASH_TERM

ADDR

1 1 1 1 9 8 7 6

PAYLOAD_KEY

CHECK_HASH

CHECK_HASH

ADDR

HW_DCP_PACKET0

OTP_KEY

HASH_OUTPUT

HASH_OUTPUT

DATA

DATA

1 1 1 1 5 4 3 2

PAYLOAD_KEY

CONSTANT_FILL

CONSTANT_FILL

1 1 1 1 9 8 7 6

OTP_KEY

KEY_BYTESWAP TEST_SEMA_IRQ

2 2 2 2 3 2 1 0

KEY_BYTESWAP

STMP 3780 STMP 3700

2 2 2 2 3 2 1 0

TEST_SEMA_IRQ

INPUT_WORDSWAP

1 1 1 1 9 8 7 6

INPUT_WORDSWAP

2 2 2 2 3 2 1 0

INPUT_BYTESWAP

2 2 2 2 7 6 5 4

OUTPUT_BYTESWAP

2 2 2 2 7 6 5 4

OUTPUT_BYTESWAP

STMP 3780 STMP 3700 3 3 2 2 1 0 9 8

2 2 2 2 7 6 5 4

OUTPUT_WORDSWAP OUTPUT_WORDSWAP

TAG

TAG

8.2.10

STMP 3700

8.2.9

STMP 3780

3 3 2 2 1 0 9 8

HW_DCP_PACKET0 0x80

HW_DCP_PACKET1 0x90

1 1 0 0 1 0 9 8 0 0 0 0 7 6 5 4 0 0 0 0 3 2 1 0

1 1 0 0 1 0 9 8 0 0 0 0 7 6 5 4 0 0 0 0 3 2 1 0

1 1 0 0 1 0 9 8 0 0 0 0 7 6 5 4 0 0 0 0 3 2 1 0

CIPHER_SELECT CIPHER_SELECT

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

KEY_SELECT KEY_SELECT

1 1 1 1 9 8 7 6

0 0 0 0 3 2 1 0

0xb0

1 1 1 1 5 4 3 2

ADDR

ADDR

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_DCP_PACKET4 HW_DCP_PACKET4 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

0xc0

1 1 1 1 5 4 3 2

ADDR

ADDR

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

8.2.14

0 0 0 0 7 6 5 4

HW_DCP_PACKET3 HW_DCP_PACKET3

8.2.13

1 1 0 0 1 0 9 8

CIPHER_MODE

1 1 1 1 5 4 3 2

HASH_SELECT

CIPHER_CFG CIPHER_CFG

1 1 1 1 9 8 7 6

HASH_SELECT

STMP 3700

2 2 2 2 3 2 1 0

CIPHER_MODE

8.2.12

2 2 2 2 7 6 5 4

STMP 3780

3 3 2 2 1 0 9 8

HW_DCP_PACKET5 HW_DCP_PACKET5

60

0xd0

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

0 0 0 0 3 2 1 0

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

COUNT

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

0xe0

1 1 1 1 5 4 3 2

ADDR

ADDR

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_DCP_CSCCTRL0

HW_DCP_CSCSTAT

61

0x310

ENABLE ENABLE

DELTA DELTA

HW_DCP_CSCSTAT

YUV_FORMAT YUV_FORMAT

SUBSAMPLE SUBSAMPLE

UPSAMPLE CLIP

STMP 3780

ROTATE

1 1 1 1 5 4 3 2

ROTATE

1 1 1 1 9 8 7 6

SCALE

2 2 2 2 3 2 1 0

UPSAMPLE

2 2 2 2 7 6 5 4

STMP 3700

3 3 2 2 1 0 9 8

0x300

RGB_FORMAT RGB_FORMAT

HW_DCP_CSCCTRL0

8.2.17

0 0 0 0 7 6 5 4

HW_DCP_PACKET6 HW_DCP_PACKET6

8.2.16

1 1 0 0 1 0 9 8

SCALE

8.2.15

1 1 1 1 5 4 3 2 COUNT

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

ERROR_SETUP

COMPLETE

ERROR_SETUP

COMPLETE

ERROR_SRC

ERROR_PAGEFAULT

0 0 0 0 3 2 1 0

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

0x320

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 3 2 1 0

LINE_SIZE

0 0 0 0 7 6 5 4

LINE_SIZE

STMP 3780

STMP 3700

FIELD_SIZE FIELD_SIZE

3 3 2 2 1 0 9 8

HW_DCP_CSCINBUFPARAM HW_DCP_CSCINBUFPARAM 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

0x330

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

LINE_SIZE

LINE_SIZE

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

8.2.20

0 0 0 0 7 6 5 4

HW_DCP_CSCOUTBUFPARAM HW_DCP_CSCOUTBUFPARAM

8.2.19

1 1 0 0 1 0 9 8

ERROR_DST

1 1 1 1 5 4 3 2

ERROR_CODE

STMP 3700 STMP 3780 8.2.18

1 1 1 1 9 8 7 6

ERROR_DST

2 2 2 2 3 2 1 0

ERROR_SRC

2 2 2 2 7 6 5 4

ERROR_CODE

3 3 2 2 1 0 9 8

HW_DCP_CSCRGB HW_DCP_CSCRGB

62

0x340

0 0 0 0 3 2 1 0

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

8.2.21

1 1 1 1 5 4 3 2

0 0 0 0 3 2 1 0

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

ADDR

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

0x350

1 1 1 1 5 4 3 2

ADDR

ADDR

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_DCP_CSCCHROMAU HW_DCP_CSCCHROMAU 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

0x360

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

ADDR

ADDR

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

8.2.23

0 0 0 0 7 6 5 4

HW_DCP_CSCLUMA HW_DCP_CSCLUMA

8.2.22

1 1 0 0 1 0 9 8

ADDR

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_DCP_CSCCHROMAV HW_DCP_CSCCHROMAV

63

0x370

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

0 0 0 0 3 2 1 0

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

ADDR

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

C0

STMP 3780

Y_OFFSET

C0

2 2 2 2 3 2 1 0

0x380

UV_OFFSET UV_OFFSET

2 2 2 2 7 6 5 4

STMP 3700

3 3 2 2 1 0 9 8

HW_DCP_CSCCOEFF1 HW_DCP_CSCCOEFF1

1 1 1 1 5 4 3 2

C4

C4

1 1 1 1 9 8 7 6

C1

2 2 2 2 3 2 1 0

0x390

C1

2 2 2 2 7 6 5 4

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

8.2.26

0 0 0 0 7 6 5 4

HW_DCP_CSCCOEFF0 HW_DCP_CSCCOEFF0

8.2.25

1 1 0 0 1 0 9 8

Y_OFFSET

8.2.24

1 1 1 1 5 4 3 2

ADDR

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_DCP_CSCCOEFF2 HW_DCP_CSCCOEFF2

64

0x3a0

0 0 0 0 3 2 1 0

2 2 2 2 7 6 5 4

1 1 1 1 9 8 7 6

0 0 0 0 7 6 5 4

C3

0 0 0 0 3 2 1 0

C3

C2

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

STMP 3700 Non-Existent

1 1 1 1 9 8 7 6

STMP 3780 0x3d0

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

HEIGHT

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

HW_DCP_CSCXSCALE HW_DCP_CSCXSCALE

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4 WIDTH

1 1 1 1 9 8 7 6

WIDTH

FRAC

2 2 2 2 3 2 1 0

0x3e0

FRAC

INT

INT

2 2 2 2 7 6 5 4

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

8.2.29

1 1 0 0 1 0 9 8

HW_DCP_CSCCLIP HW_DCP_CSCCLIP

8.2.28

1 1 1 1 5 4 3 2

WIDTH

8.2.27

2 2 2 2 3 2 1 0

C2

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_DCP_CSCYSCALE HW_DCP_CSCYSCALE

65

0x3f0

0 0 0 0 3 2 1 0

8.2.30

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

HW_DCP_DBGSELECT HW_DCP_DBGSELECT 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

0x400

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

INDEX

HW_DCP_DBGDATA HW_DCP_DBGDATA 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

0x410

1 1 1 1 5 4 3 2

DATA

DATA

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

8.2.32

0 0 0 0 3 2 1 0

INDEX

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

8.2.31

0 0 0 0 3 2 1 0

HEIGHT

FRAC

INT INT

0 0 0 0 7 6 5 4 HEIGHT

2 2 2 2 3 2 1 0

FRAC

2 2 2 2 7 6 5 4

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_DCP_PAGETABLE HW_DCP_PAGETABLE

STMP 3700 Non-Existent

66

STMP 3780 0x420

0 0 0 0 3 2 1 0

1 1 1 1 9 8 7 6

8.2.33

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

BASE

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

STMP 3700 0x420

1 1 1 1 9 8 7 6

STEP

1 1 0 0 1 0 9 8

STEP

MINOR

MAJOR

STMP 3780 0x430

1 1 1 1 5 4 3 2

MINOR

MAJOR

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

9.1

1 1 0 0 1 0 9 8

HW_DCP_VERSION HW_DCP_VERSION

9

1 1 1 1 5 4 3 2

ENABLE

2 2 2 2 3 2 1 0

FLUSH

2 2 2 2 7 6 5 4

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

Digital Control and On-Chip RAM Summary

The next table summarizes the important aspects of the Digital Control device block and the main differences between the STMP 3700 and the STMP 3780. Name Digital Control HW_DIGCTL_CTRL HW_DIGCTL_STATUS HW_DIGCTL_HCLKCOUNT HW_DIGCTL_RAMCTRL HW_DIGCTL_RAMREPAIR HW_DIGCTL_ROMCTRL HW_DIGCTL_WRITEONCE HW_DIGCTL_ENTROPY HW_DIGCTL_ENTROPY_LATCHED

Property Base Address Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields 67

STMP 3700 STMP 3780 0x8001c000 0x0 New Field(s) 0x10 New Field(s) 0x20 0x30 0x40 0x50 0x60 0x90 0xa0

Name HW_DIGCTL_SJTAGDBG HW_DIGCTL_MICROSECONDS HW_DIGCTL_DBGRD HW_DIGCTL_DBG HW_DIGCTL_OCRAM_BIST_CSR HW_DIGCTL_OCRAM_STATUS0 HW_DIGCTL_OCRAM_STATUS1 HW_DIGCTL_OCRAM_STATUS2 HW_DIGCTL_OCRAM_STATUS3 HW_DIGCTL_OCRAM_STATUS4 HW_DIGCTL_OCRAM_STATUS5 HW_DIGCTL_OCRAM_STATUS6 HW_DIGCTL_OCRAM_STATUS7 HW_DIGCTL_OCRAM_STATUS8 HW_DIGCTL_OCRAM_STATUS9 HW_DIGCTL_OCRAM_STATUS10 HW_DIGCTL_OCRAM_STATUS11 HW_DIGCTL_OCRAM_STATUS12 HW_DIGCTL_OCRAM_STATUS13 HW_DIGCTL_SCRATCH0 HW_DIGCTL_SCRATCH1 HW_DIGCTL_ARMCACHE HW_DIGCTL_DEBUG_TRAP HW_DIGCTL_SGTL HW_DIGCTL_CHIPID HW_DIGCTL_AHB_STATS_SELECT HW_DIGCTL_L0_AHB_ACTIVE_CYCLES HW_DIGCTL_L0_AHB_DATA_STALLED

Property Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address 68

STMP 3700

STMP 3780 0xb0 0xc0 0xd0 0xe0 0xf0 New Field(s) 0x110 0x120 0x130 0x140 0x150 0x160 0x170 0x180

0x190 Incompatible Field(s) Incompatible Field(s) 0x1a0 Incompatible Field(s) Incompatible Field(s) 0x1b0 Incompatible Field(s) Incompatible Field(s) 0x1c0 Incompatible Field(s) Incompatible Field(s) 0x1d0 Incompatible Field(s) Incompatible Field(s) 0x1e0 Incompatible Field(s) Incompatible Field(s) 0x290 0x2a0 0x2b0 New Field(s) 0x2d0 0x300 0x310 0x330 0x340 0x350

Property Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields

9.2.2

ANALOG_TESTMODE

DIGITAL_TESTMODE

ARM_BIST_START

UART_LOOPBACK

SAIF_LOOPBACK

SAIF_CLKMUX_SEL

ANALOG_TESTMODE

DIGITAL_TESTMODE

ARM_BIST_START

UART_LOOPBACK

SAIF_LOOPBACK

SAIF_CLKMUX_SEL

69

0x10

0 0 0 0 3 2 1 0

LATCH_ENTROPY

USB_TESTMODE USB_TESTMODE

HW_DIGCTL_STATUS

0 0 0 0 7 6 5 4

LATCH_ENTROPY

ARM_BIST_CLKEN ARM_BIST_CLKEN

HW_DIGCTL_STATUS

1 1 0 0 1 0 9 8

USB_CLKGATE

DCP_BIST_START

1 1 1 1 5 4 3 2

DCP_BIST_START

1 1 1 1 9 8 7 6

DCP_BIST_CLKEN LCD_BIST_START

LCD_BIST_CLKEN

CACHE_BIST_TMODE

2 2 2 2 3 2 1 0

DCP_BIST_CLKEN

2 2 2 2 7 6 5 4

TRAP_IRQ TRAP_IRQ

XTAL24M_GATE

STMP 3780

STMP 3700

3 3 2 2 1 0 9 8

0x0

JTAG_SHIELD

HW_DIGCTL_CTRL

JTAG_SHIELD

HW_DIGCTL_CTRL

USB_CLKGATE

9.2.1

DEBUG_DISABLE

Programmable Registers

0x500

DEBUG_DISABLE

9.2

0x480

TRAP_ENABLE

HW_DIGCTL_EMICLK_DELAY

0x3f0

TRAP_IN_RANGE

HW_DIGCTL_L3_AHB_DATA_CYCLES

0x3e0

TRAP_ENABLE

HW_DIGCTL_L3_AHB_DATA_STALLED

0x3d0

TRAP_IN_RANGE

HW_DIGCTL_L3_AHB_ACTIVE_CYCLES

0x3c0

USE_SERIAL_JTAG

HW_DIGCTL_L2_AHB_DATA_CYCLES

0x3b0

USE_SERIAL_JTAG

HW_DIGCTL_L2_AHB_DATA_STALLED

0x3a0

SY_CLKGATE

HW_DIGCTL_L2_AHB_ACTIVE_CYCLES

0x390

SY_SFTRST

HW_DIGCTL_L1_AHB_DATA_CYCLES

0x380

SY_ENDIAN

HW_DIGCTL_L1_AHB_DATA_STALLED

0x370

SAIF_ALT_BITCLK_SEL SAIF_ALT_BITCLK_SEL

HW_DIGCTL_L1_AHB_ACTIVE_CYCLES

STMP 3780 0x360

SAIF_CLKMST_SEL

HW_DIGCTL_L0_AHB_DATA_CYCLES

STMP 3700

SAIF_CLKMST_SEL

Name

WRITTEN WRITTEN

PACKAGE_TYPE

0 0 0 0 3 2 1 0

PACKAGE_TYPE

JTAG_IN_USE LCD_BIST_DONE

JTAG_IN_USE

LCD_BIST_PASS

DCP_BIST_DONE DCP_BIST_DONE

LCD_BIST_FAIL

DCP_BIST_PASS

0 0 0 0 7 6 5 4

HW_DIGCTL_HCLKCOUNT HW_DIGCTL_HCLKCOUNT 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

0x20

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

COUNT

COUNT

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_DIGCTL_RAMCTRL HW_DIGCTL_RAMCTRL 2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

0x30

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8 SPEED_SELECT

2 2 2 2 7 6 5 4

SPEED_SELECT

STMP 3700

3 3 2 2 1 0 9 8

STMP 3780

9.2.4

1 1 0 0 1 0 9 8

DCP_BIST_PASS

USB_HOST_PRESENT USB_HOST_PRESENT

1 1 1 1 5 4 3 2

DCP_BIST_FAIL

USB_OTG_PRESENT USB_OTG_PRESENT

1 1 1 1 9 8 7 6

DCP_BIST_FAIL

USB_HS_PRESENT USB_HS_PRESENT

2 2 2 2 3 2 1 0

USB_DEVICE_PRESENT USB_DEVICE_PRESENT

STMP 3700

2 2 2 2 7 6 5 4

70

RAM_REPAIR_EN RAM_REPAIR_EN

9.2.3

STMP 3780

3 3 2 2 1 0 9 8

9.2.5

HW_DIGCTL_RAMREPAIR HW_DIGCTL_RAMREPAIR 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

9.2.6

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

ADDR

ADDR

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

0x40

HW_DIGCTL_ROMCTRL HW_DIGCTL_ROMCTRL 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

STMP 3780

STMP 3700

RD_MARGIN RD_MARGIN

3 3 2 2 1 0 9 8

0x50

9.2.7

HW_DIGCTL_WRITEONCE HW_DIGCTL_WRITEONCE 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

9.2.8

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

BITS

BITS

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

0x60

HW_DIGCTL_ENTROPY HW_DIGCTL_ENTROPY

71

0x90

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

STMP 3700 STMP 3780

1 1 0 0 1 0 9 8

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

HW_DIGCTL_ENTROPY_LATCHED HW_DIGCTL_ENTROPY_LATCHED 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

0xa0 1 1 0 0 1 0 9 8

VALUE

VALUE

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_DIGCTL_SJTAGDBG

72

SJTAG_PIN_STATE SJTAG_PIN_STATE

SJTAG_DEBUG_OE

ACTIVE ACTIVE

SJTAG_DEBUG_OE

DELAYED_ACTIVE DELAYED_ACTIVE

SJTAG_DEBUG_DATA SJTAG_DEBUG_DATA

SJTAG_MODE

1 1 0 0 1 0 9 8

SJTAG_MODE

1 1 1 1 5 4 3 2

SJTAG_TDI

1 1 1 1 9 8 7 6

SJTAG_TDI

SJTAG_STATE

2 2 2 2 3 2 1 0

SJTAG_STATE

2 2 2 2 7 6 5 4

STMP 3700

3 3 2 2 1 0 9 8

0xb0

SJTAG_TDO

HW_DIGCTL_SJTAGDBG

STMP 3780

9.2.10

0 0 0 0 7 6 5 4

SJTAG_TDO

9.2.9

1 1 1 1 5 4 3 2 LATCHED_VALUE LATCHED_VALUE

3 3 2 2 1 0 9 8

9.2.11

HW_DIGCTL_MICROSECONDS HW_DIGCTL_MICROSECONDS 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

9.2.12

1 1 1 1 5 4 3 2

0 0 0 0 3 2 1 0

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

VALUE

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

0xd0

1 1 1 1 5 4 3 2

STMP 3780

STMP 3700

COMPLEMENT COMPLEMENT

3 3 2 2 1 0 9 8

HW_DIGCTL_DBG HW_DIGCTL_DBG 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

0xe0

1 1 1 1 5 4 3 2

VALUE

VALUE

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

9.2.14

0 0 0 0 7 6 5 4

HW_DIGCTL_DBGRD HW_DIGCTL_DBGRD

9.2.13

1 1 0 0 1 0 9 8

VALUE

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

0xc0

HW_DIGCTL_OCRAM_BIST_CSR HW_DIGCTL_OCRAM_BIST_CSR

73

0xf0

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

PASS

DONE

START START

0x110 1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

STMP 3780

STMP 3700

FAILDATA00 FAILDATA00

3 3 2 2 1 0 9 8

HW_DIGCTL_OCRAM_STATUS1 HW_DIGCTL_OCRAM_STATUS1 2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

0x120 1 1 0 0 1 0 9 8

FAILDATA01 FAILDATA01

2 2 2 2 7 6 5 4

STMP 3780

STMP 3700

3 3 2 2 1 0 9 8

9.2.17

DONE

HW_DIGCTL_OCRAM_STATUS0 HW_DIGCTL_OCRAM_STATUS0

9.2.16

0 0 0 0 3 2 1 0

PASS

BIST_DEBUG_MODE

STMP 3780 9.2.15

0 0 0 0 7 6 5 4

FAIL

1 1 0 0 1 0 9 8

FAIL

1 1 1 1 5 4 3 2

BIST_CLKEN

1 1 1 1 9 8 7 6

BIST_CLKEN

2 2 2 2 3 2 1 0

BIST_DATA_CHANGE BIST_DATA_CHANGE

2 2 2 2 7 6 5 4

STMP 3700

3 3 2 2 1 0 9 8

HW_DIGCTL_OCRAM_STATUS2 HW_DIGCTL_OCRAM_STATUS2

74

0x130

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

STMP 3700 STMP 3780 9.2.18

1 1 1 1 5 4 3 2

0 0 0 0 3 2 1 0

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0x140 1 1 0 0 1 0 9 8

STMP 3780

STMP 3700

FAILDATA11 FAILDATA11

3 3 2 2 1 0 9 8

HW_DIGCTL_OCRAM_STATUS4 HW_DIGCTL_OCRAM_STATUS4 2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

0x150 1 1 0 0 1 0 9 8

FAILDATA20 FAILDATA20

2 2 2 2 7 6 5 4

STMP 3780

STMP 3700

3 3 2 2 1 0 9 8

9.2.20

0 0 0 0 7 6 5 4

HW_DIGCTL_OCRAM_STATUS3 HW_DIGCTL_OCRAM_STATUS3

9.2.19

1 1 0 0 1 0 9 8

FAILDATA10 FAILDATA10

3 3 2 2 1 0 9 8

HW_DIGCTL_OCRAM_STATUS5 HW_DIGCTL_OCRAM_STATUS5

75

0x160

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

STMP 3700 STMP 3780 9.2.21

1 1 1 1 5 4 3 2

0 0 0 0 3 2 1 0

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0x170 1 1 0 0 1 0 9 8

STMP 3780

STMP 3700

FAILDATA30 FAILDATA30

3 3 2 2 1 0 9 8

HW_DIGCTL_OCRAM_STATUS7 HW_DIGCTL_OCRAM_STATUS7 2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

0x180 1 1 0 0 1 0 9 8

FAILDATA31 FAILDATA31

2 2 2 2 7 6 5 4

STMP 3780

STMP 3700

3 3 2 2 1 0 9 8

9.2.23

0 0 0 0 7 6 5 4

HW_DIGCTL_OCRAM_STATUS6 HW_DIGCTL_OCRAM_STATUS6

9.2.22

1 1 0 0 1 0 9 8

FAILDATA21 FAILDATA21

3 3 2 2 1 0 9 8

HW_DIGCTL_OCRAM_STATUS8 HW_DIGCTL_OCRAM_STATUS8

76

0x190

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 5 4 3 2

FAILADDR00

0 0 0 0 3 2 1 0

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

FAILADDR00

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

0x1a0 1 1 0 0 1 0 9 8

FAILADDR10

STMP 3780

0 0 0 0 3 2 1 0

FAILADDR10

0 0 0 0 7 6 5 4

FAILADDR11

STMP 3700

FAILADDR11

3 3 2 2 1 0 9 8

HW_DIGCTL_OCRAM_STATUS10 HW_DIGCTL_OCRAM_STATUS10 2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4 FAILADDR20

FAILADDR21

FAILADDR20

2 2 2 2 7 6 5 4

0x1b0

FAILADDR21

STMP 3780

STMP 3700

3 3 2 2 1 0 9 8

9.2.26

0 0 0 0 7 6 5 4

HW_DIGCTL_OCRAM_STATUS9 HW_DIGCTL_OCRAM_STATUS9

9.2.25

1 1 0 0 1 0 9 8

FAILADDR01

STMP 3700 STMP 3780 9.2.24

1 1 1 1 9 8 7 6

FAILADDR01

3 3 2 2 1 0 9 8

HW_DIGCTL_OCRAM_STATUS11 HW_DIGCTL_OCRAM_STATUS11

77

0x1c0

0 0 0 0 3 2 1 0

2 2 2 2 7 6 5 4

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

FAILADDR30

0 0 0 0 3 2 1 0

FAILADDR30

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

FAILSTATE00

FAILSTATE10 FAILSTATE10

FAILSTATE00

FAILSTATE11

STMP 3700 STMP 3780

1 1 1 1 9 8 7 6

FAILSTATE01

2 2 2 2 3 2 1 0

0x1d0

FAILSTATE01

2 2 2 2 7 6 5 4 FAILSTATE11

3 3 2 2 1 0 9 8

HW_DIGCTL_OCRAM_STATUS13

1 1 0 0 1 0 9 8

FAILSTATE21

HW_DIGCTL_SCRATCH0 HW_DIGCTL_SCRATCH0

78

0x290

FAILSTATE20

1 1 1 1 5 4 3 2

FAILSTATE21

1 1 1 1 9 8 7 6 FAILSTATE30

2 2 2 2 3 2 1 0

FAILSTATE30

FAILSTATE31

2 2 2 2 7 6 5 4

FAILSTATE31

STMP 3780

STMP 3700

3 3 2 2 1 0 9 8

0x1e0

FAILSTATE20

HW_DIGCTL_OCRAM_STATUS13

9.2.29

0 0 0 0 7 6 5 4

HW_DIGCTL_OCRAM_STATUS12 HW_DIGCTL_OCRAM_STATUS12

9.2.28

1 1 0 0 1 0 9 8

FAILADDR31

STMP 3700 STMP 3780 9.2.27

2 2 2 2 3 2 1 0 FAILADDR31

3 3 2 2 1 0 9 8

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

PTR

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

0x2a0

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

PTR

PTR

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_DIGCTL_ARMCACHE

HW_DIGCTL_DEBUG_TRAP HW_DIGCTL_DEBUG_TRAP

79

0x2d0

ITAG_SS ITAG_SS

1 1 0 0 1 0 9 8

DTAG_SS

1 1 1 1 5 4 3 2

DTAG_SS

1 1 1 1 9 8 7 6

CACHE_SS

2 2 2 2 3 2 1 0

VALID_SS

2 2 2 2 7 6 5 4

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

0x2b0

CACHE_SS

HW_DIGCTL_ARMCACHE

9.2.32

0 0 0 0 7 6 5 4

HW_DIGCTL_SCRATCH1 HW_DIGCTL_SCRATCH1

9.2.31

1 1 0 0 1 0 9 8

DRTY_SS

9.2.30

1 1 1 1 5 4 3 2

PTR

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

STMP 3700 STMP 3780 9.2.33

1 1 1 1 5 4 3 2

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

HW_DIGCTL_SGTL HW_DIGCTL_SGTL 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

0x300

1 1 1 1 5 4 3 2

STMP 3780

STMP 3700

COPYRIGHT COPYRIGHT

3 3 2 2 1 0 9 8

HW_DIGCTL_CHIPID HW_DIGCTL_CHIPID 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

0x310

1 1 1 1 5 4 3 2

REVISION

REVISION

PRODUCT_CODE PRODUCT_CODE

STMP 3700

3 3 2 2 1 0 9 8

STMP 3780

9.2.34

1 1 0 0 1 0 9 8

ADDR_HIGH_ADDR ADDR_HIGH_ADDR

3 3 2 2 1 0 9 8

80

HW_DIGCTL_AHB_STATS_SELECT HW_DIGCTL_AHB_STATS_SELECT 1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

HW_DIGCTL_L0_AHB_ACTIVE_CYCLES HW_DIGCTL_L0_AHB_ACTIVE_CYCLES 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

0x340 1 1 0 0 1 0 9 8

COUNT

COUNT

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_DIGCTL_L0_AHB_DATA_STALLED HW_DIGCTL_L0_AHB_DATA_STALLED 3 3 2 2 1 0 9 8

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

COUNT

COUNT

STMP 3780 STMP 3700

9.2.37

1 1 0 0 1 0 9 8 L1_MASTER_SELECT L1_MASTER_SELECT

2 2 2 2 3 2 1 0

L2_MASTER_SELECT L2_MASTER_SELECT

STMP 3700 STMP 3780 9.2.36

2 2 2 2 7 6 5 4 L3_MASTER_SELECT L3_MASTER_SELECT

3 3 2 2 1 0 9 8

0x330

L0_MASTER_SELECT L0_MASTER_SELECT

9.2.35

81

0x350 1 1 0 0 1 0 9 8

9.2.38

HW_DIGCTL_L0_AHB_DATA_CYCLES HW_DIGCTL_L0_AHB_DATA_CYCLES 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

9.2.39

1 1 1 1 5 4 3 2

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

COUNT

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

0x370 1 1 0 0 1 0 9 8

COUNT

COUNT

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_DIGCTL_L1_AHB_DATA_STALLED HW_DIGCTL_L1_AHB_DATA_STALLED 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

0x380 1 1 0 0 1 0 9 8

COUNT

COUNT

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

9.2.41

0 0 0 0 7 6 5 4

HW_DIGCTL_L1_AHB_ACTIVE_CYCLES HW_DIGCTL_L1_AHB_ACTIVE_CYCLES

9.2.40

1 1 0 0 1 0 9 8

COUNT

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

0x360

HW_DIGCTL_L1_AHB_DATA_CYCLES HW_DIGCTL_L1_AHB_DATA_CYCLES

82

0x390

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

9.2.42

1 1 1 1 5 4 3 2

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

COUNT

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

0x3a0 1 1 0 0 1 0 9 8

COUNT

COUNT

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_DIGCTL_L2_AHB_DATA_STALLED HW_DIGCTL_L2_AHB_DATA_STALLED 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

0x3b0 1 1 0 0 1 0 9 8

COUNT

COUNT

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

9.2.44

0 0 0 0 7 6 5 4

HW_DIGCTL_L2_AHB_ACTIVE_CYCLES HW_DIGCTL_L2_AHB_ACTIVE_CYCLES

9.2.43

1 1 0 0 1 0 9 8

COUNT

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_DIGCTL_L2_AHB_DATA_CYCLES HW_DIGCTL_L2_AHB_DATA_CYCLES

83

0x3c0

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

9.2.45

1 1 1 1 5 4 3 2

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

COUNT

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

0x3d0 1 1 0 0 1 0 9 8

COUNT

COUNT

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_DIGCTL_L3_AHB_DATA_STALLED HW_DIGCTL_L3_AHB_DATA_STALLED 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

0x3e0 1 1 0 0 1 0 9 8

COUNT

COUNT

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

9.2.47

0 0 0 0 7 6 5 4

HW_DIGCTL_L3_AHB_ACTIVE_CYCLES HW_DIGCTL_L3_AHB_ACTIVE_CYCLES

9.2.46

1 1 0 0 1 0 9 8

COUNT

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_DIGCTL_L3_AHB_DATA_CYCLES HW_DIGCTL_L3_AHB_DATA_CYCLES

84

0x3f0

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

9.2.48

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

COUNT

COUNT

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_DIGCTL_EMICLK_DELAY HW_DIGCTL_EMICLK_DELAY 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

STMP 3780 0x500 1 1 0 0 1 0 9 8

10 10.1

NUM_TAPS

NUM_TAPS

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

STMP 3700 0x480

DRAM Registers Summary

The next table summarizes the important aspects of the DRAM Registers device block and the main differences between the STMP 3700 and the STMP 3780. Name DRAM Registers HW_DRAM_CTL00 HW_DRAM_CTL01 HW_DRAM_CTL02 HW_DRAM_CTL03 HW_DRAM_CTL04 HW_DRAM_CTL05 HW_DRAM_CTL06 HW_DRAM_CTL07 HW_DRAM_CTL08

Property Base Address Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields 85

STMP 3700 STMP 3780 0x800e0000 0x0 0x4 0x8 0xc 0x10 0x14 0x18 0x1c 0x20

Name HW_DRAM_CTL09 HW_DRAM_CTL10 HW_DRAM_CTL11 HW_DRAM_CTL12 HW_DRAM_CTL13 HW_DRAM_CTL14 HW_DRAM_CTL15 HW_DRAM_CTL16 HW_DRAM_CTL17 HW_DRAM_CTL18 HW_DRAM_CTL19 HW_DRAM_CTL20 HW_DRAM_CTL21 HW_DRAM_CTL22 HW_DRAM_CTL23 HW_DRAM_CTL24 HW_DRAM_CTL25 HW_DRAM_CTL26 HW_DRAM_CTL27 HW_DRAM_CTL28 HW_DRAM_CTL29 HW_DRAM_CTL30 HW_DRAM_CTL31 HW_DRAM_CTL32 HW_DRAM_CTL33 HW_DRAM_CTL34 HW_DRAM_CTL35 HW_DRAM_CTL36

Property Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address 86

STMP 3700 STMP 3780 0x24 0x28 0x2c 0x30 New Field(s) 0x34 0x38 0x3c 0x40 0x44 0x48 0x4c 0x50 0x54 New Field(s) 0x58 0x5c 0x60 0x64 0x68 New Field(s) 0x6c New Field(s) 0x70 New Field(s) 0x74 0x78 0x7c 0x80 0x84 0x88 0x8c 0x90

HW_DRAM_CTL39 HW_DRAM_CTL40

10.2

Programmable Registers

10.2.1

HW_DRAM_CTL00

0x94 New Field(s) 0x98 0x9c 0xa0

HW_DRAM_CTL00

10.2.2

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

AHB0_R_PRIORITY

AHB0_W_PRIORITY AHB0_W_PRIORITY

2 2 2 2 3 2 1 0

0x0

AHB0_R_PRIORITY

STMP 3700

2 2 2 2 7 6 5 4

STMP 3780

3 3 2 2 1 0 9 8

HW_DRAM_CTL01 HW_DRAM_CTL01

87

STMP 3780

1 1 0 0 1 0 9 8

0x4

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

ADDR_CMP_EN

HW_DRAM_CTL38

STMP 3700

ADDR_CMP_EN

HW_DRAM_CTL37

Property Fields Address Fields Address Fields Address Fields Address Fields

AHB0_FIFO_TYPE_REG AHB0_FIFO_TYPE_REG

Name

10.2.4 AHB3_R_PRIORITY

AHB3_R_PRIORITY

HW_DRAM_CTL02

88 1 1 1 1 5 4 3 2

HW_DRAM_CTL03

HW_DRAM_CTL03

0xc AHB2_R_PRIORITY

1 1 1 1 9 8 7 6

STMP 3700

AHB1_R_PRIORITY

AHB1_W_PRIORITY

AHB1_R_PRIORITY

AHB1_W_PRIORITY

AHB2_FIFO_TYPE_REG AHB2_FIFO_TYPE_REG

STMP 3780

1 1 1 1 5 4 3 2

AHB2_R_PRIORITY

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

AHB2_W_PRIORITY

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

AHB2_W_PRIORITY

3 3 2 2 1 0 9 8

2 2 2 2 7 6 5 4

AHB3_FIFO_TYPE_REG AHB3_FIFO_TYPE_REG

STMP 3700

10.2.3

STMP 3780

3 3 2 2 1 0 9 8 1 1 0 0 1 0 9 8

HW_DRAM_CTL02 0x8

1 1 0 0 1 0 9 8

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4 0 0 0 0 3 2 1 0

AHB1_FIFO_TYPE_REG AHB1_FIFO_TYPE_REG

0 0 0 0 7 6 5 4

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

AHB3_W_PRIORITY

AP

HW_DRAM_CTL04

HW_DRAM_CTL05 HW_DRAM_CTL05

89

0x14

BANK_SPLIT_EN

1 1 0 0 1 0 9 8

BANK_SPLIT_EN

1 1 1 1 5 4 3 2

CONCURRENTAP

1 1 1 1 9 8 7 6

DLLLOCKREG

2 2 2 2 3 2 1 0

DLLLOCKREG

STMP 3780

DLL_BYPASS_MODE DLL_BYPASS_MODE

2 2 2 2 7 6 5 4

STMP 3700

3 3 2 2 1 0 9 8

0x10

CONCURRENTAP

HW_DRAM_CTL04

10.2.6

1 1 0 0 1 0 9 8

AHB3_W_PRIORITY

1 1 1 1 5 4 3 2

AREFRESH

1 1 1 1 9 8 7 6

AREFRESH

STMP 3700 STMP 3780 10.2.5

2 2 2 2 3 2 1 0

AP

2 2 2 2 7 6 5 4 AUTO_REFRESH_MODE AUTO_REFRESH_MODE

3 3 2 2 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

FAST_WRITE FAST_WRITE

HW_DRAM_CTL06

1 1 1 1 5 4 3 2

HW_DRAM_CTL07 HW_DRAM_CTL07

90

0x1c

1 1 0 0 1 0 9 8

INTRPTWRITEA

1 1 1 1 9 8 7 6

INTRPTWRITEA

POWER_DOWN POWER_DOWN

2 2 2 2 3 2 1 0

PLACEMENT_EN PLACEMENT_EN

STMP 3700

2 2 2 2 7 6 5 4

STMP 3780

3 3 2 2 1 0 9 8

0x18

NO_CMD_INIT

HW_DRAM_CTL06

10.2.8

1 1 0 0 1 0 9 8

EN_LOWPOWER_MODE EN_LOWPOWER_MODE

1 1 1 1 5 4 3 2

INTRPTAPBURST

INTRPTREADA INTRPTREADA

1 1 1 1 9 8 7 6

INTRPTAPBURST

STMP 3700

2 2 2 2 3 2 1 0

NO_CMD_INIT

10.2.7

2 2 2 2 7 6 5 4

STMP 3780

3 3 2 2 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

PRIORITY_EN

RD2RD_TURN

HW_DRAM_CTL08

HW_DRAM_CTL09 HW_DRAM_CTL09

91

0x24

1 1 0 0 1 0 9 8

SDR_MODE

1 1 1 1 5 4 3 2

SDR_MODE

1 1 1 1 9 8 7 6

START

2 2 2 2 3 2 1 0

START

STMP 3780

TRAS_LOCKOUT TRAS_LOCKOUT

2 2 2 2 7 6 5 4

STMP 3700

3 3 2 2 1 0 9 8

0x20

SREFRESH

HW_DRAM_CTL08

10.2.10

1 1 0 0 1 0 9 8

PRIORITY_EN

1 1 1 1 5 4 3 2

RD2RD_TURN

RW_SAME_EN RW_SAME_EN

1 1 1 1 9 8 7 6 REG_DIMM_ENABLE REG_DIMM_ENABLE

STMP 3700

2 2 2 2 3 2 1 0

SREFRESH

10.2.9

2 2 2 2 7 6 5 4

STMP 3780

3 3 2 2 1 0 9 8

1 1 1 1 5 4 3 2

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

WRITEINTERP

WRITE_MODEREG

0 0 0 0 7 6 5 4

WRITEINTERP

HW_DRAM_CTL10 HW_DRAM_CTL10 1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

TEMRS

ADDR_PINS

TEMRS

AGE_COUNT AGE_COUNT

2 2 2 2 3 2 1 0

0x28

ADDR_PINS

STMP 3700

2 2 2 2 7 6 5 4

STMP 3780

3 3 2 2 1 0 9 8

10.2.12

1 1 0 0 1 0 9 8

WRITE_MODEREG

OUT_OF_RANGE_TYPE OUT_OF_RANGE_TYPE

1 1 1 1 9 8 7 6 OUT_OF_RANGE_SOURCE_ID OUT_OF_RANGE_SOURCE_ID

STMP 3700

2 2 2 2 3 2 1 0

HW_DRAM_CTL11 HW_DRAM_CTL11

92

0x2c

Q_FULLNESS Q_FULLNESS

10.2.11

2 2 2 2 7 6 5 4

STMP 3780

3 3 2 2 1 0 9 8

1 1 1 1 5 4 3 2

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

CASLAT

COLUMN_SIZE

0 0 0 0 7 6 5 4

CASLAT

HW_DRAM_CTL12 HW_DRAM_CTL12

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

TCKE

1 1 1 1 9 8 7 6

OBSOLETE

TRRD

2 2 2 2 3 2 1 0

0x30

TRRD

TWR_INT

TWR_INT

2 2 2 2 7 6 5 4

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

10.2.14

1 1 0 0 1 0 9 8

COLUMN_SIZE

MAX_CS_REG MAX_CS_REG

1 1 1 1 9 8 7 6 COMMAND_AGE_COUNT COMMAND_AGE_COUNT

STMP 3700

2 2 2 2 3 2 1 0

HW_DRAM_CTL13 HW_DRAM_CTL13

93

0x34

TCKE

10.2.13

2 2 2 2 7 6 5 4

STMP 3780

3 3 2 2 1 0 9 8

1 1 1 1 5 4 3 2

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

TWTR TWTR

HW_DRAM_CTL14

HW_DRAM_CTL15 HW_DRAM_CTL15

94

0x3c

1 1 0 0 1 0 9 8

CS_MAP

1 1 1 1 5 4 3 2

CS_MAP

1 1 1 1 9 8 7 6

INITAREF

MAX_COL_REG MAX_COL_REG

2 2 2 2 3 2 1 0

LOWPOWER_REFRESH_ENABLE LOWPOWER_REFRESH_ENABLE

STMP 3700

2 2 2 2 7 6 5 4

STMP 3780

3 3 2 2 1 0 9 8

0x38

INITAREF

HW_DRAM_CTL14

10.2.16

1 1 0 0 1 0 9 8

APREBIT

CASLAT_LIN

1 1 1 1 9 8 7 6

CASLAT_LIN

STMP 3700 STMP 3780 10.2.15

2 2 2 2 3 2 1 0

APREBIT

2 2 2 2 7 6 5 4 CASLAT_LIN_GATE CASLAT_LIN_GATE

3 3 2 2 1 0 9 8

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

MAX_ROW_REG MAX_ROW_REG

0 0 0 0 7 6 5 4

PORT_BUSY

HW_DRAM_CTL16

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8 LOWPOWER_AUTO_ENABLE LOWPOWER_AUTO_ENABLE

1 1 1 1 9 8 7 6

LOWPOWER_CONTROL

TMRD TMRD

2 2 2 2 3 2 1 0

LOWPOWER_CONTROL

STMP 3700

2 2 2 2 7 6 5 4

STMP 3780

3 3 2 2 1 0 9 8

0x40

HW_DRAM_CTL17 HW_DRAM_CTL17

95

0x44

INT_ACK

HW_DRAM_CTL16

10.2.18

1 1 0 0 1 0 9 8 PORT_BUSY

1 1 1 1 5 4 3 2

TDAL

TRP TRP

1 1 1 1 9 8 7 6

TDAL

STMP 3700

2 2 2 2 3 2 1 0

INT_ACK

10.2.17

2 2 2 2 7 6 5 4

STMP 3780

3 3 2 2 1 0 9 8

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

TRC TRC

DLL_INCREMENT

DLL_LOCK

HW_DRAM_CTL18

HW_DRAM_CTL19 HW_DRAM_CTL19

96

0x4c

INT_MASK

1 1 1 1 5 4 3 2

INT_MASK

1 1 1 1 9 8 7 6

INT_STATUS

2 2 2 2 3 2 1 0

DLL_DQS_DELAY_0 DLL_DQS_DELAY_0

2 2 2 2 7 6 5 4 DLL_DQS_DELAY_1 DLL_DQS_DELAY_1

STMP 3780

STMP 3700

3 3 2 2 1 0 9 8

0x48

INT_STATUS

HW_DRAM_CTL18

10.2.20

1 1 0 0 1 0 9 8 DLL_INCREMENT

2 2 2 2 3 2 1 0

DLL_LOCK

STMP 3700 STMP 3780 10.2.19

2 2 2 2 7 6 5 4 DLL_START_POINT DLL_START_POINT

3 3 2 2 1 0 9 8

0 0 0 0 7 6 5 4

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

DLL_DQS_DELAY_BYPASS_0 DLL_DQS_DELAY_BYPASS_0

0 0 0 0 3 2 1 0

HW_DRAM_CTL20

1 1 1 1 5 4 3 2 WR_DQS_SHIFT_BYPASS WR_DQS_SHIFT_BYPASS

1 1 1 1 9 8 7 6

TRAS_MIN

TRCD_INT TRCD_INT

2 2 2 2 3 2 1 0

TRAS_MIN

STMP 3700

2 2 2 2 7 6 5 4

STMP 3780

3 3 2 2 1 0 9 8

0x50

HW_DRAM_CTL21 HW_DRAM_CTL21

97

0x54

0 0 0 0 3 2 1 0

WR_DQS_SHIFT

HW_DRAM_CTL20

10.2.22

1 1 0 0 1 0 9 8 DLL_DQS_DELAY_BYPASS_1 DLL_DQS_DELAY_BYPASS_1

1 1 1 1 5 4 3 2

DQS_OUT_SHIFT

DQS_OUT_SHIFT_BYPASS DQS_OUT_SHIFT_BYPASS

1 1 1 1 9 8 7 6

DQS_OUT_SHIFT

STMP 3700

2 2 2 2 3 2 1 0

WR_DQS_SHIFT

10.2.21

2 2 2 2 7 6 5 4

STMP 3780

3 3 2 2 1 0 9 8

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

TRFC

0 0 0 0 3 2 1 0

HW_DRAM_CTL22 HW_DRAM_CTL22 1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

AHB0_RDCNT AHB0_RDCNT

STMP 3780

2 2 2 2 3 2 1 0

0x58

AHB0_WRCNT AHB0_WRCNT

2 2 2 2 7 6 5 4

STMP 3700

3 3 2 2 1 0 9 8

10.2.24

0 0 0 0 7 6 5 4

TRFC

OBSOLETE

STMP 3780 10.2.23

1 1 0 0 1 0 9 8

OUT_OF_RANGE_LENGTH OUT_OF_RANGE_LENGTH

2 2 2 2 7 6 5 4

STMP 3700

3 3 2 2 1 0 9 8

HW_DRAM_CTL23 HW_DRAM_CTL23

98

0x5c

0 0 0 0 3 2 1 0

2 2 2 2 7 6 5 4

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

AHB1_RDCNT

0 0 0 0 3 2 1 0

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

0x60

1 1 1 1 5 4 3 2

AHB2_RDCNT

0 0 0 0 3 2 1 0

AHB2_RDCNT

STMP 3780

STMP 3700

AHB2_WRCNT AHB2_WRCNT

3 3 2 2 1 0 9 8

HW_DRAM_CTL25 HW_DRAM_CTL25 1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

AHB3_RDCNT AHB3_RDCNT

STMP 3780

2 2 2 2 3 2 1 0

0x64

AHB3_WRCNT AHB3_WRCNT

2 2 2 2 7 6 5 4

STMP 3700

3 3 2 2 1 0 9 8

10.2.27

0 0 0 0 7 6 5 4

HW_DRAM_CTL24 HW_DRAM_CTL24

10.2.26

1 1 0 0 1 0 9 8

AHB1_RDCNT

STMP 3700 STMP 3780 10.2.25

2 2 2 2 3 2 1 0 AHB1_WRCNT AHB1_WRCNT

3 3 2 2 1 0 9 8

HW_DRAM_CTL26 HW_DRAM_CTL26

99

0x68

0 0 0 0 3 2 1 0

2 2 2 2 7 6 5 4

10.2.28

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 3 2 1 0

TREF

OBSOLETE

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

0x6c

1 1 1 1 5 4 3 2

OBSOLETE

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_DRAM_CTL28 HW_DRAM_CTL28 2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

0x70

1 1 1 1 5 4 3 2

OBSOLETE

2 2 2 2 7 6 5 4

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

10.2.30

0 0 0 0 7 6 5 4

HW_DRAM_CTL27 HW_DRAM_CTL27

10.2.29

1 1 0 0 1 0 9 8

TREF

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_DRAM_CTL29 HW_DRAM_CTL29

100

0x74

10.2.31

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4 LOWPOWER_EXTERNAL_CNT LOWPOWER_EXTERNAL_CNT

LOWPOWER_INTERNAL_CNT LOWPOWER_INTERNAL_CNT

2 2 2 2 3 2 1 0

STMP 3700

2 2 2 2 7 6 5 4

STMP 3780

3 3 2 2 1 0 9 8

HW_DRAM_CTL30 HW_DRAM_CTL30

101

0x78

0 0 0 0 3 2 1 0

10.2.32

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4 LOWPOWER_POWER_DOWN_CNT LOWPOWER_POWER_DOWN_CNT

LOWPOWER_REFRESH_HOLD LOWPOWER_REFRESH_HOLD

2 2 2 2 3 2 1 0

STMP 3700

2 2 2 2 7 6 5 4

STMP 3780

3 3 2 2 1 0 9 8

HW_DRAM_CTL31 HW_DRAM_CTL31

102

0x7c

0 0 0 0 3 2 1 0

10.2.33

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

HW_DRAM_CTL32 HW_DRAM_CTL32 1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

TXSNR

TRAS_MAX TRAS_MAX

2 2 2 2 3 2 1 0

0x80

TXSNR

2 2 2 2 7 6 5 4

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

10.2.34

1 1 0 0 1 0 9 8 LOWPOWER_SELF_REFRESH_CNT LOWPOWER_SELF_REFRESH_CNT

TDLL TDLL

2 2 2 2 3 2 1 0

STMP 3700

2 2 2 2 7 6 5 4

STMP 3780

3 3 2 2 1 0 9 8

HW_DRAM_CTL33 HW_DRAM_CTL33

103

0x84

2 2 2 2 7 6 5 4

10.2.35

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

0 0 0 0 3 2 1 0

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

TXSR TXSR

VERSION

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

0x88

1 1 1 1 5 4 3 2

TINIT

TINIT

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_DRAM_CTL35 HW_DRAM_CTL35 2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

0x8c

1 1 1 1 5 4 3 2 OUT_OF_RANGE_ADDR OUT_OF_RANGE_ADDR

2 2 2 2 7 6 5 4

STMP 3780

STMP 3700

3 3 2 2 1 0 9 8

10.2.37

0 0 0 0 7 6 5 4

HW_DRAM_CTL34 HW_DRAM_CTL34

10.2.36

1 1 0 0 1 0 9 8

VERSION

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_DRAM_CTL36 HW_DRAM_CTL36 104

0x90

1 1 1 1 5 4 3 2

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

ACTIVE_AGING

BUS_SHARE_ENABLE

0 0 0 0 7 6 5 4

ACTIVE_AGING

HW_DRAM_CTL37

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2 BUS_SHARE_TIMEOUT BUS_SHARE_TIMEOUT

2 2 2 2 7 6 5 4

OBSOLETE

STMP 3780

STMP 3700

3 3 2 2 1 0 9 8

0x94

HW_DRAM_CTL38 HW_DRAM_CTL38

105

0x98

1 1 0 0 1 0 9 8

TREF_ENABLE

HW_DRAM_CTL37

10.2.39

1 1 0 0 1 0 9 8

BUS_SHARE_ENABLE

PWRUP_SREFRESH_EXIT PWRUP_SREFRESH_EXIT

1 1 1 1 9 8 7 6 ENABLE_QUICK_SREFRESH ENABLE_QUICK_SREFRESH

STMP 3700

2 2 2 2 3 2 1 0

TREF_ENABLE

10.2.38

2 2 2 2 7 6 5 4

STMP 3780

3 3 2 2 1 0 9 8

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 5 4 3 2

0 0 0 0 7 6 5 4

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

EMRS1_DATA

0 0 0 0 3 2 1 0

HW_DRAM_CTL39 HW_DRAM_CTL39 2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

STMP 3700 STMP 3780

0 0 0 0 3 2 1 0

EMRS2_DATA_1 EMRS2_DATA_1

2 2 2 2 7 6 5 4

0x9c

EMRS2_DATA_2 EMRS2_DATA_2

3 3 2 2 1 0 9 8

HW_DRAM_CTL40 HW_DRAM_CTL40 1 1 1 1 9 8 7 6

0xa0

1 1 1 1 5 4 3 2

EMRS2_DATA_3 EMRS2_DATA_3

TPDEX

2 2 2 2 3 2 1 0

TPDEX

2 2 2 2 7 6 5 4

STMP 3700

3 3 2 2 1 0 9 8

STMP 3780

10.2.41

1 1 0 0 1 0 9 8

EMRS1_DATA

STMP 3700 STMP 3780 10.2.40

1 1 1 1 9 8 7 6

EMRS2_DATA_0 EMRS2_DATA_0

3 3 2 2 1 0 9 8

106

0 0 0 0 3 2 1 0

11 11.1

Digital Radio Interface (DRI) Summary

The next table summarizes the important aspects of the Digital Radio Interface device block and the main differences between the STMP 3700 and the STMP 3780.

11.2.2

STOP_ON_OFLOW_ERROR

STOP_ON_PILOT_ERROR

STOP_ON_OFLOW_ERROR

STOP_ON_PILOT_ERROR

REACQUIRE_PHASE

ENABLE_INPUTS ENABLE_INPUTS

1 1 1 1 5 4 3 2

REACQUIRE_PHASE

CLKGATE CLKGATE

1 1 1 1 9 8 7 6

DMA_DELAY_COUNT

SFTRST SFTRST

2 2 2 2 3 2 1 0

DMA_DELAY_COUNT

STMP 3700

2 2 2 2 7 6 5 4

STMP 3780

3 3 2 2 1 0 9 8

0x0

HW_DRI_TIMING HW_DRI_TIMING

107

1 1 0 0 1 0 9 8

0x10

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

RUN

HW_DRI_CTRL

RUN

HW_DRI_CTRL

ATTENTION_IRQ

11.2.1

PILOT_SYNC_LOSS_IRQ

Programmable Registers

PILOT_SYNC_LOSS_IRQ

11.2

0x60

ATTENTION_IRQ

HW_DRI_VERSION

0x50

OVERFLOW_IRQ

HW_DRI_DEBUG1

0x40

OVERFLOW_IRQ

HW_DRI_DEBUG0

0x30

ATTENTION_IRQ_EN

HW_DRI_DATA

0x20

ATTENTION_IRQ_EN

HW_DRI_STAT

0x10

OVERFLOW_IRQ_EN

HW_DRI_TIMING

STMP 3700 STMP 3780 0x80074000 0x0

PILOT_SYNC_LOSS_IRQ_EN PILOT_SYNC_LOSS_IRQ_EN

HW_DRI_CTRL

Property Base Address Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields

OVERFLOW_IRQ_EN

Name Digital Radio Interface

11.2.3

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0 GAP_DETECTION_INTERVAL GAP_DETECTION_INTERVAL

2 2 2 2 3 2 1 0

PILOT_REP_RATE

2 2 2 2 7 6 5 4

PILOT_REP_RATE

STMP 3780

STMP 3700

3 3 2 2 1 0 9 8

HW_DRI_STAT HW_DRI_STAT

108

0x20

11.2.4

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

OVERFLOW_IRQ_SUMMARY

ATTENTION_IRQ_SUMMARY

0 0 0 0 7 6 5 4

HW_DRI_DATA HW_DRI_DATA 1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

DATA

2 2 2 2 3 2 1 0

0x30

DATA

2 2 2 2 7 6 5 4

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

11.2.5

1 1 0 0 1 0 9 8

ATTENTION_IRQ_SUMMARY

1 1 1 1 5 4 3 2

PILOT_SYNC_LOSS_IRQ_SUMMARY PILOT_SYNC_LOSS_IRQ_SUMMARY

1 1 1 1 9 8 7 6

OVERFLOW_IRQ_SUMMARY

2 2 2 2 3 2 1 0

PILOT_PHASE

DRI_PRESENT DRI_PRESENT

2 2 2 2 7 6 5 4

PILOT_PHASE

STMP 3700 STMP 3780

3 3 2 2 1 0 9 8

HW_DRI_DEBUG0 HW_DRI_DEBUG0

109

0x40

0 0 0 0 3 2 1 0

11.2.6

TEST_MODE TEST_MODE

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

HW_DRI_DEBUG1 HW_DRI_DEBUG1 1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8 SWIZZLED_FRAME

2 2 2 2 3 2 1 0

SWIZZLED_FRAME

REVERSE_FRAME

2 2 2 2 7 6 5 4

0x50

REVERSE_FRAME

INVERT_DRI_CLOCK INVERT_DRI_CLOCK

INVERT_DRI_DATA INVERT_DRI_DATA

INVERT_PILOT INVERT_PILOT

INVERT_ATTENTION INVERT_ATTENTION

STMP 3700 STMP 3780

3 3 2 2 1 0 9 8

HW_DRI_VERSION HW_DRI_VERSION

0x60 1 1 0 0 1 0 9 8

STEP

1 1 1 1 5 4 3 2

STEP

MINOR

1 1 1 1 9 8 7 6

MINOR

2 2 2 2 3 2 1 0

MAJOR

2 2 2 2 7 6 5 4

MAJOR

3 3 2 2 1 0 9 8 STMP 3780 STMP 3700

11.2.7

1 1 0 0 1 0 9 8

FRAME

DRI_DATA_INPUT DRI_DATA_INPUT

1 1 1 1 5 4 3 2

FRAME

DRI_CLK_INPUT DRI_CLK_INPUT

1 1 1 1 9 8 7 6

SPARE

DMACMDKICK DMACMDKICK

2 2 2 2 3 2 1 0

SPARE

DMAREQ DMAREQ

PILOT_REP_RATE PILOT_REP_RATE

STMP 3700

2 2 2 2 7 6 5 4

STMP 3780

3 3 2 2 1 0 9 8

110

12 12.1

8-Symbol Correcting ECC Accelerator (ECC8) Summary

The next table summarizes the important aspects of the Reed-Solomon ECC device block and the main differences between the STMP 3700 and the STMP 3780.

HW_ECC8_VERSION

12.2

Programmable Registers

12.2.1

HW_ECC8_CTRL

0x80 0xa0

HW_ECC8_CTRL

CLKGATE

AHBM_SFTRST

THROTTLE

CLKGATE

AHBM_SFTRST

THROTTLE

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8 DEBUG_STALL_IRQ_EN

SFTRST SFTRST

2 2 2 2 3 2 1 0

DEBUG_STALL_IRQ_EN

STMP 3700

2 2 2 2 7 6 5 4

STMP 3780

3 3 2 2 1 0 9 8

0x0

111

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

COMPLETE_IRQ

HW_ECC8_BLOCKNAME

0x70

COMPLETE_IRQ

HW_ECC8_DBGAHBMREAD

0x60

DEBUG_WRITE_IRQ

HW_ECC8_DBGSYNDGENREAD

0x50

DEBUG_STALL_IRQ

HW_ECC8_DBGCSFEREAD

0x40

DEBUG_WRITE_IRQ

HW_ECC8_DBGKESREAD

0x30

DEBUG_STALL_IRQ

HW_ECC8_DEBUG0

BM_ERROR_IRQ

HW_ECC8_STATUS1

0x10 Incompatible Field(s) Incompatible Field(s) 0x20

BM_ERROR_IRQ

HW_ECC8_STATUS0

COMPLETE_IRQ_EN

HW_ECC8_CTRL

STMP 3700 STMP 3780 0x80008000 0x0

COMPLETE_IRQ_EN

Property Base Address Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields

DEBUG_WRITE_IRQ_EN DEBUG_WRITE_IRQ_EN

Name Reed-Solomon ECC

12.2.4 3 3 2 2 1 0 9 8 2 2 2 2 7 6 5 4 2 2 2 2 3 2 1 0 1 1 1 1 9 8 7 6 1 1 1 1 5 4 3 2 1 1 0 0 1 0 9 8 0 0 0 0 7 6 5 4 0 0 0 0 3 2 1 0

STATUS_PAYLOAD6 STATUS_PAYLOAD6

STATUS_PAYLOAD5 STATUS_PAYLOAD5

STATUS_PAYLOAD4 STATUS_PAYLOAD4

STATUS_PAYLOAD3 STATUS_PAYLOAD3

STATUS_PAYLOAD2 STATUS_PAYLOAD2

STATUS_PAYLOAD1 STATUS_PAYLOAD1

STATUS_PAYLOAD0 STATUS_PAYLOAD0

STMP 3700

12.2.3

STATUS_PAYLOAD7 STATUS_PAYLOAD7

STMP 3780

112

HW_ECC8_STATUS1

HW_ECC8_DEBUG0

HW_ECC8_DEBUG0

0x30

CORRECTED UNCORRECTABLE

CORRECTED UNCORRECTABLE

0 0 0 0 7 6 5 4

COMPLETED_CE

ALLONES

1 1 0 0 1 0 9 8

ALLONES

STATUS_AUX

1 1 1 1 5 4 3 2

STATUS_AUX

HW_ECC8_STATUS0

RS4ECC_DEC_PRESENT RS4ECC_DEC_PRESENT

1 1 1 1 9 8 7 6

RS4ECC_ENC_PRESENT RS4ECC_ENC_PRESENT

2 2 2 2 3 2 1 0

RS8ECC_DEC_PRESENT RS8ECC_DEC_PRESENT

2 2 2 2 7 6 5 4

RS8ECC_ENC_PRESENT RS8ECC_ENC_PRESENT

HANDLE

STMP 3700 3 3 2 2 1 0 9 8

COMPLETED_CE

HANDLE

STMP 3780

12.2.2 HW_ECC8_STATUS0 0x10 0 0 0 0 3 2 1 0

HW_ECC8_STATUS1 0x20

3 3 2 2 1 0 9 8

12.2.6 2 2 2 2 7 6 5 4 VALUES

12.2.5 STMP 3700

2 2 2 2 3 2 1 0

113

KES_DEBUG_MODE4K KES_DEBUG_KICK KES_STANDALONE KES_DEBUG_STEP KES_DEBUG_STALL BM_KES_TEST_BYPASS

KES_DEBUG_MODE4K KES_DEBUG_KICK KES_STANDALONE KES_DEBUG_STEP KES_DEBUG_STALL BM_KES_TEST_BYPASS

1 1 1 1 5 4 3 2

HW_ECC8_DBGKESREAD

1 1 1 1 9 8 7 6 1 1 1 1 5 4 3 2

HW_ECC8_DBGCSFEREAD

1 1 0 0 1 0 9 8

1 1 0 0 1 0 9 8

HW_ECC8_DBGCSFEREAD

0x50

DEBUG_REG_SELECT

KES_DEBUG_PAYLOAD_FLAG

1 1 1 1 9 8 7 6

DEBUG_REG_SELECT

KES_DEBUG_SHIFT_SYND

KES_DEBUG_PAYLOAD_FLAG

2 2 2 2 3 2 1 0

KES_DEBUG_SHIFT_SYND

KES_DEBUG_SYNDROME_SYMBOL KES_DEBUG_SYNDROME_SYMBOL

STMP 3780

2 2 2 2 7 6 5 4

VALUES

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_ECC8_DBGKESREAD 0x40

0 0 0 0 7 6 5 4 0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4 0 0 0 0 3 2 1 0

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

12.2.7

1 1 1 1 5 4 3 2

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

VALUES

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

0x60

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

VALUES

VALUES

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_ECC8_DBGAHBMREAD HW_ECC8_DBGAHBMREAD 1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

VALUES

2 2 2 2 3 2 1 0

0x70

VALUES

2 2 2 2 7 6 5 4

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

12.2.9

0 0 0 0 7 6 5 4

HW_ECC8_DBGSYNDGENREAD HW_ECC8_DBGSYNDGENREAD

12.2.8

1 1 0 0 1 0 9 8

VALUES

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_ECC8_BLOCKNAME HW_ECC8_BLOCKNAME

114

0x80

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

12.2.10

1 1 1 1 5 4 3 2

0 0 0 0 3 2 1 0

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

NAME

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

0xa0

1 1 1 1 5 4 3 2

STEP

MINOR

STEP

MINOR

MAJOR

2 2 2 2 7 6 5 4

MAJOR

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

13.1

0 0 0 0 7 6 5 4

HW_ECC8_VERSION HW_ECC8_VERSION

13

1 1 0 0 1 0 9 8

NAME

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

External Memory Interface (EMI) Summary

The next table summarizes the important aspects of the External Memory Interface device block and the main differences between the STMP 3700 and the STMP 3780. Name External Memory Interface HW_EMI_CTRL HW_EMI_STAT HW_EMI_TIME HW_EMI_DDR_TEST_MODE_CSR HW_EMI_DEBUG HW_EMI_DDR_TEST_MODE_STATUS0 HW_EMI_DDR_TEST_MODE_STATUS1 HW_EMI_DDR_TEST_MODE_STATUS2 HW_EMI_DDR_TEST_MODE_STATUS3

Property Base Address Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields

115

STMP 3700 STMP 3780 0x80020000 0x0 New Field(s) 0x10 0x20 0x30 0x80 0x90 0xa0 0xb0 0xc0

Property Address Fields

PRIORITY_WRITE_ITER

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

CE_SELECT

1 1 1 1 5 4 3 2

CE_SELECT

1 1 1 1 9 8 7 6

PORT_PRIORITY_ORDER

2 2 2 2 3 2 1 0

ARB_MODE

DLL_RESET

DLL_SHIFT_RESET

AXI_DEPTH

CLKGATE CLKGATE

TRAP_INIT

SFTRST SFTRST

TRAP_SR

STMP 3700

2 2 2 2 7 6 5 4

HW_EMI_STAT

116

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

NOR_BUSY

1 1 1 1 9 8 7 6

NOR_BUSY

NOR_PRESENT NOR_PRESENT

2 2 2 2 3 2 1 0

DRAM_HALTED

DRAM_PRESENT DRAM_PRESENT

2 2 2 2 7 6 5 4

LARGE_DRAM_ENABLED LARGE_DRAM_ENABLED

STMP 3700

3 3 2 2 1 0 9 8

0x10

DRAM_HALTED

HW_EMI_STAT

STMP 3780

13.2.2

STMP 3780

3 3 2 2 1 0 9 8

0x0

RESET_OUT

HW_EMI_CTRL

WRITE_PROTECT

HW_EMI_CTRL

WRITE_PROTECT

13.2.1

RESET_OUT

Programmable Registers

MEM_WIDTH

13.2

MEM_WIDTH

HW_EMI_VERSION

STMP 3700 STMP 3780 0xf0

HIGH_PRIORITY_WRITE

Name

HW_EMI_TIME HW_EMI_TIME 1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

0 0 0 0 3 2 1 0

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

TAS

TDS

0 0 0 0 7 6 5 4

TAS

TDS

TDH

THZ THZ

1 1 0 0 1 0 9 8

HW_EMI_DDR_TEST_MODE_CSR

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

13.2.5

HW_EMI_DEBUG HW_EMI_DEBUG 2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

NOR_STATE NOR_STATE

2 2 2 2 7 6 5 4

0x80

STMP 3780

STMP 3700

3 3 2 2 1 0 9 8

13.2.6

START

2 2 2 2 7 6 5 4

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

0x30

START

HW_EMI_DDR_TEST_MODE_CSR

DONE

13.2.4

2 2 2 2 3 2 1 0

TDH

2 2 2 2 7 6 5 4

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

0x20

DONE

13.2.3

HW_EMI_DDR_TEST_MODE_STATUS0 HW_EMI_DDR_TEST_MODE_STATUS0

117

0x90

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

13.2.7

ADDR0

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

0xa0 1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

ADDR1

ADDR1

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_EMI_DDR_TEST_MODE_STATUS2 HW_EMI_DDR_TEST_MODE_STATUS2 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

0xb0 1 1 0 0 1 0 9 8

DATA0

DATA0

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

13.2.9

0 0 0 0 3 2 1 0

HW_EMI_DDR_TEST_MODE_STATUS1 HW_EMI_DDR_TEST_MODE_STATUS1

13.2.8

0 0 0 0 7 6 5 4

ADDR0

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_EMI_DDR_TEST_MODE_STATUS3 HW_EMI_DDR_TEST_MODE_STATUS3

118

0xc0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

13.2.10

1 1 1 1 5 4 3 2

0 0 0 0 3 2 1 0

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

DATA1

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

0xf0

1 1 1 1 5 4 3 2

STEP

MINOR

STEP

MINOR

MAJOR

2 2 2 2 7 6 5 4

MAJOR

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

14.1

0 0 0 0 7 6 5 4

HW_EMI_VERSION HW_EMI_VERSION

14

1 1 0 0 1 0 9 8

DATA1

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

GPIOMON Summary

The next table summarizes the important aspects of the GPIOMON device block and the main differences between the STMP 3700 and the STMP 3780. Name GPIOMON HW_GPIOMON_BANK0_DATAIN HW_GPIOMON_BANK1_DATAIN HW_GPIOMON_BANK2_DATAIN HW_GPIOMON_BANK3_DATAIN HW_GPIOMON_BANK0_DATAOUT HW_GPIOMON_BANK1_DATAOUT HW_GPIOMON_BANK2_DATAOUT HW_GPIOMON_BANK3_DATAOUT HW_GPIOMON_BANK0_DATAOEN

Property Base Address Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields

119

STMP 3700 0x8003c300 0x0 New Field(s) 0x10 New Field(s) 0x20 New Field(s) 0x30 New Field(s) 0x40 New Field(s) 0x50 New Field(s) 0x60 New Field(s) 0x70 New Field(s) 0x80 New Field(s)

STMP 3780 Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent

Name

Property Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields

HW_GPIOMON_BANK1_DATAOEN HW_GPIOMON_BANK2_DATAOEN HW_GPIOMON_BANK3_DATAOEN HW_GPIOMON_CTRL HW_GPIOMON_ALT1_PINMUX_BANK0 HW_GPIOMON_ALT1_PINMUX_BANK1 HW_GPIOMON_ALT1_PINMUX_BANK2 HW_GPIOMON_ALT1_PINMUX_BANK3 HW_GPIOMON_ALT2_PINMUX_BANK0 HW_GPIOMON_ALT2_PINMUX_BANK1 HW_GPIOMON_ALT2_PINMUX_BANK2 HW_GPIOMON_ALT2_PINMUX_BANK3 HW_GPIOMON_ALT3_PINMUX_BANK0 HW_GPIOMON_ALT3_PINMUX_BANK1 HW_GPIOMON_ALT3_PINMUX_BANK2 HW_GPIOMON_ALT3_PINMUX_BANK3

14.2

Programmable Registers

14.2.1

HW_GPIOMON_BANK0_DATAIN HW_GPIOMON_BANK0_DATAIN 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

14.2.2

1 1 1 1 9 8 7 6

STMP 3700 0x0 1 1 1 1 5 4 3 2

STMP 3780 Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent

STMP 3780 Non-Existent 1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

DATA

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

STMP 3700 0x90 New Field(s) 0xa0 New Field(s) 0xb0 New Field(s) 0xc0 New Field(s) 0xd0 New Field(s) 0xe0 New Field(s) 0xf0 New Field(s) 0x100 New Field(s) 0x110 New Field(s) 0x120 New Field(s) 0x130 New Field(s) 0x140 New Field(s) 0x150 New Field(s) 0x160 New Field(s) 0x170 New Field(s) 0x180 New Field(s)

HW_GPIOMON_BANK1_DATAIN HW_GPIOMON_BANK1_DATAIN 120

STMP 3700 0x10

STMP 3780 Non-Existent

0 0 0 0 3 2 1 0

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

14.2.3

1 1 1 1 5 4 3 2

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

0 0 0 0 3 2 1 0

STMP 3780 Non-Existent

STMP 3700 0x20 1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

DATA

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_GPIOMON_BANK3_DATAIN HW_GPIOMON_BANK3_DATAIN 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

STMP 3780 Non-Existent

STMP 3700 0x30 1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

DATA

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

14.2.5

0 0 0 0 7 6 5 4

HW_GPIOMON_BANK2_DATAIN HW_GPIOMON_BANK2_DATAIN

14.2.4

1 1 0 0 1 0 9 8

DATA

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_GPIOMON_BANK0_DATAOUT HW_GPIOMON_BANK0_DATAOUT

121

STMP 3700 0x40

STMP 3780 Non-Existent

0 0 0 0 3 2 1 0

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

14.2.6

1 1 1 1 5 4 3 2

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

0 0 0 0 3 2 1 0

STMP 3700 0x50 1 1 1 1 5 4 3 2

STMP 3780 Non-Existent

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

DATA

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_GPIOMON_BANK2_DATAOUT HW_GPIOMON_BANK2_DATAOUT 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

STMP 3700 0x60 1 1 1 1 5 4 3 2

STMP 3780 Non-Existent

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

DATA

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

14.2.8

0 0 0 0 7 6 5 4

HW_GPIOMON_BANK1_DATAOUT HW_GPIOMON_BANK1_DATAOUT

14.2.7

1 1 0 0 1 0 9 8

DATA

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_GPIOMON_BANK3_DATAOUT HW_GPIOMON_BANK3_DATAOUT

122

STMP 3700 0x70

STMP 3780 Non-Existent

0 0 0 0 3 2 1 0

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

14.2.9

1 1 1 1 5 4 3 2

0 0 0 0 3 2 1 0

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

STMP 3700 0x80 1 1 1 1 5 4 3 2

STMP 3780 Non-Existent

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

STMP 3780 STMP 3700

OUTPUT_ENABLES

3 3 2 2 1 0 9 8

HW_GPIOMON_BANK1_DATAOEN HW_GPIOMON_BANK1_DATAOEN 2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

STMP 3700 0x90 1 1 1 1 5 4 3 2

STMP 3780 Non-Existent

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

OUTPUT_ENABLES

2 2 2 2 7 6 5 4

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

14.2.11

0 0 0 0 7 6 5 4

HW_GPIOMON_BANK0_DATAOEN HW_GPIOMON_BANK0_DATAOEN

14.2.10

1 1 0 0 1 0 9 8

DATA

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_GPIOMON_BANK2_DATAOEN HW_GPIOMON_BANK2_DATAOEN

123

STMP 3700 0xa0

STMP 3780 Non-Existent

0 0 0 0 3 2 1 0

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

STMP 3780 STMP 3700

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

HW_GPIOMON_BANK3_DATAOEN HW_GPIOMON_BANK3_DATAOEN 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

STMP 3700 0xb0 1 1 1 1 5 4 3 2

STMP 3780 Non-Existent

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

STMP 3780 STMP 3700

OUTPUT_ENABLES

3 3 2 2 1 0 9 8

HW_GPIOMON_CTRL

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

124

OEN_NAND

2 2 2 2 7 6 5 4

STMP 3780 Non-Existent

PINMUX_ALT_RESET

3 3 2 2 1 0 9 8

STMP 3700 0xc0

OEN_4MA

HW_GPIOMON_CTRL

STMP 3780 STMP 3700

14.2.13

1 1 0 0 1 0 9 8

OEN_8MA

14.2.12

1 1 1 1 5 4 3 2 OUTPUT_ENABLES

3 3 2 2 1 0 9 8

14.2.14

HW_GPIOMON_ALT1_PINMUX_BANK0 HW_GPIOMON_ALT1_PINMUX_BANK0 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

14.2.15

1 1 1 1 5 4 3 2

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

STMP 3700 0xe0

1 1 1 1 5 4 3 2

STMP 3780 Non-Existent

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

INDEX

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_GPIOMON_ALT1_PINMUX_BANK2 HW_GPIOMON_ALT1_PINMUX_BANK2 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

STMP 3700 0xf0

1 1 1 1 5 4 3 2

STMP 3780 Non-Existent

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

INDEX

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

14.2.17

1 1 0 0 1 0 9 8

HW_GPIOMON_ALT1_PINMUX_BANK1 HW_GPIOMON_ALT1_PINMUX_BANK1

14.2.16

STMP 3780 Non-Existent

INDEX

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

STMP 3700 0xd0

HW_GPIOMON_ALT1_PINMUX_BANK3 HW_GPIOMON_ALT1_PINMUX_BANK3

125

STMP 3700 0x100

STMP 3780 Non-Existent

0 0 0 0 3 2 1 0

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

14.2.18

1 1 1 1 5 4 3 2

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

0 0 0 0 3 2 1 0

STMP 3700 0x110

1 1 1 1 5 4 3 2

STMP 3780 Non-Existent

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

INDEX

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_GPIOMON_ALT2_PINMUX_BANK1 HW_GPIOMON_ALT2_PINMUX_BANK1 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

STMP 3700 0x120

1 1 1 1 5 4 3 2

STMP 3780 Non-Existent

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

INDEX

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

14.2.20

0 0 0 0 7 6 5 4

HW_GPIOMON_ALT2_PINMUX_BANK0 HW_GPIOMON_ALT2_PINMUX_BANK0

14.2.19

1 1 0 0 1 0 9 8

INDEX

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_GPIOMON_ALT2_PINMUX_BANK2 HW_GPIOMON_ALT2_PINMUX_BANK2

126

STMP 3700 0x130

STMP 3780 Non-Existent

0 0 0 0 3 2 1 0

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

14.2.21

1 1 1 1 5 4 3 2

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

0 0 0 0 3 2 1 0

STMP 3700 0x140

1 1 1 1 5 4 3 2

STMP 3780 Non-Existent

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

INDEX

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_GPIOMON_ALT3_PINMUX_BANK0 HW_GPIOMON_ALT3_PINMUX_BANK0 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

STMP 3700 0x150

1 1 1 1 5 4 3 2

STMP 3780 Non-Existent

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

INDEX

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

14.2.23

0 0 0 0 7 6 5 4

HW_GPIOMON_ALT2_PINMUX_BANK3 HW_GPIOMON_ALT2_PINMUX_BANK3

14.2.22

1 1 0 0 1 0 9 8

INDEX

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_GPIOMON_ALT3_PINMUX_BANK1 HW_GPIOMON_ALT3_PINMUX_BANK1

127

STMP 3700 0x160

STMP 3780 Non-Existent

0 0 0 0 3 2 1 0

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

14.2.24

1 1 1 1 5 4 3 2

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

STMP 3700 0x170

1 1 1 1 5 4 3 2

STMP 3780 Non-Existent

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

HW_GPIOMON_ALT3_PINMUX_BANK3 HW_GPIOMON_ALT3_PINMUX_BANK3 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

STMP 3700 0x180

1 1 1 1 5 4 3 2

STMP 3780 Non-Existent

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

INDEX

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

15.1

0 0 0 0 3 2 1 0

INDEX

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

15

0 0 0 0 7 6 5 4

HW_GPIOMON_ALT3_PINMUX_BANK2 HW_GPIOMON_ALT3_PINMUX_BANK2

14.2.25

1 1 0 0 1 0 9 8

INDEX

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

General Purpose Media Interface Summary

The next table summarizes the important aspects of the General Purpose Media Interface device block and the main differences between the STMP 3700 and the STMP 3780. Name General Purpose Media Interface

Property Base Address 128

STMP 3700

STMP 3780

0x8000c000

Name HW_GPMI_CTRL0 HW_GPMI_COMPARE HW_GPMI_ECCCTRL HW_GPMI_ECCCOUNT HW_GPMI_PAYLOAD HW_GPMI_AUXILIARY HW_GPMI_CTRL1 HW_GPMI_TIMING0 HW_GPMI_TIMING1 HW_GPMI_TIMING2 HW_GPMI_DATA HW_GPMI_STAT HW_GPMI_DEBUG HW_GPMI_VERSION HW_GPMI_DEBUG2 HW_GPMI_DEBUG3

15.2

Programmable Registers

15.2.1

HW_GPMI_CTRL0

Property Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields

HW_GPMI_CTRL0

129

STMP 3700 STMP 3780 0x0 0x10 0x20 0x30 0x40 0x50 0x60 New Field(s) New Field(s) 0x70 0x80 0x90 0xa0 0xb0 0xc0 0xd0 Non-Existent Non-Existent

0x0

0xe0 New Field(s) 0xf0 New Field(s)

1 1 1 1 5 4 3 2

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

XFER_COUNT

XFER_COUNT

0 0 0 0 7 6 5 4

HW_GPMI_COMPARE HW_GPMI_COMPARE 1 1 1 1 9 8 7 6

0x10

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8 REFERENCE REFERENCE

MASK MASK

2 2 2 2 3 2 1 0

STMP 3700

2 2 2 2 7 6 5 4

STMP 3780

3 3 2 2 1 0 9 8

HW_GPMI_ECCCTRL HW_GPMI_ECCCTRL

130

ENABLE_ECC ENABLE_ECC

1 1 1 1 5 4 3 2

ECC_CMD

1 1 1 1 9 8 7 6

0x20

ECC_CMD

HANDLE

2 2 2 2 3 2 1 0

HANDLE

2 2 2 2 7 6 5 4

STMP 3700

3 3 2 2 1 0 9 8

STMP 3780

15.2.3

1 1 0 0 1 0 9 8

ADDRESS_INCREMENT ADDRESS_INCREMENT

ADDRESS ADDRESS

LOCK_CS LOCK_CS

CS

WORD_LENGTH WORD_LENGTH

1 1 1 1 9 8 7 6

CS

COMMAND_MODE COMMAND_MODE

DEV_IRQ_EN DEV_IRQ_EN

TIMEOUT_IRQ_EN

RUN RUN

UDMA

CLKGATE CLKGATE

UDMA

SFTRST SFTRST

2 2 2 2 3 2 1 0

TIMEOUT_IRQ_EN

STMP 3700

2 2 2 2 7 6 5 4

1 1 0 0 1 0 9 8

BUFFER_MASK BUFFER_MASK

15.2.2

STMP 3780

3 3 2 2 1 0 9 8

15.2.4

HW_GPMI_ECCCOUNT HW_GPMI_ECCCOUNT 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

15.2.5

COUNT

COUNT

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

0x30

HW_GPMI_PAYLOAD HW_GPMI_PAYLOAD 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

15.2.6

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

ADDRESS

ADDRESS

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_GPMI_AUXILIARY HW_GPMI_AUXILIARY 1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

ADDRESS

2 2 2 2 3 2 1 0

0x50

ADDRESS

2 2 2 2 7 6 5 4

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

15.2.7

0x40

HW_GPMI_CTRL1 HW_GPMI_CTRL1

131

0x60

STMP 3700

15.2.9 2 2 2 2 3 2 1 0 1 1 1 1 9 8 7 6

HW_GPMI_TIMING1

132 DATA_SETUP

HW_GPMI_TIMING0

DATA_SETUP

2 2 2 2 7 6 5 4

HW_GPMI_TIMING1

0x80

DEV_IRQ TIMEOUT_IRQ BURST_EN

DEV_IRQ TIMEOUT_IRQ BURST_EN

1 1 1 1 5 4 3 2 1 1 0 0 1 0 9 8

DEV_RESET ATA_IRQRDY_POLARITY CAMERA_MODE GPMI_MODE

DEV_RESET ATA_IRQRDY_POLARITY CAMERA_MODE GPMI_MODE

ABORT_WAIT_FOR_READY0 ABORT_WAIT_FOR_READY0

ABORT_WAIT_FOR_READY1 ABORT_WAIT_FOR_READY1

1 1 0 0 1 0 9 8 ABORT_WAIT_FOR_READY2 ABORT_WAIT_FOR_READY2

1 1 1 1 5 4 3 2 ABORT_WAIT_FOR_READY3 ABORT_WAIT_FOR_READY3

DMA2ECC_MODE

DMA2ECC_MODE

RDN_DELAY

HALF_PERIOD

DLL_ENABLE

BCH_MODE

CE0_SEL

CE1_SEL

CE2_SEL

GANGED_RDYBUSY

DSAMPLE_TIME

STMP 3700

CE3_SEL

STMP 3780

1 1 1 1 9 8 7 6

DATA_HOLD

3 3 2 2 1 0 9 8

2 2 2 2 3 2 1 0

DATA_HOLD

15.2.8 2 2 2 2 7 6 5 4

ADDRESS_SETUP ADDRESS_SETUP

STMP 3780

3 3 2 2 1 0 9 8 0 0 0 0 7 6 5 4 0 0 0 0 3 2 1 0

HW_GPMI_TIMING0 0x70

0 0 0 0 7 6 5 4 0 0 0 0 3 2 1 0

2 2 2 2 7 6 5 4

STMP 3700 STMP 3780

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

HW_GPMI_TIMING2 HW_GPMI_TIMING2

1 1 1 1 5 4 3 2 UDMA_HOLD

1 1 1 1 9 8 7 6

UDMA_HOLD

UDMA_ENV

UDMA_TRP UDMA_TRP

2 2 2 2 3 2 1 0

0x90

UDMA_ENV

STMP 3700

2 2 2 2 7 6 5 4

STMP 3780

3 3 2 2 1 0 9 8

HW_GPMI_DATA HW_GPMI_DATA 2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

0xa0

1 1 1 1 5 4 3 2

DATA

2 2 2 2 7 6 5 4

DATA

3 3 2 2 1 0 9 8 STMP 3780 STMP 3700

15.2.11

1 1 0 0 1 0 9 8

UDMA_SETUP UDMA_SETUP

15.2.10

2 2 2 2 3 2 1 0 DEVICE_BUSY_TIMEOUT DEVICE_BUSY_TIMEOUT

3 3 2 2 1 0 9 8

133

0 0 0 0 3 2 1 0

15.2.14 SENSE1

SENSE1

134

HW_GPMI_VERSION

HW_GPMI_VERSION

0xd0 MAIN_STATE

MAIN_STATE

1 1 1 1 5 4 3 2

PIN_STATE

CMD_END

CMD_END

HW_GPMI_DEBUG

PIN_STATE

DMAREQ0

DMAREQ0

1 1 1 1 9 8 7 6

ATA_IRQ

ATA_IRQ

1 1 0 0 1 0 9 8

FIFO_EMPTY FIFO_FULL DEV3_ERROR DEV2_ERROR DEV1_ERROR DEV0_ERROR

FIFO_EMPTY FIFO_FULL DEV3_ERROR DEV2_ERROR DEV1_ERROR DEV0_ERROR

1 1 0 0 1 0 9 8 INVALID_BUFFER_MASK INVALID_BUFFER_MASK

RDY_TIMEOUT

RDY_TIMEOUT

1 1 1 1 5 4 3 2

BUSY

DMAREQ1

DMAREQ1

1 1 1 1 9 8 7 6

BUSY

DMAREQ2

DMAREQ2

2 2 2 2 3 2 1 0

UDMA_STATE

DMAREQ3

DMAREQ3

HW_GPMI_STAT

UDMA_STATE

SENSE0

PRESENT

PRESENT

2 2 2 2 7 6 5 4

SENSE0

WAIT_FOR_READY_END0 WAIT_FOR_READY_END0

WAIT_FOR_READY_END1 WAIT_FOR_READY_END1

WAIT_FOR_READY_END2 WAIT_FOR_READY_END2

SENSE2

READY0

READY0

2 2 2 2 3 2 1 0

SENSE3

READY1

READY1

2 2 2 2 7 6 5 4

SENSE2

READY2

READY2

3 3 2 2 1 0 9 8

SENSE3

READY3

READY3

STMP 3700

STMP 3780 3 3 2 2 1 0 9 8

WAIT_FOR_READY_END3 WAIT_FOR_READY_END3

STMP 3700

15.2.13

STMP 3780

15.2.12 HW_GPMI_STAT 0xb0 0 0 0 0 7 6 5 4

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

HW_GPMI_DEBUG 0xc0

0 0 0 0 3 2 1 0

15.2.15

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

STEP

0 0 0 0 7 6 5 4

STEP

MINOR

MAJOR

MINOR

MAJOR

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_GPMI_DEBUG2 HW_GPMI_DEBUG2 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

STMP 3780 0xe0

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

RDN_TAP

UPDATE_WINDOW

VIEW_DELAYED_RDN

SYND2GPMI_READY

SYND2GPMI_VALID

GPMI2SYND_VALID

SYND2GPMI_BE

STMP 3780 HW_GPMI_DEBUG3 HW_GPMI_DEBUG3 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

STMP 3700 Non-Existent

1 1 1 1 9 8 7 6

STMP 3780 0xf0

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

APB_WORD_CNTR

DEV_WORD_CNTR

STMP 3700

3 3 2 2 1 0 9 8

STMP 3780

15.2.16

GPMI2SYND_READY

STMP 3700

3 3 2 2 1 0 9 8

STMP 3700 Non-Existent

135

0 0 0 0 3 2 1 0

16 16.1

I2 C Interface Summary

The next table summarizes the important aspects of the I2 C device block and the main differences between the STMP 3700 and the STMP 3780. Name I2 C HW_I2C_CTRL0 HW_I2C_TIMING0 HW_I2C_TIMING1 HW_I2C_TIMING2 HW_I2C_CTRL1 HW_I2C_STAT HW_I2C_DATA HW_I2C_DEBUG0 HW_I2C_DEBUG1 HW_I2C_VERSION

16.2

Programmable Registers

16.2.1

HW_I2C_CTRL0

Property Base Address Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields

STMP 3700 STMP 3780 0x80058000 0x0 0x10 0x20 0x30 0x40 New Field(s) 0x50 New Field(s) 0x60 0x70 Incompatible Field(s) Incompatible Field(s) 0x80 Incompatible Field(s) Incompatible Field(s) 0x90

HW_I2C_CTRL0

136

0x0

STMP 3700

16.2.3 2 2 2 2 7 6 5 4 2 2 2 2 3 2 1 0

RCV_COUNT

3 3 2 2 1 0 9 8 PRE_ACK ACKNOWLEDGE SEND_NAK_ON_LAST PIO_MODE MULTI_MASTER CLOCK_HELD RETAIN_CLOCK

PRE_ACK ACKNOWLEDGE SEND_NAK_ON_LAST PIO_MODE MULTI_MASTER CLOCK_HELD RETAIN_CLOCK

1 1 1 1 9 8 7 6

137

XFER_COUNT

DIRECTION

DIRECTION

1 1 1 1 9 8 7 6

XFER_COUNT

MASTER_MODE

MASTER_MODE

SLAVE_ADDRESS_ENABLE SLAVE_ADDRESS_ENABLE

PRE_SEND_START

RUN

RUN

PRE_SEND_START

CLKGATE

CLKGATE

POST_SEND_STOP

SFTRST

SFTRST

POST_SEND_STOP

STMP 3700

STMP 3780

2 2 2 2 3 2 1 0

RCV_COUNT

16.2.2 2 2 2 2 7 6 5 4

HIGH_COUNT HIGH_COUNT

STMP 3780

3 3 2 2 1 0 9 8 1 1 1 1 5 4 3 2

HW_I2C_TIMING0

1 1 1 1 5 4 3 2

HW_I2C_TIMING1 HW_I2C_TIMING1 0x20

1 1 0 0 1 0 9 8

HW_I2C_TIMING0 0x10

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4 0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4 0 0 0 0 3 2 1 0

16.2.4

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

0 0 0 0 7 6 5 4

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

HW_I2C_TIMING2 HW_I2C_TIMING2 1 1 1 1 9 8 7 6

0x30

1 1 1 1 5 4 3 2

LEADIN_COUNT LEADIN_COUNT

BUS_FREE BUS_FREE

2 2 2 2 3 2 1 0

STMP 3700

2 2 2 2 7 6 5 4

STMP 3780

3 3 2 2 1 0 9 8

16.2.5

1 1 0 0 1 0 9 8

XMIT_COUNT XMIT_COUNT

LOW_COUNT LOW_COUNT

2 2 2 2 3 2 1 0

STMP 3700

2 2 2 2 7 6 5 4

STMP 3780

3 3 2 2 1 0 9 8

HW_I2C_CTRL1 HW_I2C_CTRL1

138

0x40

0 0 0 0 3 2 1 0

16.2.6 SLAVE_ADDRESS_BYTE

BUS_FREE_IRQ_EN DATA_ENGINE_CMPLT_IRQ_EN NO_SLAVE_ACK_IRQ_EN

SLAVE_ADDRESS_BYTE

BUS_FREE_IRQ_EN DATA_ENGINE_CMPLT_IRQ_EN NO_SLAVE_ACK_IRQ_EN

HW_I2C_STAT

139

HW_I2C_STAT 0x50

DATA_ENGINE_CMPLT_IRQ NO_SLAVE_ACK_IRQ OVERSIZE_XFER_TERM_IRQ EARLY_TERM_IRQ MASTER_LOSS_IRQ SLAVE_STOP_IRQ SLAVE_IRQ

DATA_ENGINE_CMPLT_IRQ OVERSIZE_XFER_TERM_IRQ EARLY_TERM_IRQ MASTER_LOSS_IRQ SLAVE_STOP_IRQ SLAVE_IRQ

1 1 0 0 1 0 9 8

NO_SLAVE_ACK_IRQ

SLAVE_IRQ_EN BUS_FREE_IRQ

SLAVE_IRQ_EN

SLAVE_STOP_IRQ_EN

SLAVE_STOP_IRQ_EN BUS_FREE_IRQ

MASTER_LOSS_IRQ_EN

1 1 1 1 5 4 3 2

EARLY_TERM_IRQ_EN

1 1 1 1 9 8 7 6

MASTER_LOSS_IRQ_EN

2 2 2 2 3 2 1 0

EARLY_TERM_IRQ_EN

2 2 2 2 7 6 5 4

OVERSIZE_XFER_TERM_IRQ_EN OVERSIZE_XFER_TERM_IRQ_EN

BCAST_SLAVE_EN

STMP 3700

BCAST_SLAVE_EN

FORCE_CLK_IDLE

FORCE_DATA_IDLE

ACK_MODE

CLR_GOT_A_NAK

STMP 3780

3 3 2 2 1 0 9 8 0 0 0 0 7 6 5 4 0 0 0 0 3 2 1 0

3 3 2 2 1 0 9 8

16.2.8 2 2 2 2 7 6 5 4

DATA

16.2.7 MASTER_PRESENT SLAVE_PRESENT ANY_ENABLED_IRQ

MASTER_PRESENT SLAVE_PRESENT ANY_ENABLED_IRQ

2 2 2 2 3 2 1 0

140

HW_I2C_DATA

1 1 1 1 9 8 7 6 1 1 1 1 5 4 3 2

HW_I2C_DEBUG0

HW_I2C_DEBUG0

0x70

DATA_ENGINE_CMPLT_IRQ_SUMMARY NO_SLAVE_ACK_IRQ_SUMMARY

DATA_ENGINE_CMPLT_IRQ_SUMMARY NO_SLAVE_ACK_IRQ_SUMMARY

1 1 0 0 1 0 9 8 0 0 0 0 7 6 5 4

EARLY_TERM_IRQ_SUMMARY MASTER_LOSS_IRQ_SUMMARY SLAVE_STOP_IRQ_SUMMARY SLAVE_IRQ_SUMMARY

MASTER_LOSS_IRQ_SUMMARY SLAVE_STOP_IRQ_SUMMARY SLAVE_IRQ_SUMMARY

0 0 0 0 7 6 5 4

EARLY_TERM_IRQ_SUMMARY

1 1 0 0 1 0 9 8

OVERSIZE_XFER_TERM_IRQ_SUMMARY OVERSIZE_XFER_TERM_IRQ_SUMMARY

SLAVE_BUSY BUS_FREE_IRQ_SUMMARY

BUS_FREE_IRQ_SUMMARY

DATA_ENGINE_BUSY

DATA_ENGINE_BUSY SLAVE_BUSY

BUS_BUSY CLK_GEN_BUSY

DATA_ENGINE_DMA_WAIT

DATA_ENGINE_DMA_WAIT

1 1 1 1 5 4 3 2

CLK_GEN_BUSY

SLAVE_SEARCHING

SLAVE_SEARCHING

1 1 1 1 9 8 7 6

BUS_BUSY

SLAVE_ADDR_EQ_ZERO SLAVE_FOUND

SLAVE_FOUND

2 2 2 2 3 2 1 0

SLAVE_ADDR_EQ_ZERO

RCVD_SLAVE_ADDR

RCVD_SLAVE_ADDR

GOT_A_NAK

STMP 3700

STMP 3780

2 2 2 2 7 6 5 4

DATA

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8 0 0 0 0 3 2 1 0

HW_I2C_DATA 0x60

0 0 0 0 3 2 1 0

I2C_DATA_IN

I2C_DATA_IN

3 3 2 2 1 0 9 8

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

141

HW_I2C_VERSION

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

FORCE_ARB_LOSS FORCE_RCV_ACK

FORCE_ARB_LOSS FORCE_RCV_ACK

0 0 0 0 7 6 5 4

FORCE_I2C_CLK_OE

0 0 0 0 7 6 5 4

FORCE_I2C_CLK_OE

DMAKICK

DMAKICK

STOP_TOGGLE

STOP_TOGGLE

TESTMODE

SLAVE_STATE

SLAVE_STATE

SLAVE_HOLD_CLK SLAVE_HOLD_CLK

TESTMODE

CHANGE_TOGGLE CHANGE_TOGGLE

GRAB_TOGGLE

START_TOGGLE

START_TOGGLE GRAB_TOGGLE

DMA_STATE

DMA_STATE

TBD

0 0 0 0 7 6 5 4

FORCE_I2C_DATA_OE FORCE_I2C_DATA_OE

FORCE_CLK_IDLE

1 1 0 0 1 0 9 8

FORCE_CLK_ON

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

FORCE_CLK_ON

1 1 1 1 9 8 7 6

LOCAL_SLAVE_TEST

HW_I2C_DEBUG1

LOCAL_SLAVE_TEST

2 2 2 2 3 2 1 0

1 1 1 1 5 4 3 2

LST_MODE

DMAENDCMD

DMAENDCMD

TBD

DMAREQ

DMAREQ

DMATERMINATE

STMP 3700

STMP 3780

1 1 1 1 9 8 7 6

LST_MODE

CLK_GEN_STATE

2 2 2 2 7 6 5 4

CLK_GEN_STATE

3 3 2 2 1 0 9 8

2 2 2 2 3 2 1 0

STEP

MINOR

MINOR

I2C_CLK_IN

I2C_CLK_IN

DMA_BYTE_ENABLES DMA_BYTE_ENABLES

STMP 3700

2 2 2 2 7 6 5 4

STEP

MAJOR

MAJOR

16.2.10 STMP 3780

16.2.9

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8 0 0 0 0 3 2 1 0

HW_I2C_DEBUG1 0x80

0 0 0 0 3 2 1 0

HW_I2C_VERSION 0x90

0 0 0 0 3 2 1 0

17 17.1

Interrupt Collector Summary

The next table summarizes the important aspects of the Interrupt Collector device block and the main differences between the STMP 3700 and the STMP 3780. Name Interrupt Collector HW_ICOLL_VECTOR HW_ICOLL_LEVELACK HW_ICOLL_CTRL HW_ICOLL_VBASE HW_ICOLL_STAT HW_ICOLL_DEBUG HW_ICOLL_DBGREAD0 HW_ICOLL_DBGREAD1 HW_ICOLL_DBGFLAG HW_ICOLL_VERSION

17.2

Programmable Registers

17.2.1

HW_ICOLL_VECTOR

Property Base Address Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields

STMP 3700 STMP 3780 0x80000000 0x0 0x10 0x20 New Field(s) 0x160

0x40

0x30 Incompatible Field(s) 0x170

0x70 Incompatible Field(s) 0x1120

0x180

0x1130

0x190

0x1140

0x1a0

0x1150

0x1d0

0x11e0

HW_ICOLL_VECTOR

STMP 3780 17.2.2

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

IRQVECTOR IRQVECTOR

2 2 2 2 7 6 5 4

STMP 3700

3 3 2 2 1 0 9 8

0x0

HW_ICOLL_LEVELACK HW_ICOLL_LEVELACK

142

0x10

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

17.2.4 HW_ICOLL_VBASE

143

HW_ICOLL_VBASE STMP 3700 0x160 STMP 3780 0x40 ENABLE2FIQ_T0

ENABLE2FIQ_T1

ENABLE2FIQ_T2

ENABLE2FIQ_T3

1 1 1 1 5 4 3 2

ENABLE2FIQ32

HW_ICOLL_CTRL

ENABLE2FIQ34

1 1 1 1 9 8 7 6

IRQLEVELACK IRQLEVELACK

1 1 1 1 5 4 3 2

ENABLE2FIQ33

STMP 3700

1 1 1 1 9 8 7 6

ENABLE2FIQ35

IRQ_FINAL_ENABLE IRQ_FINAL_ENABLE

ARM_RSE_MODE FIQ_FINAL_ENABLE

2 2 2 2 3 2 1 0

ARM_RSE_MODE

NO_NESTING

NO_NESTING

STMP 3780

2 2 2 2 3 2 1 0

FIQ_FINAL_ENABLE

BYPASS_FSM

BYPASS_FSM

CLKGATE

CLKGATE

2 2 2 2 7 6 5 4 VECTOR_PITCH

SFTRST

SFTRST

3 3 2 2 1 0 9 8

2 2 2 2 7 6 5 4

VECTOR_PITCH

STMP 3700

17.2.3

STMP 3780

3 3 2 2 1 0 9 8

HW_ICOLL_CTRL 0x20

1 1 0 0 1 0 9 8 0 0 0 0 7 6 5 4 0 0 0 0 3 2 1 0

1 1 0 0 1 0 9 8 0 0 0 0 7 6 5 4 0 0 0 0 3 2 1 0

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

STMP 3700 STMP 3780 17.2.5

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

HW_ICOLL_STAT HW_ICOLL_STAT 2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

STMP 3780 0x70

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

VECTOR_NUMBER

2 2 2 2 7 6 5 4

STMP 3700 0x30

STMP 3780

VECTOR_NUMBER

STMP 3700

3 3 2 2 1 0 9 8

17.2.6

0 0 0 0 7 6 5 4

TABLE_ADDRESS TABLE_ADDRESS

3 3 2 2 1 0 9 8

HW_ICOLL_DEBUG HW_ICOLL_DEBUG

STMP 3700 0x170

144

STMP 3780 0x1120

17.2.7

0 0 0 0 3 2 1 0

VECTOR_FSM

0 0 0 0 7 6 5 4

VECTOR_FSM

IRQ IRQ

1 1 0 0 1 0 9 8

HW_ICOLL_DBGREAD0 STMP 3700 0x180

HW_ICOLL_DBGREAD0 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

STMP 3780 0x1130 1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

VALUE

VALUE

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_ICOLL_DBGREAD1 STMP 3700 0x190

HW_ICOLL_DBGREAD1 2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

VALUE

2 2 2 2 7 6 5 4

VALUE

3 3 2 2 1 0 9 8 STMP 3780 STMP 3700

17.2.8

1 1 1 1 5 4 3 2

FIQ

LEVEL_REQUESTS LEVEL_REQUESTS

1 1 1 1 9 8 7 6

FIQ

INSERVICE INSERVICE

2 2 2 2 3 2 1 0 REQUESTS_BY_LEVEL REQUESTS_BY_LEVEL

STMP 3700

2 2 2 2 7 6 5 4

STMP 3780

3 3 2 2 1 0 9 8

145

STMP 3780 0x1140 1 1 0 0 1 0 9 8

17.2.9

HW_ICOLL_DBGFLAG HW_ICOLL_DBGFLAG 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

17.2.10

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

FLAG

2 2 2 2 3 2 1 0

STMP 3700 0x1d0

1 1 1 1 9 8 7 6

STMP 3780 0x11e0

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

STEP

MINOR

STEP

MINOR

MAJOR

2 2 2 2 7 6 5 4

MAJOR

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

18.1

0 0 0 0 3 2 1 0

HW_ICOLL_VERSION HW_ICOLL_VERSION

18

0 0 0 0 7 6 5 4

FLAG

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

STMP 3780 0x1150

STMP 3700 0x1a0

IrDA Controller Summary

The next table summarizes the important aspects of the IrDA device block and the main differences between the STMP 3700 and the STMP 3780. Name IrDA HW_IR_CTRL HW_IR_TXDMA HW_IR_RXDMA HW_IR_DBGCTRL HW_IR_INTR HW_IR_DATA

Property Base Address Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields

146

STMP 3700 STMP 3780 0x80078000 0x0 0x10 0x20 0x30 0x40 0x50

CLKGATE

MTA

MODE

SPEED

CLKGATE

MTA

MODE

SPEED

1 1 1 1 5 4 3 2

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

HW_IR_TXDMA HW_IR_TXDMA

EMPTY

INT

CHANGE

NEW_MTA

NEW_MODE

NEW_SPEED

BOF_TYPE

XBOFS

EMPTY

INT

CHANGE

NEW_MTA

NEW_MODE

NEW_SPEED

BOF_TYPE

XBOFS

1 1 1 1 5 4 3 2

RUN

1 1 1 1 9 8 7 6

RUN

2 2 2 2 3 2 1 0

STMP 3700

2 2 2 2 7 6 5 4

0x10

STMP 3780

3 3 2 2 1 0 9 8

18.2.3

1 1 0 0 1 0 9 8

RXEN

SFTRST SFTRST

1 1 1 1 9 8 7 6

TC_TIME_DIV TC_TIME_DIV

STMP 3700

2 2 2 2 3 2 1 0

HW_IR_RXDMA HW_IR_RXDMA

147

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4 XFER_COUNT XFER_COUNT

18.2.2

2 2 2 2 7 6 5 4

STMP 3780

3 3 2 2 1 0 9 8

0x0

RXEN

HW_IR_CTRL

TXEN

HW_IR_CTRL

TCEN

18.2.1

TXEN

Programmable Registers

TCEN

18.2

0xa0

SIPEN

HW_IR_VERSION

0x90

SIPEN

HW_IR_DEBUG

0x80

SIR_GAP

HW_IR_SI_READ

0x70

SIR_GAP

HW_IR_TCCTRL

STMP 3700 STMP 3780 0x60

TC_TYPE

HW_IR_STAT

Property Address Fields Address Fields Address Fields Address Fields Address Fields

TC_TYPE

Name

0x20

0 0 0 0 3 2 1 0

148 0 0 0 0 7 6 5 4

MIO_EN

MIO_SCLK

MIO_EN

MIO_SCLK

MIO_TX

MIO_RX

MIO_RX MIO_TX

DUPLEX

DUPLEX

XFER_COUNT XFER_COUNT

0 0 0 0 7 6 5 4

TX_IRQ

TXINVERT

TXINVERT

1 1 0 0 1 0 9 8

TX_IRQ

TXCRCOFF

TXCRCOFF

0x30

0 0 0 0 7 6 5 4

TC_IRQ

TXUF_IRQ

TXUF_IRQ

1 1 0 0 1 0 9 8

INTLOOPBACK INTLOOPBACK

TXFRMOFF

TXFRMOFF

HW_IR_DBGCTRL

1 1 0 0 1 0 9 8

RX_IRQ

RXOF_IRQ

RXOF_IRQ

RXINVERT

1 1 1 1 5 4 3 2 RXINVERT

1 1 1 1 9 8 7 6 RXCRCOFF

0x40 RXFRMOFF

HW_IR_INTR RXCRCOFF

1 1 1 1 5 4 3 2

RXFRMOFF

RUN

RUN

1 1 1 1 5 4 3 2

TC_IRQ

SPEED_IRQ

HW_IR_INTR 1 1 1 1 9 8 7 6

VFIRSWZ

HW_IR_DBGCTRL

VFIRSWZ

STMP 3700

STMP 3780

1 1 1 1 9 8 7 6

RX_IRQ

RXABORT_IRQ

RXABORT_IRQ

RX_IRQ_EN

RX_IRQ_EN

2 2 2 2 3 2 1 0

SPEED_IRQ

TC_IRQ_EN

TC_IRQ_EN

2 2 2 2 3 2 1 0

TX_IRQ_EN

TXUF_IRQ_EN

TXUF_IRQ_EN

STMP 3700

2 2 2 2 3 2 1 0

TX_IRQ_EN

RXOF_IRQ_EN

RXOF_IRQ_EN

2 2 2 2 7 6 5 4 SPEED_IRQ_EN

3 3 2 2 1 0 9 8 2 2 2 2 7 6 5 4

SPEED_IRQ_EN

STMP 3780 3 3 2 2 1 0 9 8

2 2 2 2 7 6 5 4

RXABORT_IRQ_EN RXABORT_IRQ_EN

18.2.5

STMP 3700

18.2.4

STMP 3780

3 3 2 2 1 0 9 8 0 0 0 0 3 2 1 0

0 0 0 0 3 2 1 0

0 0 0 0 3 2 1 0

HW_IR_DATA

2 2 2 2 7 6 5 4

0x50

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

2 2 2 2 3 2 1 0

0 0 0 0 3 2 1 0

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

DATA

TX_ACTIVE TX_ACTIVE

TX_SUMMARY TX_SUMMARY

RX_ACTIVE

RX_SUMMARY RX_SUMMARY

MEDIA_BUSY

TC_SUMMARY TC_SUMMARY

RX_ACTIVE

TXUF_SUMMARY TXUF_SUMMARY

MEDIA_BUSY

1 1 1 1 5 4 3 2

RXOF_SUMMARY

ANY_IRQ ANY_IRQ

1 1 1 1 9 8 7 6

2 2 2 2 3 2 1 0 SPEED_SUMMARY

MODE_ALLOWED MODE_ALLOWED

0x60

RXOF_SUMMARY

PRESENT PRESENT

2 2 2 2 7 6 5 4

HW_IR_STAT

SPEED_SUMMARY

STMP 3700 STMP 3780

3 3 2 2 1 0 9 8

HW_IR_TCCTRL

149

INDX

C C

EXT_DATA EXT_DATA

INDX

TEMIC TEMIC

ADDR

BUSY

1 1 1 1 5 4 3 2

ADDR

GO

BUSY

1 1 1 1 9 8 7 6

GO

2 2 2 2 3 2 1 0

INIT

2 2 2 2 7 6 5 4

INIT

3 3 2 2 1 0 9 8

0x70

DATA

HW_IR_TCCTRL

STMP 3780 STMP 3700

18.2.8

0 0 0 0 7 6 5 4

HW_IR_STAT

RXABORT_SUMMARY RXABORT_SUMMARY

18.2.7

1 1 0 0 1 0 9 8

DATA

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_IR_DATA

DATA

18.2.6

HW_IR_SI_READ HW_IR_SI_READ 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

0 0 0 0 7 6 5 4

STMP 3700 STMP 3780

RXDMAREQ

0 0 0 0 7 6 5 4

RXDMAREQ

1 1 0 0 1 0 9 8

0 0 0 0 3 2 1 0 TXDMAREQ

0 0 0 0 7 6 5 4

HW_IR_VERSION HW_IR_VERSION

0xa0 0 0 0 0 3 2 1 0

STEP

1 1 1 1 5 4 3 2

STEP

MINOR

1 1 1 1 9 8 7 6

MINOR

2 2 2 2 3 2 1 0

MAJOR

2 2 2 2 7 6 5 4

MAJOR

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

19.1

DATA

1 1 0 0 1 0 9 8

RXDMAEND

1 1 1 1 5 4 3 2

TXDMAREQ

1 1 1 1 9 8 7 6

RXDMAEND

2 2 2 2 3 2 1 0

TXDMAEND

2 2 2 2 7 6 5 4

0x90

TXDMAKICK TXDMAKICK

3 3 2 2 1 0 9 8

19

DATA

ABORT

HW_IR_DEBUG HW_IR_DEBUG

18.2.11

0 0 0 0 3 2 1 0

TXDMAEND

18.2.10

1 1 0 0 1 0 9 8 ABORT

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

0x80

RXDMAKICK RXDMAKICK

18.2.9

LCD Interface (LCDIF) Summary

The next table summarizes the important aspects of the LCD Interface device block and the main differences between the STMP 3700 and the STMP 3780.

150

Name LCD Interface HW_LCDIF_CTRL HW_LCDIF_CTRL1 HW_LCDIF_TRANSFER_COUNT HW_LCDIF_CUR_BUF HW_LCDIF_NEXT_BUF HW_LCDIF_PAGETABLE HW_LCDIF_TIMING HW_LCDIF_VDCTRL0 HW_LCDIF_VDCTRL1 HW_LCDIF_VDCTRL2 HW_LCDIF_VDCTRL3 HW_LCDIF_VDCTRL4 HW_LCDIF_DVICTRL0 HW_LCDIF_DVICTRL1 HW_LCDIF_DVICTRL2 HW_LCDIF_DVICTRL3 HW_LCDIF_DVICTRL4 HW_LCDIF_CSC_COEFF0 HW_LCDIF_CSC_COEFF1 HW_LCDIF_CSC_COEFF2 HW_LCDIF_CSC_COEFF3 HW_LCDIF_CSC_COEFF4 HW_LCDIF_CSC_OFFSET HW_LCDIF_CSC_LIMIT HW_LCDIF_PIN_SHARING_CTRL0 HW_LCDIF_PIN_SHARING_CTRL1 HW_LCDIF_PIN_SHARING_CTRL2

Property Base Address Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address

151

STMP 3700 STMP 3780 0x80030000 0x0 Incompatible Field(s) Incompatible Field(s) 0x10 New Field(s) New Field(s) Non-Existent 0x20 New Field(s) Non-Existent 0x30 New Field(s) Non-Existent 0x40 New Field(s) Non-Existent 0x50 New Field(s) 0x20 0x60 0x30 New Field(s) 0x40 Incompatible Field(s) 0x50 Incompatible Field(s) 0x60 Incompatible Field(s) Non-Existent

0x80

0x70 New Field(s) 0x80 Incompatible Field(s) 0x90 Incompatible Field(s) 0xa0 Incompatible Field(s) 0xb0 New Field(s) 0xc0 New Field(s) 0xd0

0x90

0xe0

0xa0

0xf0

Non-Existent

0x100 New Field(s) 0x110 New Field(s) 0x120 New Field(s) 0x130 New Field(s) 0x140 New Field(s) 0x150 New Field(s) 0x160 New Field(s) 0x170 New Field(s) 0x180 New Field(s) 0x190 New Field(s) 0x1a0

0x70

Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent

Property Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields

19.2.2

DOTCLK_MODE

DATA_SELECT

WORD_LENGTH

RUN

BYPASS_COUNT

VSYNC_MODE

DOTCLK_MODE

DATA_SELECT

HW_LCDIF_CTRL1 HW_LCDIF_CTRL1

152

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

COUNT

VSYNC_MODE DVI_MODE

0x0

1 1 1 1 5 4 3 2

INPUT_DATA_SWIZZLE

1 1 1 1 9 8 7 6

DATA_SWIZZLE

DVI_MODE

2 2 2 2 3 2 1 0

SHIFT_NUM_BITS

SHIFT_NUM_BITS

DATA_SHIFT_DIR

READ_WRITEB YCBCR422_INPUT

DATA_SHIFT_DIR

CLKGATE CLKGATE

2 2 2 2 7 6 5 4

WAIT_FOR_VSYNC_EDGE

SFTRST SFTRST

WAIT_FOR_VSYNC_EDGE

STMP 3700 STMP 3780

3 3 2 2 1 0 9 8

BYPASS_COUNT

HW_LCDIF_CTRL

0x10

RUN

HW_LCDIF_CTRL

DATA_FORMAT_24_BIT

19.2.1

DATA_FORMAT_18_BIT

Programmable Registers

DATA_FORMAT_16_BIT

19.2

0x1f0 New Field(s) 0x200 New Field(s)

DMA_BURST_LENGTH

HW_LCDIF_DEBUG1

0xe0 New Field(s) Non-Existent

LCDIF_MASTER

HW_LCDIF_DEBUG0

0xc0 New Field(s) 0xd0

ENABLE_PXP_HANDSHAKE

HW_LCDIF_VERSION

0x1c0 New Field(s) 0x1d0 New Field(s) 0x1e0

RGB_TO_YCBCR422_CSC

HW_LCDIF_STAT

Non-Existent

WORD_LENGTH

HW_LCDIF_BM_ERROR_STAT

STMP 3780 New Field(s) 0x1b0

0xb0

LCD_DATABUS_WIDTH

HW_LCDIF_DATA

STMP 3700

CSC_DATA_SWIZZLE

Name

3 3 2 2 1 0 9 8

19.2.4 2 2 2 2 7 6 5 4 2 2 2 2 3 2 1 0

HW_LCDIF_TRANSFER_COUNT

1 1 1 1 9 8 7 6

HW_LCDIF_CUR_BUF

153

UNDERFLOW_IRQ_EN CUR_FRAME_DONE_IRQ_EN VSYNC_EDGE_IRQ_EN OVERFLOW_IRQ UNDERFLOW_IRQ CUR_FRAME_DONE_IRQ VSYNC_EDGE_IRQ

CUR_FRAME_DONE_IRQ_EN VSYNC_EDGE_IRQ_EN OVERFLOW_IRQ UNDERFLOW_IRQ CUR_FRAME_DONE_IRQ VSYNC_EDGE_IRQ

1 1 1 1 5 4 3 2

STMP 3700 Non-Existent STMP 3700 Non-Existent

1 1 0 0 1 0 9 8

HW_LCDIF_CUR_BUF

STMP 3780 0x30

FIRST_READ_DUMMY LCD_CS_CTRL BUSY_ENABLE MODE86 RESET

PAUSE_TRANSFER_IRQ LCD_CS_CTRL BUSY_ENABLE MODE86 RESET

1 1 0 0 1 0 9 8

PAUSE_TRANSFER_IRQ_EN

1 1 1 1 5 4 3 2 READ_MODE_NUM_PACKED_SUBWORDS

OVERFLOW_IRQ_EN

OVERFLOW_IRQ_EN UNDERFLOW_IRQ_EN

1 1 1 1 9 8 7 6

PAUSE_TRANSFER

BYTE_PACKING_FORMAT

STMP 3700

2 2 2 2 3 2 1 0

BYTE_PACKING_FORMAT

IRQ_ON_ALTERNATE_FIELDS

FIFO_CLEAR

START_INTERLACE_FROM_SECOND_FIELD

INTERLACE_FIELDS

RECOVER_ON_UNDERFLOW

BM_ERROR_IRQ

BM_ERROR_IRQ_EN

STMP 3780

2 2 2 2 7 6 5 4

H_COUNT

19.2.3

V_COUNT

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8 0 0 0 0 7 6 5 4

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

HW_LCDIF_TRANSFER_COUNT

STMP 3780 0x20

0 0 0 0 3 2 1 0

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

0 0 0 0 3 2 1 0

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

STMP 3780 0x40

STMP 3700 Non-Existent

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

ADDR

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_LCDIF_PAGETABLE

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

FLUSH

2 2 2 2 3 2 1 0

BASE

2 2 2 2 7 6 5 4

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

STMP 3780 0x50

STMP 3700 Non-Existent

HW_LCDIF_PAGETABLE

19.2.7

0 0 0 0 7 6 5 4

HW_LCDIF_NEXT_BUF HW_LCDIF_NEXT_BUF

19.2.6

1 1 0 0 1 0 9 8

HW_LCDIF_TIMING HW_LCDIF_TIMING

STMP 3700 0x20

154

STMP 3780 0x60

ENABLE

19.2.5

1 1 1 1 5 4 3 2

ADDR

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

19.2.9 VSYNC_OEB ENABLE_PRESENT VSYNC_POL HSYNC_POL DOTCLK_POL ENABLE_POL

VSYNC_PERIOD_UNIT

VSYNC_OEB ENABLE_PRESENT VSYNC_POL HSYNC_POL DOTCLK_POL ENABLE_POL

VSYNC_PERIOD_UNIT

DOTCLK_V_VALID_DATA_CNT

HW_LCDIF_VDCTRL0

HW_LCDIF_VDCTRL1 VSYNC_PULSE_WIDTH

2 2 2 2 3 2 1 0

DATA_HOLD

CMD_SETUP

1 1 1 1 9 8 7 6

1 1 1 1 9 8 7 6

155

1 1 1 1 5 4 3 2

STMP 3700 0x30 1 1 1 1 5 4 3 2

STMP 3700 0x40

DATA_SETUP DATA_SETUP

DATA_HOLD

CMD_SETUP

CMD_HOLD

CMD_HOLD

2 2 2 2 3 2 1 0

HALF_LINE_MODE

2 2 2 2 7 6 5 4

INTERLACE

3 3 2 2 1 0 9 8

HALF_LINE

STMP 3700

STMP 3780

2 2 2 2 7 6 5 4

VSYNC_PULSE_WIDTH_UNIT VSYNC_PULSE_WIDTH_UNIT

STMP 3700

19.2.8

STMP 3780

3 3 2 2 1 0 9 8 1 1 0 0 1 0 9 8

1 1 0 0 1 0 9 8

HW_LCDIF_VDCTRL1

STMP 3780 0x80

0 0 0 0 7 6 5 4

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

HW_LCDIF_VDCTRL0 STMP 3780 0x70

0 0 0 0 3 2 1 0

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

VSYNC_PERIOD

0 0 0 0 7 6 5 4

HW_LCDIF_VDCTRL2 STMP 3700 0x50

HW_LCDIF_VDCTRL2

1 1 1 1 9 8 7 6

STMP 3780 0x90

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

HSYNC_PERIOD

DOTCLK_H_VALID_DATA_CNT

2 2 2 2 3 2 1 0

HSYNC_PULSE_WIDTH

2 2 2 2 7 6 5 4

HSYNC_PERIOD

HSYNC_PULSE_WIDTH

STMP 3780

STMP 3700

3 3 2 2 1 0 9 8

19.2.11

1 1 0 0 1 0 9 8

VSYNC_PERIOD

STMP 3700 STMP 3780 19.2.10

1 1 1 1 5 4 3 2

VSYNC_PULSE_WIDTH

3 3 2 2 1 0 9 8

HW_LCDIF_VDCTRL3 HW_LCDIF_VDCTRL3

STMP 3700 0x60

156

STMP 3780 0xa0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

VERTICAL_WAIT_CNT

0 0 0 0 3 2 1 0

HW_LCDIF_VDCTRL4 HW_LCDIF_VDCTRL4 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

STMP 3700 Non-Existent

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

STMP 3780 0xb0 1 1 0 0 1 0 9 8

DOTCLK_H_VALID_DATA_CNT

SYNC_SIGNALS_ON

STMP 3780

STMP 3700

3 3 2 2 1 0 9 8

19.2.13

0 0 0 0 7 6 5 4

VERTICAL_WAIT_CNT

HORIZONTAL_WAIT_CNT

VSYNC_ONLY

MUX_SYNC_SIGNALS

STMP 3700 STMP 3780 19.2.12

2 2 2 2 3 2 1 0

HORIZONTAL_WAIT_CNT

2 2 2 2 7 6 5 4

SYNC_SIGNALS_ON

3 3 2 2 1 0 9 8

HW_LCDIF_DVICTRL0 HW_LCDIF_DVICTRL0

STMP 3700 0x70

157

STMP 3780 0xc0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

1 1 1 1 9 8 7 6

1 1 0 0 1 0 9 8

0 0 0 0 3 2 1 0

V_LINES_CNT

V_LINES_CNT

0 0 0 0 7 6 5 4

HW_LCDIF_DVICTRL1

1 1 1 1 9 8 7 6

1 1 0 0 1 0 9 8

F1_END_LINE

1 1 1 1 5 4 3 2

STMP 3780 0xd0

F1_END_LINE

STMP 3780

2 2 2 2 3 2 1 0

F1_START_LINE F1_START_LINE

2 2 2 2 7 6 5 4

STMP 3700

3 3 2 2 1 0 9 8

STMP 3700 0x80

HW_LCDIF_DVICTRL2 HW_LCDIF_DVICTRL2

STMP 3700 0x90

158

0 0 0 0 7 6 5 4 F2_START_LINE F2_START_LINE

HW_LCDIF_DVICTRL1

19.2.15

1 1 1 1 5 4 3 2 H_BLANKING_CNT H_BLANKING_CNT

2 2 2 2 3 2 1 0

H_ACTIVE_CNT

START_TRS

STMP 3700 STMP 3780 19.2.14

2 2 2 2 7 6 5 4 H_ACTIVE_CNT

3 3 2 2 1 0 9 8

STMP 3780 0xe0

0 0 0 0 3 2 1 0

1 1 0 0 1 0 9 8

0 0 0 0 3 2 1 0

V1_BLANK_END_LINE

0 0 0 0 7 6 5 4

HW_LCDIF_DVICTRL3 HW_LCDIF_DVICTRL3

STMP 3780

2 2 2 2 3 2 1 0

STMP 3700 0xa0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

STMP 3780 0xf0 1 1 0 0 1 0 9 8

HW_LCDIF_DVICTRL4 HW_LCDIF_DVICTRL4

0 0 0 0 7 6 5 4 V2_BLANK_END_LINE

V2_BLANK_START_LINE V2_BLANK_START_LINE

2 2 2 2 7 6 5 4

STMP 3700

3 3 2 2 1 0 9 8

19.2.17

1 1 1 1 5 4 3 2

V1_BLANK_END_LINE

F2_END_LINE F2_END_LINE

1 1 1 1 9 8 7 6

V1_BLANK_START_LINE V1_BLANK_START_LINE

STMP 3700

2 2 2 2 3 2 1 0

V2_BLANK_END_LINE

19.2.16

2 2 2 2 7 6 5 4

STMP 3780

3 3 2 2 1 0 9 8

STMP 3700 Non-Existent

159

STMP 3780 0x100

0 0 0 0 3 2 1 0

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

H_FILL_CNT

CB_FILL_VALUE

Y_FILL_VALUE

STMP 3780 19.2.18

CR_FILL_VALUE

STMP 3700

3 3 2 2 1 0 9 8

HW_LCDIF_CSC_COEFF0 HW_LCDIF_CSC_COEFF0 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

STMP 3780 0x110 1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

CSC_SUBSAMPLE_FILTER

HW_LCDIF_CSC_COEFF1 HW_LCDIF_CSC_COEFF1 2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

STMP 3780 0x120 1 1 0 0 1 0 9 8

C1

2 2 2 2 7 6 5 4

STMP 3700 Non-Existent

C2

3 3 2 2 1 0 9 8 STMP 3780 STMP 3700

19.2.19

C0

STMP 3780

STMP 3700

3 3 2 2 1 0 9 8

STMP 3700 Non-Existent

160

19.2.20

HW_LCDIF_CSC_COEFF2 HW_LCDIF_CSC_COEFF2 2 2 2 2 7 6 5 4

19.2.21

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

0 0 0 0 3 2 1 0

C3

0 0 0 0 7 6 5 4

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

STMP 3780 0x140 1 1 0 0 1 0 9 8

C6

2 2 2 2 3 2 1 0

STMP 3700 Non-Existent

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

C5

2 2 2 2 7 6 5 4

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_LCDIF_CSC_COEFF4 HW_LCDIF_CSC_COEFF4 1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

STMP 3780 0x150 1 1 0 0 1 0 9 8

C8

2 2 2 2 3 2 1 0

STMP 3700 Non-Existent

0 0 0 0 7 6 5 4

C7

2 2 2 2 7 6 5 4

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

19.2.23

1 1 0 0 1 0 9 8

HW_LCDIF_CSC_COEFF3 HW_LCDIF_CSC_COEFF3

19.2.22

1 1 1 1 5 4 3 2

STMP 3780 0x130

C4

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

STMP 3700 Non-Existent

HW_LCDIF_CSC_OFFSET HW_LCDIF_CSC_OFFSET

STMP 3700 Non-Existent

161

STMP 3780 0x160

0 0 0 0 3 2 1 0

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

HW_LCDIF_CSC_LIMIT HW_LCDIF_CSC_LIMIT

19.2.25

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

STMP 3780 0x170

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

Y_MIN

CBCR_MAX

2 2 2 2 7 6 5 4

CBCR_MIN

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

STMP 3700 Non-Existent

0 0 0 0 3 2 1 0

Y_MAX

19.2.24

Y_OFFSET

STMP 3780

CBCR_OFFSET

STMP 3700

3 3 2 2 1 0 9 8

HW_LCDIF_PIN_SHARING_CTRL0 HW_LCDIF_PIN_SHARING_CTRL0 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

STMP 3780 0x180

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

19.2.26

HW_LCDIF_PIN_SHARING_CTRL1 HW_LCDIF_PIN_SHARING_CTRL1 162

STMP 3700 Non-Existent

STMP 3780 0x190

PIN_SHARING_ENABLE

PIN_SHARING_IRQ

PIN_SHARING_IRQ_EN

STMP 3780

MUX_OVERRIDE

STMP 3700

3 3 2 2 1 0 9 8

STMP 3700 Non-Existent

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

STMP 3780

THRESHOLD1

STMP 3700

3 3 2 2 1 0 9 8

19.2.27

HW_LCDIF_PIN_SHARING_CTRL2 HW_LCDIF_PIN_SHARING_CTRL2 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

STMP 3780 0x1a0

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

STMP 3780

THRESHOLD2

STMP 3700

3 3 2 2 1 0 9 8

STMP 3700 Non-Existent

HW_LCDIF_DATA

19.2.29

2 2 2 2 3 2 1 0

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

DATA_TWO

DATA_ONE

DATA_TWO

1 1 1 1 9 8 7 6

STMP 3780 0x1b0

DATA_ZERO

2 2 2 2 7 6 5 4 DATA_THREE DATA_THREE

STMP 3780

STMP 3700

3 3 2 2 1 0 9 8

STMP 3700 0xb0

DATA_ZERO

HW_LCDIF_DATA

DATA_ONE

19.2.28

HW_LCDIF_BM_ERROR_STAT HW_LCDIF_BM_ERROR_STAT

163

STMP 3700 Non-Existent

STMP 3780 0x1c0

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

HW_LCDIF_STAT HW_LCDIF_STAT

PRESENT

DMA_REQ

RXFIFO_FULL

RXFIFO_EMPTY

TXFIFO_FULL

TXFIFO_EMPTY

BUSY

PRESENT

DMA_REQ

LFIFO_FULL

LFIFO_EMPTY

TXFIFO_FULL

TXFIFO_EMPTY

BUSY

2 2 2 2 3 2 1 0

STMP 3700 0xc0

1 1 1 1 9 8 7 6

STMP 3780 0x1d0

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

DVI_CURRENT_FIELD DVI_CURRENT_FIELD

STMP 3700

2 2 2 2 7 6 5 4

STMP 3780

3 3 2 2 1 0 9 8

HW_LCDIF_VERSION HW_LCDIF_VERSION

STMP 3700 0xd0

STMP 3780 0x1e0

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

STEP

MINOR

1 1 1 1 9 8 7 6

MINOR

2 2 2 2 3 2 1 0

MAJOR

2 2 2 2 7 6 5 4

MAJOR

3 3 2 2 1 0 9 8 STMP 3780 STMP 3700

19.2.31

1 1 0 0 1 0 9 8

STEP

19.2.30

1 1 1 1 5 4 3 2

ADDR

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

164

HW_LCDIF_DEBUG0

19.2.33

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

DATA_COUNT GPMI_LCDIF_REQ

0 0 0 0 7 6 5 4

LCDIF_GPMI_GRANT

LCDIF_PXP_B1_DONE

CUR_FRAME_TX CUR_FRAME_TX

1 1 0 0 1 0 9 8

PXP_LCDIF_B1_READY

VSYNC VSYNC

STMP 3780 0x1f0

1 1 1 1 5 4 3 2

LCDIF_PXP_B0_DONE

HSYNC HSYNC

CUR_STATE

ENABLE ENABLE

1 1 1 1 9 8 7 6

CUR_STATE

DMACMDKICK DMACMDKICK

2 2 2 2 3 2 1 0

EMPTY_WORD

SYNC_SIGNALS_ON_REG

2 2 2 2 7 6 5 4

SYNC_SIGNALS_ON_REG

STREAMING_END_DETECTED STREAMING_END_DETECTED

WAIT_FOR_VSYNC_EDGE_OUT WAIT_FOR_VSYNC_EDGE_OUT

STMP 3700 STMP 3780

3 3 2 2 1 0 9 8

STMP 3700 0xe0

EMPTY_WORD

HW_LCDIF_DEBUG0

PXP_LCDIF_B0_READY

19.2.32

HW_LCDIF_DEBUG1 HW_LCDIF_DEBUG1 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

STMP 3780 0x200

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

20 20.1

V_DATA_COUNT

H_DATA_COUNT

STMP 3780

STMP 3700

3 3 2 2 1 0 9 8

STMP 3700 Non-Existent

Low-Resolution ADC and Touch-Screen Interface Summary

The next table summarizes the important aspects of the Low Resolution ADC device block and the main differences between the STMP 3700 and the STMP 3780.

165

Name Low Resolution ADC

Property Base Address Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields

HW_LRADC_CTRL0 HW_LRADC_CTRL1 HW_LRADC_CTRL2 HW_LRADC_CTRL3 HW_LRADC_STATUS HW_LRADC_CH6 HW_LRADC_CH7 HW_LRADC_DEBUG0 HW_LRADC_DEBUG1 HW_LRADC_CONVERSION HW_LRADC_CTRL4 HW_LRADC_VERSION

20.2

Programmable Registers

20.2.1

HW_LRADC_CTRL0 HW_LRADC_CTRL0

0x30 0x40 0xb0 0xc0 0x110 0x120 0x130 0x140 0x150

0x0 1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

SCHEDULE

1 1 1 1 5 4 3 2

SCHEDULE

YPLUS_ENABLE YPLUS_ENABLE

0x20

XPLUS_ENABLE

XMINUS_ENABLE XMINUS_ENABLE

0x10

XPLUS_ENABLE

YMINUS_ENABLE

ONCHIP_GROUNDREF ONCHIP_GROUNDREF

1 1 1 1 9 8 7 6

YMINUS_ENABLE

CLKGATE CLKGATE

TOUCH_DETECT_ENABLE TOUCH_DETECT_ENABLE

SFTRST SFTRST

2 2 2 2 3 2 1 0

STMP 3700

2 2 2 2 7 6 5 4

STMP 3780

3 3 2 2 1 0 9 8

STMP 3700 STMP 3780 0x80050000 0x0

166

20.2.4 EXT_EN0

EXT_EN0

167

HW_LRADC_CTRL3

HW_LRADC_CTRL3

0x30 TEMP_ISRC0

1 1 0 0 1 0 9 8

TEMP_ISRC0

1 1 1 1 5 4 3 2

TEMP_ISRC1

HW_LRADC_CTRL2

LRADC6_IRQ LRADC5_IRQ LRADC4_IRQ LRADC3_IRQ LRADC2_IRQ LRADC1_IRQ LRADC0_IRQ

LRADC6_IRQ LRADC5_IRQ LRADC4_IRQ LRADC3_IRQ LRADC2_IRQ LRADC1_IRQ LRADC0_IRQ

TOUCH_DETECT_IRQ LRADC7_IRQ

LRADC0_IRQ_EN

LRADC0_IRQ_EN

LRADC7_IRQ

LRADC1_IRQ_EN

LRADC1_IRQ_EN

1 1 0 0 1 0 9 8

TEMP_ISRC1

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

TOUCH_DETECT_IRQ

LRADC2_IRQ_EN

LRADC2_IRQ_EN

1 1 1 1 9 8 7 6

TEMP_SENSOR_IENABLE0 TEMP_SENSOR_IENABLE0

LRADC3_IRQ_EN

LRADC3_IRQ_EN

LRADC5_IRQ_EN

LRADC5_IRQ_EN

LRADC4_IRQ_EN

LRADC6_IRQ_EN

LRADC6_IRQ_EN LRADC4_IRQ_EN

LRADC7_IRQ_EN

LRADC7_IRQ_EN

TOUCH_DETECT_IRQ_EN TOUCH_DETECT_IRQ_EN

HW_LRADC_CTRL1

TEMP_SENSOR_IENABLE1 TEMP_SENSOR_IENABLE1

EXT_EN1

2 2 2 2 3 2 1 0

EXT_EN1

BL_MUX_SELECT

BL_MUX_SELECT

2 2 2 2 7 6 5 4

TEMPSENSE_PWD

BL_ENABLE

BL_ENABLE

3 3 2 2 1 0 9 8 2 2 2 2 3 2 1 0

TEMPSENSE_PWD

BL_AMP_BYPASS

BL_AMP_BYPASS

STMP 3700

2 2 2 2 7 6 5 4

BL_BRIGHTNESS

DIVIDE_BY_TWO

DIVIDE_BY_TWO

STMP 3780 3 3 2 2 1 0 9 8

BL_BRIGHTNESS

STMP 3700

20.2.3

STMP 3780

20.2.2 HW_LRADC_CTRL1 0x10 0 0 0 0 7 6 5 4

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

HW_LRADC_CTRL2 0x20

0 0 0 0 3 2 1 0

20.2.6 TEMP1_PRESENT TEMP0_PRESENT

TEMP1_PRESENT

TEMP0_PRESENT

CHANNEL4_PRESENT CHANNEL3_PRESENT CHANNEL2_PRESENT CHANNEL1_PRESENT CHANNEL0_PRESENT

CHANNEL4_PRESENT

CHANNEL3_PRESENT

CHANNEL2_PRESENT

CHANNEL1_PRESENT

CHANNEL0_PRESENT

2 2 2 2 3 2 1 0 1 1 1 1 9 8 7 6

168

HW_LRADC_STATUS

1 1 1 1 5 4 3 2

HW_LRADC_CH6

HW_LRADC_CH6

0xb0 1 1 0 0 1 0 9 8 0 0 0 0 7 6 5 4

INVERT_CLOCK

INVERT_CLOCK

DELAY_CLOCK

0 0 0 0 7 6 5 4

DELAY_CLOCK

1 1 0 0 1 0 9 8

HIGH_TIME

CYCLE_TIME

1 1 1 1 5 4 3 2

HIGH_TIME

CYCLE_TIME

1 1 1 1 9 8 7 6

TOUCH_DETECT_RAW

CHANNEL5_PRESENT

CHANNEL5_PRESENT

FORCE_ANALOG_PWUP

FORCE_ANALOG_PWUP

FORCE_ANALOG_PWDN FORCE_ANALOG_PWDN

DISCARD

DISCARD

2 2 2 2 3 2 1 0

TOUCH_DETECT_RAW

CHANNEL6_PRESENT

CHANNEL6_PRESENT

2 2 2 2 7 6 5 4

CHANNEL7_PRESENT

STMP 3700

STMP 3780

2 2 2 2 7 6 5 4

CHANNEL7_PRESENT

3 3 2 2 1 0 9 8

TOUCH_PANEL_PRESENT TOUCH_PANEL_PRESENT

STMP 3700

20.2.5

STMP 3780

3 3 2 2 1 0 9 8 0 0 0 0 3 2 1 0

HW_LRADC_STATUS 0x40

0 0 0 0 3 2 1 0

20.2.7

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

HW_LRADC_CH7 HW_LRADC_CH7 1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

VALUE

NUM_SAMPLES NUM_SAMPLES

2 2 2 2 3 2 1 0

0xc0

VALUE

ACCUMULATE

2 2 2 2 7 6 5 4

ACCUMULATE

TOGGLE TOGGLE

TESTMODE_TOGGLE TESTMODE_TOGGLE

STMP 3700 STMP 3780

3 3 2 2 1 0 9 8

HW_LRADC_DEBUG0 HW_LRADC_DEBUG0 2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

0x110 1 1 0 0 1 0 9 8

STATE

1 1 1 1 5 4 3 2

STATE

2 2 2 2 7 6 5 4

READONLY READONLY

3 3 2 2 1 0 9 8 STMP 3780 STMP 3700

20.2.8

1 1 0 0 1 0 9 8

VALUE

ACCUMULATE ACCUMULATE

2 2 2 2 3 2 1 0

VALUE

TOGGLE TOGGLE

2 2 2 2 7 6 5 4 NUM_SAMPLES NUM_SAMPLES

STMP 3700 STMP 3780

3 3 2 2 1 0 9 8

169

HW_LRADC_DEBUG1

0 0 0 0 3 2 1 0

REQUEST

TESTMODE

0 0 0 0 7 6 5 4

TESTMODE

0 0 0 0 3 2 1 0

TESTMODE5

0 0 0 0 7 6 5 4

HW_LRADC_CONVERSION HW_LRADC_CONVERSION

SCALE_FACTOR SCALE_FACTOR

1 1 1 1 9 8 7 6

AUTOMATIC

STMP 3780

2 2 2 2 3 2 1 0

AUTOMATIC

2 2 2 2 7 6 5 4

STMP 3700

3 3 2 2 1 0 9 8

20.2.11

1 1 0 0 1 0 9 8

TESTMODE6

1 1 1 1 5 4 3 2

REQUEST

STMP 3780 20.2.10

1 1 1 1 9 8 7 6

TESTMODE5

2 2 2 2 3 2 1 0

TESTMODE_COUNT TESTMODE_COUNT

2 2 2 2 7 6 5 4

STMP 3700

3 3 2 2 1 0 9 8

0x120

TESTMODE6

HW_LRADC_DEBUG1

0x130

1 1 1 1 5 4 3 2

HW_LRADC_CTRL4 HW_LRADC_CTRL4

170

1 1 0 0 1 0 9 8

SCALED_BATT_VOLTAGE SCALED_BATT_VOLTAGE

20.2.9

0x140

1 1 1 1 5 4 3 2

LRADC6SELECT LRADC6SELECT

LRADC5SELECT LRADC5SELECT

LRADC4SELECT LRADC4SELECT

LRADC3SELECT LRADC3SELECT

2 2 2 2 3 2 1 0

0 0 0 0 3 2 1 0

1 1 1 1 9 8 7 6

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0x150

1 1 1 1 5 4 3 2

STEP

MINOR

STEP

MINOR

MAJOR

2 2 2 2 7 6 5 4

MAJOR

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

21.1

0 0 0 0 7 6 5 4

HW_LRADC_VERSION HW_LRADC_VERSION

21

1 1 0 0 1 0 9 8

LRADC0SELECT LRADC0SELECT

1 1 1 1 9 8 7 6

LRADC1SELECT LRADC1SELECT

2 2 2 2 3 2 1 0

LRADC2SELECT LRADC2SELECT

2 2 2 2 7 6 5 4

LRADC7SELECT LRADC7SELECT

STMP 3700 STMP 3780 20.2.12

3 3 2 2 1 0 9 8

Memory Copy Device Summary

The next table summarizes the important aspects of the Memory Copy Device device block and the main differences between the STMP 3700 and the STMP 3780. Name Memory Copy Device HW_MEMCPY_CTRL HW_MEMCPY_DATA HW_MEMCPY_DEBUG

21.2

Programmable Registers

21.2.1

HW_MEMCPY_CTRL

Property Base Address Address Fields Address Fields Address Fields

HW_MEMCPY_CTRL

STMP 3700 0xe0014000 0x0 New Field(s) 0x10 New Field(s) 0x20 New Field(s)

STMP 3700 0x0

171

STMP 3780 Non-Existent Non-Existent Non-Existent Non-Existent

STMP 3780 Non-Existent

1 1 1 1 9 8 7 6

BURST

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

STMP 3700 0x10

1 1 1 1 9 8 7 6

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

STMP 3780 Non-Existent

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

HW_MEMCPY_DEBUG HW_MEMCPY_DEBUG 2 2 2 2 3 2 1 0

STMP 3700 0x20

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

STMP 3780 Non-Existent 1 1 0 0 1 0 9 8

WRITE_STATE

SRC_DMA_REQ

2 2 2 2 7 6 5 4

SRC_KICK

DST_DMA_REQ

DST_KICK

DST_END_CMD

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

22.1

0 0 0 0 7 6 5 4

DATA

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

22

1 1 0 0 1 0 9 8

HW_MEMCPY_DATA HW_MEMCPY_DATA

21.2.3

1 1 1 1 5 4 3 2

XFER_SIZE

2 2 2 2 3 2 1 0

PRESENT

CLKGATE

2 2 2 2 7 6 5 4

READ_STATE

21.2.2

SFTRST

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

On-Chip OTP (OCOTP) Controller Summary

The next table summarizes the important aspects of the One-time Programmable Array Controller device block and the main differences between the STMP 3700 and the STMP 3780.

172

Property

0x8002c000

Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields

0x0

HW_OCOTP_ROM3 HW_OCOTP_ROM4 HW_OCOTP_ROM5 HW_OCOTP_ROM6 HW_OCOTP_ROM7 HW_OCOTP_VERSION

22.2.1

HW_OCOTP_CTRL

Non-Existent Non-Existent Non-Existent Non-Existent 0x220

HW_OCOTP_CTRL 1 1 1 1 9 8 7 6

0x0

1 1 1 1 5 4 3 2 RELOAD_SHADOWS RELOAD_SHADOWS

WR_UNLOCK WR_UNLOCK

2 2 2 2 3 2 1 0

STMP 3700

2 2 2 2 7 6 5 4

STMP 3780

3 3 2 2 1 0 9 8

0x1e0 New Field(s) 0x1f0 New Field(s) 0x200 New Field(s) 0x210 New Field(s)

173

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

ADDR

HW_OCOTP_ROM2

ADDR

HW_OCOTP_ROM1

BUSY

HW_OCOTP_ROM0

New Field(s) 0x120 Incompatible Field(s) Incompatible Field(s) Non-Existent 0x1a0 New Field(s) Non-Existent 0x1b0 New Field(s) Non-Existent 0x1c0 New Field(s) Non-Existent 0x1d0

BUSY

HW_OCOTP_LOCK

0x110 New Field(s)

ERROR

HW_OCOTP_CUSTCAP

0x100

ERROR

HW_OCOTP_SWCAP

0x10

RD_BANK_OPEN

HW_OCOTP_DATA

Programmable Registers

STMP 3780

Base Address

HW_OCOTP_CTRL

22.2

STMP 3700

RD_BANK_OPEN

Name One-time Programmable Array Controller

HW_OCOTP_DATA HW_OCOTP_DATA 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

DATA

HW_OCOTP_SWCAP HW_OCOTP_SWCAP 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

0x100

1 1 1 1 5 4 3 2

BITS

BITS

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_OCOTP_CUSTCAP HW_OCOTP_CUSTCAP 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

0x110

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

174

RTC_XTAL_32000_PRESENT

ENABLE_SJTAG_12MA_DRIVE

CUST_DISABLE_JANUSDRM10

CUST_DISABLE_WMADRM9

BITS

STMP 3700

3 3 2 2 1 0 9 8

STMP 3780

22.2.4

1 1 0 0 1 0 9 8

RTC_XTAL_32768_PRESENT

22.2.3

1 1 1 1 5 4 3 2

DATA

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

0x10

USE_PARALLEL_JTAG

22.2.2

22.2.7

HW_OCOTP_ROM1

175

STMP 3700 Non-Existent

HW_OCOTP_ROM1

STMP 3780 0x1b0

HWSW CUSTCAP_SHADOW HWSW_SHADOW CRYPTODCP CRYPTOKEY CUST3 CUST2 CUST1 CUST0

HWSW CUSTCAP_SHADOW HWSW_SHADOW CRYPTODCP CRYPTOKEY CUST3 CUST2 CUST1 CUST0

CUSTCAP CUSTCAP

ROM_SHADOW

UNALLOCATED

UN0

UN0

UNALLOCATED

UN2 UN1

UN1

PIN

0 0 0 0 7 6 5 4

0 0 0 0 7 6 5 4

SD_MBR_BOOT

1 1 0 0 1 0 9 8

ENABLE_UNENCRYPTED_BOOT

1 1 1 1 5 4 3 2

ENABLE_USB_BOOT_SERIAL_NUM

STMP 3700 Non-Existent

1 1 0 0 1 0 9 8

DISABLE_SPI_NOR_FAST_READ

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

SSP_SCK_INDEX

2 2 2 2 3 2 1 0 UN2

CRYPTOKEY_ALT PIN

CRYPTOKEY_ALT

OPS

CRYPTODCP_ALT

CRYPTODCP_ALT

1 1 1 1 9 8 7 6

OPS

ROM0

HW_OCOTP_LOCK

SD_BUS_WIDTH

HW_OCOTP_ROM0

SD_POWER_UP_DELAY

SD_POWER_GATE_GPIO

2 2 2 2 7 6 5 4

USE_PARALLEL_JTAG

3 3 2 2 1 0 9 8 2 2 2 2 3 2 1 0

HWSW_SHADOW_ALT HWSW_SHADOW_ALT

ROM0

ROM4

ROM4

ROM1

ROM5

ROM5

ROM1

ROM6

ROM6

ROM3

ROM7

ROM7

ROM2

STMP 3700

STMP 3780

ROM2

2 2 2 2 7 6 5 4

ROM3

3 3 2 2 1 0 9 8

ENABLE_PJTAG_12MA_DRIVE

STMP 3700

22.2.6

BOOT_MODE

STMP 3780

22.2.5 HW_OCOTP_LOCK 0x120 0 0 0 0 3 2 1 0

HW_OCOTP_ROM0 STMP 3780 0x1a0

0 0 0 0 3 2 1 0

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

ENABLE_NAND3_CE_RDY_PULLUP

UNTOUCH_INTERNAL_SSP_PULLUP

SD_INIT_SEQ_2_ENABLE

2 2 2 2 7 6 5 4

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

22.2.8

NUMBER_OF_NANDS

BOOT_SEARCH_COUNT

USE_ALT_SSP1_DATA4_7

SD_INIT_SEQ_1_DISABLE

SD_CMD0_DISABLE

SD_INCREASE_INIT_SEQ_TIME

HW_OCOTP_ROM2 HW_OCOTP_ROM2 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

STMP 3700 Non-Existent

1 1 1 1 9 8 7 6

STMP 3780 0x1c0

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

USB_PID

USB_VID

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_OCOTP_ROM3 HW_OCOTP_ROM3 3 3 2 2 1 0 9 8

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

STMP 3700 Non-Existent

1 1 1 1 9 8 7 6

STMP 3780 STMP 3700

22.2.9

SSP1_EXT_PULLUP

SSP2_EXT_PULLUP

ENABLE_NAND0_CE_RDY_PULLUP

ENABLE_NAND1_CE_RDY_PULLUP

ENABLE_NAND2_CE_RDY_PULLUP

USE_ALT_GPMI_CE2

USE_ALT_GPMI_RDY2

USE_ALT_GPMI_CE3

USE_ALT_GPMI_RDY3

STMP 3780

STMP 3700

3 3 2 2 1 0 9 8

176

STMP 3780 0x1d0

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

22.2.10

HW_OCOTP_ROM4 HW_OCOTP_ROM4 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

22.2.11

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

STMP 3700 Non-Existent

1 1 1 1 9 8 7 6

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

STMP 3780 0x1f0

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

BITS

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_OCOTP_ROM6 HW_OCOTP_ROM6 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

STMP 3700 Non-Existent

1 1 1 1 9 8 7 6

STMP 3780 0x200

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

BITS

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

22.2.13

1 1 1 1 5 4 3 2

HW_OCOTP_ROM5 HW_OCOTP_ROM5

22.2.12

STMP 3780 0x1e0

BITS

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

STMP 3700 Non-Existent

HW_OCOTP_ROM7 HW_OCOTP_ROM7

STMP 3700 Non-Existent

177

STMP 3780 0x210

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

22.2.14

1 1 1 1 5 4 3 2

2 2 2 2 3 2 1 0

0 0 0 0 3 2 1 0

1 1 1 1 9 8 7 6

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0x220

1 1 1 1 5 4 3 2

STEP

MINOR

STEP

MINOR

MAJOR

2 2 2 2 7 6 5 4

MAJOR

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

23.1

0 0 0 0 7 6 5 4

HW_OCOTP_VERSION HW_OCOTP_VERSION

23

1 1 0 0 1 0 9 8

BITS

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

Pin Control and GPIO Summary

The next table summarizes the important aspects of the Pin Control device block and the main differences between the STMP 3700 and the STMP 3780. Name Pin Control HW_PINCTRL_CTRL HW_PINCTRL_MUXSEL0 HW_PINCTRL_MUXSEL1 HW_PINCTRL_MUXSEL2 HW_PINCTRL_MUXSEL3 HW_PINCTRL_MUXSEL4 HW_PINCTRL_MUXSEL5 HW_PINCTRL_MUXSEL6 HW_PINCTRL_MUXSEL7

Property Base Address Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields

178

STMP 3700 STMP 3780 0x80018000 0x0 Incompatible Field(s) Incompatible Field(s) 0x100 0x110 New Field(s) 0x120 0x130 New Field(s) 0x140 0x150 0x160 0x170

Name HW_PINCTRL_DRIVE0 HW_PINCTRL_DRIVE1 HW_PINCTRL_DRIVE2 HW_PINCTRL_DRIVE3 HW_PINCTRL_DRIVE4 HW_PINCTRL_DRIVE5 HW_PINCTRL_DRIVE6 HW_PINCTRL_DRIVE7 HW_PINCTRL_DRIVE8 HW_PINCTRL_DRIVE9 HW_PINCTRL_DRIVE10 HW_PINCTRL_DRIVE11 HW_PINCTRL_DRIVE12 HW_PINCTRL_DRIVE13 HW_PINCTRL_DRIVE14 HW_PINCTRL_PULL0 HW_PINCTRL_PULL1 HW_PINCTRL_PULL2 HW_PINCTRL_PULL3 HW_PINCTRL_DOUT0 HW_PINCTRL_DOUT1 HW_PINCTRL_DOUT2 HW_PINCTRL_DIN0 HW_PINCTRL_DIN1 HW_PINCTRL_DIN2 HW_PINCTRL_DOE0 HW_PINCTRL_DOE1 HW_PINCTRL_DOE2

Property Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address

STMP 3700

STMP 3780 0x200

New Field(s) 0x210 New Field(s) 0x220 New Field(s) 0x230 New Field(s)

New Field(s) 0x240

New Field(s) 0x250 New Field(s) 0x260 New Field(s) 0x270 New Field(s)

New Field(s) 0x280

New Field(s) 0x290 New Field(s) 0x2a0 0x2b0 New Field(s) 0x2c0 0x2d0 0x2e0 0x300

179

0x310 New Field(s) 0x320 New Field(s) 0x330

0x400 New Field(s) 0x410 New Field(s) 0x420 New Field(s) 0x430

0x400 Incompatible Field(s) 0x410 Incompatible Field(s) 0x420

0x500 Incompatible Field(s) 0x510 Incompatible Field(s) 0x520

0x500 Incompatible Field(s) 0x510 Incompatible Field(s) 0x520

0x600 Incompatible Field(s) 0x610 Incompatible Field(s) 0x620

0x600 Incompatible Field(s) 0x610 Incompatible Field(s) 0x620

0x700 Incompatible Field(s) 0x710 Incompatible Field(s) 0x720

HW_PINCTRL_IRQEN1 HW_PINCTRL_IRQEN2 HW_PINCTRL_IRQLEVEL0 HW_PINCTRL_IRQLEVEL1 HW_PINCTRL_IRQLEVEL2 HW_PINCTRL_IRQPOL0 HW_PINCTRL_IRQPOL1 HW_PINCTRL_IRQPOL2 HW_PINCTRL_IRQSTAT0 HW_PINCTRL_IRQSTAT1 HW_PINCTRL_IRQSTAT2

23.2

Programmable Registers

23.2.1

HW_PINCTRL_CTRL

0x800 Incompatible Field(s) 0x810 Incompatible Field(s) 0x820

0x900 Incompatible Field(s) 0x910 Incompatible Field(s) 0x920

0x900 Incompatible Field(s) 0x910 Incompatible Field(s) 0x920

0xa00 Incompatible Field(s) 0xa10 Incompatible Field(s) 0xa20

0xa00 Incompatible Field(s) 0xa10 Incompatible Field(s) 0xa20

0xb00 Incompatible Field(s) 0xb10 Incompatible Field(s) 0xb20

0xb00 Incompatible Field(s) 0xb10 Incompatible Field(s) 0xb20

0xc00 Incompatible Field(s) 0xc10 Incompatible Field(s) 0xc20

HW_PINCTRL_CTRL

23.2.2

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0 IRQOUT3

2 2 2 2 3 2 1 0

PRESENT0

PRESENT0 PRESENT1

PRESENT1

PRESENT2

2 2 2 2 7 6 5 4

PRESENT3

PRESENT2

CLKGATE CLKGATE

PRESENT3

SFTRST SFTRST

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

0x0

HW_PINCTRL_MUXSEL0 HW_PINCTRL_MUXSEL0

180

0x100

IRQOUT0

HW_PINCTRL_IRQEN0

0x800 Incompatible Field(s) 0x810 Incompatible Field(s) 0x820

IRQOUT0

HW_PINCTRL_PIN2IRQ2

0x700 Incompatible Field(s) 0x710 Incompatible Field(s) 0x720

IRQOUT1

HW_PINCTRL_PIN2IRQ1

STMP 3780

IRQOUT2

HW_PINCTRL_PIN2IRQ0

STMP 3700

IRQOUT1

Property Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields

IRQOUT2

Name

STMP 3700

23.2.5

181

HW_PINCTRL_MUXSEL3

HW_PINCTRL_MUXSEL3

0x130 0 0 0 0 7 6 5 4

BANK1_PIN00 BANK1_PIN00

BANK0_PIN16 BANK0_PIN16

0 0 0 0 7 6 5 4 BANK0_PIN17 BANK0_PIN17

BANK0_PIN18 BANK0_PIN18

BANK0_PIN00 BANK0_PIN00

BANK0_PIN01 BANK0_PIN01

BANK0_PIN02 BANK0_PIN02

BANK0_PIN03 BANK0_PIN03

BANK0_PIN04 BANK0_PIN04

0 0 0 0 7 6 5 4

BANK1_PIN01 BANK1_PIN01

1 1 0 0 1 0 9 8

BANK1_PIN02 BANK1_PIN02

1 1 0 0 1 0 9 8 BANK0_PIN19 BANK0_PIN19

BANK0_PIN20 BANK0_PIN20

BANK0_PIN05 BANK0_PIN05

BANK0_PIN06 BANK0_PIN06

BANK0_PIN07 BANK0_PIN07

BANK0_PIN08 BANK0_PIN08

1 1 0 0 1 0 9 8

BANK1_PIN03 BANK1_PIN03

1 1 1 1 5 4 3 2

BANK0_PIN21 BANK0_PIN21

1 1 1 1 5 4 3 2

BANK1_PIN04 BANK1_PIN04

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

BANK1_PIN05 BANK1_PIN05

HW_PINCTRL_MUXSEL2 BANK0_PIN22 BANK0_PIN22

HW_PINCTRL_MUXSEL1

BANK1_PIN06 BANK1_PIN06

1 1 1 1 9 8 7 6

BANK0_PIN23 BANK0_PIN23

BANK0_PIN24 BANK0_PIN24

BANK0_PIN09 BANK0_PIN09

BANK0_PIN10 BANK0_PIN10

1 1 1 1 9 8 7 6

BANK1_PIN07 BANK1_PIN07

2 2 2 2 3 2 1 0

BANK1_PIN08 BANK1_PIN08

2 2 2 2 3 2 1 0

BANK0_PIN25 BANK0_PIN25

BANK0_PIN26 BANK0_PIN26

BANK0_PIN11 BANK0_PIN11

BANK0_PIN12 BANK0_PIN12

BANK0_PIN13 BANK0_PIN13

BANK0_PIN14 BANK0_PIN14

2 2 2 2 3 2 1 0

BANK1_PIN09 BANK1_PIN09

2 2 2 2 7 6 5 4

BANK1_PIN10 BANK1_PIN10

2 2 2 2 7 6 5 4

BANK0_PIN27 BANK0_PIN27

BANK0_PIN28 BANK0_PIN28

STMP 3700

BANK0_PIN15 BANK0_PIN15

STMP 3780

2 2 2 2 7 6 5 4

BANK1_PIN11 BANK1_PIN11

BANK1_PIN12 BANK1_PIN12

3 3 2 2 1 0 9 8 BANK0_PIN29 BANK0_PIN29

BANK0_PIN30

STMP 3700 3 3 2 2 1 0 9 8

BANK1_PIN13 BANK1_PIN13

BANK1_PIN14 BANK1_PIN14

23.2.4 BANK0_PIN31

STMP 3780

23.2.3

BANK1_PIN15 BANK1_PIN15

STMP 3780

3 3 2 2 1 0 9 8 0 0 0 0 3 2 1 0

HW_PINCTRL_MUXSEL1 0x110

0 0 0 0 3 2 1 0

HW_PINCTRL_MUXSEL2 0x120

0 0 0 0 3 2 1 0

STMP 3700

23.2.8

182

HW_PINCTRL_MUXSEL6

HW_PINCTRL_MUXSEL6

0x160 0 0 0 0 7 6 5 4

BANK2_PIN16 BANK2_PIN16

BANK2_PIN00 BANK2_PIN00

0 0 0 0 7 6 5 4 BANK2_PIN01 BANK2_PIN01

BANK2_PIN02 BANK2_PIN02

BANK1_PIN16 BANK1_PIN16

BANK1_PIN17 BANK1_PIN17

BANK1_PIN18 BANK1_PIN18

BANK1_PIN19 BANK1_PIN19

BANK1_PIN20 BANK1_PIN20

0 0 0 0 7 6 5 4

BANK2_PIN17 BANK2_PIN17

1 1 0 0 1 0 9 8

BANK2_PIN18 BANK2_PIN18

1 1 0 0 1 0 9 8 BANK2_PIN03 BANK2_PIN03

BANK2_PIN04 BANK2_PIN04

BANK1_PIN21 BANK1_PIN21

BANK1_PIN22 BANK1_PIN22

BANK1_PIN23 BANK1_PIN23

BANK1_PIN24 BANK1_PIN24

1 1 0 0 1 0 9 8

BANK2_PIN19 BANK2_PIN19

1 1 1 1 5 4 3 2

BANK2_PIN05 BANK2_PIN05

1 1 1 1 5 4 3 2

BANK2_PIN20 BANK2_PIN20

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

BANK2_PIN21 BANK2_PIN21

HW_PINCTRL_MUXSEL5 BANK2_PIN06 BANK2_PIN06

HW_PINCTRL_MUXSEL4

BANK2_PIN22 BANK2_PIN22

1 1 1 1 9 8 7 6

BANK2_PIN07 BANK2_PIN07

BANK2_PIN08 BANK2_PIN08

BANK1_PIN25 BANK1_PIN25

BANK1_PIN26 BANK1_PIN26

1 1 1 1 9 8 7 6

BANK2_PIN23 BANK2_PIN23

2 2 2 2 3 2 1 0

BANK2_PIN24 BANK2_PIN24

2 2 2 2 3 2 1 0

BANK2_PIN09 BANK2_PIN09

BANK2_PIN10 BANK2_PIN10

BANK1_PIN27 BANK1_PIN27

BANK1_PIN28 BANK1_PIN28

BANK1_PIN29

BANK1_PIN30

STMP 3700

2 2 2 2 3 2 1 0

BANK2_PIN25 BANK2_PIN25

2 2 2 2 7 6 5 4

BANK2_PIN26 BANK2_PIN26

2 2 2 2 7 6 5 4

BANK2_PIN11 BANK2_PIN11

BANK2_PIN12 BANK2_PIN12

BANK2_PIN13 BANK2_PIN13

BANK2_PIN14 BANK2_PIN14

STMP 3780

2 2 2 2 7 6 5 4

BANK2_PIN27 BANK2_PIN27

3 3 2 2 1 0 9 8

BANK2_PIN28 BANK2_PIN28

STMP 3700 3 3 2 2 1 0 9 8

BANK2_PIN29 BANK2_PIN29

BANK2_PIN30 BANK2_PIN30

23.2.7 BANK2_PIN15 BANK2_PIN15

STMP 3780

23.2.6

BANK2_PIN31 BANK2_PIN31

STMP 3780

3 3 2 2 1 0 9 8 0 0 0 0 3 2 1 0

HW_PINCTRL_MUXSEL4 0x140

0 0 0 0 3 2 1 0

HW_PINCTRL_MUXSEL5 0x150

0 0 0 0 3 2 1 0

23.2.11

183

HW_PINCTRL_DRIVE1

HW_PINCTRL_DRIVE1

0x210 0 0 0 0 7 6 5 4

BANK3_PIN16 BANK3_PIN16

BANK3_PIN17 BANK3_PIN17

BANK3_PIN18 BANK3_PIN18

BANK3_PIN19 BANK3_PIN19

BANK3_PIN20 BANK3_PIN20

0 0 0 0 7 6 5 4

BANK0_PIN00_MA BANK0_PIN00_MA

1 1 0 0 1 0 9 8

STMP 3700

BANK3_PIN00 BANK3_PIN00

BANK3_PIN01 BANK3_PIN01

BANK3_PIN02 BANK3_PIN02

BANK3_PIN03 BANK3_PIN03

BANK3_PIN04 BANK3_PIN04

BANK3_PIN05 BANK3_PIN05

BANK3_PIN06 BANK3_PIN06

BANK3_PIN07 BANK3_PIN07

BANK3_PIN08 BANK3_PIN08

BANK3_PIN09 BANK3_PIN09

BANK3_PIN10 BANK3_PIN10

BANK3_PIN11 BANK3_PIN11

BANK3_PIN12 BANK3_PIN12

BANK3_PIN13 BANK3_PIN13

BANK3_PIN14 BANK3_PIN14

BANK3_PIN15 BANK3_PIN15

STMP 3780

0 0 0 0 7 6 5 4

BANK0_PIN00_V

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

BANK0_PIN01_MA BANK0_PIN01_MA

HW_PINCTRL_DRIVE0

1 1 0 0 1 0 9 8

BANK0_PIN01_V

1 1 1 1 9 8 7 6 1 1 1 1 5 4 3 2

BANK0_PIN02_MA BANK0_PIN02_MA

BANK3_PIN21 BANK3_PIN21

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

BANK0_PIN02_V

HW_PINCTRL_MUXSEL7

BANK0_PIN03_MA BANK0_PIN03_MA

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

BANK0_PIN03_V

2 2 2 2 3 2 1 0

BANK0_PIN04_MA BANK0_PIN04_MA

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

BANK0_PIN04_V

2 2 2 2 7 6 5 4

BANK0_PIN05_MA BANK0_PIN05_MA

STMP 3700

2 2 2 2 7 6 5 4

BANK0_PIN05_V

3 3 2 2 1 0 9 8

BANK0_PIN06_MA BANK0_PIN06_MA

STMP 3780 3 3 2 2 1 0 9 8

BANK0_PIN06_V

23.2.10

BANK0_PIN07_V

STMP 3700

23.2.9

BANK0_PIN07_MA BANK0_PIN07_MA

STMP 3780

3 3 2 2 1 0 9 8 0 0 0 0 3 2 1 0

HW_PINCTRL_MUXSEL7 0x170

0 0 0 0 3 2 1 0

HW_PINCTRL_DRIVE0 0x200

0 0 0 0 3 2 1 0

23.2.13 BANK0_PIN23_V

STMP 3700

184

HW_PINCTRL_DRIVE3

HW_PINCTRL_DRIVE3 0x230

BANK0_PIN16_MA BANK0_PIN16_MA

0 0 0 0 7 6 5 4

BANK0_PIN08_MA BANK0_PIN08_MA

BANK0_PIN08_V

BANK0_PIN09_MA BANK0_PIN09_MA

0 0 0 0 7 6 5 4

BANK0_PIN16_V

BANK0_PIN17_MA BANK0_PIN17_MA

1 1 0 0 1 0 9 8

BANK0_PIN09_V

BANK0_PIN10_MA BANK0_PIN10_MA

1 1 0 0 1 0 9 8

BANK0_PIN17_V

BANK0_PIN18_MA BANK0_PIN18_MA

1 1 1 1 5 4 3 2

BANK0_PIN10_V

BANK0_PIN11_MA BANK0_PIN11_MA

1 1 1 1 5 4 3 2

BANK0_PIN18_V

HW_PINCTRL_DRIVE2

BANK0_PIN19_MA BANK0_PIN19_MA

1 1 1 1 9 8 7 6

BANK0_PIN11_V

BANK0_PIN12_MA BANK0_PIN12_MA

1 1 1 1 9 8 7 6

BANK0_PIN19_V

BANK0_PIN20_MA BANK0_PIN20_MA

2 2 2 2 3 2 1 0

BANK0_PIN12_V

BANK0_PIN13_MA BANK0_PIN13_MA

BANK0_PIN13_V

BANK0_PIN14_MA BANK0_PIN14_MA

BANK0_PIN14_V

2 2 2 2 3 2 1 0

BANK0_PIN20_V

2 2 2 2 7 6 5 4

BANK0_PIN21_MA BANK0_PIN21_MA

BANK0_PIN15_V

STMP 3700

BANK0_PIN15_MA BANK0_PIN15_MA

STMP 3780

2 2 2 2 7 6 5 4

BANK0_PIN21_V

BANK0_PIN22_MA BANK0_PIN22_MA

3 3 2 2 1 0 9 8

BANK0_PIN22_V

23.2.12

BANK0_PIN23_MA BANK0_PIN23_MA

STMP 3780

3 3 2 2 1 0 9 8 0 0 0 0 3 2 1 0

HW_PINCTRL_DRIVE2 0x220

0 0 0 0 3 2 1 0

23.2.15 BANK1_PIN07_V

STMP 3700

185

HW_PINCTRL_DRIVE5

HW_PINCTRL_DRIVE5 0x250

BANK1_PIN00_MA BANK1_PIN00_MA

0 0 0 0 7 6 5 4

BANK0_PIN24_MA BANK0_PIN24_MA

BANK0_PIN24_V

BANK0_PIN25_MA BANK0_PIN25_MA

0 0 0 0 7 6 5 4

BANK1_PIN00_V

BANK1_PIN01_MA BANK1_PIN01_MA

1 1 0 0 1 0 9 8

BANK0_PIN25_V

BANK0_PIN26_MA BANK0_PIN26_MA

1 1 0 0 1 0 9 8

BANK1_PIN01_V

BANK1_PIN02_MA BANK1_PIN02_MA

1 1 1 1 5 4 3 2

BANK0_PIN26_V

BANK0_PIN27_MA BANK0_PIN27_MA

1 1 1 1 5 4 3 2

BANK1_PIN02_V

HW_PINCTRL_DRIVE4

BANK1_PIN03_MA BANK1_PIN03_MA

1 1 1 1 9 8 7 6

BANK0_PIN27_V

BANK0_PIN28_MA BANK0_PIN28_MA

1 1 1 1 9 8 7 6

BANK1_PIN03_V

BANK1_PIN04_MA BANK1_PIN04_MA

2 2 2 2 3 2 1 0

BANK0_PIN28_V

BANK0_PIN29_MA BANK0_PIN29_MA

BANK0_PIN29_V

STMP 3700

2 2 2 2 3 2 1 0

BANK1_PIN04_V

2 2 2 2 7 6 5 4

BANK1_PIN05_MA BANK1_PIN05_MA

BANK0_PIN30_MA

BANK0_PIN31_MA

STMP 3780

2 2 2 2 7 6 5 4

BANK1_PIN05_V

BANK1_PIN06_MA BANK1_PIN06_MA

3 3 2 2 1 0 9 8

BANK1_PIN06_V

23.2.14

BANK1_PIN07_MA BANK1_PIN07_MA

STMP 3780

3 3 2 2 1 0 9 8 0 0 0 0 3 2 1 0

HW_PINCTRL_DRIVE4 0x240

0 0 0 0 3 2 1 0

23.2.17 BANK1_PIN23_V

STMP 3700

186

HW_PINCTRL_DRIVE7

HW_PINCTRL_DRIVE7 0x270

BANK1_PIN16_MA BANK1_PIN16_MA

0 0 0 0 7 6 5 4

BANK1_PIN08_MA BANK1_PIN08_MA

BANK1_PIN08_V

BANK1_PIN09_MA BANK1_PIN09_MA

0 0 0 0 7 6 5 4

BANK1_PIN16_V

BANK1_PIN17_MA BANK1_PIN17_MA

1 1 0 0 1 0 9 8

BANK1_PIN09_V

BANK1_PIN10_MA BANK1_PIN10_MA

1 1 0 0 1 0 9 8

BANK1_PIN17_V

BANK1_PIN18_MA BANK1_PIN18_MA

1 1 1 1 5 4 3 2

BANK1_PIN10_V

BANK1_PIN11_MA BANK1_PIN11_MA

1 1 1 1 5 4 3 2

BANK1_PIN18_V

HW_PINCTRL_DRIVE6

BANK1_PIN19_MA BANK1_PIN19_MA

1 1 1 1 9 8 7 6

BANK1_PIN11_V

BANK1_PIN12_MA BANK1_PIN12_MA

1 1 1 1 9 8 7 6

BANK1_PIN19_V

BANK1_PIN20_MA BANK1_PIN20_MA

2 2 2 2 3 2 1 0

BANK1_PIN12_V

BANK1_PIN13_MA BANK1_PIN13_MA

BANK1_PIN13_V

BANK1_PIN14_MA BANK1_PIN14_MA

BANK1_PIN14_V

2 2 2 2 3 2 1 0

BANK1_PIN20_V

2 2 2 2 7 6 5 4

BANK1_PIN21_MA BANK1_PIN21_MA

BANK1_PIN15_V

STMP 3700

BANK1_PIN15_MA BANK1_PIN15_MA

STMP 3780

2 2 2 2 7 6 5 4

BANK1_PIN21_V

BANK1_PIN22_MA BANK1_PIN22_MA

3 3 2 2 1 0 9 8

BANK1_PIN22_V

23.2.16

BANK1_PIN23_MA BANK1_PIN23_MA

STMP 3780

3 3 2 2 1 0 9 8 0 0 0 0 3 2 1 0

HW_PINCTRL_DRIVE6 0x260

0 0 0 0 3 2 1 0

23.2.19 BANK2_PIN07_V

STMP 3700

187

HW_PINCTRL_DRIVE9

HW_PINCTRL_DRIVE9 0x290

BANK2_PIN00_MA BANK2_PIN00_MA

0 0 0 0 7 6 5 4

BANK1_PIN24_MA BANK1_PIN24_MA

BANK1_PIN24_V

BANK1_PIN25_MA BANK1_PIN25_MA

0 0 0 0 7 6 5 4

BANK2_PIN00_V

BANK2_PIN01_MA BANK2_PIN01_MA

1 1 0 0 1 0 9 8

BANK1_PIN25_V

BANK1_PIN26_MA BANK1_PIN26_MA

1 1 0 0 1 0 9 8

BANK2_PIN01_V

BANK2_PIN02_MA BANK2_PIN02_MA

1 1 1 1 5 4 3 2

BANK1_PIN26_V

BANK1_PIN27_MA BANK1_PIN27_MA

1 1 1 1 5 4 3 2

BANK2_PIN02_V

HW_PINCTRL_DRIVE8

BANK2_PIN03_MA BANK2_PIN03_MA

1 1 1 1 9 8 7 6

BANK1_PIN27_V

BANK1_PIN28_MA BANK1_PIN28_MA

BANK1_PIN28_V

1 1 1 1 9 8 7 6

BANK2_PIN03_V

2 2 2 2 3 2 1 0

BANK2_PIN04_MA BANK2_PIN04_MA

BANK1_PIN29_MA

STMP 3700

2 2 2 2 3 2 1 0

BANK2_PIN04_V

2 2 2 2 7 6 5 4

BANK2_PIN05_MA BANK2_PIN05_MA

BANK1_PIN30_MA

STMP 3780

2 2 2 2 7 6 5 4

BANK2_PIN05_V

BANK2_PIN06_MA BANK2_PIN06_MA

3 3 2 2 1 0 9 8

BANK2_PIN06_V

23.2.18

BANK2_PIN07_MA BANK2_PIN07_MA

STMP 3780

3 3 2 2 1 0 9 8 0 0 0 0 3 2 1 0

HW_PINCTRL_DRIVE8 0x280

0 0 0 0 3 2 1 0

23.2.21 BANK2_PIN23_V

BANK2_PIN23_V

188

HW_PINCTRL_DRIVE11 HW_PINCTRL_DRIVE11 0x2b0

BANK2_PIN16_MA BANK2_PIN16_MA

0 0 0 0 7 6 5 4 BANK2_PIN16_V

BANK2_PIN10_V

BANK2_PIN09_V

BANK2_PIN08_MA BANK2_PIN08_MA

BANK2_PIN08_V

BANK2_PIN09_MA BANK2_PIN09_MA

BANK2_PIN09_V

BANK2_PIN10_MA BANK2_PIN10_MA

BANK2_PIN10_V

0 0 0 0 7 6 5 4

BANK2_PIN16_V

BANK2_PIN17_MA BANK2_PIN17_MA

1 1 0 0 1 0 9 8 BANK2_PIN17_V

BANK2_PIN11_V BANK2_PIN11_MA BANK2_PIN11_MA

BANK2_PIN11_V

1 1 0 0 1 0 9 8

BANK2_PIN17_V

BANK2_PIN18_MA BANK2_PIN18_MA

1 1 1 1 5 4 3 2

BANK2_PIN18_V

BANK2_PIN12_V BANK2_PIN12_MA BANK2_PIN12_MA

BANK2_PIN12_V

1 1 1 1 5 4 3 2

BANK2_PIN18_V

HW_PINCTRL_DRIVE10

BANK2_PIN19_MA BANK2_PIN19_MA

1 1 1 1 9 8 7 6

BANK2_PIN19_V

BANK2_PIN13_V

BANK2_PIN13_MA BANK2_PIN13_MA

BANK2_PIN13_V

1 1 1 1 9 8 7 6

BANK2_PIN19_V

BANK2_PIN20_MA BANK2_PIN20_MA

2 2 2 2 3 2 1 0

BANK2_PIN20_V

BANK2_PIN14_V

BANK2_PIN14_MA BANK2_PIN14_MA

BANK2_PIN14_V

2 2 2 2 3 2 1 0

BANK2_PIN20_V

BANK2_PIN21_MA BANK2_PIN21_MA

2 2 2 2 7 6 5 4

BANK2_PIN21_V

BANK2_PIN15_V

BANK2_PIN15_V

BANK2_PIN15_MA BANK2_PIN15_MA

STMP 3700

STMP 3780

2 2 2 2 7 6 5 4

BANK2_PIN21_V

BANK2_PIN22_MA BANK2_PIN22_MA

BANK2_PIN22_V

3 3 2 2 1 0 9 8

BANK2_PIN22_V

BANK2_PIN23_MA BANK2_PIN23_MA

STMP 3700

23.2.20

STMP 3780

3 3 2 2 1 0 9 8 0 0 0 0 3 2 1 0

HW_PINCTRL_DRIVE10 0x2a0

0 0 0 0 3 2 1 0

23.2.23 BANK3_PIN07_V

BANK3_PIN07_V

189

HW_PINCTRL_DRIVE13

HW_PINCTRL_DRIVE13 0x2d0

BANK3_PIN00_MA BANK3_PIN00_MA

0 0 0 0 7 6 5 4 BANK3_PIN00_V

BANK2_PIN25_V

BANK2_PIN24_V BANK2_PIN24_MA BANK2_PIN24_MA

BANK2_PIN24_V

BANK2_PIN25_MA BANK2_PIN25_MA

BANK2_PIN25_V

0 0 0 0 7 6 5 4

BANK3_PIN00_V

BANK3_PIN01_MA BANK3_PIN01_MA

1 1 0 0 1 0 9 8 BANK3_PIN01_V

BANK2_PIN26_V BANK2_PIN26_MA BANK2_PIN26_MA

BANK2_PIN26_V

1 1 0 0 1 0 9 8

BANK3_PIN01_V

BANK3_PIN02_MA BANK3_PIN02_MA

1 1 1 1 5 4 3 2

BANK3_PIN02_V

BANK2_PIN27_MA BANK2_PIN27_MA

BANK2_PIN27_V

BANK2_PIN28_MA BANK2_PIN28_MA

BANK2_PIN28_V

1 1 1 1 5 4 3 2

BANK3_PIN02_V

HW_PINCTRL_DRIVE12

BANK3_PIN03_MA BANK3_PIN03_MA

1 1 1 1 9 8 7 6

BANK3_PIN03_V

BANK2_PIN29_V

BANK2_PIN29_MA BANK2_PIN29_MA

BANK2_PIN29_V

1 1 1 1 9 8 7 6

BANK3_PIN03_V

BANK3_PIN04_MA BANK3_PIN04_MA

2 2 2 2 3 2 1 0

BANK3_PIN04_V

BANK2_PIN30_V

BANK2_PIN30_MA BANK2_PIN30_MA

BANK2_PIN30_V

2 2 2 2 3 2 1 0

BANK3_PIN04_V

BANK3_PIN05_MA BANK3_PIN05_MA

2 2 2 2 7 6 5 4

BANK3_PIN05_V

BANK2_PIN31_V

BANK2_PIN31_V

BANK2_PIN31_MA BANK2_PIN31_MA

STMP 3700

STMP 3780

2 2 2 2 7 6 5 4

BANK3_PIN05_V

BANK3_PIN06_MA BANK3_PIN06_MA

BANK3_PIN06_V

3 3 2 2 1 0 9 8

BANK3_PIN06_V

BANK3_PIN07_MA BANK3_PIN07_MA

STMP 3700

23.2.22

STMP 3780

3 3 2 2 1 0 9 8 0 0 0 0 3 2 1 0

HW_PINCTRL_DRIVE12 0x2c0

0 0 0 0 3 2 1 0

2 2 2 2 3 2 1 0 1 1 1 1 9 8 7 6

190 1 1 1 1 5 4 3 2 1 1 0 0 1 0 9 8

BANK0_PIN00

0 0 0 0 7 6 5 4

BANK0_PIN01 BANK0_PIN01

BANK3_PIN16_V BANK3_PIN16_MA BANK3_PIN16_MA

BANK3_PIN16_V

0 0 0 0 7 6 5 4

BANK0_PIN02 BANK0_PIN02

BANK3_PIN17_MA BANK3_PIN17_MA

BANK3_PIN17_V

BANK3_PIN11_V

BANK3_PIN10_V

BANK3_PIN09_V

BANK3_PIN08_V BANK3_PIN08_MA BANK3_PIN08_MA

BANK3_PIN08_V

BANK3_PIN09_MA BANK3_PIN09_MA

BANK3_PIN09_V

BANK3_PIN10_MA BANK3_PIN10_MA

BANK3_PIN10_V

BANK3_PIN11_MA BANK3_PIN11_MA

BANK3_PIN11_V

0 0 0 0 7 6 5 4

BANK0_PIN03 BANK0_PIN03

BANK0_PIN04 BANK0_PIN04

BANK0_PIN05 BANK0_PIN05

BANK3_PIN17_V

1 1 0 0 1 0 9 8

BANK0_PIN06 BANK0_PIN06

BANK3_PIN18_MA BANK3_PIN18_MA

BANK3_PIN12_V BANK3_PIN12_MA BANK3_PIN12_MA

BANK3_PIN12_V

1 1 0 0 1 0 9 8

BANK0_PIN07 BANK0_PIN07

BANK0_PIN08

BANK3_PIN18_V

1 1 1 1 5 4 3 2

BANK0_PIN09

STMP 3700 0x300 BANK3_PIN18_V

BANK3_PIN13_V

BANK3_PIN13_MA BANK3_PIN13_MA

BANK3_PIN13_V

1 1 1 1 5 4 3 2

BANK0_PIN10

BANK3_PIN19_V

HW_PINCTRL_DRIVE14

BANK3_PIN19_MA BANK3_PIN19_MA

BANK3_PIN19_V

1 1 1 1 9 8 7 6

BANK0_PIN11

BANK3_PIN20_V

BANK3_PIN14_V

BANK3_PIN14_MA BANK3_PIN14_MA

BANK3_PIN14_V

1 1 1 1 9 8 7 6

BANK0_PIN15

HW_PINCTRL_PULL0 BANK3_PIN20_MA BANK3_PIN20_MA

BANK3_PIN20_V

2 2 2 2 3 2 1 0

BANK0_PIN18

BANK3_PIN21_MA BANK3_PIN21_MA

BANK3_PIN15_V

BANK3_PIN15_V

BANK3_PIN15_MA BANK3_PIN15_MA

STMP 3700

STMP 3780

2 2 2 2 3 2 1 0

BANK0_PIN19

2 2 2 2 7 6 5 4

BANK0_PIN20 BANK0_PIN20

BANK3_PIN21_V

2 2 2 2 7 6 5 4

BANK0_PIN21

BANK3_PIN21_V

STMP 3700

2 2 2 2 7 6 5 4

BANK0_PIN22

3 3 2 2 1 0 9 8

BANK0_PIN26 BANK0_PIN26

STMP 3780 3 3 2 2 1 0 9 8

BANK0_PIN27 BANK0_PIN27

BANK0_PIN28 BANK0_PIN28

BANK0_PIN29 BANK0_PIN29

BANK0_PIN30

BANK0_PIN31

23.2.25

STMP 3700

23.2.24

STMP 3780

3 3 2 2 1 0 9 8 0 0 0 0 3 2 1 0

HW_PINCTRL_DRIVE14 0x2e0

0 0 0 0 3 2 1 0

HW_PINCTRL_PULL0 STMP 3780 0x400

0 0 0 0 3 2 1 0

3 3 2 2 1 0 9 8 2 2 2 2 7 6 5 4 2 2 2 2 3 2 1 0 1 1 1 1 9 8 7 6

191 1 1 1 1 5 4 3 2 1 1 0 0 1 0 9 8

BANK3_PIN02 BANK3_PIN02

BANK3_PIN00 BANK3_PIN00

BANK3_PIN01 BANK3_PIN01

0 0 0 0 7 6 5 4

BANK3_PIN03 BANK3_PIN03

BANK3_PIN04 BANK3_PIN04

BANK3_PIN05 BANK3_PIN05

BANK2_PIN00

BANK2_PIN01

BANK2_PIN02

BANK2_PIN03

BANK2_PIN04

BANK2_PIN05

BANK2_PIN08

1 1 0 0 1 0 9 8

BANK3_PIN06 BANK3_PIN06

STMP 3700 0x330

1 1 0 0 1 0 9 8

BANK3_PIN07 BANK3_PIN07

1 1 1 1 5 4 3 2

BANK3_PIN08 BANK3_PIN08

STMP 3700 0x320

BANK3_PIN09 BANK3_PIN09

BANK1_PIN18

1 1 1 1 5 4 3 2

BANK3_PIN10 BANK3_PIN10

1 1 1 1 9 8 7 6

BANK3_PIN11 BANK3_PIN11

HW_PINCTRL_PULL3

STMP 3700 0x310

BANK3_PIN12 BANK3_PIN12

HW_PINCTRL_PULL2

BANK3_PIN13 BANK3_PIN13

BANK2_PIN14

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

BANK3_PIN14 BANK3_PIN14

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

BANK3_PIN15 BANK3_PIN15

BANK1_PIN24

BANK1_PIN25

BANK1_PIN26

BANK1_PIN27

STMP 3700

2 2 2 2 7 6 5 4

BANK1_PIN22 BANK1_PIN22

BANK1_PIN28

STMP 3780

HW_PINCTRL_PULL1

BANK3_PIN16 BANK3_PIN16

STMP 3700 3 3 2 2 1 0 9 8

BANK2_PIN27

BANK2_PIN28

STMP 3780 3 3 2 2 1 0 9 8

BANK3_PIN17 BANK3_PIN17

23.2.28

STMP 3700

23.2.27

STMP 3780

23.2.26 HW_PINCTRL_PULL1 STMP 3780 0x410

HW_PINCTRL_PULL2 STMP 3780 0x420

0 0 0 0 7 6 5 4 0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4 0 0 0 0 3 2 1 0

HW_PINCTRL_PULL3 STMP 3780 0x430

0 0 0 0 3 2 1 0

23.2.29

HW_PINCTRL_DOUT0 HW_PINCTRL_DOUT0 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

23.2.30

1 1 1 1 5 4 3 2

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

DOUT

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

STMP 3700 0x410

1 1 1 1 9 8 7 6

STMP 3780 0x510

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

DOUT

DOUT

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_PINCTRL_DOUT2 HW_PINCTRL_DOUT2 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

STMP 3700 0x420

1 1 1 1 9 8 7 6

STMP 3780 0x520

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

DOUT

DOUT

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

23.2.32

0 0 0 0 7 6 5 4

HW_PINCTRL_DOUT1 HW_PINCTRL_DOUT1

23.2.31

1 1 0 0 1 0 9 8

DOUT

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

STMP 3780 0x500

STMP 3700 0x400

HW_PINCTRL_DIN0 HW_PINCTRL_DIN0

STMP 3700 0x500

192

STMP 3780 0x600

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

23.2.33

1 1 1 1 5 4 3 2

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

DIN

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

STMP 3700 0x510

1 1 1 1 9 8 7 6

STMP 3780 0x610

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

DIN

DIN

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_PINCTRL_DIN2 HW_PINCTRL_DIN2 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

STMP 3700 0x520

1 1 1 1 9 8 7 6

STMP 3780 0x620

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

DIN

DIN

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

23.2.35

0 0 0 0 7 6 5 4

HW_PINCTRL_DIN1 HW_PINCTRL_DIN1

23.2.34

1 1 0 0 1 0 9 8

DIN

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_PINCTRL_DOE0 HW_PINCTRL_DOE0

STMP 3700 0x600

193

STMP 3780 0x700

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

23.2.36

1 1 1 1 5 4 3 2

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

DOE

STMP 3700 0x610

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

STMP 3780 0x710

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

DOE

DOE

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_PINCTRL_DOE2 STMP 3700 0x620

HW_PINCTRL_DOE2 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

STMP 3780 0x720

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

DOE

DOE

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

23.2.38

0 0 0 0 7 6 5 4

HW_PINCTRL_DOE1 HW_PINCTRL_DOE1

23.2.37

1 1 0 0 1 0 9 8

DOE

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_PINCTRL_PIN2IRQ0 HW_PINCTRL_PIN2IRQ0

STMP 3700 0x700

194

STMP 3780 0x800

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

23.2.39

1 1 1 1 5 4 3 2

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

PIN2IRQ

STMP 3700 0x710

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

STMP 3780 0x810 1 1 0 0 1 0 9 8

PIN2IRQ

PIN2IRQ

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_PINCTRL_PIN2IRQ2 STMP 3700 0x720

HW_PINCTRL_PIN2IRQ2 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

STMP 3780 0x820 1 1 0 0 1 0 9 8

PIN2IRQ

PIN2IRQ

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

23.2.41

0 0 0 0 7 6 5 4

HW_PINCTRL_PIN2IRQ1 HW_PINCTRL_PIN2IRQ1

23.2.40

1 1 0 0 1 0 9 8

PIN2IRQ

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_PINCTRL_IRQEN0 HW_PINCTRL_IRQEN0

STMP 3700 0x800

195

STMP 3780 0x900

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

23.2.42

1 1 1 1 5 4 3 2

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

IRQEN

STMP 3700 0x810

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

STMP 3780 0x910 1 1 0 0 1 0 9 8

IRQEN

IRQEN

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_PINCTRL_IRQEN2 STMP 3700 0x820

HW_PINCTRL_IRQEN2 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

STMP 3780 0x920

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

STMP 3700 0x900

STMP 3780 0xa00

IRQEN

IRQEN

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

23.2.44

0 0 0 0 7 6 5 4

HW_PINCTRL_IRQEN1 HW_PINCTRL_IRQEN1

23.2.43

1 1 0 0 1 0 9 8

IRQEN

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_PINCTRL_IRQLEVEL0 HW_PINCTRL_IRQLEVEL0

196

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

23.2.45

1 1 1 1 5 4 3 2

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

IRQLEVEL

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

STMP 3700 0x910

STMP 3780 0xa10

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

1 1 1 1 9 8 7 6

IRQLEVEL

IRQLEVEL

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_PINCTRL_IRQLEVEL2 HW_PINCTRL_IRQLEVEL2 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

STMP 3700 0x920

STMP 3780 0xa20

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

1 1 1 1 9 8 7 6

IRQLEVEL

IRQLEVEL

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

23.2.47

0 0 0 0 7 6 5 4

HW_PINCTRL_IRQLEVEL1 HW_PINCTRL_IRQLEVEL1

23.2.46

1 1 0 0 1 0 9 8

IRQLEVEL

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_PINCTRL_IRQPOL0 HW_PINCTRL_IRQPOL0

STMP 3700 0xa00

197

STMP 3780 0xb00

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

23.2.48

1 1 1 1 5 4 3 2

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

IRQPOL

STMP 3700 0xa10

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

STMP 3780 0xb10 1 1 0 0 1 0 9 8

IRQPOL

IRQPOL

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_PINCTRL_IRQPOL2 STMP 3700 0xa20

HW_PINCTRL_IRQPOL2 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

STMP 3780 0xb20 1 1 0 0 1 0 9 8

IRQPOL

IRQPOL

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

23.2.50

0 0 0 0 7 6 5 4

HW_PINCTRL_IRQPOL1 HW_PINCTRL_IRQPOL1

23.2.49

1 1 0 0 1 0 9 8

IRQPOL

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_PINCTRL_IRQSTAT0 HW_PINCTRL_IRQSTAT0

STMP 3700 0xb00

198

STMP 3780 0xc00

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

23.2.51

1 1 1 1 5 4 3 2

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

STMP 3780 0xc10

IRQSTAT

IRQSTAT

1 1 0 0 1 0 9 8

HW_PINCTRL_IRQSTAT2 HW_PINCTRL_IRQSTAT2 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

STMP 3700 0xb20

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

STMP 3780 0xc20 1 1 0 0 1 0 9 8

IRQSTAT

IRQSTAT

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

24.1

0 0 0 0 3 2 1 0

IRQSTAT

2 2 2 2 7 6 5 4

STMP 3700 0xb10

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

24

0 0 0 0 7 6 5 4

HW_PINCTRL_IRQSTAT1 HW_PINCTRL_IRQSTAT1

23.2.52

1 1 0 0 1 0 9 8

IRQSTAT

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

Power Supply Summary

The next table summarizes the important aspects of the Power Control device block and the main differences between the STMP 3700 and the STMP 3780. Name Power Control

Property Base Address

199

STMP 3700 STMP 3780 0x80044000

Name HW_POWER_CTRL HW_POWER_5VCTRL HW_POWER_MINPWR HW_POWER_CHARGE HW_POWER_VDDDCTRL HW_POWER_VDDACTRL HW_POWER_VDDIOCTRL HW_POWER_VDDMEMCTRL HW_POWER_DCFUNCV HW_POWER_DCDC4P2 HW_POWER_MISC HW_POWER_DCLIMITS HW_POWER_LOOPCTRL HW_POWER_STS HW_POWER_SPEED HW_POWER_BATTMONITOR HW_POWER_RESET HW_POWER_DEBUG HW_POWER_SPECIAL HW_POWER_VERSION

24.2

Programmable Registers

24.2.1

HW_POWER_CTRL

Property Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields

STMP 3700

STMP 3780 0x0 Incompatible Field(s) Incompatible Field(s) 0x10 Incompatible Field(s) Incompatible Field(s) 0x20 Incompatible Field(s) Incompatible Field(s) 0x30 New Field(s) 0x40 Incompatible Field(s) Incompatible Field(s) 0x50 New Field(s) 0x60 Incompatible Field(s) Incompatible Field(s) Non-Existent 0x70 New Field(s) 0x70 Non-Existent New Field(s) Non-Existent 0x80 New Field(s) 0x80 0x90 Incompatible Field(s) Incompatible Field(s) 0x90 0xa0 New Field(s) 0xa0 0xb0 0xb0 Incompatible Field(s) 0xc0

0xc0 Incompatible Field(s) 0xd0

0xd0 Incompatible Field(s) 0xe0

0xe0 Incompatible Field(s) 0x100

0xf0

0x110

0x100

0x120

0x110

0x130

HW_POWER_CTRL

200

0x0

24.2.3

201

HW_POWER_MINPWR

HW_POWER_MINPWR

0x20 ILIMIT_EQ_ZERO OTG_PWRUP_CMPS ENABLE_DCDC

ENABLE_DCDC

VBUSVALID_TO_B

VBUSVALID_TO_B

0 0 0 0 7 6 5 4

PWRUP_VBUS_CMPS

VBUSVALID_5VDETECT

VBUSVALID_5VDETECT

ENIRQ_VDDIO_BO VDDA_BO_IRQ ENIRQ_VDDA_BO VDDD_BO_IRQ ENIRQ_VDDD_BO POLARITY_VBUSVALID VBUSVALID_IRQ ENIRQ_VBUS_VALID

ENIRQ_VDDIO_BO VDDA_BO_IRQ ENIRQ_VDDA_BO VDDD_BO_IRQ ENIRQ_VDDD_BO POLARITY_VBUSVALID VBUSVALID_IRQ ENIRQ_VBUS_VALID

VDD5V_GT_VDDIO_IRQ ENIRQ_VDD5V_GT_VDDIO

VDD5V_GT_VDDIO_IRQ ENIRQ_VDD5V_GT_VDDIO

POLARITY_VDD5V_GT_VDDIO POLARITY_VDD5V_GT_VDDIO

VDDIO_BO_IRQ

VDDIO_BO_IRQ

0 0 0 0 7 6 5 4

ILIMIT_EQ_ZERO

EN_BATT_PULLDN

DCDC_XFER

1 1 0 0 1 0 9 8

ENABLE_LINREG_ILIMIT DCDC_XFER

ENIRQBATT_BO

ENIRQBATT_BO

ENIRQ_LINREG_OK

POLARITY_DC_OK

BATT_BO_IRQ

LINREG_OK_IRQ

ENIRQ_PSWITCH

BATT_BO_IRQ

POLARITY_LINREG_OK

POLARITY_PSWITCH

DC_OK_IRQ

ENIRQ_PSWITCH

PSWITCH_IRQ_SRC

ENIRQ_DC_OK

POLARITY_PSWITCH

PSWITCH_IRQ

DC_OK_IRQ

PSWITCH_IRQ_SRC

1 1 0 0 1 0 9 8

ENABLE_ILIMIT

1 1 1 1 5 4 3 2

PWDN_5VBRNOUT

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

PWDN_5VBRNOUT

HW_POWER_5VCTRL

VBUSVALID_TRSH

VBUSVALID_TRSH

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

ENIRQ_DC_OK

PSWITCH_IRQ

VDD5V_DROOP_IRQ ENIRQ_VDD5V_DROOP

DCDC4P2_BO_IRQ ENIRQ_DCDC4P2_BO

CLKGATE

CLKGATE

2 2 2 2 3 2 1 0

PSWITCH_MID_TRAN

STMP 3700

STMP 3780

2 2 2 2 7 6 5 4

CHARGE_4P2_ILIMIT

2 2 2 2 7 6 5 4

PWD_CHARGE_4P2

3 3 2 2 1 0 9 8

HEADROOM_ADJ

STMP 3700

24.2.2

VBUSDROOP_TRSH

STMP 3780

3 3 2 2 1 0 9 8 0 0 0 0 3 2 1 0

HW_POWER_5VCTRL 0x10

0 0 0 0 3 2 1 0

24.2.5 CHRG_STS_OFF

CHRG_STS_OFF

202 1 1 1 1 5 4 3 2

HW_POWER_VDDDCTRL

HW_POWER_VDDDCTRL

0x40 BATTCHRG_I

HW_POWER_CHARGE

BATTCHRG_I

1 1 1 1 9 8 7 6

USB_I_SUSPEND ENABLE_OSC SELECT_OSC VBG_OFF DOUBLE_FETS HALF_FETS LESSANA_I PWD_XTAL24 DC_STOPCLK EN_DC_PFM DC_HALFCLK

PWD_ANA_CMPS ENABLE_OSC SELECT_OSC VBG_OFF DOUBLE_FETS HALF_FETS LESSANA_I PWD_XTAL24 DC_STOPCLK EN_DC_PFM DC_HALFCLK

USE_VDDXTAL_VBG PWD_BO

PWD_BO

VDAC_DUMP_CTRL

LOWPWR_4P2

1 1 1 1 5 4 3 2

STOP_ILIMIT

PWD_BATTCHRG

PWD_BATTCHRG

STMP 3700

1 1 1 1 9 8 7 6

STOP_ILIMIT

USE_EXTERN_R

2 2 2 2 3 2 1 0

USE_EXTERN_R

STMP 3780

2 2 2 2 3 2 1 0

LIION_4P1

ENABLE_FAULT_DETECT

ENABLE_FAULT_DETECT

2 2 2 2 7 6 5 4

ENABLE_CHARGER_RESISTORS

3 3 2 2 1 0 9 8

2 2 2 2 7 6 5 4

ENABLE_LOAD

STMP 3700

24.2.4

ADJ_VOLT

STMP 3780

3 3 2 2 1 0 9 8 1 1 0 0 1 0 9 8

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

HW_POWER_CHARGE 0x30

0 0 0 0 3 2 1 0

24.2.7

203 1 1 1 1 5 4 3 2

HW_POWER_VDDIOCTRL HW_POWER_VDDIOCTRL 0x60 TRG

HW_POWER_VDDACTRL

TRG

1 1 1 1 9 8 7 6

BO_OFFSET

LINREG_OFFSET LINREG_OFFSET

BO_OFFSET

DISABLE_FET

DISABLE_FET

1 1 1 1 5 4 3 2

BO_OFFSET

LINREG_OFFSET

LINREG_OFFSET

ENABLE_LINREG

ENABLE_LINREG

DISABLE_STEPPING LINREG_FROM_BATT

DISABLE_STEPPING

ALKALINE_CHARGE

ADJTN

ADJTN

PWDN_BRNOUT

STMP 3700

STMP 3780

1 1 1 1 9 8 7 6

BO_OFFSET

DISABLE_FET

DISABLE_FET

2 2 2 2 3 2 1 0 ENABLE_LINREG

2 2 2 2 7 6 5 4

ENABLE_LINREG

3 3 2 2 1 0 9 8

2 2 2 2 3 2 1 0

DISABLE_STEPPING DISABLE_STEPPING

STMP 3700

24.2.6 2 2 2 2 7 6 5 4

PWDN_BRNOUT

STMP 3780

3 3 2 2 1 0 9 8 1 1 0 0 1 0 9 8

HW_POWER_VDDACTRL 0x50

1 1 0 0 1 0 9 8 0 0 0 0 7 6 5 4 0 0 0 0 3 2 1 0

TRG

0 0 0 0 3 2 1 0

TRG

0 0 0 0 7 6 5 4

1 1 0 0 1 0 9 8

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

TRG

BO_OFFSET

0 0 0 0 7 6 5 4

TRG

BO_OFFSET

LINREG_OFFSET

DISABLE_FET

ADJTN DISABLE_STEPPING

PWDN_BRNOUT

ADJTN

STMP 3780 24.2.8

1 1 1 1 5 4 3 2 LINREG_OFFSET

1 1 1 1 9 8 7 6

DISABLE_STEPPING

2 2 2 2 3 2 1 0

DISABLE_FET

2 2 2 2 7 6 5 4

STMP 3700

3 3 2 2 1 0 9 8

HW_POWER_VDDMEMCTRL STMP 3700 Non-Existent

HW_POWER_VDDMEMCTRL 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

TRG

ENABLE_LINREG

HW_POWER_DCFUNCV HW_POWER_DCFUNCV 2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

STMP 3780 Non-Existent 1 1 0 0 1 0 9 8

VDDIO

2 2 2 2 7 6 5 4

STMP 3700 0x70

VDDD

3 3 2 2 1 0 9 8 STMP 3780 STMP 3700

24.2.9

ENABLE_ILIMIT

STMP 3780

PULLDOWN_ACTIVE

STMP 3700

3 3 2 2 1 0 9 8

STMP 3780 0x70

204

24.2.10

HW_POWER_DCDC4P2 HW_POWER_DCDC4P2 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

1 1 0 0 1 0 9 8

FREQSEL FREQSEL

STMP 3780 HW_POWER_DCLIMITS HW_POWER_DCLIMITS

STMP 3700 0x90

205

STMP 3780 0xa0

PERIPHERALSWOFF

1 1 1 1 5 4 3 2

SEL_PLLCLK

1 1 1 1 9 8 7 6

SEL_PLLCLK

2 2 2 2 3 2 1 0

DELAY_TIMING TEST

2 2 2 2 7 6 5 4

STMP 3780 0x90

STMP 3700

3 3 2 2 1 0 9 8

STMP 3700 0x80

TEST

HW_POWER_MISC

24.2.12

CMPTRIP

BO

TRG

HYST_THRESH

HYST_DIR

ENABLE_DCDC

ENABLE_4P2

ISTEAL_THRESH

HW_POWER_MISC

DELAY_TIMING

24.2.11

DROPOUT_CTRL

STMP 3780

STMP 3700

3 3 2 2 1 0 9 8

STMP 3780 0x80

STMP 3700 Non-Existent

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

0 0 0 0 3 2 1 0

HW_POWER_LOOPCTRL STMP 3700 0xa0

EN_RCSCALE

DC_FF

DC_R

DC_C

DC_FF

DC_R

DC_C

STMP 3700 0xb0

206

0 0 0 0 3 2 1 0

EN_RCSCALE

HW_POWER_STS HW_POWER_STS

0 0 0 0 7 6 5 4

RCSCALE_THRESH

1 1 0 0 1 0 9 8

DF_HYST_THRESH

EN_DF_HYST EN_DF_HYST

1 1 1 1 5 4 3 2

RCSCALE_THRESH

EN_CM_HYST EN_CM_HYST

CM_HYST_THRESH CM_HYST_THRESH

HYST_SIGN HYST_SIGN

1 1 1 1 9 8 7 6

TOGGLE_DIF

STMP 3780

2 2 2 2 3 2 1 0

TOGGLE_DIF

2 2 2 2 7 6 5 4

STMP 3700

3 3 2 2 1 0 9 8

STMP 3780 0xb0

DF_HYST_THRESH

HW_POWER_LOOPCTRL

24.2.14

0 0 0 0 7 6 5 4

POSLIMIT_BUCK POSLIMIT_BUCK

STMP 3700 STMP 3780 24.2.13

1 1 0 0 1 0 9 8

NEGLIMIT

2 2 2 2 3 2 1 0

NEGLIMIT

2 2 2 2 7 6 5 4

POSLIMIT_BOOST

3 3 2 2 1 0 9 8

STMP 3780 0xc0

24.2.16 HW_POWER_SPEED

2 2 2 2 3 2 1 0

CTRL

2 2 2 2 7 6 5 4

BVALID_STATUS

1 1 1 1 9 8 7 6

HW_POWER_BATTMONITOR

207 STMP 3700 0xc0

1 1 1 1 5 4 3 2

STMP 3700 0xd0 1 1 0 0 1 0 9 8

HW_POWER_BATTMONITOR

STMP 3780 0xe0

BVALID VBUSVALID SESSEND

SESSEND

VDDA_BO VDDD_BO

VBUSVALID

VDDIO_BO VDDA_BO

BVALID

DC_OK

VDDIO_BO

AVALID

LINREG_OK

DC_OK

AVALID

CHRGSTS

DCDC_4P2_BO

VDDD_BO

VDD5V_FAULT CHRGSTS

VDD5V_GT_VDDIO

BATT_BO

VDD5V_FAULT

VDD5V_DROOP

MODE

BATT_BO

1 1 1 1 5 4 3 2

VDD5V_GT_VDDIO

SESSEND_STATUS

SESSEND_STATUS

1 1 1 1 9 8 7 6 VBUSVALID_STATUS VBUSVALID_STATUS

BVALID_STATUS

AVALID_STATUS

PSWITCH

BATT_CHRG_PRESENT

STMP 3700

2 2 2 2 3 2 1 0

AVALID_STATUS

PSWITCH

PWRUP_SOURCE

STMP 3780

2 2 2 2 7 6 5 4

CTRL

3 3 2 2 1 0 9 8 STATUS

24.2.15

STATUS

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8 1 1 0 0 1 0 9 8 0 0 0 0 7 6 5 4

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

HW_POWER_SPEED STMP 3780 0xd0

0 0 0 0 3 2 1 0

BRWNOUT_LVL

BRWNOUT_PWD

PWDN_BATTBRNOUT

EN_BATADJ

BATT_VAL

0 0 0 0 3 2 1 0

BRWNOUT_LVL

0 0 0 0 7 6 5 4

BRWNOUT_PWD

1 1 0 0 1 0 9 8

HW_POWER_RESET

HW_POWER_DEBUG HW_POWER_DEBUG

STMP 3700 0xf0

208

STMP 3780 0x110

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

PWD

1 1 0 0 1 0 9 8

PWD

1 1 1 1 5 4 3 2

PWD_OFF

1 1 1 1 9 8 7 6

UNLOCK

2 2 2 2 3 2 1 0

STMP 3780 0x100

UNLOCK

2 2 2 2 7 6 5 4

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

STMP 3700 0xe0

PWD_OFF

HW_POWER_RESET

24.2.18

1 1 1 1 5 4 3 2

BATT_VAL

STMP 3780 24.2.17

1 1 1 1 9 8 7 6

PWDN_BATTBRNOUT

2 2 2 2 3 2 1 0

EN_BATADJ

2 2 2 2 7 6 5 4

STMP 3700

3 3 2 2 1 0 9 8

STMP 3700 STMP 3780 24.2.19

HW_POWER_SPECIAL HW_POWER_SPECIAL 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

STMP 3700 0x100

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

STMP 3780 0x120 1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

TEST

TEST

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_POWER_VERSION HW_POWER_VERSION

STMP 3700 0x110

1 1 0 0 1 0 9 8

STEP

1 1 1 1 5 4 3 2

STMP 3780 0x130

STEP

MINOR

1 1 1 1 9 8 7 6

MINOR

2 2 2 2 3 2 1 0

MAJOR

2 2 2 2 7 6 5 4

MAJOR

3 3 2 2 1 0 9 8 STMP 3780 STMP 3700

24.2.20

0 0 0 0 3 2 1 0 SESSENDPIOLOCK

0 0 0 0 7 6 5 4

SESSENDPIOLOCK

1 1 0 0 1 0 9 8

BVALIDPIOLOCK

1 1 1 1 5 4 3 2

AVALIDPIOLOCK

1 1 1 1 9 8 7 6

BVALIDPIOLOCK

2 2 2 2 3 2 1 0

AVALIDPIOLOCK

2 2 2 2 7 6 5 4

VBUSVALIDPIOLOCK VBUSVALIDPIOLOCK

3 3 2 2 1 0 9 8

209

25 25.1

Pulse-Width Modulator (PWM) Controller Summary

The next table summarizes the important aspects of the Pulse width Modulation device block and the main differences between the STMP 3700 and the STMP 3780.

25.2.2

PWM3_PRESENT

PWM2_PRESENT

PWM1_PRESENT

PWM0_PRESENT

PWM3_PRESENT

PWM2_PRESENT

PWM1_PRESENT

PWM0_PRESENT

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

HW_PWM_VERSION HW_PWM_VERSION

210

0xb0

0 0 0 0 3 2 1 0

PWM0_ENABLE

PWM4_PRESENT PWM4_PRESENT

1 1 1 1 5 4 3 2

PWM0_ENABLE

CLKGATE CLKGATE

1 1 1 1 9 8 7 6

PWM1_ENABLE

SFTRST SFTRST

2 2 2 2 3 2 1 0

OUTPUT_CUTOFF_EN

STMP 3700

2 2 2 2 7 6 5 4

STMP 3780

3 3 2 2 1 0 9 8

0x0

PWM2_ENABLE

HW_PWM_CTRL

PWM2_ENABLE

HW_PWM_CTRL

PWM1_ENABLE

25.2.1

PWM3_ENABLE

Programmable Registers

PWM3_ENABLE

25.2

PWM4_ENABLE

HW_PWM_VERSION

STMP 3700 STMP 3780 0x80064000 0x0 New Field(s) 0xb0

PWM4_ENABLE

HW_PWM_CTRL

Property Base Address Address Fields Address Fields

PWM2_ANA_CTRL_ENABLE PWM2_ANA_CTRL_ENABLE

Name Pulse width Modulation

26 26.1

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

STEP

MINOR

STEP

MINOR

MAJOR

2 2 2 2 7 6 5 4

MAJOR

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

Pixel Pipeline (PXP) Summary

The next table summarizes the important aspects of the Pixel Pipeline device block and the main differences between the STMP 3700 and the STMP 3780. Name Pixel Pipeline HW_PXP_CTRL HW_PXP_STAT HW_PXP_RGBBUF HW_PXP_RGBBUF2 HW_PXP_RGBSIZE HW_PXP_S0BUF HW_PXP_S0UBUF HW_PXP_S0VBUF HW_PXP_S0PARAM HW_PXP_S0BACKGROUND HW_PXP_S0CROP HW_PXP_S0SCALE HW_PXP_S0OFFSET HW_PXP_CSCCOEFF0 HW_PXP_CSCCOEFF1 HW_PXP_CSCCOEFF2 HW_PXP_NEXT

Property Base Address Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields

211

STMP 3700 Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent

STMP 3780 0x8002a000 0x0 New Field(s) 0x10 New Field(s) 0x20 New Field(s) 0x30 New Field(s) 0x40 New Field(s) 0x50 New Field(s) 0x60 New Field(s) 0x70 New Field(s) 0x80 New Field(s) 0x90 New Field(s) 0xa0 New Field(s) 0xb0 New Field(s) 0xc0 New Field(s) 0xd0 New Field(s) 0xe0 New Field(s) 0xf0 New Field(s) 0x100 New Field(s)

Name HW_PXP_PAGETABLE HW_PXP_S0COLORKEYLOW HW_PXP_S0COLORKEYHIGH HW_PXP_OLCOLORKEYLOW HW_PXP_OLCOLORKEYHIGH HW_PXP_DEBUGCTRL HW_PXP_DEBUG HW_PXP_VERSION

26.2

Programmable Registers

26.2.1

HW_PXP_CTRL HW_PXP_CTRL 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

STMP 3700 Non-Existent

STMP 3700 Non-Existent

STMP 3780 0x0

1 1 1 1 9 8 7 6

Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent

1 1 1 1 5 4 3 2

STMP 3780 0x170 New Field(s) 0x180 New Field(s) 0x190 New Field(s) 0x1a0 New Field(s) 0x1b0 New Field(s) 0x1d0 New Field(s) 0x1e0 New Field(s) 0x1f0 New Field(s)

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

26.2.2

HW_PXP_STAT HW_PXP_STAT

STMP 3700 Non-Existent

212

STMP 3780 0x10

ENABLE

IRQ_ENABLE

ENABLE_LCD_HANDSHAKE

OUTPUT_RGB_FORMAT

ROTATE

HFLIP

VFLIP

S0_FORMAT

SUBSAMPLE

UPSAMPLE

SCALE

CROP

DELTA

IN_PLACE

ALPHA_OUTPUT

INTERLACED_INPUT

INTERLACED_OUTPUT

CLKGATE

SFTRST

STMP 3780

STMP 3700

3 3 2 2 1 0 9 8

Property Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

26.2.3

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

STMP 3700 Non-Existent

1 1 1 1 9 8 7 6

IRQ

STMP 3780 0x20

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

ADDR

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_PXP_RGBBUF2 HW_PXP_RGBBUF2 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

STMP 3700 Non-Existent

1 1 1 1 9 8 7 6

STMP 3780 0x30

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

ADDR

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

26.2.5

AXI_WRITE_ERROR

HW_PXP_RGBBUF HW_PXP_RGBBUF

26.2.4

AXI_READ_ERROR

AXI_ERROR_ID

BLOCKY

BLOCKX

STMP 3780

STMP 3700

3 3 2 2 1 0 9 8

HW_PXP_RGBSIZE HW_PXP_RGBSIZE

STMP 3700 Non-Existent

213

STMP 3780 0x40

26.2.6

1 1 1 1 9 8 7 6

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

STMP 3700 Non-Existent

1 1 1 1 9 8 7 6

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

STMP 3780 0x50

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

ADDR

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_PXP_S0UBUF HW_PXP_S0UBUF 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

STMP 3700 Non-Existent

1 1 1 1 9 8 7 6

STMP 3780 0x60

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

ADDR

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

26.2.8

1 1 0 0 1 0 9 8

HW_PXP_S0BUF HW_PXP_S0BUF

26.2.7

1 1 1 1 5 4 3 2

HEIGHT

2 2 2 2 3 2 1 0

WIDTH

2 2 2 2 7 6 5 4

ALPHA

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_PXP_S0VBUF HW_PXP_S0VBUF

STMP 3700 Non-Existent

214

STMP 3780 0x70

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

0 0 0 0 3 2 1 0

2 2 2 2 3 2 1 0

STMP 3700 Non-Existent

1 1 1 1 9 8 7 6

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

STMP 3780 0x80

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

HEIGHT

2 2 2 2 7 6 5 4

YBASE

XBASE

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_PXP_S0BACKGROUND STMP 3700 Non-Existent

HW_PXP_S0BACKGROUND 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

STMP 3780 0x90 1 1 0 0 1 0 9 8

COLOR

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

26.2.11

0 0 0 0 7 6 5 4

HW_PXP_S0PARAM HW_PXP_S0PARAM

26.2.10

1 1 0 0 1 0 9 8

WIDTH

26.2.9

1 1 1 1 5 4 3 2

ADDR

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_PXP_S0CROP HW_PXP_S0CROP

STMP 3700 Non-Existent

215

STMP 3780 0xa0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

YBASE

0 0 0 0 3 2 1 0

1 1 1 1 9 8 7 6

STMP 3780 0xb0

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

YSCALE

2 2 2 2 3 2 1 0

STMP 3700 Non-Existent

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

XSCALE

2 2 2 2 7 6 5 4

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_PXP_S0OFFSET HW_PXP_S0OFFSET 2 2 2 2 3 2 1 0

STMP 3700 Non-Existent

1 1 1 1 9 8 7 6

STMP 3780 0xc0

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

YOFFSET

2 2 2 2 7 6 5 4

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

26.2.14

1 1 0 0 1 0 9 8

HW_PXP_S0SCALE HW_PXP_S0SCALE

26.2.13

1 1 1 1 5 4 3 2

HEIGHT

1 1 1 1 9 8 7 6

WIDTH

2 2 2 2 3 2 1 0

HW_PXP_CSCCOEFF0 HW_PXP_CSCCOEFF0

0 0 0 0 7 6 5 4

XOFFSET

26.2.12

2 2 2 2 7 6 5 4

XBASE

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

STMP 3700 Non-Existent

216

STMP 3780 0xd0

0 0 0 0 3 2 1 0

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

26.2.15

HW_PXP_CSCCOEFF1 HW_PXP_CSCCOEFF1

1 1 1 1 9 8 7 6

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

HW_PXP_CSCCOEFF2 HW_PXP_CSCCOEFF2 2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

STMP 3780 0xf0 1 1 0 0 1 0 9 8

HW_PXP_NEXT HW_PXP_NEXT

0 0 0 0 7 6 5 4

C3

2 2 2 2 7 6 5 4

STMP 3700 Non-Existent

C2

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

26.2.17

1 1 1 1 5 4 3 2

STMP 3780 0xe0

C1

2 2 2 2 3 2 1 0

STMP 3700 Non-Existent

C4

2 2 2 2 7 6 5 4

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

26.2.16

Y_OFFSET

UV_OFFSET

C0

YCBCR_MODE

STMP 3780

STMP 3700

3 3 2 2 1 0 9 8

STMP 3700 Non-Existent

217

STMP 3780 0x100

0 0 0 0 3 2 1 0

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

POINTER

2 2 2 2 3 2 1 0

STMP 3700 Non-Existent

1 1 1 1 9 8 7 6

STMP 3780 0x170

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

BASE

FLUSH

2 2 2 2 7 6 5 4

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_PXP_S0COLORKEYLOW HW_PXP_S0COLORKEYLOW 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

STMP 3700 Non-Existent 1 1 1 1 5 4 3 2

STMP 3780 0x180 1 1 0 0 1 0 9 8

PIXEL

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

26.2.20

0 0 0 0 7 6 5 4

HW_PXP_PAGETABLE HW_PXP_PAGETABLE

26.2.19

1 1 0 0 1 0 9 8

ENABLE

26.2.18

1 1 1 1 5 4 3 2

ENABLED

2 2 2 2 7 6 5 4

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_PXP_S0COLORKEYHIGH HW_PXP_S0COLORKEYHIGH

218

STMP 3700 Non-Existent

STMP 3780 0x190

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

26.2.21

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

STMP 3700 Non-Existent 1 1 1 1 5 4 3 2

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

STMP 3780 0x1a0 1 1 0 0 1 0 9 8

PIXEL

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_PXP_OLCOLORKEYHIGH HW_PXP_OLCOLORKEYHIGH 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

STMP 3700 Non-Existent 1 1 1 1 5 4 3 2

STMP 3780 0x1b0 1 1 0 0 1 0 9 8

PIXEL

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

26.2.23

0 0 0 0 7 6 5 4

HW_PXP_OLCOLORKEYLOW HW_PXP_OLCOLORKEYLOW

26.2.22

1 1 0 0 1 0 9 8

PIXEL

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_PXP_DEBUGCTRL HW_PXP_DEBUGCTRL

STMP 3700 Non-Existent

219

STMP 3780 0x1d0

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

26.2.24

HW_PXP_DEBUG HW_PXP_DEBUG 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

STMP 3700 Non-Existent

1 1 1 1 9 8 7 6

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

1 1 1 1 9 8 7 6

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

STMP 3780 0x1f0

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

STEP

2 2 2 2 3 2 1 0

STMP 3700 Non-Existent

MINOR

2 2 2 2 7 6 5 4

MAJOR

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

27.1

1 1 1 1 5 4 3 2

HW_PXP_VERSION HW_PXP_VERSION

27

STMP 3780 0x1e0

DATA

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

26.2.25

SELECT

STMP 3780

RESET_TLB_STATS

STMP 3700

3 3 2 2 1 0 9 8

Real-Time Clock, Alarm, Watchdog, Persistent Bits Summary

The next table summarizes the important aspects of the Real Time Clock device block and the main differences between the STMP 3700 and the STMP 3780.

220

Name Real Time Clock HW_RTC_CTRL HW_RTC_STAT HW_RTC_MILLISECONDS HW_RTC_SECONDS HW_RTC_ALARM HW_RTC_WATCHDOG HW_RTC_PERSISTENT0 HW_RTC_PERSISTENT1 HW_RTC_PERSISTENT2 HW_RTC_PERSISTENT3 HW_RTC_PERSISTENT4 HW_RTC_PERSISTENT5 HW_RTC_DEBUG HW_RTC_VERSION

27.2

Programmable Registers

27.2.1

HW_RTC_CTRL

Property Base Address Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields

HW_RTC_CTRL

221

STMP 3700 STMP 3780 0x8005c000 0x0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 0x90 0xa0 0xb0 0xc0 0xd0

0x0

27.2.3 RTC_PRESENT ALARM_PRESENT

RTC_PRESENT

ALARM_PRESENT

2 2 2 2 3 2 1 0

NEW_REGS

SFTRST CLKGATE

SFTRST CLKGATE

SUPPRESS_COPY2ANALOG SUPPRESS_COPY2ANALOG

STMP 3700

STMP 3780

2 2 2 2 3 2 1 0

NEW_REGS

2 2 2 2 7 6 5 4

STALE_REGS

XTAL32768_PRESENT

XTAL32768_PRESENT

3 3 2 2 1 0 9 8

2 2 2 2 7 6 5 4

STALE_REGS

XTAL32000_PRESENT

XTAL32000_PRESENT

WATCHDOG_PRESENT WATCHDOG_PRESENT

STMP 3700

27.2.2

STMP 3780

3 3 2 2 1 0 9 8 1 1 1 1 9 8 7 6

HW_RTC_STAT

1 1 1 1 9 8 7 6

222

1 1 1 1 5 4 3 2

HW_RTC_STAT 0x10

1 1 1 1 5 4 3 2

HW_RTC_MILLISECONDS

HW_RTC_MILLISECONDS

0x20

WATCHDOGEN ONEMSEC_IRQ ALARM_IRQ ONEMSEC_IRQ_EN ALARM_IRQ_EN

ONEMSEC_IRQ ALARM_IRQ ONEMSEC_IRQ_EN ALARM_IRQ_EN

0 0 0 0 7 6 5 4

FORCE_UPDATE

1 1 0 0 1 0 9 8 WATCHDOGEN

0 0 0 0 7 6 5 4

FORCE_UPDATE

1 1 0 0 1 0 9 8 0 0 0 0 3 2 1 0

0 0 0 0 3 2 1 0

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

27.2.4

1 1 1 1 5 4 3 2

0 0 0 0 3 2 1 0

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

COUNT

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

0x30

1 1 1 1 5 4 3 2

COUNT

COUNT

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_RTC_ALARM HW_RTC_ALARM 1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

VALUE

2 2 2 2 3 2 1 0

0x40

VALUE

2 2 2 2 7 6 5 4

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

27.2.6

0 0 0 0 7 6 5 4

HW_RTC_SECONDS HW_RTC_SECONDS

27.2.5

1 1 0 0 1 0 9 8

COUNT

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_RTC_WATCHDOG HW_RTC_WATCHDOG

223

0x50

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

COUNT

ALARM_EN

ALARM_WAKE_EN

CLOCKSOURCE

ALARM_EN

ALARM_WAKE_EN

CLOCKSOURCE

LCK_SECS

XTAL32KHZ_PWRUP XTAL32KHZ_PWRUP

LCK_SECS

XTAL32_FREQ XTAL32_FREQ

XTAL24MHZ_PWRUP XTAL24MHZ_PWRUP

ALARM_WAKE

DISABLE_XTALOK DISABLE_XTALOK

ALARM_WAKE

LOWERBIAS LOWERBIAS

1 1 0 0 1 0 9 8

MSEC_RES

DISABLE_PSWITCH

1 1 1 1 5 4 3 2

DISABLE_PSWITCH

1 1 1 1 9 8 7 6

AUTO_RESTART

SPARE_ANALOG SPARE_ANALOG

2 2 2 2 3 2 1 0

0x60

AUTO_RESTART

STMP 3700

2 2 2 2 7 6 5 4

STMP 3780

3 3 2 2 1 0 9 8

HW_RTC_PERSISTENT1 HW_RTC_PERSISTENT1 1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

GENERAL

2 2 2 2 3 2 1 0

0x70

GENERAL

2 2 2 2 7 6 5 4

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

27.2.9

0 0 0 0 7 6 5 4

HW_RTC_PERSISTENT0 HW_RTC_PERSISTENT0

27.2.8

1 1 0 0 1 0 9 8

MSEC_RES

27.2.7

1 1 1 1 5 4 3 2 COUNT

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_RTC_PERSISTENT2 HW_RTC_PERSISTENT2

224

0x80

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

27.2.10

1 1 1 1 5 4 3 2

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

GENERAL

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

0x90

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

GENERAL

GENERAL

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_RTC_PERSISTENT4 HW_RTC_PERSISTENT4 1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

GENERAL

2 2 2 2 3 2 1 0

0xa0

GENERAL

2 2 2 2 7 6 5 4

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

27.2.12

0 0 0 0 7 6 5 4

HW_RTC_PERSISTENT3 HW_RTC_PERSISTENT3

27.2.11

1 1 0 0 1 0 9 8

GENERAL

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_RTC_PERSISTENT5 HW_RTC_PERSISTENT5

225

0xb0

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

GENERAL

HW_RTC_DEBUG

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

STMP 3780

STMP 3700

WATCHDOG_RESET_MASK WATCHDOG_RESET_MASK

3 3 2 2 1 0 9 8

0xc0

HW_RTC_VERSION HW_RTC_VERSION

0xd0

STEP

1 1 1 1 5 4 3 2

STEP

MINOR

1 1 1 1 9 8 7 6

MINOR

2 2 2 2 3 2 1 0

MAJOR

2 2 2 2 7 6 5 4

MAJOR

3 3 2 2 1 0 9 8 STMP 3780 STMP 3700

27.2.14

WATCHDOG_RESET

HW_RTC_DEBUG

WATCHDOG_RESET

27.2.13

1 1 1 1 5 4 3 2 GENERAL

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

226

28 28.1

Serial Audio Interface (SAIF) Summary

The next table summarizes the important aspects of the Sync Audio Interface device block and the main differences between the STMP 3700 and the STMP 3780.

28.2.2

1 1 1 1 9 8 7 6

STMP 3780 Non-Existent

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

HW_SAIF_STAT HW_SAIF_STAT

STMP 3700 0x10

227

STMP 3780 Non-Existent

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

RUN

2 2 2 2 3 2 1 0

DMAWAIT_COUNT

FIFO_SERVICE_IRQ_EN

FIFO_ERROR_IRQ_EN

2 2 2 2 7 6 5 4

BITCLK_BASE_RATE

BITCLK_MULT_RATE

CLKGATE

SFTRST

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

STMP 3700 0x0

SLAVE_MODE

HW_SAIF_CTRL

READ_MODE

HW_SAIF_CTRL

BITCLK_48XFS_ENABLE

28.2.1

WORD_LENGTH

Programmable Registers

BITCLK_EDGE

28.2

LRCLK_POLARITY

HW_SAIF_VERSION

JUSTIFY

HW_SAIF_DATA

DELAY

HW_SAIF_STAT

STMP 3700 STMP 3780 0x80042000 0x0 Non-Existent New Field(s) 0x10 Non-Existent New Field(s) 0x20 Non-Existent New Field(s) 0x30 Non-Existent New Field(s)

BIT_ORDER

HW_SAIF_CTRL

Property Base Address Address Fields Address Fields Address Fields Address Fields

CHANNEL_NUM_SELECT

Name Sync Audio Interface

0 0 0 0 7 6 5 4

BUSY

0 0 0 0 3 2 1 0

FIFO_SERVICE_IRQ

FIFO_OVERFLOW_IRQ

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

HW_SAIF_DATA HW_SAIF_DATA 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

STMP 3700 0x20

1 1 1 1 9 8 7 6

STMP 3780 Non-Existent

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8 PCM_LEFT

STMP 3780 STMP 3700

PCM_RIGHT

3 3 2 2 1 0 9 8

HW_SAIF_VERSION HW_SAIF_VERSION 2 2 2 2 3 2 1 0

STMP 3700 0x30

1 1 1 1 9 8 7 6 MINOR

2 2 2 2 7 6 5 4 MAJOR

3 3 2 2 1 0 9 8 STMP 3780 STMP 3700

28.2.4

1 1 1 1 5 4 3 2

FIFO_UNDERFLOW_IRQ

1 1 1 1 9 8 7 6

DMA_PREQ

2 2 2 2 3 2 1 0

STMP 3780 Non-Existent

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

STEP

28.2.3

2 2 2 2 7 6 5 4

PRESENT

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

228

29 29.1

Serial Audio Interface 1 (SAIF1) Summary

The next table summarizes the important aspects of the Sync Audio Interface 1 device block and the main differences between the STMP 3700 and the STMP 3780. Name Sync Audio Interface 1

29.2

30 30.1

Property Base Address

STMP 3700 Non-Existent

STMP 3780 0x80042000

Programmable Registers

Serial Audio Interface 2 (SAIF2) Summary

The next table summarizes the important aspects of the Sync Audio Interface 2 device block and the main differences between the STMP 3700 and the STMP 3780. Name Sync Audio Interface 2

30.2

31 31.1

Property Base Address

STMP 3700 Non-Existent

STMP 3780 0x80046000

Programmable Registers

SPDIF Transmitter Summary

The next table summarizes the important aspects of the Sony/Phillips Digital Audio Interface device block and the main differences between the STMP 3700 and the STMP 3780. Name Sony/Phillips Digital Audio Interface HW_SPDIF_CTRL HW_SPDIF_STAT HW_SPDIF_FRAMECTRL HW_SPDIF_SRR HW_SPDIF_DEBUG HW_SPDIF_DATA HW_SPDIF_VERSION

31.2

Programmable Registers

31.2.1

HW_SPDIF_CTRL

Property

STMP 3700

STMP 3780

Base Address

0x80054000

Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields

0x0

HW_SPDIF_CTRL

229

0x10 0x20 0x30 0x40 0x50 0x60

0x0

31.2.2

RUN

RUN

0 0 0 0 3 2 1 0

FIFO_ERROR_IRQ_EN

0 0 0 0 7 6 5 4

FIFO_OVERFLOW_IRQ

0 0 0 0 3 2 1 0

FIFO_ERROR_IRQ_EN

0 0 0 0 7 6 5 4

FIFO_OVERFLOW_IRQ

0 0 0 0 3 2 1 0 FIFO_UNDERFLOW_IRQ FIFO_UNDERFLOW_IRQ

1 1 0 0 1 0 9 8

WAIT_END_XFER

0 0 0 0 7 6 5 4

HW_SPDIF_STAT HW_SPDIF_STAT 2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

END_XFER

PRESENT

END_XFER

2 2 2 2 7 6 5 4

0x10

PRESENT

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_SPDIF_FRAMECTRL HW_SPDIF_FRAMECTRL

230

0x20

V

L

CC

PRE

COPY

AUDIO

PRO

V

L

CC

PRE

COPY

AUDIO

PRO

1 1 0 0 1 0 9 8

USER_DATA

1 1 1 1 5 4 3 2

USER_DATA

AUTO_MUTE AUTO_MUTE

1 1 1 1 9 8 7 6 V_CONFIG

2 2 2 2 3 2 1 0

V_CONFIG

2 2 2 2 7 6 5 4

STMP 3700

3 3 2 2 1 0 9 8

STMP 3780

31.2.3

1 1 0 0 1 0 9 8

WORD_LENGTH

1 1 1 1 5 4 3 2

WORD_LENGTH

1 1 1 1 9 8 7 6

WAIT_END_XFER

CLKGATE CLKGATE

2 2 2 2 3 2 1 0

DMAWAIT_COUNT

SFTRST SFTRST

2 2 2 2 7 6 5 4

DMAWAIT_COUNT

STMP 3700 STMP 3780

3 3 2 2 1 0 9 8

HW_SPDIF_SRR HW_SPDIF_SRR

31.2.5

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

RATE

BASEMULT

2 2 2 2 7 6 5 4

RATE

BASEMULT

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

0x30

HW_SPDIF_DEBUG HW_SPDIF_DEBUG 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

STMP 3780

DMA_PREQ

STMP 3700

DMA_PREQ

3 3 2 2 1 0 9 8

0x40

31.2.6

HW_SPDIF_DATA HW_SPDIF_DATA 1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

LOW

HIGH

2 2 2 2 3 2 1 0

0x50

LOW

HIGH

2 2 2 2 7 6 5 4

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

31.2.7

FIFO_STATUS FIFO_STATUS

31.2.4

HW_SPDIF_VERSION HW_SPDIF_VERSION

231

0x60

32 32.1

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

STEP

MINOR

STEP

MINOR

MAJOR

2 2 2 2 7 6 5 4

MAJOR

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

Synchronous Serial Ports (SSP) Summary

The next table summarizes the important aspects of the Sync Serial Port device block and the main differences between the STMP 3700 and the STMP 3780. Name Sync Serial Port HW_SSP_CTRL0 HW_SSP_CMD0 HW_SSP_CMD1 HW_SSP_COMPREF HW_SSP_COMPMASK HW_SSP_TIMING HW_SSP_CTRL1 HW_SSP_DATA HW_SSP_SDRESP0 HW_SSP_SDRESP1 HW_SSP_SDRESP2 HW_SSP_SDRESP3 HW_SSP_STATUS HW_SSP_DEBUG HW_SSP_VERSION

Property Base Address Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields

232

STMP 3700 STMP 3780 0x80010000 0x0 Non-Existent New Field(s) 0x10 Non-Existent New Field(s) 0x20 Non-Existent New Field(s) 0x30 Non-Existent New Field(s) 0x40 Non-Existent New Field(s) 0x50 Non-Existent New Field(s) 0x60 Non-Existent New Field(s) 0x70 Non-Existent New Field(s) 0x80 Non-Existent New Field(s) 0x90 Non-Existent New Field(s) 0xa0 Non-Existent New Field(s) 0xb0 Non-Existent New Field(s) 0xc0 Non-Existent New Field(s) 0x100 Non-Existent New Field(s) 0x110 Non-Existent New Field(s)

32.2.1

HW_SSP_CTRL0 STMP 3700 0x0

HW_SSP_CTRL0

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

HW_SSP_CMD0

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

BLOCK_SIZE

STMP 3780 STMP 3700

STMP 3780 Non-Existent 1 1 0 0 1 0 9 8 BLOCK_COUNT

2 2 2 2 7 6 5 4

APPEND_8CYC

3 3 2 2 1 0 9 8

STMP 3700 0x10

CMD

HW_SSP_CMD0

HW_SSP_CMD1 HW_SSP_CMD1 3 3 2 2 1 0 9 8 STMP 3780 STMP 3700

32.2.3

GET_RESP

CHECK_RESP

1 1 1 1 9 8 7 6

LONG_RESP

WAIT_FOR_CMD

WAIT_FOR_IRQ

2 2 2 2 3 2 1 0

BUS_WIDTH

DATA_XFER

READ

IGNORE_CRC

LOCK_CS

SDIO_IRQ_CHECK

RUN

CLKGATE

2 2 2 2 7 6 5 4

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

STMP 3700 0x20

1 1 1 1 9 8 7 6

STMP 3780 Non-Existent

1 1 1 1 5 4 3 2 CMD_ARG

32.2.2

SFTRST

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

STMP 3780 Non-Existent

XFER_COUNT

Programmable Registers

ENABLE

32.2

233

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

HW_SSP_COMPREF

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

STMP 3780 STMP 3700 32.2.5

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

STMP 3700 0x40

1 1 1 1 9 8 7 6

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

STMP 3780 Non-Existent

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

MASK

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_SSP_TIMING HW_SSP_TIMING 2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

STMP 3780 Non-Existent

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8 CLOCK_DIVIDE

2 2 2 2 7 6 5 4

STMP 3700 0x50

TIMEOUT

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

32.2.7

1 1 0 0 1 0 9 8

HW_SSP_COMPMASK HW_SSP_COMPMASK

32.2.6

1 1 1 1 5 4 3 2 REFERENCE

3 3 2 2 1 0 9 8

STMP 3780 Non-Existent

STMP 3700 0x30

HW_SSP_COMPREF

HW_SSP_CTRL1 HW_SSP_CTRL1

STMP 3700 0x60 234

STMP 3780 Non-Existent

CLOCK_RATE

32.2.4

SLAVE_MODE

POLARITY

PHASE

SLAVE_OUT_DISABLE

CEATA_CCS_ERR_EN

DMA_ENABLE

FIFO_OVERRUN_IRQ

FIFO_OVERRUN_IRQ_EN

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

SSP_MODE

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

STMP 3700 0x70

1 1 1 1 9 8 7 6

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

STMP 3780 Non-Existent

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

DATA

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_SSP_SDRESP0 HW_SSP_SDRESP0 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

STMP 3700 0x80

1 1 1 1 9 8 7 6

STMP 3780 Non-Existent

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

RESP0

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

32.2.10

1 1 0 0 1 0 9 8

HW_SSP_DATA HW_SSP_DATA

32.2.9

1 1 1 1 5 4 3 2

RECV_TIMEOUT_IRQ_EN

RECV_TIMEOUT_IRQ

CEATA_CCS_ERR_IRQ_EN

1 1 1 1 9 8 7 6 CEATA_CCS_ERR_IRQ

FIFO_UNDERRUN_EN

FIFO_UNDERRUN_IRQ

DATA_CRC_IRQ_EN

DATA_TIMEOUT_IRQ_EN

2 2 2 2 3 2 1 0

DATA_CRC_IRQ

DATA_TIMEOUT_IRQ

RESP_TIMEOUT_IRQ_EN

RESP_TIMEOUT_IRQ

RESP_ERR_IRQ_EN

RESP_ERR_IRQ

SDIO_IRQ

2 2 2 2 7 6 5 4

WORD_LENGTH

32.2.8

SDIO_IRQ_EN

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_SSP_SDRESP1 HW_SSP_SDRESP1

STMP 3700 0x90

235

STMP 3780 Non-Existent

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

32.2.11

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

STMP 3700 0xa0

1 1 1 1 9 8 7 6

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

STMP 3780 Non-Existent

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

RESP2

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_SSP_SDRESP3 HW_SSP_SDRESP3 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

STMP 3700 0xb0

1 1 1 1 9 8 7 6

STMP 3780 Non-Existent

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

RESP3

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

32.2.13

1 1 0 0 1 0 9 8

HW_SSP_SDRESP2 HW_SSP_SDRESP2

32.2.12

1 1 1 1 5 4 3 2

RESP1

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_SSP_STATUS HW_SSP_STATUS

STMP 3700 0xc0

236

STMP 3780 Non-Existent

BUSY

DATA_BUSY

CMD_BUSY

0 0 0 0 3 2 1 0

FIFO_UNDRFLW

FIFO_EMPTY

0 0 0 0 7 6 5 4

FIFO_FULL

FIFO_OVRFLW

RECV_TIMEOUT_STAT

1 1 0 0 1 0 9 8

CEATA_CCS_ERR

TIMEOUT

DATA_CRC_ERR

RESP_ERR

RESP_TIMEOUT

RESP_CRC_ERR

1 1 1 1 5 4 3 2

HW_SSP_DEBUG STMP 3780 Non-Existent 0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

SSP_RXD

SSP_RESP

1 1 0 0 1 0 9 8

SSP_CMD

1 1 1 1 5 4 3 2

MMC_SM

1 1 1 1 9 8 7 6

CMD_OE

2 2 2 2 3 2 1 0

MSTK_SM

DAT_SM

2 2 2 2 7 6 5 4 DATA_STALL

DATACRC_ERR

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

STMP 3700 0x100

CMD_SM

HW_SSP_DEBUG

HW_SSP_VERSION HW_SSP_VERSION

1 1 1 1 9 8 7 6

STMP 3780 Non-Existent

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

STEP

2 2 2 2 3 2 1 0

STMP 3700 0x110

MINOR

2 2 2 2 7 6 5 4 MAJOR

3 3 2 2 1 0 9 8 STMP 3780 STMP 3700

32.2.15

SDIO_IRQ

DMAEND

DMAREQ

1 1 1 1 9 8 7 6

DMATERM

2 2 2 2 3 2 1 0

DMASENSE

CARD_DETECT

SD_PRESENT

MS_PRESENT

2 2 2 2 7 6 5 4

DMA_SM

32.2.14

PRESENT

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

237

0 0 0 0 3 2 1 0

33 33.1

Synchronous Serial Port 1 (SSP1) Summary

The next table summarizes the important aspects of the Sync Serial Port 1 device block and the main differences between the STMP 3700 and the STMP 3780. Name Sync Serial Port 1

33.2

34 34.1

Property Base Address

STMP 3700 Non-Existent

STMP 3780 0x80010000

Programmable Registers

Synchronous Serial Port 2 (SSP2) Summary

The next table summarizes the important aspects of the Sync Serial Port 2 device block and the main differences between the STMP 3700 and the STMP 3780. Name Sync Serial Port 2

34.2

Property Base Address

STMP 3700 Non-Existent

STMP 3780 0x80034000

Programmable Registers

35

SYDMA

35.1

Summary

The next table summarizes the important aspects of the SYDMA device block and the main differences between the STMP 3700 and the STMP 3780. Name SYDMA HW_SYDMA_CTRL HW_SYDMA_RADDR HW_SYDMA_WADDR HW_SYDMA_XFER_COUNT HW_SYDMA_BURST HW_SYDMA_DACK HW_SYDMA_DEBUG0 HW_SYDMA_DEBUG1 HW_SYDMA_DEBUG2 HW_SYDMA_VERSION

Property Base Address Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields

238

STMP 3700 Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent

STMP 3780 0x80026000 0x0 New Field(s) 0x10 New Field(s) 0x20 New Field(s) 0x30 New Field(s) 0x40 New Field(s) 0x50 New Field(s) 0x100 New Field(s) 0x110 New Field(s) 0x120 New Field(s) 0x130 New Field(s)

35.2

Programmable Registers

35.2.1

HW_SYDMA_CTRL HW_SYDMA_CTRL 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

STMP 3780 0x0

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

35.2.2

RUN

COMPLETE_IRQ

ERROR_IRQ

COMPLETE_IRQ_EN

CLKGATE

SFTRST

STMP 3780

STMP 3700

3 3 2 2 1 0 9 8

STMP 3700 Non-Existent

HW_SYDMA_RADDR HW_SYDMA_RADDR 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

STMP 3780 0x10

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

STMP 3780

RSRC_ADDR

STMP 3700

3 3 2 2 1 0 9 8

STMP 3700 Non-Existent

HW_SYDMA_WADDR HW_SYDMA_WADDR 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

STMP 3700 Non-Existent

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

WSRC_ADDR

STMP 3700

3 3 2 2 1 0 9 8

STMP 3780

35.2.3

239

STMP 3780 0x20 1 1 0 0 1 0 9 8

HW_SYDMA_XFER_COUNT

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

HW_SYDMA_BURST HW_SYDMA_BURST 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

STMP 3780 0x40

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

35.2.6

WLEN

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

STMP 3700 Non-Existent

HW_SYDMA_DACK HW_SYDMA_DACK 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

STMP 3700 Non-Existent

1 1 1 1 9 8 7 6

STMP 3780 0x50

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

35.2.7

RLEN

35.2.5

1 1 1 1 5 4 3 2

SIZE

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

STMP 3780 0x30

RDELAY

STMP 3700 Non-Existent

HW_SYDMA_XFER_COUNT

WDELAY

35.2.4

HW_SYDMA_DEBUG0 HW_SYDMA_DEBUG0

STMP 3700 Non-Existent

240

STMP 3780 0x100

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

35.2.8

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

STMP 3700 Non-Existent

1 1 1 1 9 8 7 6

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

1 1 1 1 5 4 3 2

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

STMP 3780 0x110 1 1 0 0 1 0 9 8

DATA

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_SYDMA_DEBUG2 HW_SYDMA_DEBUG2 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

STMP 3700 Non-Existent

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

STMP 3780 0x120 1 1 0 0 1 0 9 8

DATA

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

35.2.10

1 1 0 0 1 0 9 8

HW_SYDMA_DEBUG1 HW_SYDMA_DEBUG1

35.2.9

1 1 1 1 5 4 3 2

DATA

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_SYDMA_VERSION HW_SYDMA_VERSION

STMP 3700 Non-Existent

241

STMP 3780 0x130

36 36.1

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

STEP

MINOR

MAJOR

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

Timers and Rotary Decoder Summary

The next table summarizes the important aspects of the Timers/Rotary Interface device block and the main differences between the STMP 3700 and the STMP 3780.

HW_TIMROT_ROTCTRL

242

TIM0_PRESENT

STATE

DIVIDER

TIM0_PRESENT

STATE

DIVIDER

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

SELECT_A

TIM1_PRESENT TIM1_PRESENT

1 1 1 1 5 4 3 2

SELECT_A

TIM2_PRESENT

1 1 1 1 9 8 7 6

TIM2_PRESENT

2 2 2 2 3 2 1 0

TIM3_PRESENT

CLKGATE CLKGATE

2 2 2 2 7 6 5 4

TIM3_PRESENT

SFTRST SFTRST

ROTARY_PRESENT ROTARY_PRESENT

STMP 3700 STMP 3780

3 3 2 2 1 0 9 8

0x0

SELECT_B

HW_TIMROT_ROTCTRL

SELECT_B

36.2.1

POLARITY_A

Programmable Registers

POLARITY_A

36.2

0xa0

POLARITY_B

HW_TIMROT_VERSION

0x90

POLARITY_B

HW_TIMROT_TIMCOUNT3

0x80

OVERSAMPLE

HW_TIMROT_TIMCTRL3

0x10

OVERSAMPLE

HW_TIMROT_ROTCOUNT

STMP 3700 STMP 3780 0x80068000 0x0

RELATIVE

HW_TIMROT_ROTCTRL

Property Base Address Address Fields Address Fields Address Fields Address Fields Address Fields

RELATIVE

Name Timers/Rotary Interface

36.2.2

HW_TIMROT_ROTCOUNT HW_TIMROT_ROTCOUNT 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

UPDOWN

HW_TIMROT_TIMCOUNT3 HW_TIMROT_TIMCOUNT3

243

0x90

POLARITY

UPDATE

RELOAD

PRESCALE

SELECT

POLARITY

UPDATE

RELOAD

PRESCALE

SELECT

IRQ_EN

1 1 0 0 1 0 9 8 DUTY_VALID

IRQ

1 1 1 1 5 4 3 2

IRQ_EN

1 1 1 1 9 8 7 6

IRQ

STMP 3780

2 2 2 2 3 2 1 0

TEST_SIGNAL TEST_SIGNAL

2 2 2 2 7 6 5 4

STMP 3700

3 3 2 2 1 0 9 8

0x80

DUTY_CYCLE DUTY_CYCLE

HW_TIMROT_TIMCTRL3

36.2.4

0 0 0 0 3 2 1 0

HW_TIMROT_TIMCTRL3

DUTY_VALID

36.2.3

0 0 0 0 7 6 5 4 UPDOWN

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

0x10

2 2 2 2 7 6 5 4

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

HIGH_FIXED_COUNT

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

0xa0

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

STEP

MINOR

STEP

MINOR

MAJOR

2 2 2 2 7 6 5 4

MAJOR

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

37.1

0 0 0 0 7 6 5 4

HW_TIMROT_VERSION HW_TIMROT_VERSION

37

1 1 0 0 1 0 9 8

HIGH_FIXED_COUNT

STMP 3700 STMP 3780 36.2.5

2 2 2 2 3 2 1 0 LOW_RUNNING_COUNT LOW_RUNNING_COUNT

3 3 2 2 1 0 9 8

Video DAC Summary

The next table summarizes the important aspects of the TV Encoder device block and the main differences between the STMP 3700 and the STMP 3780. Name TV Encoder HW_TVENC_CTRL HW_TVENC_CONFIG HW_TVENC_FILTCTRL HW_TVENC_SYNCOFFSET HW_TVENC_HTIMINGSYNC0

Property Base Address Address Fields Address Fields Address Fields Address Fields Address Fields 244

STMP 3700 Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent

STMP 3780 0x80038000 0x0 New Field(s) 0x10 New Field(s) 0x20 New Field(s) 0x30 New Field(s) 0x40 New Field(s)

Name HW_TVENC_HTIMINGSYNC1 HW_TVENC_HTIMINGACTIVE HW_TVENC_HTIMINGBURST0 HW_TVENC_HTIMINGBURST1 HW_TVENC_VTIMING0 HW_TVENC_VTIMING1 HW_TVENC_MISC HW_TVENC_COLORSUB0 HW_TVENC_COLORSUB1 HW_TVENC_COPYPROTECT HW_TVENC_CLOSEDCAPTION HW_TVENC_COLORBURST HW_TVENC_MACROVISION0 HW_TVENC_MACROVISION1 HW_TVENC_MACROVISION2 HW_TVENC_MACROVISION3 HW_TVENC_MACROVISION4 HW_TVENC_DACCTRL HW_TVENC_DACSTATUS HW_TVENC_VDACTEST HW_TVENC_VERSION

37.2

Programmable Registers

37.2.1

HW_TVENC_CTRL HW_TVENC_CTRL

Property Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields

STMP 3700 Non-Existent

245

STMP 3700 Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent Non-Existent

STMP 3780 0x0

STMP 3780 0x50 New Field(s) 0x60 New Field(s) 0x70 New Field(s) 0x80 New Field(s) 0x90 New Field(s) 0xa0 New Field(s) 0xb0 New Field(s) 0xc0 New Field(s) 0xd0 New Field(s) 0xe0 New Field(s) 0xf0 New Field(s) 0x140 New Field(s) 0x150 New Field(s) 0x160 New Field(s) 0x170 New Field(s) 0x180 New Field(s) 0x190 New Field(s) 0x1a0 New Field(s) 0x1b0 New Field(s) 0x1c0 New Field(s) 0x1d0 New Field(s)

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

37.2.2

DAC_MUX_MODE

DAC_DATA_FIFO_RST

DAC_FIFO_NO_READ

DAC_FIFO_NO_WRITE

TVENC_COMPONENT_PRESENT

TVENC_SVIDEO_PRESENT

TVENC_COMPOSITE_PRESENT

TVENC_MACROVISION_PRESENT

CLKGATE

SFTRST

STMP 3780

STMP 3700

3 3 2 2 1 0 9 8

HW_TVENC_CONFIG HW_TVENC_CONFIG 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

STMP 3780 0x10

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

37.2.3

HW_TVENC_FILTCTRL HW_TVENC_FILTCTRL

STMP 3700 Non-Existent

246

STMP 3780 0x20

ENCD_MODE

SYNC_MODE

VSYNC_PHS

HSYNC_PHS

FSYNC_PHS

FSYNC_ENBL

CLK_PHS

CGAIN

YGAIN_SEL

COLOR_BAR_EN

NO_PED

PAL_SHAPE

ADD_YPBPR_PED

YDEL_ADJ

DEFAULT_PICFORM

STMP 3780

STMP 3700

3 3 2 2 1 0 9 8

STMP 3700 Non-Existent

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

HW_TVENC_SYNCOFFSET 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

YS_GAINSEL

YS_GAINSGN

COEFSEL_CLPF

YLPF_COEFSEL

STMP 3780 0x30

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

HW_TVENC_HTIMINGSYNC0 HW_TVENC_HTIMINGSYNC0 2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

STMP 3700 Non-Existent 1 1 1 1 5 4 3 2

STMP 3780 0x40 1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

SYNC_END

SYNC_STRT

2 2 2 2 7 6 5 4

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

37.2.6

STMP 3700 Non-Existent

VSO

HSO

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

37.2.5

SEL_YSHARP

SEL_CLPF

SEL_YLPF

HW_TVENC_SYNCOFFSET

HLC

37.2.4

YD_OFFSETSEL

STMP 3780

YSHARP_BW

STMP 3700

3 3 2 2 1 0 9 8

HW_TVENC_HTIMINGSYNC1 HW_TVENC_HTIMINGSYNC1

247

STMP 3700 Non-Existent

STMP 3780 0x50

0 0 0 0 3 2 1 0

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

37.2.7

SYNC_SREND

STMP 3780

SYNC_EQEND

STMP 3700

3 3 2 2 1 0 9 8

HW_TVENC_HTIMINGACTIVE HW_TVENC_HTIMINGACTIVE 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

STMP 3780 0x60 1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

37.2.8

ACTV_STRT

ACTV_END

STMP 3780

STMP 3700

3 3 2 2 1 0 9 8

STMP 3700 Non-Existent

HW_TVENC_HTIMINGBURST0 HW_TVENC_HTIMINGBURST0 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

STMP 3780 0x70 1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

37.2.9

NBRST_STRT

STMP 3780

WBRST_STRT

STMP 3700

3 3 2 2 1 0 9 8

STMP 3700 Non-Existent

HW_TVENC_HTIMINGBURST1 HW_TVENC_HTIMINGBURST1

248

STMP 3700 Non-Existent

STMP 3780 0x80

0 0 0 0 3 2 1 0

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

37.2.10

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

BRST_END

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_TVENC_VTIMING0 HW_TVENC_VTIMING0 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

37.2.11

VSTRT_SUBPH

VSTRT_ACTV

STMP 3780

VSTRT_PREEQ

STMP 3700

3 3 2 2 1 0 9 8

STMP 3780 0x90

STMP 3700 Non-Existent

HW_TVENC_VTIMING1 HW_TVENC_VTIMING1 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

STMP 3780 0xa0

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

37.2.12

LAST_FLD_LN

VSTRT_SERRA

VSTRT_POSTEQ

STMP 3780

STMP 3700

3 3 2 2 1 0 9 8

STMP 3700 Non-Existent

HW_TVENC_MISC HW_TVENC_MISC

STMP 3700 Non-Existent

249

STMP 3780 0xb0

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

STMP 3700 Non-Existent

STMP 3780 0xc0

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

STMP 3700 Non-Existent

STMP 3780 0xd0

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

1 1 1 1 9 8 7 6

Y_BLANK_CTRL

CS_INVERT_CTRL

AGC_LVL_CTRL

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

PHASE_INC

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_TVENC_COLORSUB1 HW_TVENC_COLORSUB1 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

STMP 3780

PHASE_OFFSET

STMP 3700

3 3 2 2 1 0 9 8

37.2.15

BRUCHB

HW_TVENC_COLORSUB0 HW_TVENC_COLORSUB0

37.2.14

FSC_PHASE_RST

NTSC_LN_CNT

LPF_RST_OFF

STMP 3780 37.2.13

PAL_FSC_PHASE_ALT

STMP 3700

3 3 2 2 1 0 9 8

HW_TVENC_COPYPROTECT HW_TVENC_COPYPROTECT

250

STMP 3700 Non-Existent

STMP 3780 0xe0

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

HW_TVENC_CLOSEDCAPTION 2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

CC_ENBL

1 1 1 1 5 4 3 2

WSS_CGMS_DATA

STMP 3780 0xf0 1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

HW_TVENC_COLORBURST HW_TVENC_COLORBURST 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

STMP 3700 Non-Existent 1 1 1 1 5 4 3 2

STMP 3780 0x140 1 1 0 0 1 0 9 8

PBA

NBA

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

37.2.18

STMP 3700 Non-Existent

CC_FILL

2 2 2 2 7 6 5 4

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

37.2.17

CGMS_ENBL

HW_TVENC_CLOSEDCAPTION

CC_DATA

37.2.16

WSS_ENBL

STMP 3780

STMP 3700

3 3 2 2 1 0 9 8

HW_TVENC_MACROVISION0 HW_TVENC_MACROVISION0

251

STMP 3700 Non-Existent

STMP 3780 0x150

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

37.2.19

1 1 1 1 5 4 3 2

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

STMP 3700 Non-Existent

1 1 1 1 9 8 7 6

0 0 0 0 3 2 1 0

1 1 1 1 5 4 3 2

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

STMP 3780 0x160 1 1 0 0 1 0 9 8

DATA

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_TVENC_MACROVISION2 STMP 3700 Non-Existent

HW_TVENC_MACROVISION2 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

STMP 3780 0x170 1 1 0 0 1 0 9 8

DATA

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

37.2.21

0 0 0 0 7 6 5 4

HW_TVENC_MACROVISION1 HW_TVENC_MACROVISION1

37.2.20

1 1 0 0 1 0 9 8

DATA

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_TVENC_MACROVISION3 HW_TVENC_MACROVISION3

252

STMP 3700 Non-Existent

STMP 3780 0x180

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

HW_TVENC_MACROVISION4

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

DATA

MACV_TST

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

STMP 3780 0x190

STMP 3700 Non-Existent

HW_TVENC_MACROVISION4

HW_TVENC_DACCTRL

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

37.2.24

HW_TVENC_DACSTATUS HW_TVENC_DACSTATUS

STMP 3700 Non-Existent

253

STMP 3780 0x1b0

CASC_ADJ

HALF_CURRENT

RVAL

DUMP_TOVDD1

WELL_TOVDD

PWRUP1

BYPASS_ACT_CASCODE

SELECT_CLK

INVERT_CLK

GAINUP

GAINDN

JACK_DIS_ADJ

DISABLE_GND_DETECT

TEST1

JACK1_DET_EN

TEST2

JACK1_DIS_DET_EN

TEST3

STMP 3780

STMP 3700

3 3 2 2 1 0 9 8

STMP 3780 0x1a0

STMP 3700 Non-Existent

HW_TVENC_DACCTRL

NO_INTERNAL_TERM

37.2.23

1 1 0 0 1 0 9 8

LOWER_SIGNAL

37.2.22

1 1 1 1 5 4 3 2

DATA

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

37.2.25

ENIRQ_JACK

JACK1_DET_IRQ

JACK1_DIS_DET_IRQ

JACK1_GROUNDED

STMP 3780

JACK1_DET_STATUS

STMP 3700

3 3 2 2 1 0 9 8

HW_TVENC_VDACTEST STMP 3700 Non-Existent

HW_TVENC_VDACTEST 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

DATA

TEST_FIFO_FULL

BYPASS_PIX_INT_DROOP

HW_TVENC_VERSION HW_TVENC_VERSION

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

STMP 3780 0x1d0 1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

STEP

2 2 2 2 3 2 1 0

STMP 3700 Non-Existent

MINOR

2 2 2 2 7 6 5 4

MAJOR

3 3 2 2 1 0 9 8 STMP 3780 STMP 3700

37.2.26

BYPASS_PIX_INT

STMP 3780

ENABLE_PIX_INT_GAIN

STMP 3700

3 3 2 2 1 0 9 8

STMP 3780 0x1c0

254

0 0 0 0 3 2 1 0

38 38.1

Application UART Summary

The next table summarizes the important aspects of the Application UART device block and the main differences between the STMP 3700 and the STMP 3780. Name Application UART HW_UARTAPP_CTRL0 HW_UARTAPP_CTRL1 HW_UARTAPP_CTRL2 HW_UARTAPP_LINECTRL HW_UARTAPP_LINECTRL2 HW_UARTAPP_INTR HW_UARTAPP_DATA HW_UARTAPP_STAT HW_UARTAPP_DEBUG HW_UARTAPP_VERSION

Programmable Registers

38.2.1

HW_UARTAPP_CTRL0 HW_UARTAPP_CTRL0

38.2.2

2 2 2 2 3 2 1 0

STMP 3700 0x0

1 1 1 1 9 8 7 6

STMP 3780 Non-Existent

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

RXTIMEOUT

2 2 2 2 7 6 5 4 RXTO_ENABLE

RX_SOURCE

RUN

CLKGATE

SFTRST

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

STMP 3700 STMP 3780 0x8006c000 0x0 Non-Existent New Field(s) 0x10 Non-Existent New Field(s) 0x20 Non-Existent New Field(s) 0x30 Non-Existent New Field(s) 0x40 Non-Existent New Field(s) 0x50 Non-Existent New Field(s) 0x60 Non-Existent New Field(s) 0x70 Non-Existent New Field(s) 0x80 Non-Existent New Field(s) 0x90 Non-Existent New Field(s)

HW_UARTAPP_CTRL1 HW_UARTAPP_CTRL1

0 0 0 0 7 6 5 4 XFER_COUNT

38.2

Property Base Address Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields

STMP 3700 0x10

255

STMP 3780 Non-Existent

0 0 0 0 3 2 1 0

1 1 1 1 9 8 7 6

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

UARTEN

SIREN

SIRLP

USE_LCR2

LBE

TXE

RXE

1 1 0 0 1 0 9 8

RTS

CTSEN

OUT1

1 1 1 1 5 4 3 2

RTSEN

1 1 1 1 9 8 7 6

STMP 3780 Non-Existent

DTR

STMP 3700 0x20

TXIFLSEL

RXIFLSEL

2 2 2 2 3 2 1 0

RXDMAE

TXDMAE

DMAONERR

2 2 2 2 7 6 5 4 RTS_SEMAPHORE

INVERT_RX

INVERT_TX

INVERT_CTS

INVERT_RTS

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_UARTAPP_LINECTRL

HW_UARTAPP_LINECTRL2 HW_UARTAPP_LINECTRL2

256

STMP 3700 0x40

STMP 3780 Non-Existent

BRK

PEN

0 0 0 0 3 2 1 0

EPS

0 0 0 0 7 6 5 4

STP2

1 1 0 0 1 0 9 8

FEN

1 1 1 1 5 4 3 2

WLEN

1 1 1 1 9 8 7 6

STMP 3780 Non-Existent

BAUD_DIVFRAC

2 2 2 2 3 2 1 0 BAUD_DIVINT

2 2 2 2 7 6 5 4

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

STMP 3700 0x30

SPS

HW_UARTAPP_LINECTRL

38.2.5

1 1 0 0 1 0 9 8

HW_UARTAPP_CTRL2 HW_UARTAPP_CTRL2

38.2.4

1 1 1 1 5 4 3 2

XFER_COUNT

2 2 2 2 3 2 1 0

OUT2

38.2.3

2 2 2 2 7 6 5 4

RUN

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

PEN

EPS

0 0 0 0 3 2 1 0

STP2

FEN

0 0 0 0 7 6 5 4

RIMIS

CTSMIS

DCDMIS

0 0 0 0 3 2 1 0 DSRMIS

RXIS

TXIS

RTIS

0 0 0 0 7 6 5 4

FEIS

OEIS

1 1 0 0 1 0 9 8

PEIS

1 1 1 1 5 4 3 2

RIMIEN

DCDMIEN

CTSMIEN

STMP 3780 Non-Existent

BEIS

STMP 3700 0x50

1 1 1 1 9 8 7 6 DSRMIEN

RXIEN

TXIEN

RTIEN

FEIEN

2 2 2 2 3 2 1 0

PEIEN

BEIEN

2 2 2 2 7 6 5 4

OEIEN

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_UARTAPP_DATA HW_UARTAPP_DATA 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

STMP 3700 0x60

1 1 1 1 9 8 7 6

STMP 3780 Non-Existent

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

DATA

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

38.2.8

1 1 0 0 1 0 9 8

HW_UARTAPP_INTR HW_UARTAPP_INTR

38.2.7

1 1 1 1 5 4 3 2

WLEN

1 1 1 1 9 8 7 6

SPS

STMP 3780 STMP 3700 38.2.6

2 2 2 2 3 2 1 0

BAUD_DIVFRAC

2 2 2 2 7 6 5 4 BAUD_DIVINT

3 3 2 2 1 0 9 8

HW_UARTAPP_STAT HW_UARTAPP_STAT

STMP 3700 0x70

257

STMP 3780 Non-Existent

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

1 1 0 0 1 0 9 8

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

STMP 3780 STMP 3700 38.2.10

RXDMARQ

1 1 1 1 5 4 3 2

TXDMARQ

1 1 1 1 9 8 7 6

RXCMDEND

2 2 2 2 3 2 1 0

TXCMDEND

2 2 2 2 7 6 5 4

STMP 3780 Non-Existent

RXDMARUN

STMP 3700 0x80

TXDMARUN

3 3 2 2 1 0 9 8

HW_UARTAPP_VERSION HW_UARTAPP_VERSION 1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

STMP 3780 Non-Existent 1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

STEP

2 2 2 2 3 2 1 0

STMP 3700 0x90

MINOR

2 2 2 2 7 6 5 4 MAJOR

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

39.1

0 0 0 0 3 2 1 0

HW_UARTAPP_DEBUG HW_UARTAPP_DEBUG

39

0 0 0 0 7 6 5 4

RXCOUNT

1 1 1 1 5 4 3 2

FERR

PERR

BERR

1 1 1 1 9 8 7 6

OERR

2 2 2 2 3 2 1 0 RXBYTE_INVALID

RXFE

TXFF

RXFF

TXFE

CTS

BUSY

HISPEED

2 2 2 2 7 6 5 4

PRESENT

STMP 3780 STMP 3700 38.2.9

3 3 2 2 1 0 9 8

Application UART 1 Summary

The next table summarizes the important aspects of the Application UART 1 device block and the main differences between the STMP 3700 and the STMP 3780.

258

Name Application UART 1

39.2

40 40.1

Property Base Address

STMP 3700 Non-Existent

STMP 3780 0x8006c000

Programmable Registers

Application UART 2 Summary

The next table summarizes the important aspects of the Application UART 2 device block and the main differences between the STMP 3700 and the STMP 3780. Name Application UART 2

40.2

41 41.1

Property Base Address

STMP 3700 Non-Existent

STMP 3780 0x8006e000

Programmable Registers

Debug UART Summary

The next table summarizes the important aspects of the Debug UART device block and the main differences between the STMP 3700 and the STMP 3780. Name Debug UART HW_UARTDBGDR HW_UARTDBGRSR_ECR HW_UARTDBGFR HW_UARTDBGILPR HW_UARTDBGIBRD HW_UARTDBGFBRD HW_UARTDBGLCR_H HW_UARTDBGCR HW_UARTDBGIFLS HW_UARTDBGIMSC HW_UARTDBGRIS HW_UARTDBGMIS HW_UARTDBGICR HW_UARTDBGDMACR

Property Base Address Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields

259

STMP 3700 STMP 3780 0x80070000 0x0 0x4 0x18 0x20 0x24 0x28 0x2c 0x30 0x34 0x38 0x3c 0x40 0x44 0x48

0 0 0 0 3 2 1 0

DATA

FE

RESERVED

0 0 0 0 7 6 5 4

HW_UARTDBGRSR_ECR

FE

STMP 3700 STMP 3780

FE

0 0 0 0 7 6 5 4

PE

1 1 0 0 1 0 9 8

0 0 0 0 3 2 1 0

BE

0 0 0 0 7 6 5 4

PE

1 1 0 0 1 0 9 8

BE

1 1 1 1 5 4 3 2

OE

1 1 1 1 9 8 7 6

OE

2 2 2 2 3 2 1 0

EC

2 2 2 2 7 6 5 4

UNAVAILABLE UNAVAILABLE

3 3 2 2 1 0 9 8

0x4

EC

HW_UARTDBGRSR_ECR

HW_UARTDBGFR

260

RXFF

TXFF

RXFE

BUSY

DCD

DSR

CTS

RXFF

TXFF

RXFE

BUSY

DCD

DSR

CTS

0 0 0 0 3 2 1 0

RI

RESERVED

1 1 1 1 5 4 3 2

TXFE

1 1 1 1 9 8 7 6

RI

2 2 2 2 3 2 1 0

RESERVED

2 2 2 2 7 6 5 4

UNAVAILABLE UNAVAILABLE

STMP 3700

3 3 2 2 1 0 9 8

0x18

TXFE

HW_UARTDBGFR

STMP 3780

41.2.3

1 1 0 0 1 0 9 8

FE

1 1 1 1 5 4 3 2

PE

1 1 1 1 9 8 7 6

RESERVED

STMP 3700 STMP 3780 41.2.2

2 2 2 2 3 2 1 0

PE

2 2 2 2 7 6 5 4

UNAVAILABLE UNAVAILABLE

3 3 2 2 1 0 9 8

0x0

DATA

HW_UARTDBGDR

OE

HW_UARTDBGDR

BE

41.2.1

BE

Programmable Registers

OE

41.2

HW_UARTDBGILPR HW_UARTDBGILPR 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 5 4 3 2

0 0 0 0 7 6 5 4

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

ILPDVSR

0 0 0 0 3 2 1 0

HW_UARTDBGIBRD HW_UARTDBGIBRD 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

0x24

1 1 1 1 5 4 3 2

BAUD_DIVINT BAUD_DIVINT

STMP 3780

STMP 3700

UNAVAILABLE UNAVAILABLE

3 3 2 2 1 0 9 8

HW_UARTDBGFBRD HW_UARTDBGFBRD

0x28

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

RESERVED

RESERVED

1 1 1 1 9 8 7 6 UNAVAILABLE

2 2 2 2 3 2 1 0

UNAVAILABLE

2 2 2 2 7 6 5 4

STMP 3700

3 3 2 2 1 0 9 8

STMP 3780

41.2.6

1 1 0 0 1 0 9 8

ILPDVSR

STMP 3700 STMP 3780 41.2.5

1 1 1 1 9 8 7 6 UNAVAILABLE UNAVAILABLE

3 3 2 2 1 0 9 8

0x20

261

BAUD_DIVFRAC BAUD_DIVFRAC

41.2.4

HW_UARTDBGLCR_H

BRK BRK

PEN

EPS

STP2 STP2

PEN

FEN FEN

0 0 0 0 3 2 1 0

WLEN

0 0 0 0 7 6 5 4

HW_UARTDBGCR

TXE

LBE

RESERVED

TXE

LBE

RESERVED

UARTEN

RXE RXE

UARTEN

DTR DTR

SIREN

RTS RTS

SIRLP

OUT1 OUT1

0 0 0 0 3 2 1 0

SIREN

OUT2

0 0 0 0 7 6 5 4

RTSEN

1 1 0 0 1 0 9 8

RTSEN

STMP 3700 STMP 3780

1 1 1 1 5 4 3 2

OUT2

1 1 1 1 9 8 7 6

CTSEN

2 2 2 2 3 2 1 0

CTSEN

2 2 2 2 7 6 5 4

UNAVAILABLE UNAVAILABLE

3 3 2 2 1 0 9 8

0x30

SIRLP

HW_UARTDBGCR

HW_UARTDBGIFLS

262

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0 TXIFLSEL

1 1 0 0 1 0 9 8

TXIFLSEL

1 1 1 1 5 4 3 2

RXIFLSEL

1 1 1 1 9 8 7 6

RXIFLSEL

2 2 2 2 3 2 1 0

RESERVED

2 2 2 2 7 6 5 4

UNAVAILABLE UNAVAILABLE

STMP 3700

3 3 2 2 1 0 9 8

0x34

RESERVED

HW_UARTDBGIFLS

STMP 3780

41.2.9

1 1 0 0 1 0 9 8

WLEN

1 1 1 1 5 4 3 2

SPS

1 1 1 1 9 8 7 6

SPS

STMP 3700 STMP 3780 41.2.8

2 2 2 2 3 2 1 0

RESERVED

2 2 2 2 7 6 5 4

UNAVAILABLE UNAVAILABLE

3 3 2 2 1 0 9 8

0x2c

EPS

HW_UARTDBGLCR_H

RESERVED

41.2.7

263

PEMIS

FEMIS

RTMIS

TXMIS

RXMIS

DSRMMIS

DCDMMIS

CTSMMIS

RIMMIS

PEMIS

FEMIS

RTMIS

TXMIS

RXMIS

DSRMMIS

DCDMMIS

CTSMMIS

RIMMIS

HW_UARTDBGMIS

BEMIS

1 1 1 1 9 8 7 6 1 1 1 1 5 4 3 2 FERIS RTRIS TXRIS RXRIS DSRRMIS

FERIS RTRIS TXRIS RXRIS DSRRMIS

1 1 0 0 1 0 9 8 0 0 0 0 7 6 5 4 RIRMIS

RIRMIS

CTSRMIS

0 0 0 0 7 6 5 4

CTSRMIS

1 1 0 0 1 0 9 8

RIMIM

CTSMIM

RIMIM

CTSMIM

DCDMIM

DSRMIM

DSRMIM DCDMIM

RXIM

RTIM

RTIM

TXIM

FEIM

FEIM TXIM

PEIM

PEIM

RXIM

BEIM

BEIM

0 0 0 0 7 6 5 4

DCDRMIS

PERIS

PERIS

OEIM

RESERVED

OEIM

RESERVED

1 1 0 0 1 0 9 8

DCDRMIS

BERIS

BERIS

1 1 1 1 5 4 3 2

OERIS

HW_UARTDBGRIS

BEMIS

2 2 2 2 3 2 1 0 1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

OERIS

RESERVED

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

OEMIS

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

OEMIS

3 3 2 2 1 0 9 8 2 2 2 2 7 6 5 4

RESERVED

3 3 2 2 1 0 9 8 2 2 2 2 7 6 5 4

RESERVED

STMP 3700

UNAVAILABLE UNAVAILABLE

STMP 3780

HW_UARTDBGIMSC

RESERVED

STMP 3700

UNAVAILABLE UNAVAILABLE

STMP 3780 3 3 2 2 1 0 9 8

UNAVAILABLE UNAVAILABLE

41.2.12

STMP 3700

41.2.11

STMP 3780

41.2.10 HW_UARTDBGIMSC 0x38 0 0 0 0 3 2 1 0

HW_UARTDBGRIS 0x3c

0 0 0 0 3 2 1 0

HW_UARTDBGMIS 0x40

0 0 0 0 3 2 1 0

HW_UARTDBGICR

RIMIC

DSRMIC DSRMIC

RIMIC

RXIC RXIC

CTSMIC

TXIC TXIC

DCDMIC

RTIC RTIC

CTSMIC

FEIC

DCDMIC

PEIC

FEIC

RESERVED

0 0 0 0 3 2 1 0

RXDMAE RXDMAE

0 0 0 0 3 2 1 0

TXDMAE

0 0 0 0 7 6 5 4

DMAONERR

STMP 3700 STMP 3780

1 1 0 0 1 0 9 8

TXDMAE

1 1 1 1 5 4 3 2

DMAONERR

1 1 1 1 9 8 7 6

RESERVED

2 2 2 2 3 2 1 0

0x48

RESERVED

2 2 2 2 7 6 5 4

UNAVAILABLE UNAVAILABLE

3 3 2 2 1 0 9 8

42.1

0 0 0 0 7 6 5 4

HW_UARTDBGDMACR HW_UARTDBGDMACR

42

1 1 0 0 1 0 9 8

PEIC

1 1 1 1 5 4 3 2

BEIC

1 1 1 1 9 8 7 6

RESERVED

STMP 3700 STMP 3780 41.2.14

2 2 2 2 3 2 1 0

BEIC

2 2 2 2 7 6 5 4

UNAVAILABLE UNAVAILABLE

3 3 2 2 1 0 9 8

0x44

OEIC

HW_UARTDBGICR

OEIC

41.2.13

USB High-Speed Host/Device Controller Summary

The next table summarizes the important aspects of the USB Controller device block and the main differences between the STMP 3700 and the STMP 3780. Name USB Controller HW_USBCTRL_ID HW_USBCTRL_HWGENERAL HW_USBCTRL_GENERAL HW_USBCTRL_HWHOST HW_USBCTRL_HOST

Property Base Address Address Fields Address Fields Address Fields Address Fields Address Fields

264

STMP 3700 STMP 3780 0x80080000 0x0 Incompatible Field(s) Incompatible Field(s) Non-Existent 0x4 New Field(s) 0x4 Non-Existent New Field(s) Non-Existent 0x8 New Field(s) 0x8 Non-Existent New Field(s)

Name HW_USBCTRL_DEVICE HW_USBCTRL_HWDEVICE HW_USBCTRL_TXBUF HW_USBCTRL_HWTXBUF HW_USBCTRL_RXBUF HW_USBCTRL_HWRXBUF HW_USBCTRL_TTTXBUF HW_USBCTRL_TTRXBUF HW_USBCTRL_GPTIMER0LD HW_USBCTRL_GPTIMER0CTRL HW_USBCTRL_GPTIMER1LD HW_USBCTRL_GPTIMER1CTRL HW_USBCTRL_SBUSCFG HW_USBCTRL_CAPLENGTH HW_USBCTRL_HCSPARAMS HW_USBCTRL_HCCPARAMS HW_USBCTRL_DCIVERSION HW_USBCTRL_DCCPARAMS HW_USBCTRL_USBCMD HW_USBCTRL_USBSTS HW_USBCTRL_USBINTR HW_USBCTRL_FRINDEX HW_USBCTRL_CTRLDSSEGMENT HW_USBCTRL_PERIODICLISTBASE HW_USBCTRL_DEVICEADDR HW_USBCTRL_ASYNCLISTADDR HW_USBCTRL_ENDPOINTLISTADDR HW_USBCTRL_TTCTRL

Property Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address 265

STMP 3700 0xc New Field(s) Non-Existent

STMP 3780 Non-Existent 0xc New Field(s) Non-Existent

0x10 New Field(s) Non-Existent

0x10 New Field(s) Non-Existent

0x14 New Field(s) Non-Existent

0x14 New Field(s) Non-Existent

0x18 New Field(s) 0x1c New Field(s) Non-Existent

Non-Existent 0x80 New Field(s) 0x84 New Field(s) 0x88 New Field(s) 0x8c New Field(s) 0x90 New Field(s)

Non-Existent Non-Existent Non-Existent Non-Existent 0x100 New Field(s)

New Field(s) 0x104

New Field(s)

New Field(s) 0x108

New Field(s)

New Field(s) 0x120

New Field(s)

New Field(s) 0x124 0x140

New Field(s)

New Field(s) 0x144 New Field(s) 0x148 New Field(s) 0x14c

New Field(s) 0x150 New Field(s)

New Field(s) Non-Existent 0x154

New Field(s) Non-Existent

New Field(s) 0x154 New Field(s) 0x158

Non-Existent

0x158 New Field(s) 0x15c

Name HW_USBCTRL_BURSTSIZE HW_USBCTRL_TXFILLTUNING HW_USBCTRL_TXTTFILLTUNING HW_USBCTRL_IC_USB HW_USBCTRL_ULPI HW_USBCTRL_VFRAME HW_USBCTRL_ENDPTNAK HW_USBCTRL_EPNAK HW_USBCTRL_ENDPTNAKEN HW_USBCTRL_EPNAKEN HW_USBCTRL_CONFIGFLAG HW_USBCTRL_PORTSC1 HW_USBCTRL_OTGSC HW_USBCTRL_USBMODE HW_USBCTRL_ENDPTSETUPSTAT HW_USBCTRL_ENDPTPRIME HW_USBCTRL_ENDPTFLUSH HW_USBCTRL_ENDPTSTAT HW_USBCTRL_ENDPTSTATUS HW_USBCTRL_ENDPTCOMPLETE HW_USBCTRL_ENDPTCTRL0

42.2

Programmable Registers

42.2.1

HW_USBCTRL_ID

Property Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields

HW_USBCTRL_ID

266

STMP 3700

STMP 3780 0x160

New Field(s)

New Field(s) 0x164 Incompatible Field(s) Incompatible Field(s) 0x168 Non-Existent New Field(s) Non-Existent 0x16c New Field(s) 0x170 New Field(s) New Field(s) 0x174 Non-Existent New Field(s) Non-Existent 0x178 New Field(s) 0x178 Non-Existent New Field(s) Non-Existent 0x17c New Field(s) 0x17c Non-Existent New Field(s) 0x180 Non-Existent New Field(s) 0x184 New Field(s) 0x1a4 0x1a8 New Field(s) 0x1ac New Field(s)

New Field(s) 0x1b0 Incompatible Field(s) Incompatible Field(s) 0x1b4 Incompatible Field(s) Incompatible Field(s) Non-Existent 0x1b8 New Field(s) 0x1b8 Non-Existent New Field(s) 0x1bc Incompatible Field(s) Incompatible Field(s) Non-Existent 0x1c0 New Field(s)

0x0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

0 0 0 0 3 2 1 0

ID ID

NID

REVISION

VERSION

TAG

SM

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

RT

1 1 1 1 5 4 3 2

CLKC

1 1 1 1 9 8 7 6

BWT

2 2 2 2 3 2 1 0

PHYW

2 2 2 2 7 6 5 4

STMP 3780 0x4

PHYM

STMP 3700 Non-Existent

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_USBCTRL_GENERAL

1 1 1 1 5 4 3 2

SM

1 1 0 0 1 0 9 8

HW_USBCTRL_HWHOST HW_USBCTRL_HWHOST

STMP 3700 Non-Existent

267

STMP 3780 0x8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

RT

1 1 1 1 9 8 7 6

CLKC

2 2 2 2 3 2 1 0

STMP 3780 Non-Existent

BWT

2 2 2 2 7 6 5 4

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

STMP 3700 0x4

PHYW

HW_USBCTRL_GENERAL

42.2.4

0 0 0 0 7 6 5 4

HW_USBCTRL_HWGENERAL HW_USBCTRL_HWGENERAL

42.2.3

1 1 0 0 1 0 9 8

ID_N

2 2 2 2 3 2 1 0

REV

2 2 2 2 7 6 5 4

PHYM

42.2.2

CIVERSION

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

1 1 0 0 1 0 9 8

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

TTASY

2 2 2 2 3 2 1 0

STMP 3700 0x8

1 1 1 1 9 8 7 6

STMP 3780 Non-Existent

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

TTASY

HC

2 2 2 2 7 6 5 4

TTPER

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_USBCTRL_DEVICE

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

DEVEP

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

STMP 3780 Non-Existent

HW_USBCTRL_HWDEVICE HW_USBCTRL_HWDEVICE

268

STMP 3700 Non-Existent

STMP 3780 0xc

DC

STMP 3700 0xc

HW_USBCTRL_DEVICE

42.2.7

0 0 0 0 7 6 5 4

HW_USBCTRL_HOST HW_USBCTRL_HOST

42.2.6

1 1 1 1 5 4 3 2

HC

1 1 1 1 9 8 7 6

NPORT

2 2 2 2 3 2 1 0

NPORT

42.2.5

2 2 2 2 7 6 5 4

TTPER

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

DEVEP

HW_USBCTRL_TXBUF STMP 3700 0x10

HW_USBCTRL_TXBUF

42.2.9

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

TXADD

TXCHANADD

2 2 2 2 7 6 5 4

TXLCR

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

STMP 3780 Non-Existent 0 0 0 0 3 2 1 0 TXBURST

42.2.8

0 0 0 0 3 2 1 0

HW_USBCTRL_HWTXBUF HW_USBCTRL_HWTXBUF 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

STMP 3700 Non-Existent

STMP 3780 0x10

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

HW_USBCTRL_RXBUF HW_USBCTRL_RXBUF

STMP 3700 0x14

269

STMP 3780 Non-Existent

TXBURST

TXADD

TXCHANADD

TXLCR

STMP 3780

STMP 3700

3 3 2 2 1 0 9 8

42.2.10

DC

2 2 2 2 7 6 5 4

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

RXADD

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

STMP 3700 Non-Existent

STMP 3780 0x14

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

1 1 1 1 9 8 7 6

0 0 0 0 7 6 5 4

RXADD

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

0 0 0 0 3 2 1 0

HW_USBCTRL_TTTXBUF HW_USBCTRL_TTTXBUF 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

STMP 3700 0x18

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

STMP 3780 Non-Existent 1 1 0 0 1 0 9 8

TTTXBUF

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

42.2.13

0 0 0 0 3 2 1 0

HW_USBCTRL_HWRXBUF HW_USBCTRL_HWRXBUF

42.2.12

0 0 0 0 7 6 5 4

RXBURST

42.2.11

1 1 0 0 1 0 9 8

RXBURST

2 2 2 2 7 6 5 4

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_USBCTRL_TTRXBUF HW_USBCTRL_TTRXBUF

STMP 3700 0x1c

270

STMP 3780 Non-Existent

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

42.2.14

1 1 1 1 5 4 3 2

0 0 0 0 3 2 1 0

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

STMP 3780 0x80

STMP 3700 Non-Existent 1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

GPTLD

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_USBCTRL_GPTIMER0CTRL HW_USBCTRL_GPTIMER0CTRL 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

STMP 3700 Non-Existent 1 1 1 1 5 4 3 2

STMP 3780 0x84

1 1 0 0 1 0 9 8

GPTCNT

GPTMODE

GPTRST

GPTRUN

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

42.2.16

0 0 0 0 7 6 5 4

HW_USBCTRL_GPTIMER0LD HW_USBCTRL_GPTIMER0LD

42.2.15

1 1 0 0 1 0 9 8

TTRXBUF

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_USBCTRL_GPTIMER1LD HW_USBCTRL_GPTIMER1LD

271

STMP 3700 Non-Existent

STMP 3780 0x88

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

42.2.17

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

STMP 3700 Non-Existent 1 1 1 1 5 4 3 2

0 0 0 0 3 2 1 0

STMP 3780 0x8c

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

GPTCNT

GPTMODE

GPTRST

GPTRUN

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_USBCTRL_SBUSCFG HW_USBCTRL_SBUSCFG 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

STMP 3700 Non-Existent

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

STMP 3780 0x90 1 1 0 0 1 0 9 8

AHBBRST

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

42.2.19

0 0 0 0 7 6 5 4

HW_USBCTRL_GPTIMER1CTRL HW_USBCTRL_GPTIMER1CTRL

42.2.18

1 1 0 0 1 0 9 8

GPTLD

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_USBCTRL_CAPLENGTH HW_USBCTRL_CAPLENGTH

272

0x100

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

0 0 0 0 3 2 1 0

CAPLENGTH

0x104

NPORTS

PPC PPC

0 0 0 0 3 2 1 0

N_PORTS

0 0 0 0 7 6 5 4

NPCC

NCC N_CC

1 1 0 0 1 0 9 8

N_PCC

PI

1 1 1 1 5 4 3 2

PI

N_TT

1 1 1 1 9 8 7 6

NPTT

2 2 2 2 3 2 1 0

N_PTT

2 2 2 2 7 6 5 4

NTT

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_USBCTRL_HCCPARAMS

HW_USBCTRL_DCIVERSION

273

0x120

IST

EECP

HW_USBCTRL_DCIVERSION

0 0 0 0 3 2 1 0

ADDR64BITCAP

0 0 0 0 7 6 5 4

ADC

1 1 0 0 1 0 9 8

ASYNC_PARK_CAP

1 1 1 1 5 4 3 2

PGM_FRM_LIST_FLAG

1 1 1 1 9 8 7 6

ASP

2 2 2 2 3 2 1 0

ISO_SCH_THRESHOLD

2 2 2 2 7 6 5 4

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

0x108

PFL

HW_USBCTRL_HCCPARAMS

42.2.22

0 0 0 0 7 6 5 4

HW_USBCTRL_HCSPARAMS HW_USBCTRL_HCSPARAMS

42.2.21

1 1 0 0 1 0 9 8

HCIVERSION HCIVER

STMP 3780 42.2.20

2 2 2 2 3 2 1 0

LENGTH

2 2 2 2 7 6 5 4

STMP 3700

3 3 2 2 1 0 9 8

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

STMP 3780

0 0 0 0 3 2 1 0

DEN DEN

1 1 0 0 1 0 9 8

DC

1 1 1 1 5 4 3 2

HC

1 1 1 1 9 8 7 6

DC

2 2 2 2 3 2 1 0

HC

2 2 2 2 7 6 5 4

0x124

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_USBCTRL_USBCMD

HW_USBCTRL_USBSTS HW_USBCTRL_USBSTS

274

0x144

IAA

ASE

PSE

FS1

FS0

RST

RS

ASE

PSE

FS1

FS0

RST

RS

0 0 0 0 3 2 1 0

IAA

0 0 0 0 7 6 5 4

LR

ASP0

ASP1

ASPE

1 1 0 0 1 0 9 8

ASPE

SUTW

ATDTW

FS2

1 1 1 1 5 4 3 2

FS2

1 1 1 1 9 8 7 6

ITC

2 2 2 2 3 2 1 0

ITC

2 2 2 2 7 6 5 4

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

0x140

ASP

HW_USBCTRL_USBCMD

42.2.25

0 0 0 0 7 6 5 4

HW_USBCTRL_DCCPARAMS HW_USBCTRL_DCCPARAMS

42.2.24

0 0 0 0 3 2 1 0

LR

42.2.23

0 0 0 0 7 6 5 4 DCIVERSION DCIVER

STMP 3700

3 3 2 2 1 0 9 8

FRI FRI

UI

SEI

UI

AAI AAI

SEI

UEI

URI URI

PCI

SRI SRI

UEI

SLI SLI

PCI

ULPII

RCL RCL

ULPII

PS PS

HCH

AS AS

0 0 0 0 3 2 1 0

PCE PCE

UE

FRE FRE

UE

SEE

UEE

AAE AAE

SEE

UEE

URE

0 0 0 0 3 2 1 0

URE

NAKE

UAIE

UPIE

TIE0

TIE1

0 0 0 0 7 6 5 4

SRE

1 1 0 0 1 0 9 8

SLE

1 1 1 1 5 4 3 2

SRE

1 1 1 1 9 8 7 6

SLE

2 2 2 2 3 2 1 0

ULPIE

2 2 2 2 7 6 5 4

0x148

NAKE

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_USBCTRL_FRINDEX

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

HW_USBCTRL_CTRLDSSEGMENT HW_USBCTRL_CTRLDSSEGMENT

275

STMP 3700 0x150

0 0 0 0 3 2 1 0 UINDEX

1 1 1 1 9 8 7 6

UINDEX

2 2 2 2 3 2 1 0

LISTINDEX

2 2 2 2 7 6 5 4

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

0x14c

FRINDEX

HW_USBCTRL_FRINDEX

42.2.28

0 0 0 0 7 6 5 4

HW_USBCTRL_USBINTR HW_USBCTRL_USBINTR

42.2.27

1 1 0 0 1 0 9 8

HCH

NAKI

1 1 1 1 5 4 3 2

NAKI

TI0

UAI

1 1 1 1 9 8 7 6

UPI

2 2 2 2 3 2 1 0

ULPIE

42.2.26

2 2 2 2 7 6 5 4

TI1

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

STMP 3780 Non-Existent

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

42.2.29

1 1 1 1 5 4 3 2

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

0 0 0 0 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0x154 1 1 0 0 1 0 9 8

PERBASE

BASEADDR

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_USBCTRL_DEVICEADDR HW_USBCTRL_DEVICEADDR 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

STMP 3700 Non-Existent 1 1 1 1 5 4 3 2

STMP 3780 0x154 1 1 0 0 1 0 9 8

USBADRA

USBADR

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

42.2.31

0 0 0 0 7 6 5 4

HW_USBCTRL_PERIODICLISTBASE HW_USBCTRL_PERIODICLISTBASE

42.2.30

1 1 0 0 1 0 9 8

EMPTY

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_USBCTRL_ASYNCLISTADDR HW_USBCTRL_ASYNCLISTADDR

276

0x158

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

42.2.32

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

0 0 0 0 3 2 1 0

ASYBASE

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

STMP 3700 Non-Existent

1 1 1 1 5 4 3 2

STMP 3780 0x158

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

EPBASE

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_USBCTRL_TTCTRL HW_USBCTRL_TTCTRL 2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

TTHA

2 2 2 2 7 6 5 4

0x15c

TTHA

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

42.2.34

0 0 0 0 7 6 5 4

HW_USBCTRL_ENDPOINTLISTADDR HW_USBCTRL_ENDPOINTLISTADDR

42.2.33

1 1 0 0 1 0 9 8

ASYBASE

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_USBCTRL_BURSTSIZE HW_USBCTRL_BURSTSIZE

277

0x160

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

RXPBURST

TX TXPBURST

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8 TXSCHEALTH TXSCHEALTH

STMP 3700 STMP 3780

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0 TXSCHOH

2 2 2 2 7 6 5 4

0x164

TXFIFOTHRES TXFIFOTHRES

3 3 2 2 1 0 9 8

HW_USBCTRL_TXTTFILLTUNING HW_USBCTRL_TXTTFILLTUNING 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

STMP 3700 0x168 1 1 1 1 5 4 3 2

STMP 3780 Non-Existent

1 1 0 0 1 0 9 8

EMPTY

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

42.2.37

0 0 0 0 3 2 1 0

HW_USBCTRL_TXFILLTUNING HW_USBCTRL_TXFILLTUNING

42.2.36

0 0 0 0 7 6 5 4

TXSCHOH

42.2.35

1 1 0 0 1 0 9 8

RX

2 2 2 2 7 6 5 4

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_USBCTRL_IC_USB HW_USBCTRL_IC_USB

STMP 3700 Non-Existent

278

STMP 3780 0x16c

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

IC_ENABLE

HW_USBCTRL_ULPI HW_USBCTRL_ULPI

42.2.39

0 0 0 0 3 2 1 0

ULPIDATRD

HW_USBCTRL_VFRAME HW_USBCTRL_VFRAME 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

STMP 3700 0x174

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

STMP 3780 Non-Existent 1 1 0 0 1 0 9 8

EMPTY

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

42.2.40

1 1 1 1 5 4 3 2

DATARD

1 1 1 1 9 8 7 6

ADDR

2 2 2 2 3 2 1 0

ULPIADDR

PORT ULPIPORT

RDWR ULPIRW

SYNC

RUN ULPIRUN

2 2 2 2 7 6 5 4

ULPISS

WAKEUP ULPIWU

ERROR

STMP 3700 STMP 3780

3 3 2 2 1 0 9 8

0x170

ULPIDATWR DATAWR

42.2.38

0 0 0 0 3 2 1 0

IC_VDD

2 2 2 2 7 6 5 4

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_USBCTRL_ENDPTNAK HW_USBCTRL_ENDPTNAK

279

STMP 3700 Non-Existent

STMP 3780 0x178

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

2 2 2 2 3 2 1 0

42.2.41

1 1 1 1 9 8 7 6

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

EPTN

STMP 3700 0x178

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

EPTN

2 2 2 2 3 2 1 0

STMP 3780 Non-Existent

EPRN

2 2 2 2 7 6 5 4

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_USBCTRL_ENDPTNAKEN STMP 3700 Non-Existent

HW_USBCTRL_ENDPTNAKEN 1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

EPTNE

2 2 2 2 3 2 1 0

STMP 3780 0x17c 0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

EPRNE

2 2 2 2 7 6 5 4

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

42.2.43

1 1 0 0 1 0 9 8

HW_USBCTRL_EPNAK HW_USBCTRL_EPNAK

42.2.42

1 1 1 1 5 4 3 2

EPRN

2 2 2 2 7 6 5 4

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_USBCTRL_EPNAKEN HW_USBCTRL_EPNAKEN

STMP 3700 0x17c

280

STMP 3780 Non-Existent

42.2.44

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

HW_USBCTRL_CONFIGFLAG

STMP 3700 0x180

1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

EPTNE

EPRNE

2 2 2 2 7 6 5 4

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_USBCTRL_CONFIGFLAG

2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

42.2.45

FLAG

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

STMP 3780 Non-Existent

HW_USBCTRL_PORTSC1 HW_USBCTRL_PORTSC1

42.2.46

WKOC

WKDS

WKCN

PTC

PIC

PO

PP

LS

HSP

PR

SUSP

FPR

OCC

OCA

PEC

PE

CSC

CCS

WKOC

WKDS

WKCN

PTC

PIC

PO

PP

LS

HSP

PR

SUSP

FPR

OCC

OCA

PEC

PE

CSC

CCS

1 1 0 0 1 0 9 8

PHCD

1 1 1 1 5 4 3 2

PHCD

PSPD PSPD

1 1 1 1 9 8 7 6

PFSC

PTW PTW

2 2 2 2 3 2 1 0

PFSC

STS STS

SRT

PTS

2 2 2 2 7 6 5 4

PTS

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

0x184

HW_USBCTRL_OTGSC HW_USBCTRL_OTGSC

281

0x1a4

ASVIS

AVVIS

IDIS

DPS

ONEMST

BSE

BSV

ASV

AVV

ID

HABA

HADP

IDPU

DP

OT

ASVIS

AVVIS

IDIS

DPS

ONEMST

BSE

BSV

ASV

AVV

ID

HABA

HADP

IDPU

DP

OT

VD

BSVIS BSVIS

VD

BSEIS

VC

ONEMSS ONEMSS

BSEIS

HAAR

DPIS DPIS

VC

IDIE IDIE

HAAR

AVVIE

CM

VBPS

0 0 0 0 3 2 1 0

CM

0 0 0 0 7 6 5 4

ES

1 1 0 0 1 0 9 8

ES

1 1 1 1 5 4 3 2

SLOM

1 1 1 1 9 8 7 6

SLOM

2 2 2 2 3 2 1 0

SDIS

2 2 2 2 7 6 5 4

0x1a8

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_USBCTRL_ENDPTSETUPSTAT HW_USBCTRL_ENDPTSETUPSTAT 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

0x1ac 1 1 0 0 1 0 9 8

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

STMP 3780

ENDPTSETUPSTAT

STS

STMP 3700

3 3 2 2 1 0 9 8

42.2.49

0 0 0 0 3 2 1 0

HW_USBCTRL_USBMODE HW_USBCTRL_USBMODE

42.2.48

0 0 0 0 7 6 5 4

AVVIE

1 1 0 0 1 0 9 8

BSVIE

1 1 1 1 5 4 3 2

ASVIE

BSEIE BSEIE

1 1 1 1 9 8 7 6

ASVIE

ONEMSE

2 2 2 2 3 2 1 0

BSVIE

DPIE

ONEMSE

2 2 2 2 7 6 5 4

SDIS

42.2.47

DPIE

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_USBCTRL_ENDPTPRIME HW_USBCTRL_ENDPTPRIME

282

0x1b0

42.2.50

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

PETB

PERB

PETB

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

FETB

FERB

FETB

2 2 2 2 3 2 1 0

0x1b4

FERB

2 2 2 2 7 6 5 4

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_USBCTRL_ENDPTSTAT HW_USBCTRL_ENDPTSTAT 2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

STMP 3700 Non-Existent 1 1 1 1 5 4 3 2

STMP 3780 0x1b8 1 1 0 0 1 0 9 8

ETBR

ERBR

2 2 2 2 7 6 5 4

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

42.2.52

0 0 0 0 7 6 5 4

HW_USBCTRL_ENDPTFLUSH HW_USBCTRL_ENDPTFLUSH

42.2.51

1 1 0 0 1 0 9 8

PERB

2 2 2 2 7 6 5 4

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_USBCTRL_ENDPTSTATUS HW_USBCTRL_ENDPTSTATUS

283

STMP 3700 0x1b8

STMP 3780 Non-Existent

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

ETBR

1 1 1 1 9 8 7 6

1 1 1 1 5 4 3 2

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0x1bc 1 1 0 0 1 0 9 8

ETCE

ERCE

ETCE

2 2 2 2 3 2 1 0

HW_USBCTRL_ENDPTCTRL0

1 1 1 1 5 4 3 2

STMP 3780 0x1c0 1 1 0 0 1 0 9 8

RXS

1 1 1 1 9 8 7 6

TXS

2 2 2 2 3 2 1 0

TXT

2 2 2 2 7 6 5 4

TXE

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

STMP 3700 Non-Existent

RXE

HW_USBCTRL_ENDPTCTRL0

43.1

0 0 0 0 3 2 1 0

ERCE

2 2 2 2 7 6 5 4

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

43

0 0 0 0 7 6 5 4

HW_USBCTRL_ENDPTCOMPLETE HW_USBCTRL_ENDPTCOMPLETE

42.2.54

1 1 0 0 1 0 9 8

RXT

42.2.53

2 2 2 2 3 2 1 0

ERBR

2 2 2 2 7 6 5 4

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

Integrated USB 2.0 PHY Summary

The next table summarizes the important aspects of the USB Physical Interface device block and the main differences between the STMP 3700 and the STMP 3780. Name USB Physical Interface HW_USBPHY_PWD

Property Base Address Address Fields 284

STMP 3700 STMP 3780 0x8007c000 0x0 New Field(s)

HW_USBPHY_DEBUG HW_USBPHY_DEBUG0_STATUS HW_USBPHY_DEBUG1 HW_USBPHY_VERSION HW_USBPHY_IP

43.2

Programmable Registers

43.2.1

HW_USBPHY_PWD

0x20 Incompatible Field(s) Incompatible Field(s) 0x30 New Field(s) 0x40 0x50 0x60 0x70 New Field(s) 0x80 Non-Existent

HW_USBPHY_PWD

43.2.2

RXPWD1PT1

RXPWDENV

RXPWD1PT1

RXPWDENV

TXPWDV2I

RXPWDDIFF RXPWDDIFF

1 1 1 1 5 4 3 2 TXPWDCOMP

RXPWDRX

1 1 1 1 9 8 7 6

RXPWDRX

2 2 2 2 3 2 1 0

STMP 3700

2 2 2 2 7 6 5 4

STMP 3780

3 3 2 2 1 0 9 8

HW_USBPHY_TX HW_USBPHY_TX

285

0x90 New Field(s)

0x0

0x10

1 1 0 0 1 0 9 8 TXPWDFS

HW_USBPHY_STATUS

New Field(s)

TXPWDFS

HW_USBPHY_CTRL

STMP 3780 0x10

TXPWDIBIAS TXPWDIBIAS

HW_USBPHY_RX

STMP 3700

TXPWDV2I

HW_USBPHY_TX

Property Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields Address Fields

TXPWDVBG

Name

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

STMP 3700

43.2.4 2 2 2 2 3 2 1 0 1 1 1 1 9 8 7 6

286

HW_USBPHY_RX

1 1 1 1 5 4 3 2

HW_USBPHY_CTRL HW_USBPHY_CTRL 0x30 1 1 0 0 1 0 9 8

D_CAL

D_CAL

1 1 0 0 1 0 9 8

TXCALIBRATE

TXCAL45DN

TXENCAL45DN

TXCAL45DP

TXENCAL45DP

TXCMPOUT_STATUS

USBPHY_TX_SYNC_MUX

1 1 1 1 5 4 3 2

TXCAL45DN

TXENCAL45DN

TXCAL45DP

TXENCAL45DP

USBPHY_TX_SYNC_MUX

1 1 1 1 9 8 7 6 0 0 0 0 7 6 5 4

0 0 0 0 7 6 5 4 ENVADJ

USBPHY_TX_EDGECTRL

USBPHY_TX_EDGECTRL

USBPHY_TX_SYNC_INVERT USBPHY_TX_SYNC_INVERT

STMP 3700

STMP 3780

2 2 2 2 3 2 1 0

ENVADJ

2 2 2 2 7 6 5 4 DISCONADJ

3 3 2 2 1 0 9 8

DISCONADJ

43.2.3 2 2 2 2 7 6 5 4

RXDBYPASS RXDBYPASS

STMP 3780

3 3 2 2 1 0 9 8 0 0 0 0 3 2 1 0

HW_USBPHY_RX 0x20

0 0 0 0 3 2 1 0

43.2.6

287 1 1 1 1 5 4 3 2

HW_USBPHY_DEBUG

HW_USBPHY_DEBUG

0x50

CLKGATE UTMI_SUSPENDM HOST_FORCE_LS_SE0

CLKGATE UTMI_SUSPENDM HOST_FORCE_LS_SE0

1 1 0 0 1 0 9 8

ENIRQDEVPLUGIN RESUME_IRQ ENIRQRESUMEDETECT

ENOTGIDDETECT DEVPLUGIN_POLARITY ENDEVPLUGINDETECT

ENIRQDEVPLUGIN RESUME_IRQ ENIRQRESUMEDETECT

ENOTGIDDETECT DEVPLUGIN_POLARITY ENDEVPLUGINDETECT

0 0 0 0 7 6 5 4

ENHOSTDISCONDETECT ENHOSTDISCONDETECT

ENHSPRECHARGEXMIT

ENIRQHOSTDISCON

ENIRQHOSTDISCON

0 0 0 0 7 6 5 4 HOSTDISCONDETECT_IRQ HOSTDISCONDETECT_IRQ

DEVPLUGIN_IRQ

DEVPLUGIN_IRQ

DATA_ON_LRADC

SFTRST

SFTRST

DATA_ON_LRADC

STMP 3700

STMP 3780

1 1 0 0 1 0 9 8

HOSTDISCONDETECT_STATUS HOSTDISCONDETECT_STATUS

1 1 1 1 9 8 7 6

DEVPLUGIN_STATUS

HW_USBPHY_STATUS

DEVPLUGIN_STATUS

2 2 2 2 3 2 1 0

1 1 1 1 5 4 3 2

OTGID_STATUS

2 2 2 2 7 6 5 4

1 1 1 1 9 8 7 6

OTGID_STATUS

3 3 2 2 1 0 9 8

2 2 2 2 3 2 1 0

RESUME_STATUS

STMP 3700

43.2.5 2 2 2 2 7 6 5 4

RESUME_STATUS

STMP 3780

3 3 2 2 1 0 9 8 0 0 0 0 3 2 1 0

HW_USBPHY_STATUS 0x40

0 0 0 0 3 2 1 0

43.2.8 SQUELCH_COUNT

SQUELCH_COUNT

2 2 2 2 3 2 1 0

LOOP_BACK_FAIL_COUNT

2 2 2 2 7 6 5 4

ENSQUELCHRESET

ENSQUELCHRESET

1 1 1 1 9 8 7 6

288

HW_USBPHY_DEBUG0_STATUS

1 1 1 1 5 4 3 2

HW_USBPHY_DEBUG1

HW_USBPHY_DEBUG1

0x70 1 1 0 0 1 0 9 8 0 0 0 0 7 6 5 4

OTGIDPIOLOCK

OTGIDPIOLOCK

DEBUG_INTERFACE_HOLD DEBUG_INTERFACE_HOLD

0 0 0 0 7 6 5 4

HSTPULLDOWN

ENHSTPULLDOWN

1 1 0 0 1 0 9 8

HSTPULLDOWN

ENHSTPULLDOWN

1 1 1 1 5 4 3 2

TX2RXCOUNT

1 1 1 1 9 8 7 6

TX2RXCOUNT

ENTX2RXCOUNT

SQUELCHRESETLENGTH

SQUELCHRESETLENGTH

ENTX2RXCOUNT

HOST_RESUME_DEBUG

HOST_RESUME_DEBUG

SQUELCHRESETCOUNT

CLKGATE

CLKGATE

SQUELCHRESETCOUNT

STMP 3700

STMP 3780

2 2 2 2 3 2 1 0

LOOP_BACK_FAIL_COUNT

3 3 2 2 1 0 9 8

2 2 2 2 7 6 5 4

UTMI_RXERROR_FAIL_COUNT UTMI_RXERROR_FAIL_COUNT

STMP 3700

43.2.7

STMP 3780

3 3 2 2 1 0 9 8 0 0 0 0 3 2 1 0

HW_USBPHY_DEBUG0_STATUS

0x60

0 0 0 0 3 2 1 0

ENTAILADJVD

STMP 3700 STMP 3780

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

0 0 0 0 7 6 5 4

0 0 0 0 3 2 1 0

HW_USBPHY_VERSION HW_USBPHY_VERSION 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

1 1 1 1 9 8 7 6

0x80

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

STEP STEP

MINOR

MAJOR

MINOR

MAJOR

STMP 3780 STMP 3700

3 3 2 2 1 0 9 8

HW_USBPHY_IP HW_USBPHY_IP 2 2 2 2 7 6 5 4

2 2 2 2 3 2 1 0

STMP 3700 Non-Existent

1 1 1 1 9 8 7 6

STMP 3780 0x90

1 1 1 1 5 4 3 2

1 1 0 0 1 0 9 8

289

PLL_POWER

PLL_LOCKED

ANALOG_TESTMODE

TSTI_TX_DM

TSTI_TX_DP

CP_SEL

LFR_SEL

DIV_SEL

STMP 3700

3 3 2 2 1 0 9 8

STMP 3780

43.2.10

0 0 0 0 7 6 5 4

EN_USB_CLKS

43.2.9

1 1 0 0 1 0 9 8

DBG_ADDRESS DBG_ADDRESS

1 1 1 1 5 4 3 2

PLL_IS_240

1 1 1 1 9 8 7 6

ENTX2TX

2 2 2 2 3 2 1 0

ENTX2TX

2 2 2 2 7 6 5 4

ENTAILADJVD

3 3 2 2 1 0 9 8