UNIVERSIDADE TÉCNICA DE LISBOA INSTITUTO SUPERIOR TÉCNICO
Design and Characterization of CMOS High-Resolution Time-to-Digital Converters
Manuel José dos Reis Gaspar Seabra Mota (Licenciado) Dissertação para a obtenção do Grau de Doutor em Engenharia Electrotécnica e de Computadores
Orientador: Doutor José de Albuquerque Epifânio da Franca
Presidente: Reitor da Universidade Técnica de Lisboa Vogais:
Doutor Dinis Gomes Magalhães dos Santos Doutor Moisés Simões Piedade Doutor José de Albuquerque Epifânio da Franca Doutor Diamantino Rui da Silva Freitas Doutor António Manuel da Cruz Serra Doutor João Paulo Calado Cordeiro Vital Doutor Alessandro Marchioro
Outubro de 2000
UNIVERSIDADE TÉCNICA DE LISBOA INSTITUTO SUPERIOR TÉCNICO
Projecto e Caracterização Experimental de Circuitos Integrados CMOS para Medição de Intervalos de Tempo com Alta Resolução Manuel José dos Reis Gaspar Seabra Mota (Licenciado) Dissertação para a obtenção do Grau de Doutor em Engenharia Electrotécnica e de Computadores
Orientador: Doutor José de Albuquerque Epifânio da Franca
Presidente: Reitor da Universidade Técnica de Lisboa Vogais:
Doutor Dinis Gomes Magalhães dos Santos Doutor Moisés Simões Piedade Doutor José de Albuquerque Epifânio da Franca Doutor Diamantino Rui da Silva Freitas Doutor António Manuel da Cruz Serra Doutor João Paulo Calado Cordeiro Vital Doutor Alessandro Marchioro
Outubro de 2000
Abstract
The subject of this thesis is the development and evaluation of high-resolution Time-to-Digital Converter architectures suitable for the measurement of very short time intervals in the context of the Time-of-Flight detector of the ALICE experiment. The selected architectures are able to measure time intervals with a Root Mean Square (RMS) resolution better than 50ps and a large dynamic range. Apart from the timing characteristics of such TDC’s, their architectures enable the design of highly integrated multi-channel converter ASIC’s operating with low power dissipation. The developed circuits are based on Delay Locked Loop (DLL) architectures. The feedback control loop of the DLL ensures that the time measurements are permanently calibrated in relation to a reference periodic signal. Schemes to obtain fine time interpolation without penalty in terms of added power dissipation or increased sensitivity to environmental changes (supply voltage or temperature) are investigated and implemented. Two different approaches are selected and their detailed analysis carried out. One uses several phase shifted DLL’s and the other a passive RC delay line. The prototypes that implement these schemes were built in a standard 0.7µm CMOS technology. In the first approach, an RMS resolution of 34.5ps across a dynamic range of 3.2µs was measured. For the second, an RMS resolution of 21ps was obtained.
Keywords Time-to-Digital Converter (TDC), Delay Locked Loop (DLL), self-calibration, high-resolution, multi-channel, passive RC delay lines.
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Resumo
O objectivo desta tese é a avaliação e desenvolvimento de arquitecturas de Conversão Tempo para Digital com alta resolução temporal adequados à medição de intervalos de tempo muito curtos, no âmbito do detector de Tempo de Voo da experiência ALICE. As arquitecturas seleccionadas são capazes de medir intervalos de tempo com uma resolução melhor do que 50ps (Desvio Quadrático Médio - RMS) ao longo de uma larga gama dinâmica. Além das características temporais destes conversores, as suas arquitecturas permitem a implementação de circuitos integrados específicos multi-canal, operando com baixa dissipação de potência. Os circuitos desenvolvidos são baseados em Malhas de Aquisição de Atraso (DLL) fechadas. A realimentação negativa da DLL garante que as medições temporais estão permanentemente calibradas tendo como referência um sinal periódico. Foram investigados e implementados esquemas que permitem uma interpolação temporal muito fina sem aumentar significativamente a dissipação de potência ou a sensibilidade do esquema à variação das condições ambientais (tensão de alimentação ou temperatura de operação). Dois destes esquemas foram seleccionados e a sua análise detalhada levada a cabo. Um dos esquemas usa várias DLL’s com um atraso de fase fixo e o outro utiliza uma linha de atraso passiva RC. Os protótipos em que foram implementados estes esquemas utilizam uma tecnologia CMOS de 0.7µm. Com estes protótipos obtiveram-se, respectivamente, resoluções de 34.5ps (RMS) ao longo de uma gama dinâmica de 3.2µs e de 21ps (RMS).
Palavras Chave Conversor Tempo para Digital (TDC), Malha de Controlo de Atraso (DLL), autocalibração, alta resolução, multi-canal, linhas de atraso passivas RC.
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Acknowledgements
It goes without saying that I am indebted to all the people whose contribution, small and large, made my work and my life easier during the period that I spent working for this thesis; the list of their names would be too long to write down. However, I wish to acknowledge in particular the help of my colleagues Jorgen Christiansen and Paulo Moreira who had the kindness and patience to answer all my questions and whose guidance and experience helped me to advance this work in the best direction. I will also acknowledge the help of my supervisor, José Epifânio da Franca who was always attentive to my requirements, even the most pressing ones. I thank Gaspar Barreira and Paulo Gomes who started it all and Alessandro Marchioro and Mike Letheren who welcomed me into the microelectronics group at CERN and provided me with the proper means and environment to proceed with my work. An acknowledgement is also due to JNICT, whose support made it all possible1 and to LIP, where the brave new world of microelectronics and High Energy Physics was first shown to me. Since life is not only work, even when that work is exciting, I greet cheerfully the friends I met in Geneva, whose warmth and imagination made life abroad very interesting. A final word is reserved to my family and friends back in Portugal who always found the right way to let me know they cared, even after being away for so much time.
1
The author is supported by a grant from the Junta Nacional de Investigação Científica e Tecnológica (JNICT) under the “Sub-Programa Ciência e Tecnologia do 2o. Quadro Comunitario de Apoio”. Page v
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Contents. PART I. Introduction.
1
1. Introduction and Structure of this Work.
3
2. Time Interval Measurements in HEP Experiments – An Introduction.
9
2.1. High Energy Physics experiments. 2.1.1. A HEP experiment at CERN: ALICE. 2.2. High resolution time interval measurements in ALICE. 3. Conversion Basics.
9 10 13 17
3.1. Performance metrics.
18
3.2. Error sources.
21
3.3. Converter calibration.
24
4. Review of TDC Architectures.
27
4.1. Overview of TDC architectures.
27
4.1.1. Current integration techniques.
27
4.1.2. Counter techniques.
29
4.1.3. Delay line-based techniques.
30
4.1.4. Phase Locked Loop (PLL) techniques.
31
4.1.5. Delay Locked Loop (DLL) techniques.
32
4.2. Beyond the limits of the technology: techniques to improve resolution.
33
4.2.1. Analogue time expansion.
33
4.2.2. Vernier differences.
35
4.2.3. Analogue time interpolation.
38
4.2.4. Array of coupled oscillators.
40
4.2.5. Array of Delay Locked Loops.
41
4.2.6. Time interpolation using passive RC delay lines.
43
4.3. Summary of characteristics of the TDC architectures.
44
References for Part I. PART II. A TDC Architecture based on an Array of Delay Locked Loops. 5. Architecture Overview.
45 49 53
5.1. The Delay Locked Loop (DLL).
53
5.2. The Array of DLL’s (ADLL).
55
5.3. Conversion dynamic range.
57
5.4. Time critical paths.
59
5.5. Measurement acquisition and storage.
59
5.6. Read-out architecture.
60
5.7. The prototype.
62
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5.7.1. Performance analysis. 6. Analysis of the Limits to the TDC Resolution. 6.1. Non-linearity due to cell mismatch.
63 65 65
6.1.1. Origins of mismatch.
65
6.1.2. Effects of cell delay mismatch.
66
6.2. Jitter due to internal phase noise.
68
6.3. Non-linearity due to static phase error.
69
6.3.1. Effects of phase detector’s phase error.
70
6.3.2. Effects of phase detector input path’s mismatch.
72
6.3.3. Effects of unbalanced conditions of the cells in the extremes of the delay chain.
72
6.3.4. Effects of propagation delay on the sampling signal path.
74
6.3.5. Overall non-linearity due to static phase error.
76
7. Detailed Implementation. 7.1. DLL building blocks.
79 79
7.1.1. Phase detector.
79
7.1.2. Charge-pump and loop filter.
82
7.1.3. Delay cell.
86
7.1.4. Delay chain.
92
7.1.5. Closed control loop.
93
7.1.6. Initialisation procedure.
94
7.2. The ADLL.
95
7.3. Channel memory.
96
7.3.1. The store sampling signal distribution. 8. Experimental Results.
99 101
8.1. Delay cell range selection and charge-pump current level.
101
8.2. Converter linearity.
102
8.3. Linear time sweeps.
106
8.4. Inter-channel crosstalk.
107
8.5. Double hit resolution.
108
8.6. Power dissipation.
108
8.7. Summary of results.
108
8.8. Conclusion.
109
References for Part II.
111
PART III. A TDC Architecture based on a DLL and a Passive RC Delay Line. 9. Architecture Overview.
113 117
9.1. Time interpolation circuit.
118
9.2. Adjustable RC delay line.
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9.2.1. Adjustable delay line by tap selection.
120
9.2.2. Adjustable delay line by lumped capacitor selection.
121
9.3. Auto calibration.
122
9.4. The prototype.
122
9.4.1. Choice of technology.
122
9.4.2. Prototype characteristics.
123
9.4.3. Performance analysis.
125
10. Adjustable RC Delay Line using a Tap Selection Scheme. 10.1. RC delay line. 10.1.1. RC delay line simulation model. 10.2. Tap selection delay line. 10.2.1. Tap selection circuitry. 10.3. Auto calibration circuitry.
127 127 129 131 136 137
10.3.1. Calibration algorithms.
138
10.3.2. Hardware implementation.
142
11. Adjustable RC Delay Line using a Variable Lumped Capacitor Scheme. 11.1. Lumped capacitor delay line. 11.1.1. Lumped capacitor selection circuitry. 11.2. Auto calibration circuitry.
145 145 147 149
11.2.1. Calibration algorithm.
150
11.2.2. Hardware implementation.
153
11.3. Comparing the two adjustment schemes. 12. Experimental Results. 12.1. Tap selection scheme. 12.1.1. The complete interpolator.
154 155 155 157
12.2. Lumped capacitor scheme.
162
12.3. Conversion time offset.
164
12.4. Power dissipation.
165
12.5. Summary of results.
165
12.6. Conclusions.
165
References for Part III. PART IV. Conclusion. 13. Summary of Results.
167 169 171
13.1. The ADLL architecture.
171
13.2. The DLL & RC delay line architecture.
172
13.3. TDC characterisation.
173
14. Future Developments.
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PART V. Appendixes.
179
A. TDC Characterisation Test Bench.
181
B. Analysis of the DLL Closed Loop Behaviour.
187
C. Analysis of the Effects of Cell Delay Mismatch on the Integral Non-linearity of a DLL.
189
D. Number of Random Samples Required for TDC Characterisation.
193
E. TDC Characterisation Hit Frequency.
197
F. Analysis of the Limits to the TDC Resolution (Alternative Tap Definition).
201
G. DNL-aware Algorithms for the RC Delay Line Calibration.
203
References for the Appendixes.
209
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List of Figures. PART I. Introduction. Chapter 1. Introduction and Structure of this Work. Chapter 2. Time Interval Measurements in HEP Experiments – An Introduction. Figure 1: The CERN particle accelerator complex (simplified) [4].
10
Figure 2: Longitudinal and transverse view of ALICE detector [3].
11
Figure 3: The hierarchical trigger data reduction block diagram of ALICE experiment [3]. 12 Figure 4: Schematic view of the TOF detector front-end.
13
Figure 5: The error propagation chain.
14
Chapter 3. Conversion Basics. Figure 1: Ideal transfer characteristic of a 3-bit converter.
18
Figure 2: Example of a converter transfer function illustrating the static performance metrics.
20
Chapter 4. Review of TDC Architectures. Figure 1: Block and timing diagram of a differential Current Integrating TAC (from [3]).
28
Figure 2: Delay line using double inverters as delay elements.
30
Figure 3: Asymmetric ring oscillator [24], able to generate a 2N number of timing signals from an odd-numbered oscillator.
31
Figure 4: Delay Locked Loop and hit registers.
32
Figure 5: Timing diagram of the dynamic range extension using a clocked time stretcher [33].
34
Figure 6: Time expander circuit and corresponding timing diagram.
35
Figure 7: Time expansion using two delay lines with different cell delay.
35
Figure 8: Circular vernier scheme for dynamic range expansion.
36
Figure 9: A vernier caliber measuring a length of 0.43 mm. Note that the third tick mark in the vernier scale (lower) lines up with a tick mark in the reference scale (upper) [36].
38
Figure 10: Time interpolation using voltage sums.
39
Figure 11: Time to analogue converter using a time interpolation technique [38].
39
Figure 12: Coupled oscillators (time resolution of td * 2 / 3).
40
Figure 13: Array of DLL’s with phase shifting DLL.
42
Figure 14: A TDC converter based on a DLL and a RC delay line.
44
PART II. A TDC Architecture based on an Array of Delay Locked Loops. Chapter 5. Architecture Overview. Figure 1: Delay Locked Loop block diagram.
54
Figure 2: Delay Locked Loop used in a time base application.
54
Figure 3: Array of DLL’s with phase shifting DLL, showing bin definition.
55
Figure 4: Interpolation limits due to cell mismatch.
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Figure 5: Dynamic range extension using two coarse time counters.
58
Figure 6: Example of the first level of a read-out buffering hierarchy.
61
Figure 7: The prototype block diagram.
62
Figure 8: Prototype circuit showing main functional blocks.
64
Chapter 6. Analysis of the Limits to the TDC Resolution. Figure 1: INL standard deviation curve resulting from a cell delay mismatch of σcell=1% (ADLL: N=35 and F=4, single DLL: N=140).
68
Figure 2: Standard deviation curve resulting from a closed loop jitter of σjitter=0.1% of the reference period (ADLL: N=35 and F=4, single DLL: N=140).
69
Figure 3: Detail of a delay locked loop depicting the important delays within the loop.
70
Figure 4: Illustration of the effect of the phase detector’s phase error (N=5).
71
Figure 5: Illustration of the effect of the phase detector input paths’ delay mismatch (N=5).
72
Figure 6: Illustration of the effect of unbalanced conditions in the first cell of the delay chain (N=5).
73
Figure 7: Illustration of the effect of unbalanced conditions in the last cell of the delay chain (N=5).
73
Figure 8: Illustration of the effect of the propagation delay on the sampling signal path - case of the linear hit signal distribution network (N=5).
74
Figure 9: The T-shaped hit signal distribution network.
75
Figure 10: Illustration of the effect of the propagation delay on the sampling signal path - case of the T-shaped hit signal distribution network (N=5).
75
Figure 11: DNL and INL curves resulting from a phase detector’s phase error (or phase detector input path’s mismatch): DPD(C / K + τdiff)=0.1% of the reference period (ADLL: N=35 and F=4, single DLL: N=140).
77
Figure 12: DNL and INL curves resulting from unbalanced conditions of the delay cells in the extremes of the delay chain: Din(δin)=1% and Dout(δout)=1% of the average cell (ADLL: N=35 and F=4, single DLL: N=140).
77
Figure 13: DNL and INL curves resulting from the propagation delay on the sampling signal path (linear hit signal distribution network): Dhit(−τhit)=0.1% of the reference period (ADLL: N=35 and F=4, single DLL: N=140).
78
Figure 14: DNL and INL curves resulting from the propagation delay on the sampling signal path (T-shaped hit signal distribution network): Dhit(−τhit)=0.1% of the reference period (ADLL: N=35 and F=4, single DLL: N=140).
78
Figure 15: DNL and INL curves resulting from the combination of the previous curves (ADLL: N=35 and F=4, single DLL: N=140).
78
Chapter 7. Detailed Implementation. Figure 1: D-flip-flop operating as a two-state phase detector.
79
Figure 2: General and D-FF based two-state phase detector transfer characteristic.
80
Figure 3: Balanced D-flip-flop topology.
81
Figure 4: Balanced D-flip-flop topology featuring fast SR#1 operation.
82
Figure 5: Charge-pump and filter capacitor block diagram.
83
Figure 6: Charge-pump topologies (simplified).
84
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Figure 7: Rising edge propagation along the DLL delay line and corresponding current consumption.
87
Figure 8: The self-biased differential delay cell (from [18]).
88
Figure 9: The current-starved inverter delay cell (simplified version).
88
Figure 10: Cell delay variation due to a 100mV supply voltage step, respectively for the differential and current-starved inverter structure.
89
Figure 11: Simplified representation of the delay range partition.
90
Figure 12: The selectable-range current-starved inverter cell.
91
Figure 13: The selectable delay ranges (simulation).
92
Figure 14: Detail of the closed control loop illustrating the propagation delay mismatch of the phase signals.
93
Figure 15: Schematic representation of the delay range partition illustrating the viable locking regions.
95
Figure 16: The ADLL tap distribution arrangement.
96
Figure 17: Functional diagram of the channel memory controller [3].
97
Figure 18: The two-level hit register (1 bit).
97
Figure 19: Two-stage synchroniser using D flip-flops.
98
Figure 20: Alternative control signal distribution configurations within a channel memory row.
99
Figure 21: Integrated error histogram for the two proposed distribution configurations (simulation).
100
Chapter 8. Experimental Results. Figure 1: DNL and INL graphs for the ADLL.
102
Figure 2: Analytical DNL and INL curves (Din=1% and Dout=-1% of the delay cell, DPD=-0.1% and Dhit=0.1% of the reference period).
103
Figure 3: DNL and INL graphs for the different Timing DLLs (LSBDLL=4·LSB).
103
Figure 4: DNL and INL graphs for the Phase Shifting DLL (LSBDLL=5·LSB).
104
Figure 5: The ADLL auto-correlation graph.
105
Figure 6: DNL and INL graphs for the converter along four reference clock periods.
105
Figure 7: Error graph and histogram resulting from a delay sweep of two reference periods (σ=0.39LSB).
106
Figure 8: DNL and INL graphs obtained from the linear delay sweep results.
106
Figure 9: Conversion error histogram for the first Timing DLL (σ=0.30LSBDLL).
107
Figure 10: Delay sweep over the full dynamic range.
107
Figure 11: Measurement error due to crosstalk in the worst configuration.
108
PART III. A TDC Architecture based on a DLL and a Passive RC Delay Line. Chapter 9. Architecture Overview. Figure 1: Detail of DLL signal propagation illustrating time interpolation through multiple delay line samples (in this example the number of samples acquired is M=5).
117
Figure 2: Time interpolation circuit.
119
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Figure 3: Continuous delay adjustment scheme based on control of the distributed parameters (simplified).
120
Figure 4: Adjustable delay line using a tap selection scheme.
121
Figure 5: Adjustable delay line using a variable lumped capacitor scheme.
121
Figure 6: Block diagram of the prototype.
123
Figure 7: Prototype circuit showing main functional blocks.
125
Chapter 10. The Adjustable RC Delay Line using a Tap Selection Scheme. Figure 1: RC line divided in two segments at access point x. R and C are, respectively resistance and capacitance per unit length.
128
Figure 2: Delay line division into equally sized sections.
129
Figure 3: Electrical model of an infinitesimal segment of a transmission line (the T-network).
130
Figure 4: Detail of the physical microstrip line and its equivalent simulation model.
130
Figure 5: Delay line segments’ length adjustment.
133
Figure 6: Adjustment function values.
134
Figure 7: Signal’s rise time along the original and the adjusted delay line, in typical conditions (simulated).
134
Figure 8: Delay and cumulative delay of each line segment (from simulations).
135
Figure 9: The leading and trailing adaptation sections.
135
Figure 10: Segment delay sensitivity to operating conditions (from simulations). The first and second graphs correspond, respectively, to the same line with and without leading and trailing sections.
136
Figure 11: The access point selection circuitry.
137
Figure 12: Calibration procedure for the tap selection adjustment scheme.
140
Figure 13: Results of calibration for different conditions, using the iterative algorithm (from simulation).
140
Figure 14: Results of calibration using the optimum linearity limit (from simulation).
141
Figure 15: Results of calibration for different conditions (from simulation).
142
Chapter 11. The Adjustable RC Delay Line using a Variable Lumped Capacitor Scheme. Figure 1: Adjustment function values (calculated and actually implemented).
146
Figure 2: Bin size (from simulation). The first graph compares different design corners. The second graph shows the effects of extreme environment variations for the typical process.
147
Figure 3: The unit capacitor bank.
148
Figure 4: The lumped capacitor selection circuitry.
148
Figure 5: The effects of lumped capacitor unit variation in the bin size (from simulation).
149
Figure 6: The coarse calibration procedure.
151
Figure 7: The fine calibration procedure.
152
Figure 8: Results of the coarse calibration step for different conditions using the proposed algorithm (from simulation).
152
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Figure 9: Results of the fine calibration for different conditions using restrictive linearity limits (from simulation).
153
Chapter 12. Experimental Results. Figure 1: Delay line calibration results: DNL and INL graphs.
156
Figure 2: Spread of the RC line tap delay over the DLL cells.
156
Figure 3: Temperature dependency of the RC delay line.
157
Figure 4: DNL and INL graphs of the converter (using the tap selection adjustable delay line).
157
Figure 5: INL of the DLL, showing spread of the tap delay along the hit register rows.
158
Figure 6: Comparison of the INL graphs of the DLL and of the complete converter.
159
Figure 7: Conversion error (σ=0.51LSB).
159
Figure 8: Temperature effects on the conversion error (σ=0.50LSB/30oC and σ=0.52LSB/60oC).
160
Figure 9: DLL linear time sweep.
160
Figure 10: Detail of the DLL time sweep showing code transitions in opposite extremes of the delay chain.
161
Figure 11: DLL conversion error (σ=0.29LSBDLL).
161
Figure 12: RC delay line’s DNL and INL graphs (using the lumped capacitor adjustment scheme).
162
Figure 13: DNL and INL graphs of the converter (using the lumped capacitor adjustable delay line).
163
Figure 14: Comparison of the INL graphs of the DLL and of the complete converter.
163
Figure 15: Conversion error (σ=0.44LSB).
164
Figure 16: DLL conversion error (σ=0.29LSBDLL).
164
PART IV. Conclusion. Chapter 13. Summary of Results. Chapter 14. Future Developments. Figure 1: A four channel TDC using a DLL based scheme and a single channel TDC with four times smaller LSB, using the same building blocks and an RC delay line.
176
Figure 2: The general purpose TDC architecture.
176
Figure 3: Block diagram of the general purpose TDC.
177
PART V. Appendixes. Appendix A. TDC Characterisation Test Bench. Figure 1: The linear passive delay generator block diagram (computer controlled).
183
Figure 2: The linear passive delay generator block diagram (automated).
184
Appendix B. Analysis of the DLL Closed Loop Behaviour. Appendix C. Analysis of the Effects of Cell Delay Mismatch on the Integral Non-linearity of a DLL. Figure 1: Voltage controlled delay line with fixed length.
189
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Appendix D. Number of Random Samples Required for TDC Characterisation. Figure 1: P(-zα/2 < Z < zα/2) = 1-α.
194
Appendix E. TDC Characterisation Hit Frequency. Figure 1: The clock multiplying PLL.
199
Appendix F. Analysis of the Limits to the TDC Resolution (Alternative Tap Definition). Figure 1: Detail of a delay locked loop depicting the important delays within the loop (notice the alternative location of tap 0).
201
Appendix G. DNL-aware Algorithms for the RC Delay Line Calibration. Figure 1: Calibration procedure for the tap selection adjustment scheme.
204
Figure 2: The coarse calibration procedure.
206
Figure 3: The fine calibration procedure (first loop).
207
Figure 4: The fine calibration procedure (second loop).
208
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List of Tables. PART I. Introduction. Chapter 1. Introduction and Structure of this Work. Chapter 2. Time Interval Measurements in HEP Experiments – An Introduction. Chapter 3. Conversion Basics. Chapter 4. Review of TDC Architectures. Table 1: Comparison between the different architectures discussed in the chapter.
44
PART II. A TDC Architecture based on an Array of Delay Locked Loops. Chapter 5. Architecture Overview. Chapter 6. Analysis of the Limits to the TDC Resolution. Chapter 7. Detailed Implementation. Table 1: Summary of noise sensitivity and power consumption analysis.
90
Table 2: Summary of noise sensitivity and power consumption analysis for the proposed cell.
92
Chapter 8. Experimental Results. Table 1: Locking status for each working range, after the initialisation procedure.
101
Table 2: Summary of the linearity obtained for each DLL in the array (LSBDLL=4·LSB and LSBDLL-PS=5·LSB).
104
Table 3: Characteristics of the TDC prototype.
109
PART III. A TDC Architecture based on a DLL and a Passive RC Delay Line. Chapter 9. Architecture Overview. Chapter 10. The Adjustable RC Delay Line using a Tap Selection Scheme. Table 1: Comparison of the two proposed algorithms.
143
Table 2: Register (accumulator) requirements for the two proposed algorithms.
143
Table 3: Comparator requirements for the two proposed algorithms.
144
Chapter 11. The Adjustable RC Delay Line using a Variable Lumped Capacitor Scheme. Table 1: Register (accumulator) requirements for the present algorithm.
153
Table 2: Comparator requirements for the present algorithm.
153
Chapter 12. Experimental Results. Table 1: Characteristics of the TDC prototype.
165
PART IV. Conclusion. Chapter 13. Summary of Results. Chapter 14. Future Developments. Table 1: Timing specification of the general purpose TDC.
178
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PART V. Appendixes. Appendix A. TDC Characterisation Test Bench.
Appendix B. Analysis of the DLL Closed Loop Behaviour. Appendix C. Analysis of the Effects of Cell Delay Mismatch on the Integral Non-linearity of a DLL. Appendix D. Number of Random Samples Required for TDC Characterisation. Appendix E. TDC Characterisation Hit Frequency. Appendix F. Analysis of the Limits to the TDC Resolution (Alternative Tap Definition). Appendix G. DNL-aware Algorithms for the RC Delay Line Calibration.
Page xviii
Glossary of Acronyms.
ADC
Analogue-to-Digital Converter
ADLL
Array of Delay Locked Loops
ALICE
A Large Ion Collider Experiment
ASIC
Application Specific Integrated Circuit
CDT
Code Density Test
CERN
European Organisation for Nuclear Research
CMRR
Common Mode Rejection Ratio
CMOS
Complementary Metal-Oxide-Silicon Field Effect Transistor Logic
CUT
Channel Under Test
DAQ
Data Acquisition System
D-FF
D-type Flip-Flop
DLL
Delay Locked Loop
DNL
Differential Non-Linearity
DUT
Device Under Test
HEP
High Energy Physics
HMPID
High-Momentum Particle Identification
HRTDC
High Resolution Time-to-Digital Converter
IC
Integrated Circuit
INL
Integral Non-Linearity
ITS
Inner Tracking System
JLCC
J-Leaded Chip Carrier
LADAR
Laser Radar
LHC
Large Hadron Collider
LIDAR
Light Detection and Ranging
LIP
Laboratório de Instrumentação e Física Experimental de Partículas
Page xix
LSB
Least Significant Bit
NMOS
N-Channel Metal-Oxide-Silicon Field Effect Transistor
PDF
Probability Density Function
PECL
Positive Emitter Coupled Logic
PHOS
Photon Spectrometer
PID
Particle Identification
PLCC
Plastic Leaded Chip Carrier
PLL
Phase Locked Loop
PMOS
P-Channel Metal-Oxide-Silicon Field Effect Transistor
RC
Resistive-Capacitive
RMS
Root Mean Square
TAC
Time-to-Amplitude Converter
TDC
Time-to-Digital Converter
T/D
Time-to-Digital
TOF
Time-of-Flight
TPC
Time Projection Chamber
VCDL
Voltage Controlled Delay Line
VCO
Voltage Controlled Oscillator
Page xx
PART I. INTRODUCTION.
Page 1
Page 2
Chapter 1. Introduction and Structure of this Work.
In this thesis we describe the development and demonstration of architectures adapted for the accurate measurement of short time intervals. High-resolution time measurements have been performed in the past using instruments based on analogue measurement techniques. These instruments were built using discrete components or using a single Integrated Circuit (IC) employing special high performance “analogue” technologies. Our goal is to evaluate and demonstrate architectures that are suitable for monolithic integration and which can be built in a standard CMOS technology. The ability to share the same time interpolator between several measurement channels is also a major aim of the work. Furthermore, it is intended that these architectures be implemented together with all the necessary digital signal processing circuitry to build a converter with full functionality. Although the emphasis of this work is the architecture development, we carried out detailed analysis of the critical circuitry that determines the timing performance of the converter. Domain of application of this work. The work was carried out at the “European Organisation for Nuclear Research” (CERN), in Geneva, as a collaboration between the Microelectronics group and the “Laboratório de Instrumentação e Física Experimental de Partículas” (LIP), Lisbon. Therefore, emphasis is given to the specific requirements of the High-Energy Physics experimental environment. Nevertheless, the conclusions we obtain from the work are applicable in any domain where high-resolution time measurements are required, for example in LIDAR (LIght Detection And Ranging) and LADAR (Laser rADAR) applications. Our work contains contributions that can be useful in the domain of phase and delay synthesis, in applications such as time bases for digital oscilloscopes, phase modulation and demodulation as well as phase synchronisation.
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Structure of the thesis. The structure of this thesis follows naturally the developments achieved along the duration of the work. It is divided into four parts, each describing a major milestone of the work. In the first part of this thesis, we start with an introduction to the subject. It includes a brief description of the goals of a High-Energy Physics experiment and the systems needed to achieve them. The necessity of high-resolution time measurements is emphasised together with the particular constrains of the experimental environment (Chapter 2.). A general overview of the interesting characteristics of a Time-to-Digital Converter (TDC) is given in the form of the set of characterisation metrics that we used throughout the work to evaluate the time performance of T/D converters. A short description of the effects of the quantisation error and of the different noise sources that may be present is also given (Chapter 3.). We then present a brief review of the common types of time interval measurement systems that have been used in the past, highlighting their advantages and disadvantages. This review includes recent proposals that aim at the same goals as the ones pursued in this work (Chapter 4.). In the second part of this thesis we develop the analysis carried out to evaluate an architecture based on an Array of Delay Locked Loops (ADLL). As a corollary of this evaluation, a TDC demonstrator was built based on this architecture. An overview of the time interpolation scheme resulting from the phase shifting of a number of Delay Locked Loops (DLL) is presented. We review the main features of the scheme, emphasising its inherent advantages and difficulties. A block diagram and a short description of the TDC prototype is presented, together with the estimated timing performance (Chapter 5.). A detailed analysis of the causes of non-linearity that degrade the performance of a DLL-based converter is derived and an analytical model that predicts their effects in the conversion characteristic is presented. This analysis is extended to the ADLL-based converter. A similar analysis is carried out for the phase noise generated due to the dynamics of the DLL operation (Chapter 6.). Having established a model for the causes and consequences of non-linearity and phase noise, the critical circuit blocks are then described. Ways to improve their performance and ensure that they match the required characteristics are proposed (Chapter 7.). We then proceed to present the experimental results obtained from the prototype TDC that was built based on this architecture, and demonstrate that these results are in accordance with the analysis carried out (Chapter 8.).
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Chapter 1: Introduction and Structure of this Work.
In the third part of this thesis, a new architecture suitable for low power operation is proposed. The basic building block of this architecture is also a DLL, but finer time interpolation is obtained using passive RC delay lines. The principle of operation of this new architecture is described. The main characteristics of the architecture are detailed, with an emphasis on the interesting properties of RC delay lines. Two alternative adjustable delay line schemes are proposed. A block diagram and a short description of the TDC prototype built using this architecture is presented and an estimation of the timing performance exposed (Chapter 9.). We then carry out the detailed analysis of the adjustable RC delay line based on a tap selection scheme. We develop a simulation model of the distributed delay line that includes all the significant devices (lumped or distributed) that contribute to its delay characteristics. We propose a method to derive the dimensions of each of the segments into which the line is divided based on the delay requirements as well as on the dimension of the surrounding circuitry. A few calibration algorithms are also proposed and their performance is illustrated based on simulated delay line conditions (Chapter 10.). The same kind of analysis is performed for the adjustable RC delay line based on a variable lumped capacitor scheme. We present different calibration algorithms (Chapter 11.). As a corollary of this part of the work we present the experimental results obtained from a demonstrator TDC built using this architecture. Based on these results, we validate our analysis and confirm that this architecture performs as expected (Chapter 12.). The concluding part of this work is divided into two chapters. In the first, we highlight the contributions and developments carried out during this work (Chapter 13.). In the second, we propose what amounts to be the logical conclusion of this work: a general purpose TDC architecture using the DLL / RC delay line based architecture that we developed. This TDC is able to perform alternatively low resolution measurements in a large number of integrated channels or high-resolution time measurements in a small number of integrated channels (Chapter 14.). Finally a few appendices, complimentary to the main text, are included. They expand and complete the explanations given in the main text. Of relevance is the description of the test bench that we developed specifically for TDC characterisation. This test bench was used throughout the work to evaluate the TDC prototypes that were built (Appendix A.).
Main contributions of this work. As the structure of the thesis makes clear, we will present two integrated circuits that demonstrate two different solutions for the multi-channel, high-resolution time measurement system requirements. Page 5
• A four channel high-resolution TDC. This IC implements the Array of Delay Locked Loops (ADLL) architecture. Apart from the extended dynamic range time interpolation core this circuit also integrates digital logic to perform important functions such as encoding, buffering and read-out management. • A two channel high-resolution TDC. This IC implements a novel time interpolation architecture, based on a DLL and a passive RC delay line. This architecture allows for higher resolution with lower power operation. Some important results were obtained while designing these circuits. They are presented in this work: • A detailed study of the behaviour of a Delay Locked Loop (DLL) was carried out. We show how different error mechanisms affect the accuracy of the time interpolation and propose solutions to minimise these effects. • These studies are extended to the more complex case of the Array of DLL’s (ADLL). We show that for a given device mismatch level, there is an optimal interpolation factor (number of DLL’s in the array) that results in a consequent improvement of the resolution of a converter built this way. • An alternative architecture that avoids some of the limitations identified on the ADLL-based architecture, such as power dissipation and maximum resolution that can be obtained. • A procedure to compensate for technological tolerances in tapped passive RC delay lines is proposed. We proceed to present several methods to characterise and adjust these lines. We then analyse the possibility of integrating the adjustment algorithms in the same IC. Related publications. The contributions made during the course of this research led to the following publications: Mota, M., Christiansen, J., A high-resolution time interpolator based on a Delay Locked Loop and an RC delay line, IEEE Journal of Solid-State Circuits, vol. 34, no. 10, pp. 1360-1366, Oct. 1999. Mota, M., Christiansen, J., A four channel, self –calibrating, high-resolution Timeto-Digital Converter, Proceedings of the 5th. IEEE International Conference on Electronics, Circuits and Systems (ICECS’98), Lisboa, Portugal, Sep. 1998. Mota, M., Christiansen, J., A high-resolution Time-to-Digital Converter based on an Array of Delay Locked Loops, Proceedings of the 3rd. Workshop on Electronics for LHC Experiments, London, UK, Sep. 1997.
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Chapter 1: Introduction and Structure of this Work.
Almasi, L. et al., New TDC electronics for a PesTOF tower – in NA49, ALICE/2000-02 internal note/TOF, Mar. 2000. Mota, M., A high-resolution Time-to-Digital Converter – users manual, CERN/EP internal note, Geneva, Switzerland, 1997. Contributions in the field of microelectronics applied to the High-Energy Physics domain led to the following additional publications: Mota, M., Gomes, P., Christiansen, J., MEC3 – A pipelined zero-suppression and trigger matching chip, IEEE Transactions on Nuclear Science, vol. 42, no. 4, pt. 1, pp. 808-811, Aug. 1995. Gomes, P., Mota, M., Christiansen, J., NANA – An integrated signal processor and record builder for level-2 read-out of asynchronous event-filtering digital pipelines, IEEE Transactions on Nuclear Science, vol. 42, no. 4, pt.1, pp. 849-853, Aug. 1995.
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Chapter 2. Time Interval Measurements in HEP Experiments – An Introduction.
High-Energy Physics (HEP), or particle physics, is the discipline that explores and tries to understand the deep structure of matter [1]. As the discipline evolved, some models where developed to explain this structure. As in any scientific endeavour, the particle physicist is not satisfied until his theoretical developments – the models – have been demonstrated by experimental means. His experiments may, however, bring to light finer, and not completely understood, phenomena. The cycle of scientific progress is now closed: new models have to be developed which require the elaboration of new and more performant experiments to verify them.
2.1.
High-Energy Physics experiments.
The quest for the structure of the matter has been a progressive effort. In parallel with this effort, and enabling it, a big development effort has been dedicated to the design of new and more powerful machines that act as “microscopes” exposing the ever smaller and hidden constituents of the matter. These “microscopes” take the form of particle accelerators, where bunches of particles (for example ions, protons, electrons, etc) accelerated to very high energies are made to collide. The interaction between these particles, due to the bunch collision, results in the conversion of the original particles into a diversity of new particles, in a process akin to the breaking up of a nucleus into its constituent protons and neutrons, when bombarded by other energetic particles. It’s these new particles that are the object of the attention of the physicist, since they explain how the original particle is made and how it interacts with its environment. Surrounding the interaction point (where bunches of particles collide) is a complex set of detectors, sensitive to the different kinds of particles generated at the interaction moment. As these resulting particles transverse the detectors, some of their energy is captured by the detector, which converts it into an electrical signal (charge, current or voltage). This signal is then amplified and processed by the front-end electronics from where it is transferred to powerful computers.
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Traditionally, only the pre-amplifier would be mounted close to the respective detector cell. Its function was to optimally shape the detector signal and drive it through 15 to 50 meters of cable up to the electronics hut, where all the front-end processing would be performed. In modern experiments, where very high granularity is needed, with well over 106 cells with independent sensors, this topology is no longer applicable. Fortunately, state-of-the-art technology can be used to integrate the required front-end electronics into a limited number, or even a single ASIC (Application Specific Integrated Circuit) that can be directly mounted on the detector. In this way, a vast quantity of cables is avoided and a higher function density and lower power dissipation is achieved [2]. All the phenomena that are studied in a HEP experiment abide to statistical laws. The quantities that are to be measured with a detector sensor, either the amount energy deposited or the moment and position of the particle crossing also include some uncertainty in relation to their exact value. Therefore, multiple similar events must be analysed, the standard deviation of their statistical distribution being of relevance to their identification. 2.1.1.
A HEP experiment at CERN1: ALICE.
One of such detector systems is being developed in the context of the ALICE collaboration (A Large Ion Collider Experiment) [3]. The main goal of this collaboration is to study experimentally the collision of heavy ions (for example, lead ions) at high energy densities.
Figure 1: The CERN particle accelerator complex (simplified) [4].
These ions are accelerated to very high energies by a group of accelerator machines connected in series that culminate on the Large Hadron Collider (LHC), a 27Km 1
CERN: European Organisation for Nuclear Research, Geneva, Switzerland.
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Chapter 2: Time Interval Measurements in HEP Experiments – An Introduction.
perimeter circular accelerator. The LHC will include the interaction point where the ALICE detector will be built to observe the particle collision (see Figure 1). The LHC accelerator itself is made of two identical rings where bunches of ions (or, alternatively, protons) travel in opposite directions with high energy. In the interaction points, the two rings intercept and the particle bunches are allowed to collide. The detector system itself is a group of detectors [3], each optimised to observe different ranges of particles emerging from the interaction point. These detectors comprise an Inner Tracking System (ITS) with six layers of high-resolution silicon tracking detectors, a cylindrical Time Projection Chamber (TPC) and finally a large area Particle IDentification (PID) array of Time-Of-Flight (TOF) counters. The TPC is the main tracking system of the experiment. The ITS in mainly used for detailed reconstruction of the vertex of the interaction very close to its origin. Both of them also aid the PID detector in the identification of particles. In addition, a few specialised detectors are included: the electromagnetic calorimeter (PHOS – PHOton Spectrometer), the High Momentum PID (HMPID), the muon spectrometer and others. An outer magnet is necessary to bend the trajectory of charged particles, thereby easing their identification (Figure 2). Particle are identified by two different mechanisms. Low and medium momentum particles are identified, respectively, in the ITS and in the TPC by the dE/dx technique (the rate at which they loose energy as they transverse the detector). Higher momentum particles are identified in the PID detector using the TOF technique (the time that the particle takes to progress from the interaction point to the detector surface).
Figure 2: Longitudinal and transverse view of the ALICE detector [3].
The amount of data generated after each bunch collision (or event) is very large. To reduce the bandwidth requirements on the data acquisition (DAQ) system, and also the
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amount of memory needed for data storage, on-line data reduction algorithms are applied to the data. The data reduction algorithms take advantage of the spatial and temporal characteristics of the events: only a limited number of detector cells are actually crossed by an emerging particle. The output of the other, idle, cells can safely be discarded since it contains no information. This operation is called “zero-suppression”. Furthermore, not all the events are interesting to study. It is possible to implement in hardware algorithms that sample the data of selected detectors to decide if an event includes some interesting characteristics that deserve further attention. Otherwise, all data pertaining to that event may be discarded. This operation is called “trigger based data reduction”. In general, several levels of trigger based data reduction are implemented. They correspond to a hierarchy of data reduction algorithms that are progressively more selective. However, they are also more complex and slow.
Figure 3: The hierarchical trigger data reduction block diagram of the ALICE experiment [3].
The principle of the trigger based data reduction hierarchy in ALICE is pictured in Figure 3 [3]. A first level of data reduction (L0) is used simply to signal the existence of an interaction as soon as possible. It is not a very selective filter. The second level of data reduction (L1) already uses information on the quality of the event to produce a large reduction in accepted event rate. Both of these trigger processors produce a decision with a fixed latency. After the L1 trigger decision is taken, the read-out of the data from all detectors is started, pending the more selective decision of the third level trigger (L2). At Page 12
Chapter 2: Time Interval Measurements in HEP Experiments – An Introduction.
that moment, the read-out of the detector’s data into the DAQ system can be finalised. Overall, an event rate reduction of the order of 103 is obtained. Consequently, the bandwidth of the DAQ system that is needed is proportionally reduced.
2.2.
High-resolution time interval measurements in ALICE.
The efficiency of the particle identification using the TOF technique is directly related to its time resolution. This is especially critical in the higher momentum side of the identification range [5]. As a consequence, the TOF detector in the ALICE experiment is an array of sensors (counters) having a high time resolution (from σdet~40ps to 100ps, depending on the detector technology chosen). The detector sensor is only a small part of the system. The front-end electronics also generate some time uncertainties that will add up to the intrinsic detector resolution, limiting the overall time resolution of the system. A simplified view of the front-end electronics proposed for the TOF detector is shown in Figure 4. The time of flight of the particle resulting from the interaction is the difference between the instant when the interaction occurred, t0, which is captured by a specialised detector (the t0 detector) and the instant when the emerging particle transverses the TOF detector surface. Traditionally, this time interval would be measured in a single device (a Time-toDigital Converter – TDC). However, the dimensions of the detector system (>150,000 cells distributed over ~100m2) render impractical the distribution of t0 over the whole system. A better solution is to rely on the reference clock (clkref), which has to be distributed anyway, as the time reference of the measurements. Each limit of the time interval can then be measured individually and later subtracted digitally to obtain the original interval. 7m TDC
TOF detector cells
3.5m Interaction
t0 detector
clkref distribution
pre-amplifier & discriminator time of flight TDC
time of interaction (bunch ID)
Figure 4: Schematic view of the TOF detector front-end.
The actual interaction and crossing instants are reflected in the timing characteristics of the electrical signal that the respective detector generates. These signals are the object
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of some processing (amplification, discrimination, etc) in order to render them usable by the TDC that converts the timing information they carry into a binary word. The timing uncertainties created by such processing, and by the digital conversion procedure, must be added to the intrinsic uncertainty of the TOF and t0 detectors (σdet and σt0, respectively) in order to obtain the overall time resolution of the system.
σt0
σdet
detector cell (t0 / TOF)
σfe
σfe
front-end electronics (pre-amp & discriminator)
σTDC
σTDC
TDC
σclk
σclk
clkref distribution
clkref Figure 5: The error propagation chain.
In such a distributed system, it is reasonable to assume that all the time uncertainties generated in the different blocks are uncorrelated. Therefore, following the error propagation scheme of Figure 5, the time uncertainty of the TOF system is: 2 2 2 σTOF = σ t20 + σ 2det + 2 ⋅ σ 2fe + 2 ⋅ σTDC + 2 ⋅ σ clk ,
where, for simplicity, the time uncertainty of the front-end block (σfe), of the T/D converter (σTDC) and of the clock distribution network (σclk) were considered having the same statistical properties in the two independent chains. If the intrinsic time resolution of the detector is to be respected, it is important to minimise the time uncertainty created by all the electronic components of the chain. The overall contribution of the electronics should only be a small fraction of the time uncertainty of the complete TOF system. To obtain an overall time uncertainty better than σTOF=150ps, as required by the ALICE experiment, the resolution of the T/D converter must be σTDC T2 Reset Stop
T2
T2 Tap 0
T2 Tap 1
T2 Tap 2
T2 Tap 3
Tap 4
Figure 8: Circular vernier scheme for dynamic range expansion.
Both the “start” and “stop” signals are fed into the respective delay line via a multiplexer. As soon as these signals are progressing within the delay line, the Page 36
Chapter 4: Review of TDC Architectures.
multiplexers are switched thereby establishing a ring oscillator like structure. Counting the number of oscillations completed by each of the signals before they coincide enables the correct expansion of the dynamic range. Unfortunately the inversion of the signal propagating on these ring oscillators makes the decoding of the moment when the two signals coincide difficult. Solutions have been proposed where different structures are used to detect the coincidence of the two signals in a different way depending on the number of oscillations that occurred in each oscillator [35]. However the usage of different structures in the time critical circuitry makes it hard to equalise their dynamic response in all conditions. This may produce considerable non-linearity on the conversion transfer function. Another undesirable side effect of this closed loop topology is that all timing errors that may occur during the measurement time (due to noise or any other source) will accumulate in the final measurement. This scheme has the property of integrating all the errors present during the measurement time. Calibration, using a PLL-like control around the closed delay line may only be done off-line, when there are no measurements. In a high hit rate environment calibration can only be performed infrequently, which may result in loss of accuracy. Furthermore, coupling between the two closed delay lines may also be a problem. Due to layout considerations they should be implemented close together, and to obtain good resolution, their oscillation frequency (delay of cells) should be very similar. If coupling is present and there is no active control of the lines during measurement, one of the lines may be pulled to oscillate at the frequency of the other line, which would ruin the measurement. To avoid this problem, calibration can be performed using a dummy channel in a double PLL like structure. Control information derived from it can be used to control the delay of the lines even when measurements are being performed. In this way all the lines are actively pulled to their correct oscillation frequency. The calibration circuitry can be shared between all channels in a circuit, therefore resulting in an efficient use of silicon. Dual scale vernier method. There is an alternative implementation of the vernier technique where the dead time between measurements is small and the converter is self-calibrating. Contrary to previous techniques, this technique results in time stamp measurements. The principle of operation is the same as the vernier caliber (Figure 9) used to measure length [36]. Two scales are required, the reference scale, which has a time bin T and the vernier scale, which has a time bin slightly shorter, but spans N reference bins. The difference between the two scales determines the bin size of the converter. For example, to obtain a bin of 0.1·T the vernier scale must span 9 reference bins, being divided into 10 time bins. A measurement word is made of two components, the higher order bits are obtained from the reference scale and the lower order bits form the vernier scale.
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0
1
0.43
Figure 9: A vernier caliber measuring a length of 0.43 mm. Note that the third tick mark in the vernier scale (lower) lines up with a tick mark in the reference scale (upper) [36].
The reference scale can be made with a counter counting cycles of a reference clock. The vernier scale is, for example, a DLL calibrated delay line that spans 9 clock cycles and is divided into 10 time bins1. When the hit signal is asserted the status of the two scales is captured. The low order bits of the measurement result from the identification of the next bin that will switch. If this bin number is n, then the resulting time measure is: 1 t = Mod 1 − ⋅ T ⋅ n, T + m ⋅ T , F where Mod(a,b) is the modulus operation, F is the interpolation factor and m is the reference scale measurement. The number of time bins into which the vernier line is divided is equal to the interpolator factor F. The number N of clock cycles that it spans is F-1. This technique is very sensitive to the accumulation of non-linearity along the vernier delay line. This sensitivity is amplified if a high interpolation factor is implemented since the length of the line is increased and the LSB is shortened. 4.2.3.
Analogue time interpolation.
In a locked DLL, the signals propagating through the delay chain have edges with almost constant slopes, directly related to the delay of the delay elements. By performing an analogue sum of the signals in consecutive time taps, it is possible to obtain a time interpolation between these taps, thereby increasing the resolution to a level that is better than the intrinsic delay of a delay cell (Figure 10). The design of such a system is made difficult by the need to match the delay through the summing circuitry with the direct signal from the taps themselves. An alternative approach is to store all the analogue voltages from each tap when a hit occurs, and later perform the interpolation, either by analogue summing, or by using the stored voltages as inputs to a weighted filter which output would then be converted using an ADC. 1
In fact the delay line includes many more delay elements to avoid interactions between leading and trailing edges of the signal that progresses in it. Page 38
Chapter 4: Review of TDC Architectures.
Clock
Phase Detector
+
+
+
Hit
+
+
Charge Pump
+
Hit registers
Figure 10: Time interpolation using voltage sums.
Small ring oscillators, controlled by a PLL structure, can also be used as the basis of the time interpolation [37]. First order equalisation of the delay between different time taps is obtained by including a dummy analogue phase interpolator (weighted sum of the voltage at its two inputs) in the non-interpolating taps. In this scheme the phase interpolator circuit must be calibrated to improve the linearity of the interpolation. Other interpolation techniques try to generate the voltage ramp typical of current integration schemes in a “digital” form [38]. As the “start” signal progresses along the delay line, a voltage ladder is generated on the summing node. Each step represents the crossing of a new delay cell by the “start” signal. A high order filter can be used to smooth out the edges of the steps, thus obtaining the intended voltage ramp. The “stop” signal forces each delay cell into high impedance and disconnects the hold capacitor at the filter’s output, allowing the resulting measurement to be kept stable for the time necessary to process it via an ADC. 1 Stop
Start
Q
enable
0 16 digital gates with tri-statable outputs
Q 1 0
R
R
R
R
R
Reset High order filter
*1
Analog output
*1
Hold capacitor
Figure 11: Time to analogue converter using a time interpolation technique [38].
When compared to current integration techniques, this scheme has the advantage of being potentially less sensitive to noise coupling into the summing node. Since the interpolation is done resistively, the node has much less impedance than a capacitive node and there is no integration of noise effects over the measurement period. To convert the Page 39
measurement into a binary word, an ADC must be used, which will increase power dissipation and system costs. 4.2.4.
Array of coupled oscillators.
Some techniques have been proposed to increase the resolution of PLL based time interpolation circuits to time intervals smaller than the intrinsic gate delay. One way of achieving this is to use an array of coupled oscillator rings [39]. Each delay cell is made of a dual input voltage controlled buffer. Both inputs have the same polarity and together they define the output transition time. One of the inputs is used to form the ring oscillator, the other to couple consecutive ring in the array as shown in Figure 12. If a fixed phase shift is established between two consecutive oscillators, then the identical coupling between oscillators will create a uniform phase shift between all oscillators. The oscillation frequency remains the same for all oscillators. The time resolution achieved is the cell delay (td in Figure 12) divided by the number of rings in the array. The fixed phase shift is established by connecting the outputs of the boundary oscillator to the inputs of a cell located in a different position on the oscillator in the opposite extreme of the array. In this architecture the time bin is defined by two closely coupled delay cells that belong to separate ring oscillators. The inter-coupling between consecutive rings forces the size of each time bin to be set by the complete array. This intimate coupling guarantees a good linearity of the conversion function. However, device matching is a critical parameter for this topology. T4
T5
T1
T2
T3
T2
T3
T4
T5
td
T1
Figure 12: Coupled oscillators (time resolution of td * 2 / 3).
At initialisation time several modes of oscillation for which the array’s boundary conditions are met will be present. Each corresponds to the case of having a phase shift between the boundary oscillators that is a multiple of the oscillation period. The locking Page 40
Chapter 4: Review of TDC Architectures.
procedure has to be able to force the circuit into the correct mode, where phase shift is smaller than one oscillation period. This task may not be trivial. The resolution achievable with this architecture is defined as: Tbin =
x ⋅ T + k ⋅ T (2 ⋅ N ) , M
where T is the oscillation period set by a PLL control loop, N is the number of delay cells per oscillator and M is the number of oscillators in the array. Variable k reflects coupling topology of the boundary oscillators (offset in number of delay cells) and x the arrays’ modes of oscillation. The correct mode of oscillation is when x= 0. It results in the smallest bin size. Layout of these circuits is critical to their correct behaviour. Every delay cell must drive exactly the same load, if a good linearity of the measurements is to be maintained. Therefore, a good layout of the consecutive rings is essential in order to guarantee that the rings on the extreme of the array are in the same conditions as the rings in the middle and that there is no systematic effect that affects the size of some time bins. The same considerations apply to the delay cells on the extreme of each ring. Interleaving oscillators and the delay cells that make them is, therefore, essential. This architecture enables high time resolution and large dynamic range in a conveniently dead-timeless converter system. It can be implemented in standard CMOS technologies, thereby allowing for high levels of integration and low system costs. However it suffers from the same drawbacks of other PLL’s such as sensitivity to VCO internal noise and error feedback from the end to the beginning of each oscillator ring, etc. Sharing the array of coupled oscillators between several channels is an effective way to compensate for the higher power dissipation required by the use of several ring oscillators. 4.2.5.
Array of Delay Locked Loops.
The use of an array of several uniformly offset DLL’s can increase the resolution of a system to a fraction of the intrinsic gate delay [23][40]. A different DLL (herein referred as Phase Shifting DLL), made with a smaller number of delay elements, is used to precisely generate the required offsets. In order to increase the resolution of the converter, the offset between DLL’s should only be a fraction of the delay of the basic cell. This fraction cannot be obtained directly, but a delay that is a fraction bigger than the basic cell delay is easily obtained using a phase shifting DLL locked to the same reference. An arrangement like the one in Figure 13, due to the symmetry of the array, is made to look like the DLL’s in the array are only offset by a fraction of the basic cell delay. The time bin of such a circuit is
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Tbin = Tm − Tn =
Tclk Tclk − . M N
If the required time bin size is a fraction F of the basic cell delay of the DLL’s of the array, then the relation between M, N and F can be expressed as M =N⋅
F , F +1
where M, N and F are integers. One disadvantage of this scheme is its inability to divide the reference period in a number of bins that is a power of two. This means that the measurement obtained will not be in a pure binary unit of 1/2N, but rather in a unit of 1/(N·F). A special encoder that converts this code into a normal binary code must be used, if it is to be used together with other binary measurements such as dynamic range extension using the coarse time counter results. Clk
N
φ1
tn tm
φ2
Vc
φ1
tn
φ2
Vc
φ1
tn
M
φ2
Vc
φ1
tn
φ2
Vc
M
