Rev. 1.22, Dec. 2010 M471B5773CHS M471B5273CH0
204pin Unbuffered SODIMM based on 2Gb C-die 78FBGA with Lead-Free & Halogen-Free (RoHS compliant)
datasheet
SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind. This document and all information discussed herein remain the sole and exclusive property of Samsung Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or otherwise. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. For updates or additional information about Samsung products, contact your nearest Samsung office. All brand names, trademarks and registered trademarks belong to their respective owners. ⓒ 2010 Samsung Electronics Co., Ltd. All rights reserved.
-1-
Rev. 1.22
datasheet
Unbuffered SODIMM
DDR3 SDRAM
Revision History Revision No.
History
Draft Date
Remark
Editor
1.0
- First Release
Dec. 2009
-
S.H.Kim
1.1
- Changed DIMM IDD Definition
Jan. 2010
-
S.H.Kim
- Added DIMM IDD Specification 1.2
- Added "CL5" to supported CL setting
Feb. 2010
-
S.H.Kim
1.21
- Corrected Typo.
Mar. 2010
-
S.H.Kim
1.22
- Corrected Typo.
Dec. 2010
-
S.H.Kim
-2-
Unbuffered SODIMM
datasheet
Rev. 1.22
DDR3 SDRAM
Table Of Contents 204pin Unbuffered SODIMM based on 2Gb C-die 1. DDR3 Unbuffered SODIMM Ordering Information........................................................................................................ 4 2. Key Features................................................................................................................................................................. 4 3. Address Configuration .................................................................................................................................................. 4 4. x64 DIMM Pin Configurations (Front side/Back Side)................................................................................................... 5 5. Pin Description ............................................................................................................................................................. 6 6. Input/Output Functional Description.............................................................................................................................. 7 7. Function Block Diagram: ............................................................................................................................................... 8 7.1 2GB, 256Mx64 Module (Populated as 1 rank of x8 DDR3 SDRAMs) ..................................................................... 8 7.2 4GB, 512Mx64 Module (Populated as 2 ranks of x8 DDR3 SDRAMs) ................................................................... 9 8. Absolute Maximum Ratings .......................................................................................................................................... 10 8.1 Absolute Maximum DC Ratings............................................................................................................................... 10 8.2 DRAM Component Operating Temperature Range ................................................................................................ 10 9. AC & DC Operating Conditions..................................................................................................................................... 10 9.1 Recommended DC Operating Conditions (SSTL-15).............................................................................................. 10 10. AC & DC Input Measurement Levels .......................................................................................................................... 11 10.1 AC & DC Logic Input Levels for Single-ended Signals .......................................................................................... 11 10.2 VREF Tolerances.................................................................................................................................................... 12 10.3 AC and DC Logic Input Levels for Differential Signals .......................................................................................... 13 10.3.1. Differential Signals Definition ......................................................................................................................... 13 10.3.2. Differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS) ............................................. 13 10.3.3. Single-ended Requirements for Differential Signals ...................................................................................... 14 10.3.4. Differential Input Cross Point Voltage ............................................................................................................ 15 10.4 Slew Rate Definition for Single Ended Input Signals............................................................................................. 15 10.5 Slew rate definition for Differential Input Signals ................................................................................................... 15 11. AC & DC Output Measurement Levels ....................................................................................................................... 16 11.1 Single Ended AC and DC Output Levels ............................................................................................................... 16 11.2 Differential AC and DC Output Levels ................................................................................................................... 16 11.3 Single-ended Output Slew Rate ............................................................................................................................ 16 11.4 Differential Output Slew Rate ................................................................................................................................ 17 12. DIMM IDD specification definition ............................................................................................................................... 18 13. IDD SPEC Table ......................................................................................................................................................... 20 14. Input/Output Capacitance ........................................................................................................................................... 21 15. Electrical Characteristics and AC timing ..................................................................................................................... 22 15.1 Refresh Parameters by Device Density................................................................................................................. 22 15.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ................................................................ 22 15.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin ................................................................. 22 15.3.1. Speed Bin Table Notes .................................................................................................................................. 26 16. Timing Parameters by Speed Grade .......................................................................................................................... 27 16.1 Jitter Notes ............................................................................................................................................................ 30 16.2 Timing Parameter Notes........................................................................................................................................ 31 17. Physical Dimensions : ................................................................................................................................................. 32 17.1 256Mbx8 based 256Mx64 Module (1 Rank) - M471B5773CHS ........................................................................... 32 17.2 256Mbx8 based 512Mx64 Module (2 Ranks) - M471B5273CH0 .......................................................................... 33
-3-
Rev. 1.22
datasheet
Unbuffered SODIMM
DDR3 SDRAM
1. DDR3 Unbuffered SODIMM Ordering Information Number of Rank
Part Number2
Density
Organization
M471B5773CHS-CF8/H9/K0
2GB
256Mx64
256Mx8(K4B2G0846C-HC##)*8
1
30mm
M471B5273CH0-CF8/H9/K0
4GB
512Mx64
256Mx8(K4B2G0846C-HC##)*16
2
30mm
Component Composition
Height
NOTE : 1. "##" - F8/H9/K0 2. F8 - 1066Mbps 7-7-7 / H9 - 1333Mbps 9-9-9 / K0 - 1600Mbps 11-11-11 - DDR3-1600(11-11-11) is backward compatible to DDR3-1333(9-9-9), DDR3-1066(7-7-7) - DDR3-1333(9-9-9) is backward compatible to DDR3-1066(7-7-7)
2. Key Features Speed
• • • • • • • • • • • • •
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
6-6-6
7-7-7
9-9-9
11-11-11
Unit
tCK(min)
2.5
1.875
1.5
1.25
ns
CAS Latency
6
7
9
11
tCK
tRCD(min)
15
13.125
13.5
13.75
ns
tRP(min)
15
13.125
13.5
13.75
ns
tRAS(min)
37.5
37.5
36
35
ns
tRC(min)
52.5
50.625
49.5
48.75
ns
JEDEC standard 1.5V ± 0.075V Power Supply VDDQ = 1.5V ± 0.075V 400 MHz fCK for 800Mb/sec/pin, 533MHz fCK for 1066Mb/sec/pin, 667MHz fCK for 1333Mb/sec/pin, 800MHz fCK for 1600Mb/sec/pin 8 independent internal bank Programmable CAS Latency: 5,6,7,8,9,10,11 Programmable Additive Latency(Posted CAS) : 0, CL - 2, or CL - 1 clock Programmable CAS Write Latency(CWL) = 5 (DDR3-800), 6 (DDR3-1066), 7 (DDR3-1333) and 8 (DDR3-1600) Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4 which does not allow seamless read or write [either On the fly using A12 or MRS] Bi-directional Differential Data Strobe Internal(self) calibration : Internal self calibration through ZQ pin (RZQ : 240 ohm ± 1%) On Die Termination using ODT pin Average Refresh Period 7.8us at lower then TCASE 85°C, 3.9us at 85°C < TCASE ≤ 95°C Asynchronous Reset
3. Address Configuration Organization
Row Address
Column Address
Bank Address
Auto Precharge
256Mx8(2Gb) based Module
A0-A14
A0-A9
BA0-BA2
A10/AP
-4-
Rev. 1.22
datasheet
Unbuffered SODIMM
DDR3 SDRAM
4. x64 DIMM Pin Configurations (Front side/Back Side) Pin
Front
Pin
Back
Pin
Front
Pin
Back
Pin
Front
Pin
Back
1
VREFDQ
2
VSS
71
VSS
72
VSS
139
VSS
140
DQ38
3
VSS
4
DQ4
141
DQ34
142
DQ39
5
DQ0
6
DQ5
73
CKE0
74
CKE1
143
DQ35
144
VSS
7
DQ1
8
VSS
75
VDD
76
VDD
145
VSS
146
DQ44
9
VSS
78
A153
147
DQ40
148
DQ45
3
149
DQ41
150
VSS
151
VSS
152
DQS5
10
DQS0
KEY
77
NC
11
DM0
12
DQS0
79
BA2
80
A14
13
VSS
14
VSS
81
VDD
82
VDD
15
DQ2
16
DQ6
83
A12/BC
84
A11
153
DM5
154
DQS5
17
DQ3
18
DQ7
85
A9
86
A7
155
VSS
156
VSS
19
VSS
20
VSS
87
VDD
88
VDD
157
DQ42
158
DQ46
21
DQ8
22
DQ12
89
A8
90
A6
159
DQ43
160
DQ47
23
DQ9
24
DQ13
91
A5
92
A4
161
VSS
162
VSS
25
VSS
26
VSS
93
VDD
94
VDD
163
DQ48
164
DQ52
27
DQS1
28
DM1
95
A3
96
A2
165
DQ49
166
DQ53
29
DQS1
30
RESET
97
A1
98
A0
167
VSS
168
VSS
31
VSS
32
VSS
99
VDD
100
VDD
169
DQS6
170
DM6
33
DQ10
34
DQ14
101
CK0
102
CK1
171
DQS6
172
VSS
35
DQ11
36
DQ15
103
CK0
104
CK1
173
VSS
174
DQ54
37
VSS
38
VSS
105
VDD
106
VDD
175
DQ50
176
DQ55
39
DQ16
40
DQ20
107
A10/AP
108
BA1
177
DQ51
178
VSS
41
DQ17
42
DQ21
109
BA0
110
RAS
179
VSS
180
DQ60
43
VSS
44
VSS
111
VDD
112
VDD
181
DQ56
182
DQ61
45
DQS2
46
DM2
113
WE
114
S0
183
DQ57
184
VSS
47
DQS2
48
VSS
115
CAS
116
ODT0
185
VSS
186
DQS7
49
VSS
50
DQ22
117
VDD
118
VDD
187
DM7
188
DQS7
50
DQ18
52
DQ23
119
A133
120
ODT1
189
VSS
190
VSS
53
DQ19
54
VSS
121
S1
122
NC
191
DQ58
192
DQ62
55
VSS
56
DQ28
123
VDD
124
VDD
193
DQ59
194
DQ63
57
DQ24
58
DQ29
125
TEST
126
VREFCA
195
VSS
196
VSS
59
DQ25
60
VSS
127
VSS
128
VSS
197
SA0
198
NC
61
VSS
62
DQS3
129
DQ32
130
DQ36
199
VDDSPD
200
SDA
63
DM3
64
DQS3
131
DQ33
132
DQ37
201
SA1
202
SCL
65
VSS
66
VSS
133
VSS
134
VSS
203
VTT
204
VTT
67
DQ26
68
DQ30
135
DQS4
136
DM4
69
DQ27
70
DQ31
137
DQS4
138
VSS
NOTE : 1. NC = No Connect, NU = Not Usable, RFU = Reserved Future Use 2. TEST(pin 125) is reserved for bus analysis probes and is NC on normal memory modules. 3. This address might be connected to NC balls of the DRAMs (depending on density); either way they will be connected to the termination resistor.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
-5-
Rev. 1.22
datasheet
Unbuffered SODIMM
DDR3 SDRAM
5. Pin Description Pin Name CK0, CK1 CK0, CK1 CKE0, CKE1
Description Clock Inputs, positive line
Number
Pin Name
Description
Number
2
DQ0-DQ63
Data Input/Output
64
Data Masks/ Data strobes, Termination data strobes
8 8
Clock Inputs, negative line
2
DM0-DM7
Clock Enables
2
DQS0-DQS7
Data strobes Data strobes complement
8
Reset Pin
1
Logic Analyzer specific test pin (No connect on SODIMM)
1
RAS
Row Address Strobe
1
DQS0-DQS7
CAS
Column Address Strobe
1
RESET
WE
Write Enable
1
TEST
S0, S1
Chip Selects
2
VDD
Core and I/O Power
18
Address Inputs
14
VSS
Ground
52
A10/AP
Address Input/Autoprecharge
1
VREFDQ VREFCA
Input/Output Reference
2
A12/BC
Address Input/Burst chop
1
VDDSPD
SPD and Temp sensor Power
1
BA0-BA2
SDRAM Bank Addresses
3
VTT
Termination Voltage
2
ODT0, ODT1
On-die termination control
2
NC
Reserved for future use
3
SCL
Serial Presence Detect (SPD) Clock Input
1
SDA
SPD Data Input/Output
1
SPD Address
2
A0-A9, A11, A13-A15
SA0-SA1
Total
NOTE: *The VDD and VDDQ pins are tied common to a single power-plane on these designs.
-6-
204
datasheet
Unbuffered SODIMM
Rev. 1.22
DDR3 SDRAM
6. Input/Output Functional Description Symbol
Type
Function
CK0-CK1 CK0-CK1
Input
The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and falling edge of CK. A Delay Locked Loop (DLL) circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock.
CKE0-CKE1
Input
Activates the DDR3 SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode.
S0-S1
Input
Enables the associated DDR3 SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by S1.
RAS, CAS, WE
Input
When sampled at the cross point of the rising edge of CK and falling edge of CK, signals CAS, RAS, and WE define the operation to be executed by the SDRAM.
BA0-BA2
Input
Selects which DDR3 SDRAM internal bank of eight is activated.
ODT0-ODT1
Input
Asserts on-die termination for DQ, DM, DQS, and DQS signals if enabled via the DDR3 SDRAM mode register.
A0-A9, A10/AP, A11 A12/BC A13-A15
Input
During a Bank Activate command cycle, defines the row address when sampled at the cross point of the rising edge of CK and falling edge of CK. During a Read or Write command cycle, defines the column address when sampled at the cross point of the rising edge of CK and falling edge of CK. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define which bank to precharge.A12(BC) is sampled during READ and WRITE commands to determine if burst chop (on-the fly) will be performed (HIGH, no burst chop; LOW, burst chopped)
DQ0-DQ63
I/O
DM0-DM7
Input
The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect.
DQS0-DQS7 DQS0-DQS7
I/O
The data strobes, associated with one data byte, sourced with data transfers. In Write mode, the data strobe is sourced by the controller and is centered in the data window. In Read mode, the data strobe is sourced by the DDR3 SDRAMs and is sent at the leading edge of the data window. DQS signals are complements, and timing is relative to the crosspoint of respective DQS and DQS.
VDD,VDDSPD, VSS
Supply
Power supplies for core, I/O, Serial Presence Detect, Temp sensor, and ground for the module.
VREFDQ, VREFCA
Supply
Reference voltage for SSTL15 inputs.
SDA
I/O
SCL
Input
This signal is used to clock data into and out of the SPD EEPROM and Temp sensor.
SA0-SA1
Input
Address pins used to select the Serial Presence Detect and Temp sensor base address.
TEST
I/O
RESET
Input
Data Input/Output pins.
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM and Temp sensor. A resistor must be connected from the SDA bus line to VDDSPD on the system planar to act as a pull up.
The TEST pin is reserved for bus analysis tools and is not connected on normal memory modules RESET In Active Low This signal resets the DDR3 SDRAM
-7-
Rev. 1.22
datasheet
Unbuffered SODIMM
DDR3 SDRAM
7. Function Block Diagram:
S0 RAS CAS WE CK0 CK0 CKE0 ODT0 A[0:N] /BA[0:N]
7.1 2GB, 256Mx64 Module (Populated as 1 rank of x8 DDR3 SDRAMs)
240Ω
± 1% ZQ
D0
DQS1 DQS1 DM1 DQ[8:15]
240Ω
± 1% ZQ
D1
240Ω
± 1%
DQS3 DQS3 DM3 DQ[24:31]
DQS DQS DM DQ[0:7]
SCL A0 A1 A2
(SPD)
D4
240Ω
± 1% ZQ
D5
Vtt
Vtt
VDDSPD
SPD
VREFCA
D0 - D7
VREFDQ
D0 - D7
VDD
D0 - D7
VSS
D0 - D7, SPD
CK0
D0 - D7
CK0
D0 - D7
CK1
Terminated near card edge
CK1 S1
NC
ODT1
NC
CKE1
NC D0 - D7
RESET
± 1% ZQ
D2
DQS5 DQS5 DM5 DQ[40:47]
± 1% ZQ
D3
± 1% ZQ
D6
DQS7 DQS7 DM7 DQ[56:63]
DQS DQS DM DQ[0:7]
V1
V1
240Ω
± 1% ZQ
D4
D0
V2
V2
D5
D1
V3
V3
D6
D2
V4
V4
D7
D3
D7
CS RAS CAS WE CK CK CKE ODT A[0:N]/BA[0:N]
240Ω
CS RAS CAS WE CK CK CKE ODT A[0:N]/BA[0:N]
DQS DQS DM DQ[0:7]
240Ω
Vtt
DQS6 DQS6 DM6 DQ[48:55]
DQS DQS DM DQ[0:7]
Vtt
240Ω
CS RAS CAS WE CK CK CKE ODT A[0:N]/BA[0:N]
DQS DQS DM DQ[0:7]
CS RAS CAS WE CK CK CKE ODT A[0:N]/BA[0:N]
DQS4 DQS4 DM4 DQ[32:39]
SDA
WP
ZQ
CS RAS CAS WE CK CK CKE ODT A[0:N]/BA[0:N]
DQS DQS DM DQ[0:7]
CS RAS CAS WE CK CK CKE ODT A[0:N]/BA[0:N]
DQS2 DQS2 DM2 DQ[16:23]
DQS DQS DM DQ[0:7]
CS RAS CAS WE CK CK CKE ODT A[0:N]/BA[0:N]
DQS DQS DM DQ[0:7]
CS RAS CAS WE CK CK CKE ODT A[0:N]/BA[0:N]
DQS0 DQS0 DM0 DQ[0:7]
SCL SA0 SA1
Address and Controllines
Rank0 Vtt Vtt VDD
-8-
NOTE : 1. DQ wiring may differ from that shown however ,DQ, DM, DQS and DQS relationships are maintained as shown.
Rev. 1.22
datasheet
Unbuffered SODIMM
DDR3 SDRAM
7.2 4GB, 512Mx64 Module (Populated as 2 ranks of x8 DDR3 SDRAMs) VDD
VDD
240Ω
± 1% ZQ
CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]
D0
240Ω
± 1% ZQ
CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]
D2
SCL SA0 SA1
SCL A0 A1 A2
CK0 CK0 CKE0 ODT0
DQS DQS DM DQ[0:7]
240Ω
DQS DQS DM DQ[0:7]
± 1% ZQ
D9
240Ω
± 1% ZQ
D8
DQS DQS DM DQ[0:7]
Rank0 Rank1
240Ω
SDA
WP
NOTE : 1. DQ wiring may differ from that shown however ,DQ, DM, DQS and DQS relationships are maintained as shown
DQS DQS DM DQ[0:7]
DQS DQS DM DQ[0:7]
± 1% ZQ
D10
Vtt (SPD)
ZQ
240Ω
DQS DQS DM DQ[0:7]
± 1% ZQ
D14
240Ω
DQS DQS DM DQ[0:7]
± 1% ZQ
D15
240Ω
DQS DQS DM DQ[0:7]
± 1% ZQ
D13
Vtt
VDDSPD
SPD
VREFCA
D0 - D15
VREFDQ
D0 - D15
VDD
D0 - D15
VSS
D0 - D15, SPD
CK0
D0 - D7
CK1
D8 - D15
CK0
D0 - D7
CK1
D8 - D15
DQS4 DQS4 DM4 DQ[32:39]
± 1% ZQ
D12
CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]
D4
240Ω
240Ω
DQS6 DQS6 DM6 DQ[48:55]
± 1% ZQ
D6
CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]
S0 DQS DQS DM DQ[0:7]
DQS DQS DM DQ[0:7]
± 1%
240Ω
DQS7 DQS7 DM7 DQ[56:63]
± 1% ZQ
D7
CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]
CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]
D1
D3
240Ω
240Ω
DQS5 DQS5 DM5 DQ[40:47]
± 1% ZQ
D5
CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]
ZQ
ZQ
CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]
DQS DQS DM DQ[0:7]
± 1%
DQS DQS DM DQ[0:7]
± 1%
CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]
DQS2 DQS2 DM2 DQ[16:23]
240Ω
240Ω
CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]
DQS DQS DM DQ[0:7]
D11
DQS DQS DM DQ[0:7]
Vtt
CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]
DQS0 DQS0 DM0 DQ[0:7]
ZQ
CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]
DQS DQS DM DQ[0:7]
± 1%
CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]
DQS1 DQS1 DM1 DQ[8:15]
240Ω
CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]
DQS DQS DM DQ[0:7]
CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]
DQS3 DQS3 DM3 DQ[24:31]
Vtt
CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]
S1 RAS CAS WE CK1 CK1 CKE1 ODT1 A[0:N] /BA[0:N]
Vtt
D9
V2
D3
V1 V9
V3 D8
D0
V4 V4
D10
D2
V3 D1
V2
D11
V5 V1 V5 Vtt V1 V9
D12
V8
D6 V7
D5
D13
V6 V6
D7
D15 V7
D4
V8
D14
D0 - D7
RESET
Address and Controllines
-9-
Rev. 1.22
datasheet
Unbuffered SODIMM
DDR3 SDRAM
8. Absolute Maximum Ratings 8.1 Absolute Maximum DC Ratings Symbol
Parameter
Rating
Units
NOTE
VDD
Voltage on VDD pin relative to VSS
-0.4 V ~ 1.975 V
V
1,3
VDDQ
Voltage on VDDQ pin relative to VSS
-0.4 V ~ 1.975 V
V
1,3
VIN, VOUT
Voltage on any pin relative to VSS
-0.4 V ~ 1.975 V
V
1
TSTG
Storage Temperature
-55 to +100
°C
1, 2
NOTE : 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. 3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must be not greater than 0.6 x VDDQ, When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV.
8.2 DRAM Component Operating Temperature Range Symbol
Parameter
rating
Unit
NOTE
TOPER
Operating Temperature Range
0 to 95
°C
1, 2, 3
NOTE : 1. Operating Temperature TOPER is the case surface temperature on the center/top side of the DRAM. For measurement conditions, please refer to the JEDEC document JESD51-2. 2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0-85°C under all operating conditions 3. Some applications require operation of the Extended Temperature Range between 85°C and 95°C case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply: a) Refresh commands must be doubled in frequency, therefore reducing the refresh interval tREFI to 3.9us. b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b), in this case IDD6 current can be increased around 10~20% than normal Temperature range.
9. AC & DC Operating Conditions 9.1 Recommended DC Operating Conditions (SSTL-15) Symbol VDD VDDQ
Parameter
Rating
Units
NOTE
1.575
V
1,2
1.575
V
1,2
Min.
Typ.
Max.
Supply Voltage
1.425
1.5
Supply Voltage for Output
1.425
1.5
NOTE: 1. Under all conditions VDDQ must be less than or equal to VDD. 2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
- 10 -
Unbuffered SODIMM
Rev. 1.22
datasheet
DDR3 SDRAM
10. AC & DC Input Measurement Levels 10.1 AC & DC Logic Input Levels for Single-ended Signals [ Table 1 ] Single Ended AC and DC input levels for Command and Address Symbol
DDR3-800/1066/1333/1600
Parameter
Unit
NOTE
VDD
mV
1,5
VSS
VREF - 100
mV
1,6
VREF + 175
NOTE 2
mV
1,2,7
VIL.CA(AC175) AC input logic low
NOTE 2
VREF - 175
mV
1,2,8
VIH.CA(AC150) AC input logic high
VREF+150
NOTE 2
mV
1,2,7
NOTE 2
VREF-150
mV
1,2,8
0.49*VDD
0.51*VDD
V
3,4
Min.
Max.
VIH.CA(DC100) DC input logic high
VREF + 100
VIL.CA(DC100) DC input logic low VIH.CA(AC175) AC input logic high
VIL.CA(AC150) AC input logic low VREFCA(DC)
Reference Voltage for ADD, CMD inputs
NOTE : 1. For input only pins except RESET, VREF = VREFCA(DC) 2. See ’Overshoot/Undershoot Specification’ on page 18. 3. The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than ± 1% VDD (for reference : approx. ± 15mV) 4. For reference : approx. VDD/2 ± 15mV 5. VIH(dc) is used as a simplified symbol for VIH.CA(DC100) 6. VIL(dc) is used as a simplified symbol for VIL.CA(DC100) 7. VIH(ac) is used as a simplified symbol for VIH.CA(AC175) and VIH.CA(AC150); VIH.CA(AC175) value is used when VREF + 175mV is referenced and VIH.CA(AC150) value is used when VREF + 150mV is referenced. 8. VIL(ac) is used as a simplified symbol for VIL.CA(AC175) and VIL.CA(AC150); VIL.CA(AC175) value is used when VREF - 175mV is referenced and VIL.CA(AC150) value is used when VREF - 150mV is referenced.
[ Table 2 ] Single Ended AC and DC input levels for DQ and DM Symbol
Parameter
DDR3-800/1066 Min.
DDR3-1333/1600 Max.
Min.
Max.
Unit
NOTE
mV
1,5
VIH.DQ(DC100) DC input logic high
VREF + 100
VDD
VREF + 100
VDD
VIL.DQ(DC100) DC input logic low
VSS
VREF - 100
VSS
VREF - 100
mV
1,6
VIH.DQ(AC175) AC input logic high
VREF + 175
NOTE 2
-
-
mV
1,2,7
VIL.DQ(AC175) AC input logic low
NOTE 2
VREF - 175
-
-
mV
1,2,8
VIH.DQ(AC150) AC input logic high
VREF + 150
NOTE 2
VREF + 150
NOTE 2
mV
1,2,7
VIL.DQ(AC150) AC input logic low
NOTE 2
VREF - 150
NOTE 2
VREF - 150
mV
1,2,8
0.49*VDD
0.51*VDD
0.49*VDD
0.51*VDD
V
3,4
VREFDQ(DC)
Reference Voltage for DQ, DM inputs
NOTE : 1. For input only pins except RESET, VREF = VREFDQ(DC) 2. See ’Overshoot/Undershoot Specification’ on page 18. 3. The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than ± 1% VDD (for reference : approx. ± 15mV) 4. For reference : approx. VDD/2 ± 15mV 5. VIH(dc) is used as a simplified symbol for VIH.DQ(DC100) 6. VIL(dc) is used as a simplified symbol for VIL.DQ(DC100) 7. VIH(ac) is used as a simplified symbol for VIH.DQ(AC175), VIH.DQ(AC150) ; VIH.DQ(AC175) value is used when VREF + 175mV is referenced, VIH.DQ(AC150) value is used when VREF + 150mV is referenced. 8. VIL(ac) is used as a simplified symbol for VIL.DQ(AC175), VIL.DQ(AC150) ; VIL.DQ(AC175) value is used when VREF - 175mV is referenced, VIL.DQ(AC150) value is used when VREF - 150mV is referenced.
- 11 -
Rev. 1.22
datasheet
Unbuffered SODIMM
DDR3 SDRAM
10.2 VREF Tolerances. The dc-tolerance limits and ac-noise limits for the reference voltages VREFCA and VREFDQ are illustrate in Figure 1. It shows a valid reference voltage VREF(t) as a function of time. (VREF stands for VREFCA and VREFDQ likewise). VREF(DC) is the linear average of VREF(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirements of VREF. Furthermore VREF(t) may temporarily deviate from VREF(DC) by no more than ± 1% VDD.
voltage
VDD
VSS
time
Figure 1. Illustration of VREF(DC) tolerance and VREF ac-noise limits
The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on VREF. "VREF" shall be understood as VREF(DC), as defined in Figure 1. This clarifies, that dc-variations of VREF affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured. System timing and voltage budgets need to account for VREF(DC) deviations from the optimum position within the data-eye of the input signals. This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with VREF ac-noise. Timing and voltage effects due to ac-noise on VREF up to the specified limit (+/-1% of VDD) are included in DRAM timings and their associated deratings.
- 12 -
Rev. 1.22
datasheet
Unbuffered SODIMM
DDR3 SDRAM
10.3 AC and DC Logic Input Levels for Differential Signals 10.3.1 Differential Signals Definition
tDVAC Differential Input Voltage (i.e. DQS-DQS, CK-CK)
VIH.DIFF.AC.MIN
VIH.DIFF.MIN
0.0 half cycle
VIL.DIFF.MAX
VIL.DIFF.AC.MAX tDVAC time
Figure 2. Definition of differential ac-swing and "time above ac level" tDVAC
10.3.2 Differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS) Symbol
Parameter
VIHdiff
DDR3-800/1066/1333/1600
unit
NOTE
NOTE 3
V
1
NOTE 3
-0.2
V
1
differential input high ac
2 x (VIH(AC) - VREF)
NOTE 3
V
2
differential input low ac
NOTE 3
2 x (VIL(AC) - VREF)
V
2
min
max
differential input high
+0.2
VILdiff
differential input low
VIHdiff(AC) VILdiff(AC)
NOTE : 1. Used to define a differential signal slew-rate. 2. for CK - CK use VIH/VIL(AC) of ADD/CMD and VREFCA; for DQS - DQS use VIH/VIL(AC) of DQs and VREFDQ; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here. 3. These values are not defined, however they single-ended signals CK, CK, DQS, DQS, DQSL need to be within the respective limits (VIH(DC) max, VIL(DC)min) for singleended signals as well as the limitations for overshoot and undershoot. Refer to "overshoot and Undersheet Specification"
[ Table 3 ] Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS. Slew Rate [V/ns]
tDVAC [ps] @ |VIH/Ldiff(AC)| = 350mV
tDVAC [ps] @ |VIH/Ldiff(AC)| = 300mV
min
max
min
max
> 4.0
75
-
175
-
4.0
57
-
170
-
3.0
50
-
167
-
2.0
38
-
163
-
1.8
34
-
162
-
1.6
29
-
161
-
1.4
22
-
159
-
1.2
13
-
155
-
1.0
0
-
150
-
< 1.0
0
-
150
-
- 13 -
Rev. 1.22
datasheet
Unbuffered SODIMM
DDR3 SDRAM
10.3.3 Single-ended Requirements for Differential Signals Each individual component of a differential signal (CK, DQS, CK, DQS) has also to comply with certain requirements for single-ended signals. CK and CK have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels ( VIH(AC) / VIL(AC) ) for ADD/CMD signals) in every half-cycle. DQS, DQS have to reach VSEHmin / VSELmax (approximately the ac-levels ( VIH(AC) / VIL(AC) ) for DQ signals) in every half-cycle proceeding and following a valid transition. Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g. if VIH150(AC)/VIL150(AC) is used for ADD/CMD signals, then these ac-levels apply also for the single-ended signals CK and CK .
VDD or VDDQ
VSEH min
VSEH VDD/2 or VDDQ/2 CK or DQS VSEL max VSEL
VSS or VSSQ
time Figure 3. Single-ended requirement for differential signals
Note that while ADD/CMD and DQ signal requirements are with respect to VREF, the single-ended components of differential signals have a requirement with respect to VDD/2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For singleended components of differential signals the requirement to reach VSELmax, VSEHmin has no bearing on timing, but adds a restriction on the common mode characteristics of these signals.
[ Table 4 ] Single ended levels for CK, DQS, CK, DQS Symbol VSEH VSEL
Parameter
DDR3-800/1066/1333/1600
Unit
NOTE
NOTE 3
V
1, 2
(VDD/2)+0.175
NOTE 3
V
1, 2
NOTE 3
(VDD/2)-0.175
V
1, 2
NOTE 3
(VDD/2)-0.175
V
1, 2
Min
Max
Single-ended high-level for strobes
(VDD/2)+0.175
Single-ended high-level for CK, CK Single-ended low-level for strobes Single-ended low-level for CK, CK
NOTE : 1. For CK, CK use VIH/VIL(AC) of ADD/CMD; for strobes (DQS, DQS) use VIH/VIL(AC) of DQs. 2. VIH(AC)/VIL(AC) for DQs is based on VREFDQ; VIH(AC)/VIL(AC) for ADD/CMD is based on VREFCA; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here 3. These values are not defined, however the single-ended signals CK, CK, DQS, DQS need to be within the respective limits (VIH(DC) max, VIL(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to "Overshoot and Undershoot Specification"
- 14 -
Rev. 1.22
datasheet
Unbuffered SODIMM
DDR3 SDRAM
10.3.4 Differential Input Cross Point Voltage To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (CK, CK and DQS, DQS) must meet the requirements in below table. The differential input cross point voltage VIX is measured from the actual cross point of true and complement signal to the mid level between of VDD and VSS. VDD CK, DQS VIX VDD/2 VIX
VIX CK, DQS VSS Figure 4. VIX Definition
[ Table 5 ] Cross point voltage for differential input signals (CK, DQS) Symbol
DDR3-800/1066/1333/1600
Parameter
VIX
Differential Input Cross Point Voltage relative to VDD/2 for CK,CK
VIX
Differential Input Cross Point Voltage relative to VDD/2 for DQS,DQS
Unit
Min
Max
-150
150
mV
-175
175
mV
-150
150
mV
NOTE
1
NOTE : 1. Extended range for VIX is only allowed for clock and if single-ended clock input signals CK and CK are monotonic, have a single-ended swing VSEL / VSEH of at least VDD/2 ±250 mV, and the differential slew rate of CK-CK is larger than 3 V/ ns.
10.4 Slew Rate Definition for Single Ended Input Signals See "Address / Command Setup, Hold and Derating" for single-ended slew rate definitions for address and command signals. See "Data Setup, Hold and Slew Rate Derating" for single-ended slew rate definitions for data signals.
10.5 Slew rate definition for Differential Input Signals Input slew rate for differential signals (CK, CK and DQS, DQS) are defined and measured as shown in below. [ Table 6 ] Differential input slew rate definition Measured
Description Differential input slew rate for rising edge (CK-CK and DQS-DQS) Differential input slew rate for falling edge (CK-CK and DQS-DQS)
Defined by
From
To
VILdiffmax
VIHdiffmin
VIHdiffmin
VILdiffmax
NOTE : The differential signal (i.e. CK - CK and DQS - DQS) must be linear between these thresholds
VIHdiffmin 0 VILdiffmax
delta TRdiff
delta TFdiff
Figure 5. Differential input slew rate definition for DQS, DQS and CK, CK
- 15 -
VIHdiffmin - VILdiffmax Delta TRdiff VIHdiffmin - VILdiffmax Delta TFdiff
Rev. 1.22
datasheet
Unbuffered SODIMM
DDR3 SDRAM
11. AC & DC Output Measurement Levels 11.1 Single Ended AC and DC Output Levels [ Table 7 ] Single Ended AC and DC output levels Symbol
Parameter
DDR3-800/1066/1333/1600
Units
VOH(DC)
NOTE
DC output high measurement level (for IV curve linearity)
0.8 x VDDQ
V
VOM(DC)
DC output mid measurement level (for IV curve linearity)
0.5 x VDDQ
V
VOL(DC)
DC output low measurement level (for IV curve linearity)
0.2 x VDDQ
V
VOH(AC)
AC output high measurement level (for output SR)
VTT + 0.1 x VDDQ
V
1
VOL(AC)
AC output low measurement level (for output SR)
VTT - 0.1 x VDDQ
V
1
NOTE : 1. The swing of +/-0.1 x VDDQ is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40Ω and an effective test load of 25Ω to VTT=VDDQ/2.
11.2 Differential AC and DC Output Levels [ Table 8 ] Differential AC and DC output levels DDR3-800/1066/1333/1600
Units
NOTE
VOHdiff(AC)
Symbol
AC differential output high measurement level (for output SR)
Parameter
+0.2 x VDDQ
V
1
VOLdiff(AC)
AC differential output low measurement level (for output SR)
-0.2 x VDDQ
V
1
NOTE : 1. The swing of +/-0.2xVDDQ is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40Ω and an effective test load of 25Ω to VTT=VDDQ/2 at each of the differential outputs.
11.3 Single-ended Output Slew Rate With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC) for single ended signals as shown in below. [ Table 9 ] Single ended Output slew rate definition Measured
Description Single ended output slew rate for rising edge
To
VOL(AC)
VOH(AC)
VOH(AC)
Single ended output slew rate for falling edge
Defined by
From
VOH(AC)-VOL(AC) Delta TRse VOH(AC)-VOL(AC)
VOL(AC)
Delta TFse
NOTE : Output slew rate is verified by design and characterization, and may not be subject to production test.
[ Table 10 ] Single ended output slew rate Parameter Single ended output slew rate
Symbol SRQse
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Min
Max
Min
Max
Min
Max
Min
Max
2.5
5
2.5
5
2.5
5
2.5
5
Description : SR : Slew Rate Q : Query Output (like in DQ, which stands for Data-in, Query-Output) se : Single-ended Signals For Ron = RZQ/7 setting VOHdiff(AC)
VTT VOLdiff(AC)
delta TFdiff
delta TRdiff
Figure 6. Single-ended output slew rate definition
- 16 -
Units V/ns
Rev. 1.22
datasheet
Unbuffered SODIMM
DDR3 SDRAM
11.4 Differential Output Slew Rate With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOLdiff(AC) and VOHdiff(AC)
for differential signals as shown in below.
[ Table 11 ] Differential Output slew rate definition Measured
Description Differential output slew rate for rising edge
To
VOLdiff(AC)
VOHdiff(AC)
VOHdiff(AC)
Differential output slew rate for falling edge
Defined by
From
VOHdiff(AC)-VOLdiff(AC) Delta TRdiff VOHdiff(AC)-VOLdiff(AC)
VOLdiff(AC)
Delta TFdiff
NOTE : Output slew rate is verified by design and characterization, and may not be subject to production test.
[ Table 12 ] Differential Output slew rate Parameter Differential output slew rate
Symbol SRQdiff
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Min
Max
Min
Max
Min
Max
Min
Max
5
10
5
10
5
10
5
10
Description : SR : Slew Rate Q : Query Output (like in DQ, which stands for Data-in, Query-Output) diff : Differential Signals For Ron = RZQ/7 setting
VOHdiff(AC)
VTT VOLdiff(AC)
delta TFdiff
delta TRdiff
Figure 7. Differential output slew rate definition
- 17 -
Units V/ns
Unbuffered SODIMM
datasheet
Rev. 1.22
DDR3 SDRAM
12. DIMM IDD specification definition Symbol
Description
IDD0
Operating One Bank Active-Precharge Current CKE: High; External clock: On; tCK, nRC, nRAS, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0; CS: High between ACT and PRE; Command, Address, Bank Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
IDD1
Operating One Bank Active-Read-Precharge Current CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0; CS: High between ACT, RD and PRE; Command, Address, Bank Address Inputs, Data IO: partially toggling ; DM:stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
IDD2N
Precharge Standby Current CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
IDD2P0
Precharge Power-Down Current Slow Exit CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Precharge Power Down Mode: Slow Exit3)
IDD2P1
Precharge Power-Down Current Fast Exit CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Precharge Power Down Mode: Fast Exit3)
IDD2Q
Precharge Quiet Standby Current CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0
IDD3N
Active Standby Current CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
IDD3P
Active Power-Down Current CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: FLOATING;DM:stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0
IDD4R
Operating Burst Read Current CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0; CS: High between RD; Command, Address, Bank Address Inputs: partially toggling ; Data IO: seamless read data burst with different data between one burst and the next one ; DM:stable at 0; Bank Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
IDD4W
Operating Burst Write Current CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0; CS: High between WR; Command, Address, Bank Address Inputs: partially toggling ; Data IO: seamless write data burst with different data between one burst and the next one ; DM: stable at 0; Bank Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at HIGH; Pattern Details: Refer to Component Datasheet for detail pattern
IDD5B
Burst Refresh Current CKE: High; External clock: On; tCK, CL, nRFC: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0; CS: High between REF; Command, Address, Bank Address Inputs: partially toggling ; Data IO: FLOATING;DM:stable at 0; Bank Activity: REF command every nRFC ; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
IDD6
Self Refresh Current: Normal Temperature Range TCASE: 0 - 85°C; Auto Self-Refresh (ASR): Disabled4); Self-Refresh Temperature Range (SRT): Normal5); CKE: Low; External clock: Off; CK and CK: LOW; CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0; Bank Activity: Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: FLOATING
IDD6ET
Self-Refresh Current: Extended Temperature Range (optional)6) TCASE: 0 - 95°C; Auto Self-Refresh (ASR): Disabled4); Self-Refresh Temperature Range (SRT): Extended5); CKE: Low; External clock: Off; CK and CK: LOW; CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0; Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: FLOATING
IDD7
Operating Bank Interleave Read Current CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: CL-1; CS: High between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling ; Data IO: read data bursts with different data between one burst and the next one ; DM:stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing ; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
IDD8
RESET Low Current RESET : Low; External clock : off; CK and CK : LOW; CKE : FLOATING ; CS, Command, Address, Bank Address, Data IO : FLOATING ; ODT Signal : FLOATING
- 18 -
Unbuffered SODIMM
datasheet
Rev. 1.22
DDR3 SDRAM
NOTE : 1) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B 2) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B; RTT_Wr enable: set MR2 A[10,9] = 10B 3) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12=1B for Fast Exit 4) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature 5) Self-Refresh Temperature Range (SRT): set MR2 A7=0B for normal or 1B for extended temperature range 6) Refer to DRAM supplier data sheet and/or DIMM SPD to determine if optional features or requirements are supported by DDR3 SDRAM device 7) IDD current measure method and detail patterns are described on DDR3 component datasheet 8) VDD and VDDQ are merged on module PCB. 9) DIMM IDD SPEC is measured with Qoff condition (IDDQ values are not considered)
- 19 -
Rev. 1.22
datasheet
Unbuffered SODIMM
DDR3 SDRAM
13. IDD SPEC Table M471B5773CHS : 2GB (256Mx64) Module Symbol
CF8 (DDR3-1066@CL=7)
CH9 (DDR3-1333@CL=9)
CK0 (DDR3-1600@CL=11)
Unit
NOTE
IDD0
440
480
520
mA
1
IDD1
560
600
640
mA
1
IDD2P0(slow exit)
96
96
96
mA
IDD2P1(fast exit)
160
160
200
mA mA
IDD2N
240
280
280
IDD2Q
240
240
280
mA
IDD3P
240
240
280
mA
IDD3N
400
440
480
mA
IDD4R
800
920
1040
mA
IDD4W
920
1120
1200
mA
1 1
IDD5B
1360
1360
1440
mA
1
IDD6
96
96
96
mA
IDD7
1360
1680
1720
mA
IDD8
96
96
96
mA
1
NOTE : 1. DIMM IDD SPEC is calculated with considering de-actived rank(IDLE) is IDD2N.
M471B5273CH0 : 4GB (512Mx64) Module Symbol
CF8 (DDR3-1066@CL=7)
CH9 (DDR3-1333@CL=9)
CK0 (DDR3-1600@CL=11)
Unit
NOTE
IDD0
680
760
800
mA
1
IDD1
800
880
920
mA
1
IDD2P0(slow exit)
192
192
192
mA
IDD2P1(fast exit)
320
320
400
mA mA
IDD2N
480
560
560
IDD2Q
480
480
560
mA
IDD3P
480
480
560
mA
IDD3N
640
720
760
mA
IDD4R
1040
1200
1320
mA
IDD4W
1160
1400
1480
mA
1
IDD5B
1600
1640
1720
mA
1
IDD6
192
192
192
mA
IDD7
1600
1960
2000
mA
IDD8
192
192
192
mA
NOTE : 1. DIMM IDD SPEC is calculated with considering de-actived rank(IDLE) is IDD2N.
- 20 -
1
1
Rev. 1.22
datasheet
Unbuffered SODIMM
DDR3 SDRAM
14. Input/Output Capacitance [ Table 13 ] Input/Output Capacitance Parameter
Symbol
Input/output capacitance (DQ, DM, DQS, DQS, TDQS, TDQS) Input capacitance (CK and CK)
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Units
NOTE
2.3
pF
1,2,3
0.8
1.4
pF
2,3
0.15
0
0.15
pF
2,3,4
0.75
1.3
0.75
1.3
pF
2,3,6
0.2
0
0.15
0
0.15
pF
2,3,5
-0.5
0.3
-0.4
0.2
-0.4
0.2
pF
2,3,7,8
0.5
-0.5
0.5
-0.4
0.4
-0.4
0.4
pF
2,3,9,10
-0.5
0.3
-0.5
0.3
-0.5
0.3
-0.5
0.3
pF
2,3,11
-
3
-
3
-
3
-
3
pF
2, 3, 12
Min
Max
Min
Max
Min
Max
Min
Max
CIO
1.5
3.0
1.5
2.7
1.5
2.5
1.5
CCK
0.8
1.6
0.8
1.6
0.8
1.4
CDCK
0
0.15
0
0.15
0
CI
0.75
1.5
0.75
1.5
CDDQS
0
0.2
0
CDI_CTRL
-0.5
0.3
CDI_ADD_CMD
-0.5
Input/output capacitance delta (DQ, DM, DQS, DQS, TDQS, TDQS)
CDIO
Input/output capacitance of ZQ pin
CZQ
Input capacitance delta (CK and CK) Input capacitance (All other input-only pins) Input capacitance delta (DQS and DQS) Input capacitance delta (All control input-only pins) Input capacitance delta (all ADD and CMD input-only pins)
NOTE : This parameter is Component Input/Output Capacitance so that is different from Module level Capacitance. 1. Although the DM, TDQS and TDQS pins have different functions, the loading matches DQ and DQS 2. This parameter is not subject to production test. It is verified by design and characterization. The capacitance is measured according to JEP147("PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER( VNA)") with VDD, VDDQ, VSS, VSSQ applied and all other pins floating (except the pin under test, CKE, RESET and ODT as necessary). VDD=VDDQ=1.5V, VBIAS=VDD/2 and on-die termination off. 3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here 4. Absolute value of CCK-CCK 5. Absolute value of CIO(DQS)-CIO(DQS) 6. CI applies to ODT, CS, CKE, A0-A15, BA0-BA2, RAS, CAS, WE. 7. CDI_CTRL applies to ODT, CS and CKE 8. CDI_CTRL=CI(CTRL)-0.5*(CI(CLK)+CI(CLK)) 9. CDI_ADD_CMD applies to A0-A15, BA0-BA2, RAS, CAS and WE 10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(CLK)) 11. CDIO=CIO(DQ,DM) - 0.5*(CIO(DQS)+CIO(DQS)) 12. Maximum external load capacitance on ZQ pin: 5pF
- 21 -
Rev. 1.22
datasheet
Unbuffered SODIMM
DDR3 SDRAM
15. Electrical Characteristics and AC timing (0 °C
