General Information
DDR SDRAM
DDR SDRAM Product Guide
July 2006
Memory Division
Rev. 1.1 July 2006
General Information
DDR SDRAM
A. DDR SDRAM Component Ordering Information 1
2
3
4
5
6
7
8
9
10
11
K 4 H X X X X X X X - X X X X Speed
SAMSUNG Memory
Temperature & Power
DRAM
Package Type
Product Density & Refresh
Revision Interface (VDD, VDDQ)
Organization
Bank 1. SAMSUNG Memory : K
2. DRAM : 4
3. Product H : DDR SDRAM
8. Revision M : 1st Gen. A : 2nd Gen. B : 3rd Gen. C : 4th Gen. D : 5th Gen. E : 6th Gen. F : 7th Gen. G : 8th Gen. H : 9th Gen.
4. Density & Refresh 28 : 128Mb, 4K/64ms 56 : 256Mb, 8K/64ms 51 : 512Mb, 8K/64ms 1G: 1Gb, 8K/64ms 2G: 2Gb, 8K/64ms
9. Package Type T : TSOP II N : sTSOP II G : FBGA
U : TSOP II (Lead Free)*1 V : sTSOP II (Lead Free)*1 Z : FBGA (Lead Free)*1
(note 1: All of Pb-free product are in compliance with RoHS) 5. Organization 04 : x 4 06 : x 4 Stack 07 : x 8 Stack 08 : x 8 16 : x16 6. Bank 3 : 4 Banks
10. Temperature & Power C L I P
: Commercial Temp.( 0°C ~ 70°C) & Normal Power : Commercial Temp.( 0°C ~ 70°C) & Low Power : Industrial Temp.( -40°C ~ 85°C) & Normal Power : Industrial Temp.( -40°C ~ 85°C) & Low Power
11. Speed
7. Interface ( VDD, VDDQ) 8 : SSTL-2 (2.5V, 2.5V)
CC B3 A2 B0
: : : :
DDR400 DDR333 DDR266 DDR266
(200MHz @ CL=3, tRCD=3, tRP=3) (166MHz @ CL=2.5, tRCD=3, tRP=3) (133MHz @ CL=2 , tRCD=3, tRP=3) (133MHz @ CL=2.5, tRCD=3, tRP=3)
Rev. 1.1 July 2006
General Information
DDR SDRAM
B. DDR SDRAM Component Product Guide Density
Bank
Part Number
K4H560438E 256Mb E-die K4H560838E
K4H560438H
K4H560838H 256Mb H-die K4H561638H
K4H561638H stacked 512Mb E-die
K4H510638E
stacked 512Mb H-die
K4H510638H
K4H510738E
K4H510738H 4Banks
K4H510438C
K4H510838C
512Mb C-die*5
K4H511638C
K4H510838C
K4H511638C
K4H510838D
512Mb D-die*5
K4H511638D stacked 1Gb C-die*5
K4H1G0438A
1Gb A-die stacked 2Gb A-die*5
Note 1: T : TSOP II N : sTSOP II G: FBGA
K4H1G0638C K4H1G0738C
VDD/VDDQ
T(U)CB3/CA2/CB0 T(U)LB3/LA2/LB0
Org.
60ball FBGA 66pin TSOP(II) 64M x 4
ZCCC/CB3 ZLCC/LB3
60ball FBGA
UCCC/CB3/CA2/CB0 ULCC/LB3/LA2/LB0
66pin TSOP(II) 32M x 8
ZCCC/CB3 ZLCC/LB3
60ball FBGA
UCCC/CB3/CA2/CB0 ULCC/LB3/LA2/LB0
66pin TSOP(II) 16M x 16
ZCCC/CB3 ZLCC/LB3
60ball FBGA
UIB3/IA2/IB0 UPB3/PA2/PB0
66pin TSOP(II) 16M x 16
ZIB3/IA2/IB0 ZPB3/PA2/PB0
60ball FBGA 128M x 4
T(U)CA2/CB0 T(U)LA2/LB0
64M x 8
66pin stacked TSOP(II)
128M x 4
UCA2/CB0 ULA2/LB0
64M x 8
UCB3/CA2/CB0 ULB3/LA2/LB0
128M x 4
ZCCC/CB3 ZLCC/LB3
SSTL_2
2.5 ± 0.2V*4
8K/64m
66pin TSOP(II)
Now
60ball FBGA
UCCC/CB3/CA2/CB0 ULCC/LB3/LA2/LB0
66pin TSOP(II) 64M x 8
ZCCC/CB3 ZLCC/LB3
60ball FBGA
UCCC/CB3/CA2/CB0 ULCC/LB3/LA2/LB0
66pin TSOP(II) 32M x 16
ZCCC/CB3 ZLCC/LB3
60ball FBGA
UIB3/IA2/IB0 UPB3/PA2/PB0
66pin TSOP(II) 64M x 8
ZIB3/IA2/IB0 ZPB3/PA2/PB0
60ball FBGA
UIB3/IA2/IB0 UPB3/PA2/PB0
66pin TSOP(II) 32M x 16
ZIB3/IA2/IB0 ZPB3/PA2/PB0
60ball FBGA
UCCC/CB3/CA2/CB0 ULCC/LB3/LA2/LB0
66pin TSOP(II) 64M x 8
VCCC/CB3/CA2/CB0 VLCC/LB3/LA2/LB0
54pin sTSOP(II)
UCCC/CB3/CA2/CB0 ULCC/LB3/LA2/LB0
32M x 16
66pin TSOP(II)
256M x 4
UCA2/CB0 ULA2/LB0
66pin TSOP(II)
128M x 8
UCCC/CB3/CA2/CB0 ULCC/LB3/LA2/LB0
256M x 4
K4H2G0638A
UCCC/CB3/CA2/CB0, ULCC/LB3/LA2/LB0
512M x 4
2.5V ± 0.2V
Avail.
66pin TSOP(II)
UCA2/CB0 ULA2/LB0
DDR333/266
PKG*1
32M x 8
G(Z)CCC/CB3 G(Z)LCC/LB3
DDR400
Power (V)
60ball FBGA
T(U)CCC/CB3/CA2/CB0 T(U)LCC/LB3/LA2/LB0
2.6V ± 0.1V
Ref.
66pinTSOP(II)
G(Z)CCC/CB3 G(Z)LCC/LB3
Note 2:
Interface
64M x 4
K4H1G0838A
U:TSOP II (Lead Free) V:sTSOP II (Lead Free) Z:FBGA II (Lead Free)
Note 4:
Package & Power, Temp.*2(-C/-L/-I/-P) & Speed *3
66pin TSOP(II)
128M x 8
66pin TSOP(II)
Note 3:
C
Commercial Temperature, Normal Power
133Mhz
166Mhz
L
Commercial Temperature, Low Power
CL = 2
DDR266(A2)
-
200Mhz -
I
Industrial Temperature, Normal Power
CL = 2.5
DDR266(B0)
DDR333(B3)
-
P
Industrial Temperature, Low Power
CL = 3
-
-
DDR400(CC)
Note 5: All of DDR components support both Leaded and lead-free. And from 512Mb C-die, D-die and 1Gb A-die Lead-free is default PKG Type.
Rev. 1.1 July 2006
General Information
DDR SDRAM
C. DDR SDRAM Module Ordering Information 1
2
3
4
5
6
7
8
9
10
11
12
M X X X L X X X X X X X - X X X Memory Module
Speed
DIMM Configuration
Power
Data bits
PCB revision & Type
Feature
Package
Depth
Component Revision Composition Component
Refresh, # of Banks in Comp. & Interface 1. Memory Module : M
7. Composition Component 0 3 4 8 9
2. DIMM Configuration 3 : DIMM 4 : SODIMM 3. Data Bits 68 : 81 : 83 : 12 : 70 : 63 :
x64 x72 x72 x72 x64 x64
184pin Unbuffered DIMM 184pin ECC unbuffered DIMM 184pin Registered DIMM 184pin Low Profile Registered DIMM 200pin Unbuffered SODIMM 172pin Micro DIMM
4. Feature L : DDR SDRAM (2.5V VDD) 5. Depth 16 : 16M 32 : 32M 64 : 64M 28 : 128M 56 : 256M 51 : 512M
17 33 65 29 57
: 16M (for 128Mb/512Mb) : 32M (for 128Mb/512Mb) : 64M (for 128Mb/512Mb) : 128M (for 128Mb/512Mb) : 256M (for 512Mb)
: : : : :
x4 x8 x16 x 4 Stack x 8 Stack
8. Component Revision M : 1st Gen. B : 3rd Gen. D : 5th Gen. F : 7th Gen. H : 9th Gen.
A C E G
: : : :
2nd Gen. 4th Gen. 6th Gen. 8th Gen
9. Package U : TSOP II*1 (Lead Free) T : TSOP II (400mil) : V : sTSOP II*1 (Lead Free) N sTSOP Z : FBGA*1 (Lead Free) G : FBGA (note 1 : All of Pb-free product are in compliance with RoHS) 10. PCB Revision & Type 0 : Mother PCB 1 : 1st Rev. 2 : 2nd Rev. 3 : 3rd Rev. S : Reduced layer PCB
11. Temp & Power C : Commercial Temp.( 0°C ~ 70°C) & Normal Power L : Commercial Temp.( 0°C ~ 70°C) & Low Power
6. Refresh, # of Banks in comp. & Interface 1 : 2 :
4K/ 64ms Ref., 4Banks & SSTL-2 8K/ 64ms Ref., 4Banks & SSTL-2
12. Speed CC : B3 : A2 : B0 :
DDR400 DDR333 DDR266 DDR266
(200MHz @ CL=3, tRCD=3, tRP=3) (166MHz @ CL=2.5, tRCD=3, tRP=3) (133MHz @ CL=2 , tRCD=3, tRP=3) (133MHz @ CL=2.5, tRCD=3, tRP=3)
Rev. 1.1 July 2006
General Information
DDR SDRAM
D. DDR SDRAM Module Product Guide Org.
Density
Part Number
Composition
Speed
Comp. Version
Voltage
Internal External Banks Banks
PKG*1
Feature
Avail.
184Pin DDR Unbuffered DIMM M368L3223ET(U)N CB3, LB3
32Mx 8
* 8pcs
M368L3223ET(U)M CCC, LCC
32Mx 8
* 8pcs
CCC/CB3, LCC/LB3
32Mx 8
* 8pcs
256Mb 9th
CCC/CB3, LCC/LB3
32Mx 16 * 4pcs
512Mb 4th
M368L3324DUS*2 CCC/CB3, LCC/LB3
32Mx 16 * 4pcs
512Mb 5th
M368L3223HUS
32Mx 64 256MB
M368L3324CUS
*2
M381L3223ET(U)M CCC/CB3, LCC/LB3
32Mx 72
32Mx 8
* 9pcs
256Mb 6th
32Mx 8
* 9pcs
256Mb 9th
M368L6423ET(U)N CB3, LB3
32Mx 8
* 16pcs
256Mb 6th
M368L6423ET(U)M CCC, LCC
32Mx 8
* 16pcs
256Mb 6th
CCC/CB3, LCC/LB3
64Mx 8
* 8pcs
256Mb 9th
M368L6523CUS*2 CCC/CB3, LCC/LB3
64Mx 8
* 8pcs
512Mb 4th
M381L3223HUM
M368L6423HUN
64Mx 64
512MB
CCC/CB3, LCC/LB3
M368L6523DUS*2 CCC/CB3, LCC/LB3
64Mx 8
* 8pcs
512Mb 5th
M381L6423ET(U)M CCC/CB3, LCC/LB3
32Mx 8
* 18pcs
256Mb 6th
CCC/CB3, LCC/LB3
32Mx 8
* 18pcs
512Mb 3rd
M381L6523CUM*2 CCC/CB3, LCC/LB3
64Mx 8
* 9pcs
512Mb 4th
M381L6523DUM*2 CCC/CB3, LCC/LB3
64Mx 8
* 9pcs
512Mb 5th
64Mx 8
* 16pcs
M381L6423HUM 64Mx 72
M368L2923CUN*2 CCC/CB3, LCC/LB3
128Mx 64 1GB 128Mx 72
256Mb 6th
M368L2923DUN*2 CCC/CB3, LCC/LB3 M381L2923CUM*2 CCC/CB3, LCC/LB3 M381L2923DUM*2 CCC/CB3, LCC/LB3
64Mx 8
* 18pcs
1
SS,1250mil
2 2.5 ± 0.2V*3
4
1
DS,1250mil Now
66TSOP(II) SS,1250mil
2
DS,1250mil
1
SS,1250mil
2
DS,1250mil
512Mb 4th 512Mb 5th 512Mb 4th 512Mb 5th
Note 2: All of DDR components support both Leaded and lead-free. And from 512Mb C-die, D-die and 1Gb A-die Lead-free is default PKG Type.
Note 1:(All of DDR DIMMs can support Pb-free) T : TSOP II U : TSOP II (Lead Free) N : sTSOP II V : sTSOP II (Lead Free) G : FBGA Z : FBGA (Lead Free) Note 3:
VDD/VDDQ
DDR400
DDR333/266
2.6V ± 0.1V
2.5V ± 0.2V
Rev. 1.1 July 2006
General Information
DDR SDRAM 184Pin DDR Low Profile Registered DIMM
Density
Org.
Part Number
Speed
M312L3223ET(U)S CA2/CB0, LA2/LB0 32Mx 72
256MB
M312L3223HUS
CA2/CB0, LA2/LB0
M312L3223EG(Z)0 CCC/CB3, LCC/LB3 M312L3223HZ0
CCC/CB3, LCC/LB3
M312L6423ET(U)S CA2/CB0, LA2/LB0
256Mb 6th
* 9pcs
256Mb 9th
32Mx 8
* 9pcs
256Mb 6th
32Mx 8
* 9pcs
256Mb 9th
* 18pcs
256Mb 6th
* 18pcs
256Mb 9th
M312L6420ET(U)S CA2/CB0, LA2/LB0
64Mx 4
* 18pcs
256Mb 6th
64Mx 4
* 18pcs
256Mb 9th
CA2/CB0, LA2/LB0
M312L6523CUS*2 CA2/CB0, LA2/LB0
64Mx 8
* 9pcs
512Mb 4th
M312L6420EG(Z)0 CCC/CB3, LCC/LB3
64Mx 4
* 18pcs
256Mb 6th
CCC/CB3, LCC/LB3
64Mx 4
* 18pcs
256Mb 9th
M312L6423EG(Z)0 CCC/CB3, LCC/LB3
32Mx 8
* 18pcs
256Mb 6th
32Mx 8
* 18pcs
256Mb 9th
64Mx 8
M312L6423HZ0 *2
CCC/CB3, LCC/LB3 CCC/CB3, LCC/LB3
Voltage
Internal External Banks Banks
2
256Mb 6th
CA2/CB0, LA2/LB0
st.128Mx 4
* 18pcs
256Mb 9th
CA2/CB0, LA2/LB0
64Mx 8
* 18pcs
512Mb 4th
M312L2920CUS*2 CA2/CB0, LA2/LB0
128Mx 4
* 18pcs
512Mb 4th
1
M312L2820EG(Z)0 CCC/CB3, LCC/LB3
64Mx 4
* 36pcs
256Mb 6th
2
CCC/CB3, LCC/LB3
64Mx 4
* 36pcs
256Mb 9th
2
M312L2920CZ0*2 CCC/CB3, LCC/LB3
128Mx 4
* 18pcs
512Mb 4th
1
128Mx 8
* 18pcs
512Mb 4th
2
st.256Mx 4
* 18pcs
512Mb 4th
M312L2820HZ0
*2
M312L2923CZ0
CCC/CB3, LCC/LB3
M312L5628CU0*2 CA2/CB0, LA2/LB0
2GB
M312L5720CZ0*2 CCC/CB3, LCC/LB3
128Mx 4
* 36pcs
512Mb 4th
CCC/CB3/CA2/CB0 M312L5620AUS*2 LCC/LB3/LA2/LB0
256Mx 4
* 18pcs
1Gb 2nd
CCC/CB3/CA2/CB0 M312L5623AUS*2 LCC/LB3/LA2/LB0
128Mx 8
* 18pcs
1Gb 2nd
st.512MX 4
* 18pcs
1Gb 2nd
st.512MX 4
* 18pcs
1Gb 2nd
M312L5128AU0*2 512Mx72
4GB
CB3/CA2/CB0 LB3/LA2/LB0
60ball FBGA
DS,1125mil
66pin TSOP(II)
DS,1200mil
60ball FBGA
1
2.5 ± 0.2V*3
4
2
2 256Mx 72
DS,1200mil
1
512Mb 4th
M312L2923CUS
66pin TSOP(II)
Avail.
1
* 18pcs
*2
Feature
2
* 9pcs
M312L2828HU0
PKG*1
1
st.128Mx 4
M312L6523CZ0
M312L2828ET(U)0 CA2/CB0, LA2/LB0
1GB
* 9pcs
32Mx 8
32Mx 8
M312L6420HZ0
128Mx 72
32Mx 8
32Mx 8
M312L6420HUS 512MB
Comp. Version
CA2/CB0, LA2/LB0
M312L6423HUS
64Mx 72
Composition
DS,1125mil
SS,1125mil
66pin TSOP(II)
DS,1200mill
Now
DS,1200mil 60ball FBGA DS,1125mil 66pin TSOP(II) 60ball FBGA
DS,1200mil
1
2
66pin TSOP(II) DS,1200mil
CCC M312L5128AU1*2 LCC
Note 2: All of DDR components support both Leaded and lead-free. And from 512Mb C-die, D-die and 1Gb A-die Lead-free is default PKG Type.
Note 1:(All of DDR DIMMs can support Pb-free) U : TSOP II (Lead Free) T : TSOP II V : sTSOP II (Lead Free) N : sTSOP II Z : FBGA (Lead Free) G : FBGA Note 3:
VDD/VDDQ
DDR400
DDR333/266
2.6V ± 0.1V
2.5V ± 0.2V
Rev. 1.1 July 2006
General Information
DDR SDRAM 200Pin DDR SODIMM
Org.
Density
Part Number
Speed
16Mx64
128MB
M470L1624HU0
CCC/CB3/CA2/CB0 LCC/LB3/LA2/LB0
16Mx 16 * 4pcs
256Mb 9th
1
SS,1250mi
M470L3224HU0
CCC/CB3/CA2/CB0 LCC/LB3/LA2/LB0
16Mx 16 * 8pcs
256Mb 9th
2
DS,1250mi
CCC/CB3/CA2/CB0 M470L3324CU0*2 LCC/LB3/LA2/LB0
32Mx 16 * 4pcs
512Mb 4th
CCC/CB3/CA2/CB0 M470L3324DU0*2 LCC/LB3/LA2/LB0
32Mx 16 * 4pcs
512Mb 5th
CCC/CB3/CA2/CB0 M470L6524CU0*2 LCC/LB3/LA2/LB0
32Mx 16 * 8pcs
512Mb 4th
CCC/CB3/CA2/CB0 M470L6524DU0*2 LCC/LB3/LA2/LB0
32Mx 16 * 8pcs
512Mb 5th
CCC/CB3/CA2/CB0 M470L2923DV0*2 LCC/LB3/LA2/LB0
64Mx 8
512Mb 5rd
32Mx 64
64Mx 64
128Mx 64
256MB
512MB
1GB
Composition
* 16pcs
Comp. Version
Voltage
2.5 ± 0.2V*3
Internal External Banks Banks
1 4
PKG*1
66pin TSOP(II)
2
Feature
Avail.
SS,1250mi Now
DS,1250mi 54pin sTSOP(II)
Note 2: All of DDR components support both Leaded and lead-free. And from 512Mb C-die, D-die and 1Gb A-die Lead-free is default PKG Type.
Note 1:(All of DDR DIMMs can support Pb-free) T : TSOP II U : TSOP II (Lead Free) N : sTSOP II V : sTSOP II (Lead Free) G : FBGA Z : FBGA (Lead Free) Note 3:
VDD/VDDQ
DDR400
DDR333/266
2.6V ± 0.1V
2.5V ± 0.2V
Rev. 1.1 July 2006
General Information
DDR SDRAM
E. Package Dimension 66pin TSOP-II
(0.71)
0.65TYP 0.65±0.08
(10.16) 0.10 MAX
0.30±0.08 (10×)
NOTE 1. ( ) IS REFERENCE 2. [ ] IS ASS’Y OUT QUALITY
) 25 0. (R
[
0.075 MAX ]
(R 0.2 5)
) 15 0. (R
0.125 +0.075 -0.035
(4× )
(10×)
)
1.20MAX
.1 5
1.00±0.10
22.22±0.10
(R 0
0.05 MIN
0.210±0.05
0.665±0.05
(1.50)
(0.50)
(0.80)
#33
(10×)
0.45~0.75
(1.50)
(10×)
#1
11.76±0.20
(0.80)
#34
10.16±0.20
#66
(0.50)
Units : Millimeters
0.25TYP
0×~8×
66pin TSOP-II stack
0.65
NOTE 1. ( ) IS REFERENCE 2. [ ] IS ASS’Y OUT QUALITY
0.25 ± 0.08
0.45~0.75 (0.50)
10.16 +0.075
0.05(min)
0.45~0.75
(R
2.54(max) (0.71)
0. 25 )
0.125 - 0.035
22.62MAX 22.22 ± 0.10
)
#33
(4×
#1
Units : Millimeters
(R 0.2 5)
#34
10.16±0.20
#66
0.25TYP
0×~8×
Rev. 1.1 July 2006
General Information
DDR SDRAM
54pin sTSOP-II 300 #54
(0.50)
Units : Millimeters #28
(2-R 0.30)
(8.22)
7.6
(∅ 2.00 Dp0~0.05 BTM)
(1.00)
(1.00)
9.22±0.20
(0.80)
(2-R 0.15)
(14°)
) 25
°) (14 )
0.40~0.60
(0.50)
(0.80)
1.20MAX
0.10 MAX
(R 0.
+0.075 -0.035
.2 5
0.20
0.125 +0.075 -0.035
(R 0
30 0. -R (2
NOTE 1. ( ) IS REFERENCE 2. [ ] IS ASS’Y OUT QUALITY
0.50TYP 0.50±0.05 [ 0.07 MAX ]
(1.10)
(14°)
5)
(0.50)
1.00±0.05
0 .1
14.40MAX (14.20) 14.00±0.10
0.05 MIN
(2R
(14°)
#27
)
0.210±0.05
0.665±0.05
#1
0.25TYP
0×~8×
0.08 MAX
54pin sTSOP-II 400
#54
(0.16) +0.07 -0.03
11.20±0.10
#28
(0.18)+0.07/-0.03
#27
11.40MAX
(0.40)
#1
0.40
10.16
∼8
0°
0.25 TYP
+0.75
0.125 -0.035
11.76±0.20
0.05MIN
°
0.665±0.05 0.210±0.05
(0.50)
0.45~0.75
1.00±0.10 1.20MAX
Rev. 1.1 July 2006
General Information
DDR SDRAM
60Ball FBGA (For 256Mb) 0.10 Max
8.00 ± 0.10 0.80 x 8 = 6.40 ENCAPSULANT AREA
0.80 x 4 = 3.20 1.60
1.60
8.0 0± 0.10
9
8
7
6
5
4
3
2
1 0.80
1.00
A B
0.50 5.50
0.45 ± 0.05
H J
14.00 ± 0.10
F G
1.00 x 11 = 11.00
0.50
E
14.0 ± 0.10
14.00 ± 0.10
D
5.50
C
K L M
0.35 ± 0.05 60 - 0.45
TOP VIEW
π
(0.90)
(0.90) ± 0.05 (1.80)
1.10± 0.10
BOTTOM VIEW
60Ball FBGA (For 512Mb) 10.00 ± 0.10 A
1.00MAX
0.80 x8 = 10.00 ± 0.10
6.40 0.80 x4 = 3.20 #A1 MARK(option)
WINDOW MOLD AREA
0.80 x2= 1.60
0.80 x2 = 1.60 B
9
8
7
6
5
4
3
2
1
0.80
A
0.50
H J
12.00 ± 0.10
F G
1.00 x11 11.00
E
0.45 ± 0.05
12.00 ± 0.10
12.00 ± 0.10
D
0.50
1.00
(Datum B) C
5.50
B
#A1
K L M
Top view
1.20 MAX
60-∅0.45 ± 0.05 0.20 M A B
(0.90)
(0.90) (1.80)
(Datum A)
4-CORNER MARK(option)
Bottom view
Rev. 1.1 July 2006
General Information
DDR SDRAM
For further information, ( DDR )
eunicechoi @sec.samsung.com, Tel : 82-31-208-4880
( General )
KHHAN
@sec.samsung.com, Tel : 82-31-208-6433
Rev. 1.1 July 2006
