TDA9205 DC CONTROLLED 130MHz RGB PREAMPLIFIER
.. . . . .. . .. .
130MHz TYPICAL BANDWIDTH AT 1VPP 2.8ns TYP. RISE/FALL TIME (3VPP/12pF LOAD) DC ADJUSTMENT : CONT, BRT, RGB DRIVE, RGB CUT-OFF COMP. VIDEO INPUT AND POSITIVE OR NEGATIVE SYNC INPUT INTERNAL BACKPORCH CLAMPING PULSE GENERATOR WITH 3 SELECTABLE WIDTH BLANKING STAGE INTERNAL PULSE GENERATOR FOR CUTOFF LOOP GATING (INSIDE BLANKING) POSSIBILITY OF AC OR DC COUPLING TO HIGH VOLTAGE AMPLIFIER VOLTAGE REFERENCE GENERATOR POWERFULL OUTPUT DRIVE CAPABILITY BICMOS PROCESS
SHRINK42 (Plastic Package) ORDER CODE : TDA9205
DESCRIPTION The TDA9205 is a DC controlled wideband video amplifier intended for use in high resolution color monitor. DC (0 to 5V) contrast and brightness commands apply to the 3 channels. White balance adjustment is performed using 3 separated drive inputs. 3 feed-back inputs give a flexible DC level shift of the output signals. Cut-off adjustments can be easily performed with these 3 inputs. Separated ground and supply for each channel and large swing output voltage (0.5 to 8V) make the TDA9205 suitable for AC or DC drive of discrete, hybrid or monolitic high voltage CRT amplifier. Attractive functions like sync separator, line blanking, backporch generator, voltage reference generator, feed-back polarity selection give to the TDA9205 efficient features for performant and cost effective application. March 1996
CONT
1
42
VREF
BRT
2
41
FDBKPOL
G BRT CAP
3
40
DC ADJ
B BRT CAP
4
39
R CLAMP
R BRT CAP
5
38
B CLAMP
R DRIVE
6
37
PVCC R
R VCC
7
36
R OUT
R GND
8
35
R FDBK
R IN
9
34
PGND R
B DRIVE
10
33
PVCC B B OUT
B VCC
11
32
B GND
12
31
B FDBK
B IN
13
30
PGND B
G DRIVE
14
29
PVCC G
G VCC
15
28
G OUT
G GND
16
27
G FDBK
G IN
17
26
PGND G
COMPVIDEO
18
25
G CLAMP
HSYNC
19
24
BP ADJ
SYNCOUT
20
23
BLK
DC VCC
21
22
DC GND
9205-01.EPS
PIN CONNECTIONS
1/11
TDA9205 PIN DESCRIPTION Pin Number
Symbol
I/O
Function
1
CONT
I
Contrast Adjustment (0 to 5V)
2
BRT
I
Brightness Adjustment (0 to 5V)
3-4-5
G,B,R, BRT CAP
I
G,B,R Capacitor for Brightness Loop
6-10-14
R,B,G DRIVE
I
R,B,G Drive Adjutment
7-11-15
R,B,G VCC
S
Supply Voltage of Input Stage (12V)
8-12-16
R,B,G GND
GND
Signal Ground of Input Stage
9-13-17
R,B,G IN
I
Video Signal Inputs
18
COMPVIDEO
I
Composite Video Input (or Sync on Green)
19
HSYNC
I
Horizontal Synchronization Input
20
SYNCOUT
O
Composite Sync Output
21
DC VCC
S
Supply Voltage (12V)
22
DC GND
GND
23
BLK
I
Blanking Input
24
BP ADJ
I
Backporch Clamping Pulse Width Adjustment
39-25-38
R,G,B CLAMP
I
34-26-30
R,G,B PGND
GND
35-27-31
R,G,B FDBK
I
36-28-32
R,G,B OUT
O
Video Ouput Signals
37-29-33
R,G,B PVCC
S
Supply Voltage of Output Stage (12V)
40
DC ADJ
I
DC Level ADjustment of Output Signals
41
FDBKPOL
I
Selection of the Signal Polarity of the Feed-back Inputs
42
VREF
O
Voltage Reference Output (5V)
Ground
R,G,B Capacitor Clamp for Output Stage Ground of Output Stage
9205-01.TBL
Feed-back Input of Output Stage
BLOCK DIAGRAM RVCC
R BRT CAP
B BRT CAP
G BRT CAP
7
5
4
3
R DRIVE B DRIVE G DRIVE 6
10
R CLAMP B CLAMP G CLAMP 39
14
38
25
TDA9205 35 RFDBK A2 Gm2
Gm5
41 FDBKPOL
Gm3
VREF 37 PVCC R
R IN 9 Gm1
A1
R GND 8
ATTENUATOR
DC LEVEL SHIFT
A2
36 ROUT 34 PGND R 31 BFDBK
B IN 13 BLUE CHANNEL
33 PVCC B
10 PINS
B GND 12
32 BOUT
G IN 17
30 PGND B GREEN CHANNEL
10 PINS
G GND 16 SYNCH EXTRACTOR
BACKPORCH PULSE
29 PVCC G
PULSE GENERATOR
28 GOUT VREF
19 HSYNC
2/11
20
1
SYNC CONT OUT
24 BP ADJ
21
22
2
DC DC BRT VCC GND
26 PGND G
23
42
40
BLK
VREF
DC ADJ
9205-02.EPS
COMP VIDEO 18 INPUT
27 GFDBK
TDA9205
Symbol tR , tF
Parameter Signal Bandwidth (1V PP/12pF laod) Rise and Fall Time (3.5VPP /12pF load) Gain Matching Contrast Tracking Drive Adjustment Range on the 3 Channels Separately Reference Voltage Nominal Output Voltage (V IN = 0.7VPP) Output Voltage (AC + DC)
Min.
Typ. 130 3.8 0.3 0.2 6 5 2.8
Max.
8
Unit MHz ns dB dB dB V V V
Value 13.5 30 GND < VIN < VS 2 -40, +150 150 0, +70
Unit V mA V kV o C o C o C
9205-02.TBL
QUIK REFERENCE DATA
Symbol VS IS VIN VESD Tstg Tj Toper
Parameter Supply Voltage (Pins 7-11-15-21-29-33-37) Peak Video Output Sink/Source Current (Pins 28-32-36) Voltage at any Input Pins ESD Susceptability (Human body model ; 100pF discharge through 1.5kΩ) Storage Temperature Junction Temperature Operating Temperature
9205-03.TBL
ABSOLUTE MAXIMUM RATINGS
Symbol R th (j-a)
Parameter
Value
Junction-ambient Thermal Resistance
Max.
Unit o
60
C/W
9205-04.TBL
THERMAL DATA
Symbol VS IS VREF IREF VI VO VADJ
Parameter Supply Voltage Supply Current Reference Voltage Max. Sourced Current on Reference Voltage Input Voltage Amplitude Typ. Output Voltage Range Typ. DC Control Voltage Range
Test Conditions Addition of all VS Pins Current Pin 42 Pin 42 Pins 9-13-17 Pins 28-32-36 Pins 1-2-6-10-14-40
Min. 10.8
0.5 0
Typ. 12 75 5 4 0.7 -
Max. 13.2
1 8 5
Unit V mA V mA V V V
9205-05.TBL
DC ELECTRICAL CHARACTERISTICS (Tamb = 25oC, VCC = 12V, unless otherwise specified
Symbol R IN GM GN GI DAR
Parameter Video Input Resistance Maximum Gain (20 log x VOUT AC / VIN AC) Nominal Gain Minimum Gain Typical Drive Attenuation Range
BW
DIS tR , tF CT1 CT2
Bandwidth Large Signal Bandwidth Small Signal Video Output Distorsion Video Output Rise and Fall Time Crosstalk
Test Conditions Pins 9-13-17 VCONT1 = 5V, VDRIVE 6-10-14 = 5V VCONT1 = 2.5V, VDRIVE 6-10-14 = 5V VCONT1 = 0V, VDRIVE 6-10-14 = 5V Pins 28-32-36 Amplitude vs Voltage on Pins 6-10-14 At -3dB, Load = 12pF, VIN = 1VPP VOUT = 3.5VPP VOUT = 1VPP f = 1MHz, VOUT = 1V PP, VIN = 1VPP VOUT = 3.5V PP, Load = 12pF, Measured at 10/90% At 1MHz At 40MHz
Min.
Typ. 15 14 12.5
Max.
6.3
Unit kΩ dB dB dB dB
100 130 0.3 2.8
MHz MHz % ns
32
dB dB
-18
50
3/11
9205-06.TBL
AC ELECTRICAL CHARACTERISTICS (Tamb = 25oC, VCC = 12V, unless otherwise specified)
TDA9205 GENERAL DESCRIPTION 1- Input Stage The R, G and B signals must be fed to the three RGB inputs through coupling capacitors (10µF). The maximum peak-to-peak video amplitude is 1V. In case of synch on green or composite video input signal, the IC will operates normally.
Figure 2 Pins 3-4-5 GM1
BRT Adjust.
C
From CONT ADJ
A1 9205-04.EPS
2 - Contrast Adjustment The contrast adjustment is made by controlling simultaneously the gain of three internal variable gain amplifiers, by the DC voltage on Pin 1. The control voltage range as for all other DC controls on TDA9205 is 0 to 5V. The contrastadjustmentallows to cover a minimum range of 30dB. The contrast tracking (when contrats is changed) is equalto 0.2dB. Typical curve is given in Figure 1. Figure 1 :
2 GM2
BP H-S
GM2 comparator have a current output which charge or discharge the memory capacitors (C), connected on the input of the transconductors (GM1). The loop stabilize when the DC value on the output of A1 reaches the desired value setted by the DC voltage on Pin 2. The 3 Video channels works according to this description. Typical curve is given in Figure 3.
Contrast Adjustment versus Control Voltage
GM (dB)
Figure 3 :
14 10
Brightness Adjustment versus Control Voltage
VBRIGHTNESS (V)
0
2
-10
0
1
2
3
4
5
6
VBRIGHT (V)
3 - Brightness Adjustment As for the contrast adjustment, the brightness is controlled by a DC voltage applied on Pin2. The brightness function consits to add the same DC offset to the three RGB signals after contrast amplification. First the DC level of A1 output is compared to the brightness command on Pin 2 by the comparator GM2. This comparison is made during the internally generated backporch clamping pulse (BP). As shown on the Figure 2, this pulse occurs when the input video signals are at black level (after the end of sync pulse).
4/11
0
1
2
3
4
5
4 - Drive Adjustment In order to make the white balance, the TDA9205 offers the possibility to adjust separatelythe overall gain of each complete video channel. The gain of each channel is controlled by the DC voltage on the Pins 6-10-14. These pins are connected to the three internal attenuators located after the contrast and brightness processing. The attenuation range is from 0dB to -6dB.
9205-05.EPS
-20
9205-03.EPS
1 VCONT (V)
TDA9205 GENERAL DESCRIPTION (continued) The three outputs are able to sink or source 30mA maximum current. As can be seen in the electrical specifications, 3.8ns rise and fall time are possible to achieved with 3.5VPP on 12pF load. Typical large bandwidth is given in Figure 6.
0dB is achieved for 5V on drive adjustment and -6dB for 0V. Typical curves are given in Figures 4 and 5. Figure 4 : Drive Adjustment versus Frequency GAIN (dB) 15
Figure 6 : Typical Large Signal Bandwidth
0dB -1dB -2dB -3dB -4dB -5dB -6dB
3
VIDEO IN = 0.7 VCC CONTRAST = Max. VBRIGHTNESS = 2V VDC LEVEL = 1V
2
10
100
f (MHz)
Figure 5 : Drive Adjustment versus Control Voltage
0
DAR (dB)
10
0
-2
-4
VDRIVE (V) -8 1
2
3
4
5
5 - Blanking The blankingstage switches the outputs to the infra black level when a positive pulse is applied on the TTL BLK input (Pin 23). The infra black level is defined as black level minus 400mV on the video outputs. Black level is reached with minimal brightness and black level on video signal inputs. 6 - Output Stage The output stage allows maximum voltage range (between 0.5 and 8V). To allow the TDA9205 to drive either discrete (with cascade stage) or hybrid or monolitic high voltage amplifier, the output has been designed to be able to drive either capacitive or resistive load.
9205-07.EPS
-6
0
1
100
9205-08.EPS
F (MHz)
0
7 - Output Clamp The output clamp centers the output voltages to the desired DC value. As for the brightness loop, the output clamp includes a sample and hold system (please refer to Figure 2). The sampling is made by an internal pulse. This pulse (CLPP) is located inside the blanking pulse. Each blanking pulse will trigger a 1µs internal monostable (see Figure 7). Figure 7 BLANKING PIN 23 9205-09.EPS
5
9205-06.EPS
10
VIDEO OUT (VPP ) 4
CLPP 1µs
During CLPP, the DC voltage of Pin 40 will be compared to the Red, Green or Blue feed-back signals on Pins 35, 27 or 31. In order to allow DC or AC coupling between high voltage amplifier and cathode, the polarity of this feed-back signal can be either positive or negative. The desired polarity is selectable by Pin 41. If Pin 41 is at high level, the feed-back signals (Pins 27-31-35) must have positive polarity (See Figure 8a). 5/11
TDA9205 GENERAL DESCRIPTION (continued) Figure 8a
Of course individual DC settings (cut-off) are possible to achieve by inserting a potentiometer (or a system with D/A converter) on each feed-back Pin (see Figure 8b).
85V
To Cathode
8 - Sync Processing In order to generate the internal backporch clamping pulse, it is necessary to provide the IC with an horizontal sync signal.
Cut-Off Out IN
1/3 TDA9205 (Red) 9205-10.EPS
Feed-Back
If Pin 41 is grounded, than the feed-back signals (Pins 27-31-35) must have negative polarity (see Figure 8b). Figure 8b 140V
1/3 TDA9205 (Red)
This latter allows for example to cope with sync on green standards. An internal OR function will take either the TTL synch or the composite synch extracted from the composite video input. The extracted composite pulse is available on Pin 20. During the vertical pulse, the brightness loop will stay in HOLD mode.
To Cathode
IN
This sync can be entered two ways, the first one is through the TTL horizontal synch input (positive or negative polarity, Pin 20), the second one is by using the internal synch extractor input (Pin 18).
9 - Backporch Pulse Generator As explained in chapter 3, the backporch clamping pulse which is used in the brightness adjustment loop, is internally generated.
Out
D/A Cut-Off
Feed-Back
The result of the comparison is stored on the external capacitors (Pins 39-25-35). These voltages will then be used by the three internal amplifiers to control the DC level shifter blocks. The system will stabilize when the output DC levels (on IC output or on the cathode) will reach the value selected by the voltage on Pin 40.
6/11
9205-11.EPS
It start just after the end of the sync pulse and its duration is adjustable by the voltage on Pin 24 as shown in the Table here below. V24 (V)
Duration (Typ.) (µs)
0
1.0 0.5 0.35
VREF/2 VREF
10 - Voltage Reference The IC also includes a 5V stable reference voltage (band gap type) which can be used for biasing external potentiometers or external reference voltage input of digital to analog converters.
TDA9205 INTERNAL SCHEMATICS Figure 4
Figure 5 VCC DC VCC DC
1
Figure 6
9205-15.EPS
GND DC
9205-12.EPS
2
GND DC
Figure 7 VCC DC
VCC DC
Pins 3-4-5
Figure 8
9205-16.EPS
GND DC
9205-13.EPS
P ins 6-10-14
GND DC
Figure 9 P ins 7-11-15 VCC DC
9205-17.EPS
P ins 8-11-16
9205-14.EPS
Pins 9-13-17
GND DC
7/11
TDA9205 INTERNAL SCHEMATICS (continued) Figure 10
Figure 11 VCC DC
VCC DC
19
GND DC
Figure 12
GND DC
9205-19.EPS
9205-18.EPS
18
Figure 13 21
VCC DC
Figure 14
22
9205-21.EPS
GNDC
9205-20.EPS
20
Figure 15 VCC DC
VCC DC
23
Figure 16
GND DC
9205-23.EPS
GND DC
9205-22.EPS
24
Figure 17 VCC DC
P ins 29 33-37
8/11
P ins 26 30-34
9205-25.EPS
GND DC
9205-24.EPS
P ins 25 38-39
TDA9205 INTERNAL SCHEMATICS (continued) Figure 18
Figure 19 VCC DC
P VCC
P ins 28 32-36
GND DC
Figure 20
9205-27.EPS
9205-26.EPS
P ins 27 3 1-35
GND DC
Figure 21 VCC DC
VCC DC
9205-28.EPS
GND DC
9205-29.EPS
41
40
GND DC
Figure 22 VCC DC
GND DC
9205-30.EPS
42
9/11
TDA9205 TYPICAL APPLICATION DIAGRAM VR R9 6 2kΩ J1 4 3 2 1
C43 22 nF
R7 1kΩ BRIGHT CONT
C23 47µF
R31 22Ω
R8 1kΩ 1
C42 4 7µF
C4 10 nF
R53 6 2kΩ
+1 2V R52
IC2
42
C44 2
41
3
40
10 nF
VC C 10Ω
C5 R10 2 2kΩ
22 nF
R29
C6
22 nF
C7
22 nF
4
39
22 nF
5
38
22 nF
6
37
7
36
8
35
C8 1 0n F
1kΩ
R12 VC C 1 0Ω C10 10 0n F
C19 10 0n F
C20 10µF
9 R14
100 Ω
11 1 0Ω
C14 10 0n F
C12 10µF
C38 10 0n F
C13 10µF VR5 50kΩ
R17 10Ω
R18 1 0Ω
C40 10 0n F
100 Ω
C37 10 0n F
R57 75Ω
R58
2
32
5
D12
D1 1 N41 48
1 N41 48
VDD
2 2Ω
D5
D4
C55 33 pF
C17 1 00n F
C18 10µF
10Ω
R36
C25
33Ω
82p F
R38
C27
33Ω
82p F
R37
C26
33Ω
82p F
D3 C49 1 00n F 250 V
U1
C50 10µF 25 0V
D6
R24 R59
31
2 2Ω C56 33 pF
22Ω 30
D7
R28 14
29
15
28
16
27
17
26
18
25
C16 10µF
C15 1 00n F
10Ω R23
R60 22Ω
19
23
21
22
1kΩ
1N41 48
C52 1 00 nF
C53 10 0nF
VDD R40 1 MΩ
L2 R46
R22 20
C51 10 0n F
C57 3 3pF
VR2 50 kΩ
24
D2
D8
2 2Ω
C30
22 nF
VCC
C48 10µF
C47 10 0n F
33
100 Ω
4.7 Ω
10Ω
C29 10µF
R25
R19
R20 C36 10µF
C20 10µF
C28 10 0n F
R27
C1 1 0n F C46 10µF
C19 1 00n F
0 13
VC C
C35 470 nF
12
R16
VR
9
L5 1 0µH
R26
34
A
C11 1 0n F
VC C
R56 75Ω
T D
10 10Ω
R15
+12 V L1 10µH
22Ω
R13
VR C9 1 0µF VR1 50kΩ
VC C
C21
R11
J2
R55 75Ω
2kΩ
C22
R54 2 2kΩ
1 2 3 4 5 6 7 8 9 10
R30 1 0kΩ
BLK
D9 1 N41 48
R39 18 kΩ
C31 1 0µF 2 50 V
R45 L4
R47
U2 R50
+5V
1 00Ω
1 00Ω
VDD L2 R42 1 MΩ
C34 R33 1kΩ
J3 1 2 3 4 5 6 7 8
H+ BLK V+
R34 4 70Ω
IC1A 7 4HC86
10µF
D1 0 1 N41 48
R39 18 kΩ
IC1 B 7 4HC86 +5V
1 00Ω R2 3 .3Ω 1 /2W
R3 1 00Ω
C32 1 0µF 2 50 V
SW1
+1 2V
J6 1
C3 1 nF 1 kV
VDD
J5
R1
+5V
+5 V
VR4 50 kΩ
R44 1 MΩ
R4 1 kΩ VSYNC C24 R5 1kΩ
R6 4 70Ω
IC1D 7 4HC86
10µF
+5V
10/11
R49 R48
IC1C 7 4HC86
R53 18 kΩ
C2 1n F 1kV
10 0Ω
R61 22 0kΩ
J4
D1 1 1 N41 48 C33 1 0µF 2 50 V
1 2 3
R35 VDD 3 .3Ω
1 2 3
9205-31.EPS
VR3 50 kΩ
R32 1 kΩ HSYNC
TDA9205 PACKAGE MECHANICAL DATA 42 PINS - PLASTIC SHRINK DIP E
A2
A L
A1
E1
B
B1
e
e1 e2
D c E 42
22
.015 0,38
1
PMSDIP42.EPS
Gage Plane
e3
21
e2 SDIP42
A A1 A2 B B1 c D E E1 e e1 e2 e3 L
Min. 0.51 3.05 0.36 0.76 0.23 37.85 15.24 12.70
2.54
Millimeters Typ.
3.81 0.46 1.02 0.25 38.10 13.72 1.778 15.24
3.30
Max. 5.08 4.57 0.56 1.14 0.38 38.35 16.00 14.48
18.54 1.52 3.56
Min. 0.020 0.120 0.0142 0.030 0.0090 1.490 0.60 0.50
0.10
Inches Typ.
0.150 0.0181 0.040 0.0098 1.5 0.540 0.070 0.60
0.130
Max. 0.200 0.180 0.0220 0.045 0.0150 1.510 0.629 0.570
0.730 0.060 0.140
SDIP42.TBL
Dimensions
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without noti ce. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. 1996 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
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