DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC
Dual 4-input NAND gate DESCRIPTION The HEF4012B provides the positive dual 4-input NAND function. The outputs are fully buffered for highest noise immunity and pattern insensitivity of output impedance.
Fig.2 Pinning diagram.
Fig.1 Functional diagram.
HEF4012BP(N):
14-lead DIL; plastic
HEF4012BD(F):
14-lead DIL; ceramic (cerdip)
(SOT27-1) (SOT73) HEF4012BT(D):
14-lead SO; plastic (SOT108-1)
( ): Package Designator North America
Fig.3 Logic diagram (one gate).
FAMILY DATA, IDD LIMITS category GATES see Family Specifications
January 1995
2
Philips Semiconductors
Product specification
HEF4012B gates
Dual 4-input NAND gate AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V
TYPICAL EXTRAPOLATION FORMULA
SYMBOL
TYP
MAX
70
135
ns
43 ns + (0,55 ns/pF) CL
tPHL
25
50
ns
14 ns + (0,23 ns/pF) CL
20
35
ns
12 ns + (0,16 ns/pF) CL
Propagation delays In → On HIGH to LOW
5 10 15 5
LOW to HIGH
10
tPLH
15 Output transition times HIGH to LOW
5 10
tTHL
15 5 LOW to HIGH
10 15
VDD V Dynamic power
5
tTLH
70
140
ns
43 ns + (0,55 ns/pF) CL
30
60
ns
19 ns + (0,23 ns/pF) CL
25
50
ns
17 ns + (0,16 ns/pF) CL 10 ns + (1,0 ns/pF) CL
60
120
ns
30
60
ns
9 ns + (0,42 ns/pF) CL
20
40
ns
6 ns + (0,28 ns/pF) CL 10 ns + (1,0 ns/pF) CL
60
120
ns
30
60
ns
9 ns + (0,42 ns/pF) CL
20
40
ns
6 ns + (0,28 ns/pF) CL
TYPICAL FORMULA FOR P (µW) 1100 fi + ∑ (foCL) × VDD2
where fi = input freq. (MHz)
dissipation per
10
4400 fi + ∑ (foCL) ×
package (P)
15
12 900 fi + ∑ (foCL) ×
VDD2 VDD2
fo = output freq. (MHz) CL = load capacitance (pF) ∑ (foCL) = sum of outputs VDD = supply voltage (V)
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both 1Gb and 10Gb. Fabric Extender TAP Capabilities. Provides mirroring capabilities for SFP+ based Direct Attach Copper (DAC), Twinax, or Active Optical ...
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for 1Gb, 10Gb, 40Gb, and 100Gb connections. A combination of split ratios are available. Highly reliable construction ensures maximum link continuity. G-TAP ...
Jan 4, 1995 - The system comprising one HEF4751V U.D. together with ... Programming is performed in BCD code in a bit-parallel, ... to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.
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Mar 4, 1997 - mA. Ptot total power dissipation. Tamb ⤠25 °C. â. â. 250. mW. hFE. DC current gain. IC = 10 mA; VCE = 1 V. 20. 80. â. fT transition frequency.
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Product specification. Schottky barrier diode. BAT17. GRAPHICAL DATA. Fig.2 Forward current as a function of forward voltage; typical values. (1) Tamb = 100 ...
Jul 1, 1997 - ... the original dimensions). 0.45. 0.15. SOT323. SC-70 w M bp. D e1 e. A. B. A1. Lp. Q detail X .... +66 2 398 0793. Turkey: Talatpasa Cad. No.
Sep 1, 1983 - Product specification. File under Integrated ... 1,3. â. V. Fig.2 Power derating curve. .... fine solder particles, flux and binding agent) to be applied.
