A voltage buffer takes the input voltage which may have a relatively large ... Effective voltage buffer stage. ⢠v. G ..... Common-drain amplifier: good voltage buffer.
A voltage buffer takes the input voltage which may have a relatively large Thevenin resistance and replicates the voltage at the output port, which has a low output resistance Input signal is applied to the gate Output is taken from the source To first order, voltage gain ≈ 1 Input resistance is high Output resistance is low
• • • • •
– Effective voltage buffer stage
How does it work? •
vG ↑⇒ iD cannot change ⇒ vS ↑ – Source follower
6.012 Spring 2004
2
Biasing the Common-drain amplifier VDD
signal source
RS
VSS +
vs iSUP
vOUT
signal load
RL
VBIAS -
VSS
• •
Assume device in saturation; neglect RS and RL; neglect CLM (λ = 0) Obtain desired output bias voltage – Typically set VOUT to”halfway” between VSS and VDD.
• •
Output voltage maximum VDD-VDSsat Output voltage minimum set by voltage requirement across ISUP.
vin = v gs + vout vout = gm v gs (ro // roc ) Then:
Avo =
6.012 Spring 2004
gm 1 gm + ro // roc
≈1
4
Input and Output Impedance Input Impedance : Rin = ∞ Output Impedance: +
+
vin
RS
it
+ vgs -
gmvgs
ro//roc
-
-
vt
vin = 0; vt = -vgs effectively: resistance of value 1/gm
Rout =
it +
gmvt
1 gm +
1 ro // roc
ro//roc
≈
-
vt
1 gm
Small! Loaded voltage gain:
Av = Avo
6.012 Spring 2004
RL RL ≈ ≈1 1 R L + Rout R + L gm 5
Effect of Back Bias If MOSFET was not fabricated in an isolated p-well, then body is tied to wafer substrate (connected to VSS) VDD
signal source RS VSS +
vs iSUP
vOUT
signal load RL
VBIAS VSS
Two consequences: •
Bias is affected – VT depends on VBS – VBS = VSS – VOUT ≠ 0
•
Small signal figures of merit affected – Signal shows up between B and S – vbs = -vout
6.012 Spring 2004
6
Small-signal Analysis (with back-bias) See text pp.523-527 for details D
G
+
gmvgs
gmbvbs
ro
S
vin
+
roc -
vout
B
-
vbs=-vout
+ vgs -
+
vin
+
gmvgs
gmbvout
ro//roc
-
Avo =
vout -
gm 1 g m + g mb + ro // roc
≈
gm > CE Amplifier Input resistance ~ CS Amplifier – We want a large input resistance because the controlled generator is voltage controlled
•
Output resistance CS Amplifier – We want a large output resistance to deliver most of the output current to the load
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Relationship between circuit figures of merit and device parameters: W gm = 2I D µ nCox L γ gm gmb = 2 −2φ p − VBS ro ≈
1 λn I D Circuit Parameters
Device* Parameters
|Aio|
Rin
Rout
-1
1 g m + g mb
roc //[ro (1 + g m R s )]
ISUP ↑
-
↓
↓
W↑
-
↓
↑
µnCox ↑
-
↓
↑
L↑
-
↑
↑
* VBIAS is adjusted so that none of the other parameters change
Common Gate amplifier is often used as a current buffer i.e. transform a current source with medium source resistance to an equal current with high source resistance (in multistage amplifiers, other stages provide the current gain). 6.012 Spring 2004
16
What did we learn today? Summary of Key Concepts •
Common-source amplifier: good voltage amplifier better transconductance amplifier – Large voltage gain – High input resistance – Medium / high output resistance
•
Common-drain amplifier: good voltage buffer – Voltage gain ≈ 1 – High input resistance – Low output resistance
•
Common-gate amplifier: good current buffer – Current gain ≈ 1 – Low input resistance – High output resistance
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