COEN 313 – Digital Design II Lab Report – Lab 02 by Olivier

An ALU (Arithmetic and Logic Unit) is a circuit that does the mathematical operations inside a CPU. It generally operates on 2 operands and control signals ...
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COEN 313 – Digital Design II Lab Report – Lab 02

by Olivier Milla ID: 5774853

1. Objectives 1. Implement a simple ALU. 2. Compare two implementations and consequences on the final circuit.

2. Theory An ALU (Arithmetic and Logic Unit) is a circuit that does the mathematical operations inside a CPU. It generally operates on 2 operands and control signals generated by a Control Unit (CU). It is a purely combinational circuit (in our case). In VHDL, a combinational circuit can be written with direct concurrent statements or with a combinational process. We are interested here in knowing how the final circuit will differ if one implementation is chosen above the other one.

3.Design Approach The design is straightforward. We code the ALU according to the given specifications in the two required styles (conccurent and process) as given in appendix.

4. The Simulation The complete simulation of both implementation leads to the same diagram as given in the appendix. We first test the required feature that without any control set (add,inc,dec,neg) the output must be X. Then we test all the 4 control one by one.

5. Synthesis The synthesis scripts are given in appendix. They contain a typo due to copy/paste from previous script. (this typo generates a warning in the synthesis as the synthesis log show (also in appendix) but doesn't prevent the synthesis to finish without any error.) Also in index is the report_fpga for the processed implementation of the ALU. We can then compare the FPGA use for both implementation and they are exactly the same. The circuit as produced by the design_analyzer doesnt show any difference as well. One of this circuit is also attached in appendix. The timing will be the same in both implementation as they produce the same circuit. The critical path is from the input A(or B) to the output Z.

6.Hardware Implementation Once synthesized, our code can be implemented by the Xilinx place and route software and then downloaded to the card with the hardware debugger. The place and route software doesn't report any error and go through all the needed steps.

7. Conclusion If properly written, a combinational process produces a purely combinational circuit that can be equivalent to purely conccurent statements. If not, some unwanted latch can be produced, changing both the FPGA floorplan and circuit timing.