COEN 313 – Digital Design II Lab Report – Lab 01

by Olivier Milla ID: 5774853

1. Objectives 1. Design and Implement our first circuit using VHDL. How to write a structural design. 2. Use the tools that compose the chain from code compilation to the downloading of the produced file to the FPGA.

2. Theory The design of a simple circuit with a VHDL implementation fits an analyze scheme as provided for instance by a MCSE design methodology. Moreovoer, the design of the circuit in terms of functionals blocks fits particularly the architectural writing of VHDL. Once the code written, the designer has to go through a serie of tools to: 1. Get sure of the correctness of both his design and implementation 2. Get an idea of his performances in terms of FPGA space, timing analysis, etc. 3. Get the final file containing all his design including his port mapping to real hardware I/O. Globally this chain can be organized as follow:

MCSE « block » design

Structural VHDL code

compiler (vhdlan) (gvan)

Error Report

simulator (vhdldbx) (vhdlsim)

Timing diagram

Design Analyzer (design_analyzer)

Circuit diagram

Synthesis Tool (dc_shell)

Downloader (dsgnmgr)

Configured FPGA

Synthesis Report Synthesized File

*.bit

3.Design Approach My block/VHDL design is the following:

buff1

Buff1 in(4bits)

buff4

out(4bits)

mux41

out

buff1 sel (2bits) buff1

enable

mayor

This design can be viewed in the files buff1.vhd, buff4.vhfd, mux41.vhd, mayor.vhd provided in appendix. No error is produced by the compiler (gvan). There is no particular design issue except the main data line which has to be of type std_logic to provide 3-states logic. So only « sel » and « enable » are of bit logic, « in », »out4 » and « out » are std logic.

4. The Simulation The complete simulation of mayor.vhd with the Synopsys VHDL simulator can be seen in the appendix. The functionnment is as expected for all the cases that should be needed.

5. Synthesis This code is synthesizable as it only uses synthesizable VHDL keywords and structures. The Synopsys Design Analyzer hence doesn't complain as expected. We also make use of a dc_shell script also provided in the appendix. Note that as we use mutliple instances of a component we have to use the uniquify command to create a unique design for each cell instance.

6.Hardware Implementation Once synthesized, our code can be implemented by the Xilinx place and route software and then downloaded to the card with the hardware debugger. The final on-board behaviour is as expected if we exclude the fact that the result LED is active low and not active high as expected by our VHDL code. So the result led is inverted to our initial expectation.

7. Conclusion Even though a long serie of software are provided between the VHDL code and the final configured FPGA we can go through them in a pretty straightforward manner. Moreover it provides us with a serie of tests on our code and design.