Challenges of Deep Submicron Design
Jacques-Olivier Piednoir
Marc Heyberger
Cadence, VP R&D Europe
Cadence, Product Engineer Nanometer flow: 1
Introduction • Impact of Very Deep submicron technologies 90nm on EDA flow and tools • Flows and tools are in constant evolution • Note : This presentation only covers Cell based Digital design. –Does not cover Full custom implementation. –Does not cover Analog design.
• The presentation is very long 120 foils! We might have to skip some parts based on our progress and your background. Nanometer flow: 2
Summary of Tutorial
• Overview of 90nm Effects : –1) Introduction. –2) 90nm flow. –3) Step by step through the flow components: –5) Conclusion
Nanometer flow: 3
What do you get from the tutorial • Introduction to 90nm effect: Changing nature of delay, signal integrity. • Recap on basic notions: Delay calculation, Parasitic prediction, Floorplanning, Physical Synthesis • Limitation of current flow: Physical synthesis based. • New flow based on silicon virtual prototype • Introduction to 90nm hierarchical flow concepts: Block based topology, pin positioning, channelless architecture… • You will not become an expert in 90nm physical design but you will have the background to start investigating this new frontier.
Nanometer flow: 4
Technology Trends • Feature sizes are getting smaller : 250nm, 180nm, 130nm, 90nm, 65 nm • Gates counts and memory sizes are increasing : 10M, 20M, 100M • Clock speeds are increasing : 100Mhz, 400Mhz, 1 GHz • Power cannot increase at the same pace : 10W, 20W, 50W • Design time cannot increase : 3m, 6m, 12m Nanometer flow: 5
Tomorrow’s Design Technology Gates 65 nm 100M
Pins 1500
Frequency Power 1 GHz 100W
Reuse 75%
Power dissipation is limited
Design Time cannot increase Nanometer flow: 6
Chapter 1)
Short Overview of Top Down Design Methodology. Recap for beginners in the field. Can be skipped with students with design experience.
CADENCE CONFIDENTIAL
Top Down Design Function RTL Description
Software
Gate level Design Transistor Mask Layout
Complexity is addressed through Top-Down Methodology. Designing is refining the Chip description from High Level (RTL) to low level (Layout). Going from one level to the next and verifying each level is done semi automatically using EDA software Nanometer flow: 8
RTL Level • Describes the architecture of the chip in term of tranfer between registers. • Thousands lines of code for a complete chip.
module (nom + liste des ports à rajouter) always @(posedge ck) case (ir[15:13]) 3’b000: pc T3 (at least 0.5ns) since FF3 has significant slack while FF2 does not. Thus FF2 “borrows” slack from FF3 improving the margins General Concepts
Nanometer flow: 85
Clock Tree Synthesis (CTS) Overview • Match delays at leaf nodes using equivalent receiving loads and interconnect segments • Commonly implemented using Routing Estimation Advantages
Disadvantages
• Low power compared to mesh
• Netlist changes
• Supports clock gating
• Larger/unpredictable insertion delay and skew
• Distributed power consumption (less temperature gradient in substrate)
• Sensitive to process/voltage/temp variations • May alter port connections
Approaches:CTS
Nanometer flow: 86
Clock Ports after CTS
chip
chip
Clk Clk
sb1
Before
Approaches:CTS
sb1
multiple clock ports when the clock tree is built
After Nanometer flow: 87
Parasitic Extraction
Through the flow step by step
CADENCE CONFIDENTIAL
2D Extraction • Area, fringe(periphery) coefficients • No topology affect • No coupling affect • Handles full chip extraction • Fast but Inaccurate w
Valid for older technologies where wire aspect ratios (w/t) were large and area cap dominated
lateral cap
t area cap
2-D extraction
General Concepts:Accuracy
Nanometer flow: 89
2.5D Extraction • 2D orthogonal structures • Coefficients from 3D field solvers • Eliminate conductors 2-3 levels away
m2 horizontal cut m1 m1
m2 vertical cut
m2 m1
General Concepts:Accuracy
Nanometer flow: 90
3D Extraction and Field Solvers • Field Solvers use Maxwell’s equations to determine capacitance – Time consuming – Capacity limited
• 3D Extractors use pre-solved profiles based on 3D field solver results – Inaccuracies occur where profiles don’t exactly match design – Accurately model coupling effects necessary for 0.13µm and below Typical 3D extractor 3D field solutions table-look up or analytical model
layout pattern recognition algorithm 3D field solution
General Concepts:Accuracy
Nanometer flow: 91
Back Annotation Formats: DSPF • DSPF (Detailed Standard Parasitic Format) – Distributed R, C of interconnect as well as lumped net capacitance – Encapsulates blocks via pin properties (direction, loading, driving cell) – DSPF is independent of cell driver and cell load – DSPF files can be very large – If the extraction is less granular the data size gets smaller at the cost of reduced accuracy Distributed RC network R1
R2
C1
Rn C2
Cn
DSPF of interconnect
General Concepts:Formats:DSPF
Nanometer flow: 92
Back Annotation Formats: RSPF RSPF (Reduced Standard Parasitic Format) • Reduced model – Driver represented by a PI model
Driver side
Loads
– Interconnect loading Elmore
RL1
– An order of magnitude smaller than DSPF file
• RSPF reduction is done with known cell driver and known cell load
Rπ C1
V
CL1 RL2
C2
– Changing drive cell change RSPF – Necessary to know boundary conditions of design for accurate RSPF
• RSPF of different levels of hierarchy in hierarchical designs can not be combined in simple manner
General Concepts:Formats:RSPF
V
CL2
RSPF of interconnect
Nanometer flow: 93
Back Annotation Formats: SPEF • SPEF (Standard Parasitic Exchange Format) – IEEE standard 1481 (part of Delay and Power Calculation System) based on DSPF/RSPF – Mixed mode representation (detailed/reduced in a single file) – Triplet to account for process variations on R, C, L (best:typical:worst) External driver cell is included in block level SPEF but external net parasitics are not
block SPEF pin
General Concepts:Formats:SPEF
Nanometer flow: 94
Coupling Parasitics • Coupling can only be extracted and analyzed after detailed routing
• Capacitive coupling – Local phenomenon
• Inductive coupling (mutual inductance)
• Size of files necessary to represent coupling becoming increasingly large
– Can span large areas of the design
• Difficult to model across hierarchical – Few solutions and very difficult to analyze boundaries
self inductance
magnetic field couples two loops (current return path)
coupling caps
active current loop mutual inductance
substrate
General Concepts
ground grid
Nanometer flow: 95
Inductance Overview • When should inductance be considered – Self Inductive impedance is comparable to R
Length (cm) 10.00 1. Inductance is not important because of high attenuation.
– Lower R (wider global net). – Higher Frequency (shorter transition time).
l>
tr 2 LC
1&2
1.00
– Longer Net (but not too long)
Inductance is important
• Impact of on-chip inductance
l
