SN54/74LS377 SN54/74LS378 SN54/74LS379

OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE The SN54 / 74LS377 is an 8-bit register built using advanced Low Power Schottky technology. This register consists of eight D-type flip-flops with a buffered common clock and a buffered common clock enable. The SN54 / 74LS378 is a 6-Bit Register with a buffered common enable. This device is similar to the SN54 / 74LS174, but with common Enable rather than common Master Reset. The SN54 / 74LS379 is a 4-Bit Register with buffered common Enable. This device is similar to the SN54 / 74LS175 but features the common Enable rather then common Master Reset.

• • • • •

8-Bit High Speed Parallel Registers Positive Edge-Triggered D-Type Flip Flops Fully Buffered Common Clock and Enable Inputs True and Complement Outputs Input Clamp Diodes Limit High Speed Termination Effects

PIN NAMES

E D0 – D3 CP Q0 – Q3 Q0 – Q 3

LOW POWER SCHOTTKY

J SUFFIX CERAMIC CASE 732-03

20 1

LOADING (Note a)

Enable (Active LOW) Input Data Inputs Clock (Active HIGH Going Edge) Input True Outputs (Note b) Complemented Outputs (Note b)

OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE

HIGH

LOW

0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. 10 U.L.

0.25 U.L. 0.25 U.L. 0.25 U.L. 5 (2.5) U.L. 5 (2.5) U.L.

N SUFFIX PLASTIC CASE 738-03

20 1

DW SUFFIX SOIC CASE 751D-03

20 1

NOTES: a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges.

J SUFFIX CERAMIC CASE 620-09 16 1

N SUFFIX PLASTIC CASE 648-08

16 1

16 1

D SUFFIX SOIC CASE 751B-03

ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXDW SN74LSXXXD

FAST AND LS TTL DATA 5-1

Ceramic Plastic SOIC SOIC

SN54/74LS377 • SN54/74LS378 • SN54/74LS379 CONNECTION DIAGRAM DIPS (TOP VIEW) SN54 / 74LS377 VCC Q7 20 19

D7 18

D6 17

Q6

Q5

16

15

D5 14

D4 13

Q4

CP

12

11 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.

1 E

2 Q0

3 D0

4 D1

5 Q1

6 Q2

7 D2

8 D3

9 Q3

10 GND

SN54 / 74LS378 VCC 16

Q5 15

D5 14

D4 13

Q4 12

D3 11

Q3

CP

10

9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.

1 E

2 Q0

3 D0

4 D1

5 Q1

6 D2

7 Q2

8 GND

Q2

CP

10

9

SN54 / 74LS379 VCC 16

Q3 15

Q3 14

D3 13

D2 12

Q2 11

NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.

1 E

2 Q0

3 Q0

4 D0

5 D1

6 Q1

7 Q1

FAST AND LS TTL DATA 5-2

8 GND

SN54/74LS377 • SN54/74LS378 • SN54/74LS379 LOGIC DIAGRAMS SN54 / 74LS377 3

4

7

8

13

14

17

18

D0

D1

D2

D3

D4

D5

D6

D7

CP D Q

CP D Q

CP D Q

CP D Q

CP D Q

CP D Q

CP D Q

CP D Q

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

2

5

6

9

12

15

16

19

E ENABLE 1

CP CLOCK 11

SN54 / 74LS378 3

4

6

11

13

14

D0

D1

D2

D3

D4

D5

CP D E Q

CP D E Q

CP D E Q

CP D E Q

CP D E Q

CP D E Q

Q0

Q1

Q2

Q3

Q4

Q5

2

5

7

10

12

15

CP 9

1

E

SN54 / 74LS379

CP

4

5

12

13

D0

D1

D2

D3

9

CP

D

E

CP

D

E

CP

D

E

CP

D

E

Q

Q

Q

Q

Q

Q

Q

Q

Q0

Q0

Q1

Q1

Q2

Q2

Q3

Q3

3

2

6

7

11

10

14

15

1

E

FAST AND LS TTL DATA 5-3

SN54/74LS377 • SN54/74LS378 • SN54/74LS379 GUARANTEED OPERATING RANGES Symbol

Parameter

Min

Typ

Max

Unit

VCC

Supply Voltage

54 74

4.5 4.75

5.0 5.0

5.5 5.25

V

TA

Operating Ambient Temperature Range

54 74

– 55 0

25 25

125 70

°C

IOH IOL

Output Current — High

54, 74

– 0.4

mA

Output Current — Low

54 74

4.0 8.0

mA

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol S b l

Parameter P

Min

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

VIK

Input Clamp Diode Voltage

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

IIH

Input HIGH Current

IIL IOS

Input LOW Current

ICC

Power Supply Current

Typ

Max

Unit U i

2.0 54

0.7

74

0.8 – 0.65

– 1.5

Test Conditions T C di i

V

Guaranteed Input HIGH Voltage for All Inputs

V

Guaranteed Input LOW Voltage for All Inputs

V

VCC = MIN, IIN = – 18 mA

54

2.5

3.5

V

74

2.7

3.5

V

VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table VCC = VCC MIN, VIN = VIL or VIH per Truth Table

54, 74

0.25

0.4

V

IOL = 4.0 mA

74

0.35

0.5

V

IOL = 8.0 mA

VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V

Short Circuit Current (Note 1)

– 20

LS377 LS378 LS379

20

µA

0.1

mA

– 0.4

mA

– 100

mA

VCC = MAX, VIN = 0.4 V VCC = MAX

28 22 15

mA

VCC = MAX, NOTE 1

NOTE: With all inputs open and GND applied to all data and enable inputs, ICC is measured after a momentary GND, then 4.5 V is applied to clock. Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V) Limits S b l Symbol fMAX tPLH tPHL

P Parameter Maximum Clock Frequency

Min

Typ

30

40

Propagation Delay, Clock to Output

Max

U i Unit

T Test C Conditions di i

MHz

17 18

27 27

VCC = 5 5.0 0V CL = 15 pF

ns

AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V) Limits Symbol S b l tW ts

Parameter P

Min

Typ

Max

Unit U i

Any Pulse Width

20

ns

Data Setup Time

20

ns

Inactive — State

10

ns

Active — State

25

ns

5.0

ns

ts

Enable Setup Time

th

Any Hold Time

DEFINITION OF TERMS SETUP TIME (ts) — is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW-to-HIGH in order to be recognized and transferred to the outputs.

Test Conditions T C di i

VCC = 5.0 50V

the clock transition from LOW-to-HIGH that the logic level must be maintained at the input in order to ensure continued recognition. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW-to-HIGH and still be recognized.

HOLD TIME (th) — is defined as the minimum time following

FAST AND LS TTL DATA 5-4

SN54/74LS377 • SN54/74LS378 • SN54/74LS379 TRUTH TABLE Dn

Qn

Qn

H

E

CP

X

No Change

No Change

L

H

H

L

L

L

L

H

L = LOW Voltage Level H = HIGH Voltage Level X = Immaterial

AC WAVEFORMS

SN54 / 74LS377 1/fmax

1/fmax tW

1.3 V

CP

1.3 V

*

CP

ts(L) th(H)

ts(H) D OR E

SN54 / 74LS378

1.3 V

1.3 V tPLH

Q

ts(H)

th(L) E, D

1.3 V

th(H)

ts(L)

tPHL

1.3 V

1.3 V

Q

Figure 1. Clock to Output Delays Clock Pulse Width, Frequency, Setup and Hold Times Data or Enable to Clock

1/fmax

tW

1.3 V

1.3 V

ts(H) E, D

*

ts(L) th(H) 1.3 V

th(L) 1.3 V

tPLH Q

tPLH 1.3 V

Figure 2. Clock to Output Delays Clock Pulse Width, Frequency, Setup and Hold Times Data or Enable to Clock

SN54 / 74LS379

CP

th(L) 1.3 V

1.3 V

*

tPHL

tW 1.3 V

1.3 V

1.3 V

tPHL 1.3 V

*The shaded areas indicate when the input is permitted to change for predictable output performance.

Figure 3. Clock to Output Delays Clock Pulse Width, Frequency, Setup and Hold Times Data, Enable to Clock

FAST AND LS TTL DATA 5-5