202 PRC PIC18 Peripheral Configuration and MPLAB-C18 Programming Techniques

V3.2 August 10, 2007

Objectives When you finish this class, you will understand PIC18: Architecture Interrupts Interrupt Handlers Basic Peripherals Peripheral Configuration Programming in C using MPLAB C18 © 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 2

Agenda Architecture Overview Programmers’ Model Program Memory Stack Data Memory

Instruction Set Overview

PIC18 Interrupts

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 3

Agenda (continued) Development Tools MPLAB IDE, ICD2, PICDEM2 Plus MPLAB C18 C Language Extensions Program Memory Variables SFR Access Inline Assembly Mixing C and Assembly Defining Sections Configuration Settings Support Interrupt Support

Lab 0: My First C18 Project © 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 4

Agenda (continued) Peripherals and Hands-On Exercises I/O Ports & External Interrupts Lab 1: I/O Ports and Ext. Interrupts

Analog: Comparators, VREF, and ADC Lab 2: A/D Converter

Timers Lab 3: Counters

CCP (Capture, Compare & PWM) Lab 4: PWM: Generating PWM signals and Lab 5: Capture: Measuring frequency and duty cycle © 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 5

Agenda (continued) MSSP (I2C™, SPI™ and Microwire™) Lab 6: Communicate with I2C Temp Sensor

USART Lab 7: RS-232 Communications with PC and Table Read/Write Operations

Oscillators and Power Saving Modes Special features PLVD, PBOR, ICSP, WDT, Resets

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 6

PIC18 Architecture Overview

V3.2 August 10, 2007

Harvard Architecture 8-bit microcontroller 16-bit Instruction width Data Transfer Mechanism between PM and DM 8 – bit window

Program Memory (Up to 2MB)

Data Memory

PIC18

16

© 2006 Microchip Technology Incorporated. All Rights Reserved.

RISC CPU

202 PRC

8

(Up to 4KB)

Slide 8

PIC18 Block Diagram

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 9

PIC18 Programmers’ Model Program Memory, Data Memory, Data Path, CPU Registers, HW Stack

V3.2 August 10, 2007

Program Memory Organization 21-Bit Program Counter 2MB Address Space

PC always = 0 16-bit Program Memory is Byte Addressable

Reset Vector @ 0x00 Interrupt Vectors High Priority @ 0x08 Low Priority @ 0x18 © 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 11

Return Address Stack Stack Memory – 31 Levels Used by interrupts, CALL, RCALL, RETURN, RETLW and RETFIE instructions 20

0

Top of Stack Registers: Stack Pointer:

4

0

20

0

RESET State: No RAM at level 0

Stack grows “up”

No rollover back to level 0! © 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 12

STKPTR Register R/C-0

R/C-0

R/W-0

R/W-0

R/W-0

R/W-0

bit 7

R/W-0 bit 0

bit 7

STKFUL: Stack Full Flag Bit 1 = Stack full or overflow occurred 0 = Reset or cleared by user software

bit 6

STKUNF: Stack Underflow Flag Bit 1 = Stack underflow occurred 0 = Reset or cleared by user software

bit 4-0

SP4:SP0: Stack Pointer Bits

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 13

Programmer’s Model

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 14

Table Pointer Program Memory Data Access (R/W) Register file (8 bits)

Program memory (16 bits) TBLPTR 21-bit Address High byte

TABLAT

Low byte

Data 055h

TBLPTRU TBLPTRH TBLPTRL TABLAT

TBLPTR pointer is used to address program memory TBLRD instruction is used to read a byte 2 cycles not incl. TBLPTR set-up

TBLWT instruction is used to load write buffer EECON1 register controls actual write cycle Erase block size 32 or 64 bytes (see data sheet) 6 ms to update one row of 64 bytes See section 6.5 of the datasheet for an example of the code sequence © 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 15

Table Pointer Assembly Operations

TBLRD/TBLWT * no change to table pointer

TBLRD/TBLWT *+ auto post-increment of table pointer

TBLRD/TBLWT *auto post-decrement of table pointer

TBLRD/TBLWT +* auto pre-increment of table pointer

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 16

Table Pointer Use in C

rom - data type qualifier indicates that a variable is located in program memory space Compiler will access variable using TBLRD and TBLWT instructions Can be used on any data type Examples in C18 section…

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 17

Data Memory Organization Data Memory up to 4k bytes Divided into 256 byte banks Half of bank 0 and half of bank 15 form a virtual bank that is accessible no matter which bank is selected BSR determines which bank is currently selected © 2006 Microchip Technology Incorporated. All Rights Reserved.

000h 07Fh

Access Access RAM RAM

080h 0FFh

Bank Bank 00 GPR GPR

PIC18F2520/4520 Register File Map

100h

1FFh

Bank Bank 11 GPR GPR

200h

2FFh

Bank Bank 22 GPR GPR

D00h

DFFh

Bank Bank 13 13 GPR GPR

Access Bank Access Access RAM RAM

00h 7Fh

Access Access SFR SFR

80h FFh

256 Bytes

E00h

EFFh

Bank Bank 14 14 GPR GPR

F00h F7Fh

Bank Bank 15 15 GPR GPR

F80h FFFh

Access Access SFR SFR

202 PRC

Slide 18

PIC18 Instruction Set Overview, Extended Mode

V3.2 August 10, 2007

Instruction Set Overview Data Move Instructions Data memory to data memory Data memory to program memory (& vice-versa) Literal

Arithmetic, Logic, Shift Instructions Single Cycle 8 x 8 Multiply (100ns) Powerful Bit Manipulation Single cycle bit set, clear or toggle Operate directly on all registers including I/O

Branching / Conditional Branching © 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 20

Instruction Set Overview 77 Standard Instructions 73 are single word 4 two-word MOVFF, LFSR, CALL, GOTO

Most Instructions Are Single Cycle 4 two word instructions are two cycle 10 branches, 10 skip instructions are 1 or 2 cycle 8 table operation instructions are two cycle 3 returns are 2 cycle

Table Read/Write 8 Extended Instructions © 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 21

PIC18F: Extended Mode Enable/Disable by XINST configuration bit Indexed Literal Offset Addressing mode and… Instruction

Description

ADDFSR

f, k

Add literal to FSR

ADDULNK

k

Add literal to FSR2 and return

CALLW

Call subroutine using WREG

MOVSF

Zs, fd

Move zs (source) to 1st word fd (destination) 2nd word

MOVSS

Zs, Zd

Move zs (source) to 1st word zd (destination) 2nd word

PUSHL

k

Store literal at FSR2, decrement FSR2

SUBFSR

f, k

Subtract literal from FSR

SUBULNK

k

Subtract literal from FSR2 and return

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 22

Extended Mode Advantage C Compiler Optimized

Software Stack Pointer manipulation Dynamic allocation and de-allocation of software stack Manipulation of variables located in a software stack Direct Function pointer invocation

Result:

Reduced code size & execution time of C-based programs

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 23

PIC18 Interrupts

V3.2 August 10, 2007

Interrupt Overview Multiple Internal and External Sources Global Enable Bit Individual Enable, Flag and Priority Bits Two Modes of Operation Legacy: RCON.IPEN = 0 (Default) Priority: RCON.IPEN = 1

Most Interrupts Wake PIC from Sleep Fast Context Save/Restore Latency of 3-4 Instruction Cycles © 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 25

Interrupt Logic Legacy Mode TMR0IF

Core Interrupts

TMR0IE Other Core Interrupts

TMR1IF TMR1IE

Wakeup to CPU Peripheral Interrupts

Interrupt to CPU Vector to 0x0008

Other Peripheral Interrupts

GIE

PEIE

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 26

Interrupt Logic Priority Mode IP IE IF

INT0IF

INT0IE GIEH

Vector to 0x0008 High Priority Interrupt to CPU Wakeup to CPU Low Priority Interrupt to CPU

IP IE IF

© 2006 Microchip Technology Incorporated. All Rights Reserved.

GIEL

202 PRC

Vector to 0x0018

Slide 27

Interrupt Overview Interrupt Sources 3 or 4 External Interrupts (INT0-INT3) Edge Triggered Rising or Falling selected in INTCON2 register

PORTB Interrupt on Change (RB4-RB7) Timer Rollover/Overflow Events Comparator Output Change A/D Conversion Complete Communication Channel Events Other Peripheral Events… © 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 28

Enabling Interrupts (slide 1 of 7)

Set Interrupt Priority Enable Legacy or priority mode interrupt operation RCON Register

IPEN

SBOREN

---

RI

TO

PD

POR

BOR

IPEN: Interrupt Priority Enable 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupt (PIC16 compatibility mode)

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 29

Enabling Interrupts (slide 2 of 7) Set Peripheral Interrupt Priority 1 = High Priority, 0 = Low Priority IPR1 Register

PSPIP PSPIP: ADIP: RCIP: TXIP:

ADIP

RCIP

TXIP

Parallel Slave Interrupt Priority A/D Converter Interrupt Priority EUSART Rcv Interrupt Priority EUSART Tx Interrupt Priority

SSPIP

SSPIP: CCPIP: TMR2IP: TMR1IP:

CCP1IP

TMR2IP

TMR1IP

MSSP Interrupt Priority CCP1 Interrupt Priority Timer2 Interrupt Priority Timer1 Interrupt Priority

IPR2 Register

OSCIP OSCIP: CMIP: ---EEIP:

CMIP

---

EEIP

Oscillator Fail Interrupt Priority Comparator Interrupt Priority Unimplemented Bit Data EEPROM/Flash Write Operation Interrupt Priority

© 2006 Microchip Technology Incorporated. All Rights Reserved.

BCLIP

BCLIP: HLVDIP: TMR3IP: CCP2IP:

202 PRC

HLVDIP

TMR3IP

CCP2IP

Bus Collision Interrupt Priority High/Low Voltage Detect Interrupt Priority Timer3 Interrupt Priority CCP2 Interrupt Priority

Slide 30

Enabling Interrupts (slide 3 of 7)

Set Peripheral Interrupt Enables 1 = Enabled, 0 = Disabled PIE1 Register

PSPIE PSPIE: ADIE: RCIE: TXIE:

ADIE

RCIE

TXIE

SSPIE SSPIE: CCPIE: TMR2IE: TMR1IE:

Parallel Slave Interrupt Enable A/D Converter Interrupt Enable EUSART Rcv Interrupt Enable EUSART Tx Interrupt Enable

CCPIE

TMR2IE

TMR1IE

MSSP Interrupt Enable CCP1 Interrupt Enable Timer2 Interrupt Enable Timer1 Interrupt Enable

PIE2 Register

OSCIE OSCIE: CMIE: ---EEIE:

CMIE

---

EEIE

Oscillator Fail Interrupt Enable Comparator Interrupt Enable Unimplemented Bit Data EEPROM/Flash Write Operation Interrupt Enable

© 2006 Microchip Technology Incorporated. All Rights Reserved.

BCLIE

BCLIE: HLVDIE: TMR3IE: CCP2IE:

202 PRC

HLVDIE

TMR3IE

CCP2IE

Bus Collision Interrupt Enable High/Low Voltage Detect Interrupt Enable Timer3 Interrupt Enable CCP2 Interrupt Enable

Slide 31

Enabling Interrupts (slide 4 of 7)

Set Core Interrupt Priority 1 = High Priority, 0 = Low Priority INTCON2 Register

RBPU

INTEDG0 INTEDG1 INTEDG2

---

TMR0IP

---

RBIP

TMR0IP: TMR0 Overflow Interrupt Priority RBIP: RB Port Change Interrupt Priority INTCON3 Register

INT2IP INT2IP: INT1IP:

INT1IP

---

INT2IE

INT1IE

---

INT2IF

INT1IF

INT2 External Interrupt Priority INT1 External Interrupt Priority

NOTE: INT0 does not have an IP bit – it is always a high priority interrupt

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 32

Enabling Interrupts (slide 5 of 7)

Set Core Interrupt Enables 1 = Enabled, 0 = Disabled INTCON Register

GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

INT2IF

INT1IF

TMR0IE: TMR0 Overflow Interrupt Enable INT0IE: INT0 External Interrupt Enable RBIE: RB Port Change Interrupt Enable INTCON3 Register

INT2IP

INT1IP

INT2IE

--INT2IE: INT1IE:

INT1IE

---

INT2 External Interrupt Enable INT1 External Interrupt Enable

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 33

Enabling Interrupts (slide 6 of 7)

Enable Peripheral Interrupts (set PEIE) INTCON Register

GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

PEIE/GIEL: Peripheral Interrupt Enable When IPEN = 0 (legacy mode) 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts When IPEN = 1 (priority mode) 1 = Enables all low priority peripheral interrupts 0 = Disables all low priority peripheral interrupts

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 34

Enabling Interrupts (slide 7 of 7)

Enable Global Interrupts INTCON Register

GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

GIE/GIEH: Global Interrupt Enable When IPEN = 0 (legacy mode) 1 = Enables all unmasked interrupts 0 = Disables all interrupts When IPEN = 1 (priority mode): 1 = Enables all high priority interrupts 0 = Disables all interrupts

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 35

Development Tools MPLAB IDE, ICD2, PICDEM2 Plus

V3.2 August 10, 2007

MPLAB IDE MPLAB® Integrated Development Environment Integrates Microchip and 3rd Party Tools Code Editor Assembler and Compilers Linker and Librarian Simulator, Debuggers and Emulators Programmers © 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 37

MPLAB®-ICD 2 and PICDEM™ 2 Plus

ICSP over RJ11

USB

All labs will use the ICD 2 and PICDEM 2 Plus ICD2 In-circuit programmer and debugger PICDEM 2 Plus demo board for most PIC16/18 devices © 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 38

PICDEM 2 Plus Demo Board

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 39

Hands-on Exercises All labs are in the following directory: C:\RTC\202_PRC\LabN, where N is the number of the lab Solution workspaces are supplied in the following directory: C:\RTC\202_PRC\LabN\Solution, where N is the number of the lab Directions for the labs are in the file C:\RTC\202_PRC\Presentation & Handouts\202_PRC Handout.pdf

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 40

MPLAB C18 C Language Extensions

V3.2 August 10, 2007

MPLAB C18 Compiler PIC18 only Targets ANSI:1989 standard Standard C functions Run time libraries $495 US – One-time cost. Student Version ($free): www.microchip.com/c18 After 60 days: Optimizations disabled Extended mode disabled © 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 42

C18 C Language Extensions Program Memory Variables SFR Access Inline Assembly Mixing C and Assembly Defining Sections Configuration Settings Support Interrupt Support

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 43

Variables in Program Memory rom - data type qualifier indicates that a variable is located in program memory space Compiler will access variable using TBLRD and TBLWT instructions Can be used on any data type

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 44

Program Memory Variables struct personal { char age; char weight; }; variable in data memory struct personal Jane = { 84, 110 }; variable in program memory rom struct personal Bob

= { 24, 180 };

rom -> ram struct personal * rom person1 = & Jane; ram -> rom rom struct personal * person2 = & Bob; rom -> rom rom struct personal * rom person3 = & Bob;

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 45

String Constants String literals (e.g., “Hello World”) are of type: const rom char [] Multiple versions of standard C string libraries are provided to help accommodate this: strcpypgm2ram( myvar, “Hello..” ); strlenpgm( “Hello World” );

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 46

Pointers Pointers to ram are always 16 bits wide: near char * access_var; // 16 bit ptr far char * gpr_var; // 16 bit ptr

Pointers to rom are 16 or 24 bits wide, depending on the memory model: near rom char * red_ptr; // 16 bit ptr far rom char * tan_ptr; // 24 bit ptr

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 47

C18 C Language Extensions Program Memory Variables SFR Access Inline Assembly Mixing C and Assembly Defining Sections Configuration Settings Support Interrupt Support

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 48

SFR Access: Byte Special Function Registers can be accessed directly in C code. For example: TRISD = 0x0f; if (PORTB == 0x55) {...}

Bit mask operations will typically generate PIC18 bit operations: PORTD |= 0x40; PORTD &= 0xfe;

© 2006 Microchip Technology Incorporated. All Rights Reserved.

// bsf PORTD, 6 // bcf PORTD, 0

202 PRC

Slide 49

SFR Access: Bits Bits may be referenced using the syntax: SFRbits.bitname

For example: PORTBbits.RB0 = 1; INTCONbits.GIEH = 0; © 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 50

C18 C Language Extensions Program Memory Variables SFR Access Inline Assembly Mixing C and Assembly Defining Sections Configuration Settings Support Interrupt Support

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 51

Inline Assembly Provides an interface between C and assembly language Typical uses: Generate specialized instructions (e.g. CLRWDT) Generate specific sequence of instructions

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 52

Inline Assembly Syntax: Specify all operands Directives are not supported C style comments Labels require a colon

void add5 (void) { static char foo=0; _asm // foo += 5 movlb foo

Use C-style literals (0x12 or 18, not H’12’)

movlw 0x5 addwf foo,1,1

Note: optimizations are disabled in functions with inline assembly.

_endasm }

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 53

Inline Assembly When using extended mode, specify indexed addressing using the access bit: char local; _asm movlw 0x5 addwf local,1,0 _endasm

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 54

C18 C Language Extensions Program Memory Variables SFR Access Inline Assembly Mixing C and Assembly Defining Sections Configuration Settings Support Interrupt Support

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 55

Mixing C and Assembly Requires sharing of symbols C

Assembly

Export

(nothing)

GLOBAL

Import

external declaration

EXTERN

Parameter passing is described in the MPLAB® C18 C Compiler User’s Guide as part of the calling convention © 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 56

Example of Mixing C / Asm // import function void infinite_asm( void );

; import function & data EXTERN infinite_c, c_count

// import data extern char asm_count;

udata asm_count res 1

char c_count;

code infinite_asm: movlb c_count incf c_count goto infinite_c

void infinite_c( void ) { asm_count++; infinite_asm(); }

; export function & data GLOBAL infinite_asm, asm_count

C file © 2006 Microchip Technology Incorporated. All Rights Reserved.

Assembly file 202 PRC

Slide 57

C18 C Language Extensions Program Memory Variables SFR Access Inline Assembly Mixing C and Assembly Defining Sections Configuration Settings Support Interrupt Support

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 58

Memory Sections A section is a collection of objects All data and code is allocated into sections Sections are located into memory regions by the linker

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 59

C18 Section Types MPLAB® C18 uses four types of sections: Data Memory udata

uninitialized data

int x;

idata

initialized data

int y = 5;

romdata data in program memory rom int z = 12;

Program Memory code program void foo (void) { }

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 60

Section Assignment A default section of each type is created for each C file ._ Ex. .code_foo.o, .idata_bar.o

Declarations are placed into the active section of the appropriate type

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 61

Specifying Sections It is possible to specify the section name and absolute address of a section #pragma type [access] [name[=address]]

Example Create a section to contain a function at the high priority interrupt vector address #pragma code high_vector_scn=0x0008 void high_vector (void) { _asm goto high_isr _endasm } © 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 62

Practical Use of Sections Create a section in order to place variables in access RAM #pragma udata access AccessSection; near long counter;

Variables in access memory must provide near keyword

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 63

C18 C Language Extensions Program Memory Variables SFR Access Inline Assembly Mixing C and Assembly Defining Sections Configuration Settings Support Interrupt Support

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 64

Configuration Settings Support Language extension to specify hardware configuration settings #pragma config

Used to specify “one-time” setting of hardware resources Ex. watchdog timer

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 65

Configuration Settings Support Example #pragma config WDT = ON Enables watchdog timer

Configuration bits and settings documented in MPLAB-IDE Help utility

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 66

C18 C Language Extensions Program Memory Variables Inline Assembly Mixing C and Assembly Defining Sections Configuration Settings Support Interrupt Support © 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 67

Interrupt Support Managing interrupts with the compiler has three components: Defining the interrupt service routine (ISR) Creating function(s) to vector to the interrupt service routines Preserving compiler managed resources (Prior to v3.00) Preserving compiler managed resources (After v3.00) © 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 68

Declaring Interrupt Service Routines

Defining a low priority ISR void isr_low (void); #pragma interruptlow isr_low void isr_low (void) { // Code for low priority ISR }

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 69

Declaring Interrupt Service Routines

Defining a high priority ISR void isr_high (void); #pragma interrupt isr_high void isr_high (void) { // Code for high priority ISR }

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 70

Vectoring to an ISR Create a section to contain a function at the high priority interrupt vector address #pragma code high_vector_scn=0x0008 void high_vector (void) { _asm goto high_isr _endasm }

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 71

ISR and Temporary Data Each ISR receives its own unique temporary data section Distinct from temporary data section used by normal C functions (.tmpdata)

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 72

Low vs. High Priority ISRs Low Priority ISR

High Priority ISR

Can be nested WREG, BSR, and STATUS saved by compiler Additional 10 words overhead compared to high priority ISR

© 2006 Microchip Technology Incorporated. All Rights Reserved.

Cannot be nested WREG, BSR, and STATUS saved in shadow registers by hardware Returns with “fast” return from interrupt

202 PRC

Slide 73

Creating an ISR Vector Create a function at the (high) ISR vector address: void high_isr (void); #pragma code high_vector_scn=0x0008 void high_vector (void) { _asm goto high_isr _endasm } #pragma code

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 74

Preserving Compiler Resources Prior to C18 v3.00 users were required to preserve compiler resources #pragma interrupt isr \ save=section(“.tmpdata”), PROD void isr (void) { int result; result = poll_device(); ... }

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 75

Preserving Compiler Resources C18 v3.xx automatically saves and restores context #pragma interrupt isr void isr (void) { int result; result = poll_device(); ... }

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 76

Lab 0 Objectives Upon completion of Lab 0 you should understand: How to create a C project within MPLAB using C18 How to successfully build the project, and program the device LEDs on RB1&RB3 should flash (make sure J6=ON!)

The implementation of some C language extensions provided by C18 How to inspect the code generated by the compiler

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 77

Launch MPLAB® IDE

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 78

Create a New Project

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 79

Name The New Project

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 80

Select the Language Tool C18, MPASM, or Third Party

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 81

Select MPLAB C18 Toolsuite

Note: mplink.exe, mcc18.exe & mplib.exe are located in c:\mcc18\bin (default C18 install) © 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 82

Select the Required MCU

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 83

Select The Required MCU

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 84

Set The Configuration Bits You configure the device core from this window if you want to override them for debugging purposes However, it is best to put the settings into the source code using #pragma _config macro to set the configuration word

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 85

Check The Configuration Bits

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 86

Add Source File(s) to Project Right-Click on ‘Source Files’ÆAdd Files

Source file: c:\rtc\202_PRC\Lab0\template_PIC18.c © 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 87

Add Header File(s) to Project Right-Click on ‘Header Files’ÆAdd Files

Header file: c:\mcc18\h\p18f4520.h © 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 88

Add Linker Script To Project Right-Click on ‘Linker Scripts’ÆAdd Files

Linker File: c:\mcc18\lkr\18f4520i.lkr © 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 89

Set The Project ‘Build’ Options

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 90

Set Include & LIB Search Paths

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 91

Enable .map File Generation

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 92

Build The Project

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 93

Successful Build

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 94

Select The Programmer (ICD2)

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 95

Connect To The Programmer Connect to the Programmer

Successful Connection

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 96

Program The Device

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 97

Project Review (follow along) Open template_PIC18.c using the editor Review the code sections and declarations

ViewÆProgram memory Find Interrupt Vectors Inspect C start-up code (file:c018i.c) Find main( )

Open .map file (where did the sections go?) ViewÆWatch Add ram_array, rom_array, ram_ptr, near_rom_ptr to watch window & run the code Do the addresses make sense?

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 98

PIC18 Peripherals

V3.2 August 10, 2007

PIC18 Common Peripherals Digital I/O Ports Analog Comparator Analog to Digital Converter Timers (0,1,2,3) Capture, Compare, PWM (CCP) Addressable USART (AUSART) Master Synchronous Serial Port (MSSP) Parallel Slave Port (PSP) © 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 100

Digital I/O Ports

V3.2 August 10, 2007

Digital I/O Ports Up to 70 bi-directional I/O pins Some multiplexed with peripheral functions

High drive capability 25mA source/sink capability

Direct, single cycle bit manipulation 4kV ESD protection diodes Based on human body model

After reset: Digital I/O default to Input (Hi-Z) Analog capable pins default to analog © 2006 Microchip Technology Incorporated. All Rights Reserved.

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Slide 102

Configuring Analog Pins for Digital Method depends on specific device Could be in ADCON1 register ADC Control Register 1 (ADCON1)

Port Configuration Bits

VCFG1 VCFG1 VCFG0 VCFG0 PCFG3 PCFG3 PCFG2 PCFG2 PCFG1 PCFG1 PCFG0 PCFG0

Could be in ANSEL registers 1 = Analog; 0 = Digital ANS7 ANS7 ANS6 ANS6 ANS5 ANS5 ANS4 ANS4 ANS3 ANS3 ANS2 ANS2 ANS1 ANS1 ANS0 ANS0 ANS13 ANS13 ANS12 ANS12 ANS11 ANS11 ANS10 ANS10 ANS9 ANS9 ANS8 ANS8

Some devices allow Port B configuration in configuration registers © 2006 Microchip Technology Incorporated. All Rights Reserved.

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Slide 103

I/O Port Direction Control

Bit n in TRISx controls the data direction of Bit n in PORTx 1 = Input, 0 = Output © 2006 Microchip Technology Incorporated. All Rights Reserved.

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Slide 104

Digital I/O Ports MOVF MOVF MOVWF MOVWF

Reads PORTX Pins (Physical state of pin) Reads PORTX Output Latch Register Writes to PORTX / LATX Writes to PORTX / LATX

PORTX,w LATX,w PORTX LATX

8-bit Data Bus

Read LATX

Write PORTX Write LATX LATX (PORTX Latches)

77

66

55

44

33

22

11

Read PORTX

00

PORTX I/O Pins © 2006 Microchip Technology Incorporated. All Rights Reserved.

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Slide 105

Why do we have LAT Reg? At Low Frequency or Low Capacitive Loading BSET PORTA,PIN0 BSET PORTA,PIN1

Q4

Q1

Q2

Q3

Voltage VIL V on PORTA,PIN0

Qclks Port A Read in RMW Operation

At High Frequency or High Capacitive Loading BSET PORTA,PIN0

BSET PORTA,PIN1

Q4 Q1 Q2 Q3 Q4 Voltage VIL V on PORTA,PIN0

Qclks Port A Read in RMW Operation

© 2006 Microchip Technology Incorporated. All Rights Reserved.

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Slide 106

Port B Options Configuring PORTB Interrupt on Change

RB7:RB4 have interrupt on change option Pins must be set as INPUT to be included INTCON Register R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

bit 7

R/W-x bit 0

bit 7

GIE/GIEH: Global Interrupt Enable bit 1 = Enables all unmasked (IPEN=0) / high priority (IPEN=1) interrupts 0 = Disables all interrupts

bit 3

RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt

bit 0

RBIF: RB Port Change Interrupt Flag bit 1 = At least one of the pins RB7:RB4 changed state (must be cleared in software) 0 = None of the RB7:RB4 pins changed state

© 2006 Microchip Technology Incorporated. All Rights Reserved.

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Slide 107

PORTB Options All PORTB pins have weak internal pull up. One bit controls all pins INTCON2 Register R/W-1

R/W-1

R/W-1

R/W-1

U-0

R/W-1

bit 7

bit 7

U-0

R/W-1 bit 0

RBPU: PORTB Pull-up Enable bit 1 = All PORTB Pull-ups are disabled 0 = PORTB Pull-ups are enabled by individual port latch values

bit 0

RBIP: RB Port Change Interrupt Priority bit 1 = High Priority 0 = Low Priority

© 2006 Microchip Technology Incorporated. All Rights Reserved.

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Slide 108

Lab 1 I/O Ports and External Interrupts

V3.2 August 10, 2007

Lab 1 Objectives

Upon completion of Lab 1 you should understand: I/O Port Configuration I/O Port Read and Write (entire byte) I/O Pin Read and Write (single bit) External Interrupts (INT0 pin)

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 110

Lab 1 Application Overview

Increment a software counter and display the count on the LCD each time switch S3 is pressed. 4.7k Ω S3

PIC18F4520

LCD Control

3

470 Ω

RA1:3 RB0

4 RD0:3

0.1 μ F

© 2006 Microchip Technology Incorporated. All Rights Reserved.

LCD Data

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Slide 111

Lab 1: The Task Main Loop

Configure bit 0 of PORTB as an input (other bits can be inputs too) Configure interrupt for RB0/INT0 (SW3 is connected to this pin) If FLAG set by interrupt, increment count © 2006 Microchip Technology Incorporated. All Rights Reserved.

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Slide 112

Lab 1: The Task Interrupt Service Routine

Check INT0 interrupt flag INT0IF If INT0IF is set, set FLAG Clear INT0IF

© 2006 Microchip Technology Incorporated. All Rights Reserved.

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Slide 113

Lab 1 Expected Results

The LCD should display the count The count will increment each time SW3 is pressed The count should increment sequentially without skipping any values © 2006 Microchip Technology Incorporated. All Rights Reserved.

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Slide 114

Analog: Comparators

V3.2 August 10, 2007

Analog Comparator Module V REF

Two comparators Operates in sleep mode Generates interrupt / wakeup on output change Comparator output pins available Eight programmable modes © 2006 Microchip Technology Incorporated. All Rights Reserved.

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Slide 116

Analog Comparator Key Registers CMCON Register R-0

R-0

R/W-0

R/W-0

R/W-0

R/W-1

R/W-1

bit 7

R/W-1 bit 0

C2OUT: Comparator 2 Output C1OUT: Comparator 1 Output C2INV: Comparator 2 Inversion

C1INV: Comparator 1 Inversion CIS: Comparator Input Switch CM2:CM0: Comparator Mode

CVRCON Register R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

bit 7

R/W-0 bit 0

CVRSS: Comparator Vref Source CVREN: Comparator Vref Enable Selection CVROE: Comparator Vref Output Enable CVRR: Comparator Vref Range Selection CVR3:CVR0: Comparator Vref Value Selection

© 2006 Microchip Technology Incorporated. All Rights Reserved.

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Slide 117

Analog Comparator Module Modes of Operation Comparators Reset

CMCON Register R-0

R-0

R/W-0

R/W-0

R/W-0

R/W-1

R/W-1

bit 7

R/W-1 bit 0

C1OUT C1OUT RA0/AN0 RA3/AN3 CM2 CM2 == 00

VINVIN+

C1 +

C1INV C1INV == 00

Off (Read as ‘0’)

State Change

CMIF Interrupt Flag

CM1 CM1 == 00 CM0 CM0 == 00 RA1/AN1 RA2/AN2

VINVIN+

C2INV C2INV == 00

C2 +

State Change

C2OUT C2OUT

Off (Read as ‘0’)

CIS CIS == X X © 2006 Microchip Technology Incorporated. All Rights Reserved.

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Slide 118

Analog Comparator Module Configuraton CMCON Register R-0

R-0

R/W-0

bit 7

R/W-0

R/W-0

R/W-1

R/W-1

R/W-1 bit 0

Two Independent Comparators C1OUT C1OUT RA0/AN0

RA3/AN3 CM2 CM2 == 00

VINVIN+

C1 +

C1INV C1INV == 00

State Change

CMIF Interrupt Flag

CM1 CM1 == 11 CM0 CM0 == 00 RA1/AN1 RA2/AN2

VINVIN+

C2INV C2INV == 00

C2 +

State Change

C2OUT C2OUT CIS CIS == X X © 2006 Microchip Technology Incorporated. All Rights Reserved.

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Slide 119

Analog Comparator Module Configuraton CMCON Register R-0

R-0

bit 7

R/W-0

R/W-0

R/W-0

R/W-1

Two Common Reference Comparators

R/W-1

R/W-1 bit 0

C1OUT C1OUT RA0/AN0 RA3/AN3 CM2 CM2 == 11

VINVIN+

C1 +

C1INV C1INV == 00

State Change

CMIF Interrupt Flag

CM1 CM1 == 00 CM0 CM0 == 00 RA1/AN1 RA2/AN2

VINVIN+

C2INV C2INV == 00

C2 +

State Change

C2OUT C2OUT CIS CIS == X X © 2006 Microchip Technology Incorporated. All Rights Reserved.

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Slide 120

Analog Comparator Module Configuraton CMCON Register R-0

R-0

bit 7

R/W-0

R/W-0

R/W-0

R/W-1

One Independent Comparator with Output

R/W-1

R/W-1 bit 0

C1OUT C1OUT RA0/AN0 RA3/AN3 CM2 CM2 == 00

VINVIN+

C1 +

RA4/C1OUT

C1INV C1INV == 00

State Change

CMIF Interrupt Flag

CM1 CM1 == 00 CM0 CM0 == 11 RA1/AN1 RA2/AN2

VINVIN+

C2INV C2INV == 00

C2 +

State Change

C2OUT C2OUT CIS CIS == X X © 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 121

Analog Comparator Module Configuraton CMCON Register R-0

R-0

bit 7

R/W-0

R/W-0

R/W-0

R/W-1

R/W-1

Two Independent Comparators with Outputs

R/W-1 bit 0

C1OUT C1OUT RA0/AN0 RA3/AN3 CM2 CM2 == 00

VINVIN+

C1 +

RA4/C1OUT

C1INV C1INV == 00

State Change

CMIF Interrupt Flag

CM1 CM1 == 11 CM0 CM0 == 11 RA1/AN1 RA2/AN2

VINVIN+

C2INV C2INV == 00

C2 +

State Change

RA5/C2OUT

C2OUT C2OUT CIS CIS == X X © 2006 Microchip Technology Incorporated. All Rights Reserved.

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Slide 122

Analog Comparator Module Configuraton CMCON Register R-0 bit 7

R-0

R/W-0

R/W-0

R/W-0

R/W-1

R/W-1

Two Common Reference Comparators with Outputs

R/W-1 bit 0

C1OUT C1OUT RA0/AN0 RA3/AN3 CM2 CM2 == 11

VINVIN+

C1 +

RA4/C1OUT

C1INV C1INV == 00

State Change

CMIF Interrupt Flag

CM1 CM1 == 00 CM0 CM0 == 11 RA1/AN1 RA2/AN2

VINVIN+

C2INV C2INV == 00

C2 +

State Change

RA5/C2OUT

C2OUT C2OUT CIS CIS == X X © 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 123

Analog Comparator Module Configuraton CMCON Register R-0

R-0

bit 7

R/W-0

R/W-0

R/W-0

R/W-1

R/W-1

Four Inputs Multiplexed to Two Comparators

R/W-1 bit 0

C1OUT C1OUT RA0/AN0

VIN-

RA3/AN3 VIN+

CM2 CM2 == 11

C1 +

C1INV C1INV == 00

State Change

CMIF Interrupt Flag

CM1 CM1 == 11 CM0 CM0 == 00

RA1/AN1

VIN-

RA2/AN2 VIN+

C2INV C2INV == 00

C2 +

State Change

C2OUT C2OUT

From VREF Module

CIS CIS == 00 © 2006 Microchip Technology Incorporated. All Rights Reserved.

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Slide 124

Analog Comparator Module Configuraton CMCON Register R-0

R-0

R/W-0

bit 7

R/W-0

R/W-0

R/W-1

R/W-1

bit 0

Comparators Off C1OUT C1OUT RA0/AN0

RA3/AN3 CM2 CM2 == 11

VINVIN+

C1 +

C1INV C1INV == 00

Off (Read as ‘0’)

State Change

CMIF Interrupt Flag

CM1 CM1 == 11 CM0 CM0 == 11 RA1/AN1 RA2/AN2

VINVIN+

C2INV C2INV == 00

C2 +

R/W-1

State Change

C2OUT C2OUT

Off (Read as ‘0’)

CIS CIS == X X © 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 125

Analog: Comparator Vref

V3.2 August 10, 2007

Comparator Voltage Reference 16 Tap Resistor Ladder Network 24 or 32 Step Sizes Internal or External Voltage Source for Reference Generation VREF output can be directed to I/O pin Can be used as 4-bit D/A Converter © 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 127

Comparator Voltage Reference Configuration CVRCON Register R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

bit 7

bit 0 CVRSRC

VREF+ VDD

Value Select 8R R

CVREN CVREN

When When CVRR CVRR == 0: 0:

R 16 Steps

Source Select

CV = ((CVR3:CVR0)/24)y(CV RSRC)) CVREF REF = ((CVR3:CVR0)/24)y(CVRSRC

CV = (CV RSRC/4) ) CVREF /4)++((CVR3:CVR0)/32)y(CV ((CVR3:CVR0)/32)y(CVRSRC REF = (CVRSRC RSRC)

CVRSS CVRSS == 00

R R

Range Select VREF-

16:1 Mux

VREF Enable

CVR3:0 CVR3:0

When When CVRR CVRR == 1: 1:

RA2/AN2/CVREF

R

CVRR CVRR

CVREF

8R

Output Enable

CVOE CVOE © 2006 Microchip Technology Incorporated. All Rights Reserved.

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Slide 128

Analog: 10-bit A/D Converter Module

V3.2 August 10, 2007

10-bit A/D Converter Channel Select

CHS3:CHS0 CHS3:CHS0 In ADCON0 Register AN12 AN12 AN9 AN8 AN7* AN6* AN5* AN4

VREF+ / AN3 VREF- / AN2

13:1 Analog Mux

AN10

VAIN

10-bit A/D Result Registers

ADC VREF+

AN1

ADRESH

ADRESL

VREF-

VDD

AN0 x0 x1 1x 0x

VSS VREF Select VCFG1:VCFG0 VCFG1:VCFG0 In ADCON1 Register *AN5-AN7 not available on 28-pin devices © 2006 Microchip Technology Incorporated. All Rights Reserved.

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Slide 130

Input Signal Acquisition Time Acquisition Time

Conversion Time

time VC

VIN

ADRES

time

10

SOURCE

ADC + VC -

CHOLD

Acquisition Time is determined RS < 2.5kΩ by Time allows Acquisition Pin Capacitance and time Source Hold Capacitor to fullyimpedance charge to VIN V (recommend 700ns

* The Internal RC has a typical TAD time of 1.2μs

Minimum TAD = 0.7μs See data sheet for official specification. © 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 140

10-bit A/D Converter Configuration

Calculating Acquisition Time TACQ = TAMP + TC + TCOFF TAMP = Amplifier Settling Time = Tamp internal + Tamp external TC = Charging Time = -(CHOLD)·(RIC + RSS + RS)·ln(1/2047)μs TCOFF = Temperature Coefficient = (Temp – 25°C)·(0.02μs/°C) for Temp > 25°C = 0 for Temp < 25°C © 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 141

10-bit A/D Converter Configuration

Calculating amplifier settling time TAMP = TAMP INT+ TAMP EXT TAMP INT : Internal amplifier settling time. Check datasheet for specific part. For the PIC18F4520, TAMP INT is 2 µs. TAMP EXT: External amplifier (circuitry) settling time. This becomes important when external components are used to pre-condition the signal. Since the external circuitry on the PICDEM2 Plus is a mechanical POT, this number is 0 µs.

TAMP = 2 μs © 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 142

10-bit A/D Converter Configuration

Calculating Charging Time TC = -(CHOLD)·(RIC + RSS + RS)·ln(1/2047)μs CHOLD RIC RSS RS

= Holding Capacitor Value = 25pF = Interconnect Resistance = 1kΩ = Sampling Switch Impedance = 2kΩ = Source Impedance = 2.5kΩ MAX

Assuming a maximum source impedance of 2.5kΩ, we have: TC = 1.05μs © 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 143

10-bit A/D Converter Configuration

Calculating Temperature Coefficient TCOFF = (Temp – 25°C)·(0.02μs/°C) Temp = Operating Temperature Valid for Temp > 25°C. TCOFF = 0 for Temp < 25°C Using the maximum operating temperature of 85°C for an Industrial grade part, we have: TCOFF = 1.2μs © 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 144

10-bit A/D Converter Configuration

Calculating Acquisition Time TACQ = TAMP + TC + TCOFF For Rs = 2.5k Ω Temp = 85° C TAMP = 2 µs

TACQ = 2 + 1 + 1.2 = 4.2 µs © 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 145

10-bit A/D Converter Configuration ADCON2 Register U-0

U-0

R/W-0

R/W-0

R/W-0*

R/W*

R/W*

bit 7

R/W* bit 0

bit 5-3 ACQT2:ACQT0: A/D Acquisition Time Selection bits 111 = 20 TAD 110 = 16 TAD

Given: TACQ = 4.2 µs TAD = 1000 ns

101 = 12 TAD 100 = 8 TAD 011 = 6 TAD 010 = 4 TAD

Then: ACQT2:0 = 011 = 6.0 µs

001 = 2 TAD 000 = 0 TAD

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 146

10-bit A/D Converter Configuration ADCON2 Register R/W-0

U-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

bit 7

R/W-0 bit 0

bit 7

ADFM: A/D Result Format Selection bit 1 = Right Justified ADRESH

ADRESL bb99 bb88

bb77 bb66 bb55 bb44

bb33 bb22 bb11 bb00

0 = Left Justified ADRESH bb99 bb88 bb77 bb66 bb55

© 2006 Microchip Technology Incorporated. All Rights Reserved.

ADRESL bb44 bb33 bb22

bb11 bb00

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Slide 147

C18 ADC Library Functions #include char BusyADC (void); Checks whether the ADC is currently performing a conversion. Returns ‘1’ if busy

void CloseADC (void); Disables ADC and ADC interrupt

void ConvertADC (void); Starts and ADC conversion

void OpenADC (unsigned char config, unsigned char config2); Used to configure the ADC Some PIC18 have 3rd argument portconfig Values of config and config2 will vary by device © 2006 Microchip Technology Incorporated. All Rights Reserved.

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Slide 148

C18 ADC Library Functions int ReadADC (void); Reads the result of ADC conversion Returns a 16-bit signed value Result will be right or left justified as determined by configuration

void SetChanADC (unsigned char channel); Selects the pin used for ADC input Channel value can be ADC_CH0 through ADC_CH15) © 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 149

Lab 2 A/D Converter

V3.2 August 10, 2007

Lab 2 Objectives

Understand A/D Conversion Understand Reading ADC Channels Understand Selecting ADC Channels Understand Scaling ADC Results © 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 151

Lab 2 Application Overview

Use the integrated ADC to measure the potentiometer voltage then display the result on the LCD. +5V

PIC18F4520

LCD Control

3

470 Ω

RA1:3 RA0 / AN0

5KΩ

4 RD0:3 LCD Data

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 152

Lab 2: The Task 2 functions to edit init_ADC get_ADC Vref+ = Vdd Vref- = Vss AN0 = Analog Input

Enable ADC

Yes

Select Channel 0 Tacq = 12 Tad Tad = 8 Tosc

Is GO bit Set? No Return

Enable ADC

Return

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 153

Timers Timer 0, Timer 1 and Timer 3 Modules

V3.2 August 10, 2007

Timer Comparison TIMER 0

TIMERS 1 & 3

TIMERS 2 & 4

SIZE OF REGISTER

8-bits or 16-bits

16-bits

8-bits

CLOCK SOURCE (Internal)

Fosc/4

Fosc/4

Fosc/4

CLOCK SOURCE (External )

T0CKI pin

T13CKI pin or Timer 1 oscillator (T1OSC)

None

CLOCK SCALING AVAILABLE (Resolution)

Prescaler 8-bits (1:2Æ1:256)

Prescaler 2-bits (1:1, 1:2, 1:4, 1:8)

Prescaler (1:1,1:4,1:16) Postscaler (1:1Æ1:16)

INTERRUPT EVENT

On overflow FFhÆ00h

On overflow FFFFhÆ0000h

TMR REG matches PR2

CAN WAKE PIC FROM SLEEP?

NO

YES

NO

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 155

Timer 0 PIC16 Compatibility Mode

8-bit Timer/Counter 8-bit Programmable Prescaler Internal or External Clock Source Interrupt on Overflow from FF to 00 FOSC/4

TMR0IF TMR0IF

0 0

T0CKI

1

T0SE T0SE

Programmable Prescaler

Clock Sync

TMR0L

1

T0CS T0CS T0PS2:T0PS0 T0PS2:T0PS0

PSA PSA 8-bit Data Bus

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 156

Timer 0 16-bit Mode

16-bit Timer / Counter 16-bit Read / Write Mode Interrupt on overflow from FFFF to 0000 Same basic features as compatibility mode FOSC/4

TMR0IF TMR0IF

0 0

T0CKI

1

T0SE T0SE

Programmable Prescaler

1

T0CS T0CS T0PS2:T0PS0 T0PS2:T0PS0

PSA PSA

Clock Sync

High Byte

TMR0L

READ TMR0L

WRITE TMR0L

TMR0H

8-bit Data Bus © 2006 Microchip Technology Incorporated. All Rights Reserved.

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Slide 157

Timer 0 Operation TMR0IF TMR0IF

FOSC/4

0 0

T0CKI

1

T0SE T0SE

Programmable Prescaler

Clock Sync

TMR0L

1

T0CS T0CS T0PS2:T0PS0 T0PS2:T0PS0

PSA PSA

DATA BUS

T0CON Register TMR0ON

T08BIT

T0CS

T0SE

PSA

T0PS2:0

T08BIT 1 = 8 BIT 0 = 16 BIT © 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 158

Timer 0 Operation FOSC/4

TMR0IF TMR0IF

0 0

T0CKI

1

T0SE T0SE

Programmable Prescaler

Clock Sync

1

READ TMR0L

T0CS T0CS T0PS2:T0PS0 T0PS2:T0PS0

PSA PSA

T08BIT

T0CS

TMR0L WRITE TMR0L

TMR0H

DATA BUS

T0CON Register TMR0ON

High Byte

T0SE

PSA

T0PS2:0

T08BIT 1 = 8 BIT 0 = 16 BIT © 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 159

Timer 0 Operation FOSC/4

TMR0IF TMR0IF

0 0

T0CKI

1

T0SE T0SE

Programmable Prescaler

Clock Sync

1

READ TMR0L

T0CS T0CS T0PS2:T0PS0 T0PS2:T0PS0

High Byte

PSA PSA

TMR0L WRITE TMR0L

TMR0H

DATA BUS

T0CON Register TMR0ON

T08BIT

T0CS

T0SE

PSA

T0PS2:0

TMR0 Clock Source Select 1 = T0CKI, 0 = Fosc/4

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 160

Timer 0 Operation FOSC/4

TMR0IF TMR0IF

0 0

T0CKI

1

T0SE T0SE

Programmable Prescaler

Clock Sync

1

T0CS T0CS T0PS2:T0PS0 T0PS2:T0PS0

PSA PSA

High Byte

TMR0L

READ TMR0L

WRITE TMR0L

TMR0H

DATA BUS

T0CON Register TMR0ON

T08BIT

T0CS

T0SE

PSA

T0PS2:0

Source Edge Select 1 = increment TMR0 on rising edge 0 = increment TMR0 on falling edge

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 161

Timer 0 Operation FOSC/4

TMR0IF TMR0IF

0 0

T0CKI

1

T0SE T0SE

Programmable Prescaler

Clock Sync

1

READ TMR0L

T0CS T0CS T0PS2:T0PS0 T0PS2:T0PS0

PSA PSA

T08BIT

T0CS

TMR0L WRITE TMR0L

TMR0H

DATA BUS

T0CON Register TMR0ON

High Byte

T0SE

PSA

T0PS2:0

Prescaler Assignment 1= prescaler NOT assigned 0= prescaler IS assigned © 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 162

Timer 0 Operation FOSC/4

TMR0IF TMR0IF

0 0

T0CKI

1

T0SE T0SE

Programmable Prescaler

Clock Sync

1

TMR0L

READ TMR0L

T0CS T0CS T0PS2:T0PS0 T0PS2:T0PS0

High Byte

WRITE TMR0L

PSA PSA

TMR0H

DATA BUS

T0CON Register TMR0ON

T08BIT

T0CS

T0SE

PSA

T0PS2:0

Prescaler Rate Select Bits

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

PS2

PS1

PS0

TMR0 RATE

0

0

0

1:2

0

0

1

1:4

0

1

0

1:8

0

1

1

1:16

1

0

0

1:32

1

0

1

1:64

1

1

0

1:128

1

1

1

1:256 Slide 163

Timer 0 Operation FOSC/4

TMR0IF TMR0IF

0 0

T0CKI

1

T0SE T0SE

Programmable Prescaler

Clock Sync

1

T0CS T0CS T0PS2:T0PS0 T0PS2:T0PS0

PSA PSA

T08BIT

T0CS

READ TMR0L

TMR0L WRITE TMR0L

TMR0H

DATA BUS

T0CON Register TMR0ON

High Byte

T0SE

PSA

T0PS2:0

TMR0ON 1 = ON 0 = STOPPED © 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 164

Timer 1 and Timer 3 16-bit Timer / Counter Timer, Synchronous Counter or Asynchronous Counter Can operate from separate external crystal Two readable and writeable 8-bit registers ÷1, ÷2, ÷4, or ÷8 Prescaler Interrupt on overflow from FFFFh to 0000h © 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 165

Timer 1 and Timer 3 Timer 1 Oscillator

1

T1OSO/ T13CKI

1

FOSC/4

T1OSI

Prescaler 1, 2, 4, 8

Sync Detect

0

Sleep Input

T1OSCEN T1OSCEN

0

T1SYNC T1SYNC

TMR1CS TMR1CS TMR1ON TMR1ON

T1CKPS1: T1CKPS1: T1CKPS0 T1CKPS0

TMR1IF TMR1IF Clear Timer 1 (CCP Special Event Trigger)

High Byte

TMR1L

READ TMR1L

WRITE TMR1L

TMR1H

8-bit Data Bus RD16 Bit 7

T1RUN

TCKPS1:0

T1OSCEN

T1SYNC

Bit 0

T1CON Register

© 2006 Microchip Technology Incorporated. All Rights Reserved.

TMR1CS TMR1ON

202 PRC

Slide 166

Timer 1 and Timer 3 Timer 1 Oscillator

1

T1OSO/ T13CKI

1

FOSC/4

T1OSI

Prescaler 1, 2, 4, 8

Sync Detect

0

Sleep Input

T1OSCEN T1OSCEN

0

T1SYNC T1SYNC

TMR1CS TMR1CS TMR1ON TMR1ON

T1CKPS1: T1CKPS1: T1CKPS0 T1CKPS0

16-bit Read/Write Mode Enable 1 = Read/Write of Timer in one operation 0 = Read/Write of Timer in two 8-bit operations

TMR1IF TMR1IF TMR1H

TMR1L

Clear Timer 1 (CCP Special Event Trigger)

8-bit Data Bus

T1CON / T3CON Register RD16

T1RUN

TCKPS1:0

T1OSCEN

T1SYNC

Bit 7 © 2006 Microchip Technology Incorporated. All Rights Reserved.

TMR1CS TMR1ON Bit 0

202 PRC

Slide 167

Timer 1 and Timer 3 Timer 1 Oscillator

1

T1OSO/ T13CKI

1

FOSC/4

T1OSI

Prescaler 1, 2, 4, 8

Sync Detect

0

Sleep Input

T1OSCEN T1OSCEN

16-bit Read/Write Mode Enable 1 = Read/Write of Timer in one operation 0 = Read/Write of Timer in two 8-bit operations

0

T1SYNC T1SYNC

TMR1CS TMR1CS TMR1ON TMR1ON

T1CKPS1: T1CKPS1: T1CKPS0 T1CKPS0

TMR1IF TMR1IF

Clear Timer 1 (CCP Special Event Trigger) High Byte

TMR1L

READ TMR1L

WRITE TMR1L

TMR1H

8-bit Data Bus

T1CON / T3CON Register RD16

T1RUN

TCKPS1:0

T1OSCEN

T1SYNC

Bit 7 © 2006 Microchip Technology Incorporated. All Rights Reserved.

TMR1CS TMR1ON Bit 0

202 PRC

Slide 168

Timer 1 and Timer 3 Timer 1 Oscillator

1

T1OSO/ T13CKI

1

FOSC/4

T1OSI

Prescaler 1, 2, 4, 8

Sync Detect

0

Sleep Input

T1OSCEN T1OSCEN

0

T1SYNC T1SYNC

TMR1CS TMR1CS TMR1ON TMR1ON

T1CKPS1: T1CKPS1: T1CKPS0 T1CKPS0

TMR1IF TMR1IF Clear Timer 1 (CCP Special Event Trigger)

High Byte READ TMR1L

Timer1 Oscillator Enable 1 = T1OSC Enabled 0 = T1OSC off

WRITE TMR1L

TMR1H

8-bit Data Bus

T1CON / T3CON Register RD16

T1RUN

TCKPS1:0

TMR1L

T1OSCEN

T1SYNC

Bit 7 © 2006 Microchip Technology Incorporated. All Rights Reserved.

TMR1CS TMR1ON Bit 0

202 PRC

Slide 169

Timer 1 and Timer 3 Timer 1 Oscillator

1

T1OSO/ T13CKI

1

FOSC/4

T1OSI

Prescaler 1, 2, 4, 8

Sync Detect

0

Sleep Input

T1OSCEN T1OSCEN

0

T1SYNC T1SYNC

TMR1CS TMR1CS TMR1ON TMR1ON

T1CKPS1: T1CKPS1: T1CKPS0 T1CKPS0

TMR1IF TMR1IF Clear Timer 1 (CCP Special Event Trigger)

High Byte READ TMR1L

Timer1 Clock Source 1= External Clock 0 = Fosc/4

WRITE TMR1L

TMR1H

8-bit Data Bus

T1CON / T3CON Register RD16

T1RUN

TCKPS1:0

T1OSCEN

T1SYNC

Bit 7 © 2006 Microchip Technology Incorporated. All Rights Reserved.

TMR1L

TMR1CS TMR1ON Bit 0

202 PRC

Slide 170

Timer 1 and Timer 3 Timer 1 Oscillator

1

T1OSO/ T13CKI

1

FOSC/4

T1OSI

Prescaler 1, 2, 4, 8

Sync Detect

0

Sleep Input

T1OSCEN T1OSCEN

0

T1SYNC T1SYNC

TMR1CS TMR1CS TMR1ON TMR1ON

T1CKPS1: T1CKPS1: T1CKPS0 T1CKPS0

TMR1IF TMR1IF Clear Timer 1 (CCP Special Event Trigger)

Timer1 Prescale Select 11 = 1:8 10 = 1:4 01 = 1:2 00 = 1:1

High Byte READ TMR1L

WRITE TMR1L

TMR1H

8-bit Data Bus

T1CON / T3CON Register RD16

T1RUN

TCKPS1:0

TMR1L

T1OSCEN

T1SYNC

Bit 7 © 2006 Microchip Technology Incorporated. All Rights Reserved.

TMR1CS TMR1ON Bit 0

202 PRC

Slide 171

Timer 1 and Timer 3 Timer 1 Oscillator

1

T1OSO/ T13CKI

1

FOSC/4

T1OSI

Prescaler 1, 2, 4, 8

Sync Detect

0

Sleep Input

T1OSCEN T1OSCEN

0

T1SYNC T1SYNC

TMR1CS TMR1CS TMR1ON TMR1ON

T1CKPS1: T1CKPS1: T1CKPS0 T1CKPS0

TMR1IF TMR1IF Clear Timer 1 (CCP Special Event Trigger)

Timer1 System Clock Status Read Only Bit 1 = Device clock derived from Timer1 OSC 0 = Device clock derived from another source

High Byte READ TMR1L

WRITE TMR1L

TMR1H

8-bit Data Bus

T1CON / T3CON Register RD16

T1RUN

TCKPS1:0

T1OSCEN

T1SYNC

Bit 7 © 2006 Microchip Technology Incorporated. All Rights Reserved.

TMR1L

TMR1CS TMR1ON Bit 0

202 PRC

Slide 172

Timer 1 and Timer 3 Timer 1 Oscillator

1

T1OSO/ T13CKI

1

FOSC/4

T1OSI

Prescaler 1, 2, 4, 8

Sync Detect

0

Sleep Input

T1OSCEN T1OSCEN

0

T1SYNC T1SYNC

TMR1CS TMR1CS TMR1ON TMR1ON

T1CKPS1: T1CKPS1: T1CKPS0 T1CKPS0

TMR1IF TMR1IF

Timer1 External Clock Synchronization Bit only used when TMR1CS = 1 1 = Synchronize external clock input 0 = Do not synchronize

Clear Timer 1 (CCP Special Event Trigger)

High Byte

READ TMR1L

WRITE TMR1L

TMR1H

8-bit Data Bus

T1CON / T3CON Register RD16

T1RUN

TCKPS1:0

T1OSCEN

T1SYNC

Bit 7 © 2006 Microchip Technology Incorporated. All Rights Reserved.

TMR1L

TMR1CS TMR1ON Bit 0

202 PRC

Slide 173

Timer 1 and Timer 3 Timer 1 Oscillator

1

T1OSO/ T13CKI

1

FOSC/4

T1OSI

Prescaler 1, 2, 4, 8

Sync Detect

0

Sleep Input

T1OSCEN T1OSCEN

0

T1SYNC T1SYNC

TMR1CS TMR1CS TMR1ON TMR1ON

T1CKPS1: T1CKPS1: T1CKPS0 T1CKPS0

TMR1IF TMR1IF

Timer On 1 = Enables Timer 0 = Stops Timer

Clear Timer 1 (CCP Special Event Trigger)

High Byte

TMR1L

READ TMR1L

WRITE TMR1L

TMR1H

8-bit Data Bus

T1CON / T3CON Register RD16

T1RUN

TCKPS1:0

T1OSCEN

T1SYNC

Bit 7

© 2006 Microchip Technology Incorporated. All Rights Reserved.

TMR1CS TMR1ON Bit 0

202 PRC

Slide 174

Lab 3 Working with Counters

V3.2 August 10, 2007

Lab 3 Objectives

Upon completion of Lab 3 you should understand: Understand TIMER configuration for counter mode Understand TMR1 external crystal mode Understand Frequency measurement techniques

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 176

Lab 3 Application Overview Implement a real time clock (RTC) with a 1 second resolution and display the time on the LCD. Switch S3 will be used to set the hours and switch S2 will be used to set the minutes.

S2

4.7k Ω

470 Ω

PIC18F4520 RA4 LCD Control

3

S3

4.7k Ω

RA1:3 4

470Ω

RD0:3 RB0

LCD Data

0.1 μ F

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 177

Lab 3 Calculation for Timer1 initial value

Equation: Interrupt Interval (sec) = ( Prescaler / Clock Frequency ) * (216 – preloaded value)

For RTC, need one interrupt per second Determine initial value for Timer1: 1 sec = ( 1 / 32.768 kHz ) * (65536 – preloaded value) Preload Value = 32768 = 0x8000

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 178

Lab 3 START

Main Loop

SupportFn

Initialize LCD Flag= 1?

Initialize I/O Pins

Yes

Display Start Message

Display Time

Configure TIMER1

Clear Flag

Enable Interrupts

Is S2 Pressed?

Clear TMR1IF

No

Yes Display Message

Preload TIMER1

Set Time

SupportFn

© 2006 Microchip Technology Incorporated. All Rights Reserved.

No

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Slide 179

Lab 3 TIMER1 ISR

TMR1ISR Increment Secs Secs >= 60? Yes Increment Mins Secs = 00 Mins >= 60? Yes

No

Reload TMR1H Clear TMR1L Flag = 1

No RETURN

Increment Hours Mins = 00 Hrs >= 13?

No

Hours = 1 © 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 180

Lab 3 Expected Results LCD displaying Time in HH:MM:SS format Where HHÆ Hours MM Æ Minutes SS Æ Seconds

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 181

CCP Module PWM Mode

V3.2 August 10, 2007

Timer 2 8-bit Timer with prescaler and postscaler Used as PWM time base TMR2 is readable & writable TMR2 resets on match with PR2 Match with PR2 generates interrupt Used as baud clock for MSSP (SPI™) © 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 183

Timer 2 T2CON Register R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

--

T2OUTPS3 T2OUTPS3

T2OUTPS2 T2OUTPS2

T2OUTPS1 T2OUTPS1

T2OUTPS0 T2OUTPS0

TMR2ON TMR2ON

T2CKPS1 T2CKPS1

T2CKPS0 T2CKPS0 bit 0

bit 7

00 = 1:1 01 = 1:4 1x = 1:16

0000 = 1:1 0001 = 1:2

TMR2 Postscale Value Selection Bits T2OUTPS3:T2OUTPS0 T2OUTPS3:T2OUTPS0

TMR2 Prescale Value Selection Bits

1:1 to 1:16 Postscaler

1111 = 1:16 TMR2IF TMR2IF

T2CKPS1:T2CKPS0 T2CKPS1:T2CKPS0 Reset

FOSC/4

1:1, 1:4, 1:16 Prescaler

TMR2

Timer 2 Output (To PWM or MSSP)

TMR2/PR2 Match

Comparator

PR2

8-bit Data Bus

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 184

CCP and ECCP Modules Standard CCP Module (CCP2): Input Capture Output Compare Standard, Single Output PWM

Enhanced CCP Module (CCP1): Same Input Capture and Output Compare functions as Standard CCP Provides enhanced PWM capabilities such as complementary outputs and dead band control © 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 185

CCP2 PWM Mode CCPxCON Master

CCPR2L

5

High Time (Duty Cycle)

4

Duty Cycle Slave

TMR2 = CCPRxH:2 LSb

CCPR2H CCPx Output

R

Comparator

Q

VSS

S TMR2

Comparator

*

*

VDD

Corresponding TRIS Bit

TMR2 = PR2

TMR2 = PR2

Period

Clear Timer, CCPx pin and latch D.C.

PR2

© 2006 Microchip Technology Incorporated. All Rights Reserved.

Period

202 PRC

Slide 186

Configuring CCP2 for PWM 1.

Set Period by writing to PR2 register.

2.

Set Duty Cycle by writing to CCPR2L and CCP2CON bits.

3.

Make the CCP2 pin an output by clearing the appropriate TRIS bit

4.

Set the TMR2 prescale value, then enable TMR2 by writing to T2CON

5.

Configure the CCP2 module for PWM mode

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 187

PWM Configuration: Step 1 Calculating the Period Value

TPWM = (PR2 + 1) y 4 y TOSC y TMR2PRE TPWM = Desired PWM Signal Period = 1 / fPWM PR2 = TMR2’s Period Register TOSC = System Oscillator Period = 1 / fOSC TMR2PRE = TMR2 Prescale Value (1, 4, or 16) © 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 188

PWM Configuration: Step 1 Calculating the Period Value

Rearranging the equation we get: PR2 =

fOSC 4 y fPWM y TMR2PRE

-1

Choose TMR2PRE to ensure that PR2 is in the range of 0 to 255 for the desired PWM frequency.

TMR2PRE may be 1, 4, or 16. © 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 189

PWM Configuration: Step 2 Calculating the Duty Cycle Value DCPWM = (CCPR2L:CCP2CON) y TOSC y TMR2PRE

DCPWM = Desired PWM Duty Cycle (time, not %) CCPR2L = Upper 8-bits of Duty Cycle Value CCP2CON = Low 2-bits of Duty Cycle Value TOSC = System Oscillator Period TMR2PRE = TMR2 Prescale Value (1, 4, or 16) © 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 190

PWM Configuration: Step 2 Calculating the Duty Cycle Value

Rearranging the equation we get: CCPR2L:CCP2CON =

%DCPWM y fOSC 100 y TMR2PRE y fPWM

Choose TMR2PRE to ensure that CCPR2L:CCP2CON is in the range of 0 to 1023 for the desired PWM duty cycle.

TMR2PRE may be 1, 4, or 16.

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 191

PWM Configuration: Step 2 Calculating the Duty Cycle Value

10-bit Duty Cycle value is stored across two registers: CCPR2L Register R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

DC2B9 DC2B9

DC2B8 DC2B8

DC2B7 DC2B7

DC2B6 DC2B6

DC2B5 DC2B5

DC2B4 DC2B4

DC2B3 DC2B3

DC2B2 DC2B2 bit 0

R/W-0

bit 7

88 Most Most Significant Significant Bits Bits

CCP2CON Register R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

--

--

DC2B1 DC2B1

DC2B0 DC2B0

CCP2M3 CCP2M3

CCP2M2 CCP2M2

CCP2M1 CCP2M1

bit 7

22 Least Least Significant Significant Bits Bits

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

CCP2M0 CCP2M0 bit 0

Slide 192

PWM Configuration: Step 3 Configure the CCP2 Pin as an Output Clear the appropriate TRIS bit

RC1/T1OSI/CCP2(1)

Default CCP2 on RC1: If CONFIG3H = 1 (1)

TRISC TRISC == 00

© 2006 Microchip Technology Incorporated. All Rights Reserved.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

202 PRC

RB3/AN9/CCP2(1)

Optional CCP2 on RB3: If CONFIG3H = 0 (1)

TRISB TRISB == 00

Slide 193

PWM Configuration: Step 4 Set TMR2 Prescale Value and Enable TMR2 T2CON Register R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

--

T2OUTPS3 T2OUTPS3

T2OUTPS2 T2OUTPS2

T2OUTPS1 T2OUTPS1

T2OUTPS0 T2OUTPS0

TMR2ON TMR2ON

T2CKPS1 T2CKPS1

T2CKPS0 T2CKPS0 bit 0

bit 7

bit 2

TMR2ON: Timer2 On bit 1 = Timer2 is On 0 = Timer 2 is Off

bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16

© 2006 Microchip Technology Incorporated. All Rights Reserved.

T2CKPS1:T2CKPS0 T2CKPS1:T2CKPS0 values values determined determined when when calculating PWM period calculating PWM period and and duty duty cycle cycle

202 PRC

Slide 194

PWM Configuration: Step 5 Configure CCP for PWM Mode CCP2CON Register R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

--

--

DC2B1 DC2B1

DC2B0 DC2B0

CCP2M3 CCP2M3

CCP2M2 CCP2M2

CCP2M1 CCP2M1

bit 7

R/W-0 CCP2M0 CCP2M0 bit 0

bit 5-4 DC2B1:DC2B0: PWM Duty Cycle bit 1 and bit 0 for CCP2 These bits are the two LSbs of the 10-bit PWM duty cycle. The 8 MSbs (DCx9:DCx2) of the duty cycle are found in CCPR2L. DC2B1:DC2B0 DC2B1:DC2B0 values values determined determined when when calculating calculating PWM PWM duty duty cycle cycle

bit 3-0 CCP2M3:CCP2M0: CCP Module 2 Mode Select bits 0000 = Capture/Compare/PWM disabled (resets CCP module) 0001 = Reserved 0010 = Compare mode, toggle output on match (CCP2IF bit is set) 0011 = Reserved 0100 = Capture mode, every falling edge 11xx = PWM mode © 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 195

Lab 4 CCP in PWM Mode

V3.2 August 10, 2007

Lab 4 Objectives

Understand TIMER configuration for PWM Understand TIMER-2 PWM mode of operation Learn how to calculate period value from system frequency

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 197

Lab 4: Working with PWM

Code for Lab 4:

Open the project Lab4.mcp Write C source code in the file Lab4_main.c to configure Timer-2 for Single output PWM mode of operation Set Prescaler to 1:4 Set default frequency to 4.9KHz Set default duty cycle to 50%

CCP1CON = 0Ch, T2CON = 05h, PR2 = 80h, CCP1CON = 3 Start PWM if S3 is pressed (RB0) Stop PWM if S2 is pressed (RA4) Modify the period proportional to the Analog input(0VÆ PR=00h, 5VÆ PR=FFh) © 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 198

Lab 4: Working with PWM

Expected Result: Once you complete the lab you can expect: Sound on the buzzer The PWM will start/stop by pressing switches SW3/SW2 The frequency of sound will vary if you turn the pot

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 199

CCP Module Capture Mode

V3.2 August 10, 2007

CCP Module Input Capture Mode

Captures 16-bit TMR1/3 value when an event occurs on CCPx pin: Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge

Capture generates an interrupt

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 201

CCP Module Input Capture Mode

TMR3H

TMR3L

T3ECCP1

CCP1M: 3-0

TMR 3 Enable

Prescaler

CCPR1H

Edge detect

CCPR1L

TMR 1 Enable TMR1H

CCP Pin

TMR1L

Set CCP1IF

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 202

CCP Module Output Compare Mode

16-bit CCPRn register value is compared to TMR1/3, and on match the CCPn pin is Driven High/Low Toggled Unchanged

Compare match generates interrupt Compare match can trigger a Special event Can start A/D conversion

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 203

CCP Module Output Compare Mode

Set CCPIF CCPR1H

Special Event Trigger

CCPR1L

16

PORT Pin O/P Logic

Comparator T3ECCP1

O/P Logic

16

0

1 16

CCP1M: 3-0

TRIS O/P Enable

16

TMR1

TMR3 16

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 204

Lab 5 CCP in Capture Mode

V3.2 August 10, 2007

Lab 5 Objectives

Understand TIMER configuration for input capture Understand TIMER-1 Capture mode of operation Learn how to calculate period from captured counts

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 206

Lab 5: Working with CCP

Code for Lab 5:

Open the project Lab5.mcp Write C source code in the file Lab5_main.c to configure: Timer-3 for CCP clock source input Set Timer-3 to run on internal clock source (FOSC/4) Configure and Enable capture interrupt for both rising and falling edges

T3CON = 0xA9, CCP2CON = 0x05(For rising edge) CCP2CON = 0x04(For Falling edge)

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 207

Lab 5: Working with CCP Connect PWM port pin to Capture port pin Jumper provided

Write Capture ISR to

Read Capture register and PORT pin status Calculate Period and Duty cycle

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 208

Lab 5: Working with CCP

Expected Result: Once you complete the lab you can expect: LCD displaying Period/Frequency and Duty Cycle The PWM will start or stop by pressing switches SW2 and SW3 The period will vary if you turn the pot

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 209

MSSP (Master Synchronous Serial Port) (I2C™, SPI™ and Microwire™)

V3.2 August 10, 2007

Master Synchronous Serial Port Operates in either SPI™ or I2C™ mode SPI Mode Programmable baud rate Maximum baud rates (@ 40MHz) Master: 10 Mbps Slave: 2.5 Mbps Single Byte Tx

I2C Mode

Supports standard (100kHz), fast (400kHz), and Microchip’s 1MHz I2C standards Hardware Master/Slave implementation Glitch filter and Slew rate control on SCL and SDA pins

SPI is a trademark of Motorola Semiconductor I2C is a trademark of Philips Semiconductors © 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 211

MSSP I2C Slave Mode Data Bus

Read

Write SSPBUF

RC3/SCK/SCL

Shift Clock

RC4/SDI/SDA

SSPSR MSb

LSb

Match Detect

Addr Match

SSPADD

Start and Stop bit Detect

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Set, Reset S, P bits (SSPSTAT)

Slide 212

MSSP I2C Master Mode SSPADD

Data Bus

Write

SDA In

SDA

Shift Clock SSPSR LSb

Start bit, Stop bit, ACK Generate

Bus Collision

SCL

SCL In

© 2006 Microchip Technology Incorporated. All Rights Reserved.

Start, Stop, WCOL Detect Clock Arbitration State Counter for end of TX/RX

202 PRC

Clock Ctrl

Receive Enable

MSb

(hold off clock source)

Baud Rate Generator

SSPBUF

Clock Arbitrate/WCOL Detect

Read

SSPM3:SSPM0 SSPM3:SSPM0

Set/Reset, S, P, WCOL (SSPSTAT) Set SSPIF, BCLIF Reset ACKSTAT, PEN (SSPCON2)

Slide 213

MSSP I2C Master Mode Baud Rate Generator SSPADD SSPM3:SSPM0 SSPM3:SSPM0

SCL

Reload Control CLKO

SSPADD

Reload

BRG Down Counter

FOSC/4

Decremented twice per instruction cycle (TCY)

FFSCL SCL

FFCY CY

2*F 2*FCY CY

BRG BRG Value Value

10 10 MHz MHz 10 10 MHz MHz

20 20 MHz MHz 20 20 MHz MHz

18h 18h 1Fh 1Fh

(2 (2 Rollovers Rollovers of of BRG) BRG) 400 400 kHz kHz 312.5 312.5 kHz kHz

10 10 MHz MHz 44 MHz MHz

20 20 MHz MHz 88 MHz MHz

63h 63h 09h 09h

100 100 kHz kHz 400 400 kHz kHz

44 MHz MHz 44 MHz MHz

88 MHz MHz 88 MHz MHz

0Ch 0Ch 27h 27h

308 308 kHz kHz 100 100 kHz kHz

11 MHz MHz 11 MHz MHz

22 MHz MHz 22 MHz MHz

02h 02h 09h 09h

333 333 kHz kHz 100 100 kHz kHz

11 MHz MHz

22 MHz MHz

00h 00h

11 MHz MHz

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 214

Lab 6 Communicate with I2C Temp Sensor using MSSP

V3.2 August 10, 2007

Lab 6 Objectives

Understand MSSP configuration Understand I2C Master mode of operation Understand steps required to communicate with I2C slave device

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 216

Lab 6: Working with I2C Code for Lab 6:

Open the project Lab6.mcp Write C source code in the file Lab6_main.c to configure: CLK, and SDA as inputs TRISC (TRISC = 11). Configure as Master. SSPCON2 = 0x28;

Clock for master mode = (FOSC /(4 x (SSPADD + 1)) SSPADD = 0x63; (Note: Choose any desired baud rate)

Send Temperature read request command to Temperature sensor using I2C_read() function Convert received Temperature data to BCD (use Bin2BCD() function) Display the Received temperature on on-board LCD using LCD write function

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 217

Lab 6: Working with I2C Expected Result: Once you complete the lab you can expect: LCD displaying Temperature data

© 2006 Microchip Technology Incorporated. All Rights Reserved.

202 PRC

Slide 218

EUSART Enhanced Universal Synchronous Receiver/Transmitter

V3.2 August 10, 2007

EUSART Summary Full-duplex asynchronous -or- half-duplex synchronous 8- or 9-bit data Double-buffered transmit and receive buffers Separate transmit and receive interrupts LSB-first transmission and reception Dedicated 16 bit baud rate generator Max baud rates @ 40 MHz Synchronous: 10 Mbaud Asynchronous: 625 Kbaud/2.5 Mbaud 9-bit addressable mode Auto-Wake-up on character reception Auto-Baud calibration 12-bit Break character transmission

© 2006 Microchip Technology Incorporated. All Rights Reserved.

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EUSART Block Diagram TXD8

TXEN SYNC SREN CSRC CREN

TXREG

TXIE

SPEN

TX8/9

Interrupt

TXDATA RC6/TX/CK

TSR

TXIF

TXCLK

OERR FERR RC7/RX/DT

RSR

RXDATA RCCLK TO RC6, RC7 I/O Port Logic

ADDEN RC8/9

RCD8

RCREG

Baud Rate Clock

RCIF

SPBRG

RCIE

© 2006 Microchip Technology Incorporated. All Rights Reserved.

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Tcy

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EUSART Transmit Operation TXREG empty, will set TXIF Loading TXREG resets TXIF TSR empty will set TRMT Loading TSR resets TRMT

TXIF

TXREG

TRMT

TSR

RC6/TX/CK

If TXREG is loaded and TRMT is set, then data is immediately loaded to TSR. Serial data shifting starts and TXIF will be set © 2006 Microchip Technology Incorporated. All Rights Reserved.

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EUSART Receive Operation RSR receives data with valid start/stop Data loaded into RCREG FIFO and RCIF = 1 If 2nd byte is received before the 1st has been serviced, then new data will be placed in the 2nd location on the FIFO When servicing the receive interrupt, after reading the 1st byte, if another byte is still in the FIFO, then a second RCIF interrupt is generated © 2006 Microchip Technology Incorporated. All Rights Reserved.

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RSR

RC7/RX/DT

ADDEN

RCREG RCIF

2 deep FIFO

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Lab 7 RS-232 Communications with PC and Table Read/Write Operations

V3.2 August 10, 2007

Lab 7 Objectives

Initializing SFRs for USART peripheral setup Understand data Transmission and Reception using USART Writing code to handle interrupt events Understand the usage of Table read/write instructions © 2006 Microchip Technology Incorporated. All Rights Reserved.

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Lab 7: Working with USART Code for Lab 7:

Open the project Lab_7.mcp Write C source code in the file Lab7_main.c to configure USART 19,200 baud async. @ 4 MHz Transmit enabled, Continuous Reception Address Detection disabled Configure as a high-priority interrupt source

Add I2C file to the project (to read temperature data) Add code in ‘HighISR’ to: Check for USART receive interrupt Echo data back to PC terminal When Key ‘T’ is received transmit the Temperature data When Key ‘S’ is received transmit the Constant string

Verify results with HyperTerminal

© 2006 Microchip Technology Incorporated. All Rights Reserved.

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Lab 7: Working with USART Code for Lab 7:

Here is the formula to calculate the baud rate

Click on the following link to open the Hyper terminal Link to Hyper Terminal © 2006 Microchip Technology Incorporated. All Rights Reserved.

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Lab 7: Working with USART

Expected Result: Once you complete the lab you can expect You can see echoed data on the Hyper terminal for every key press If you press Shift-T you will receive Temperature data If you press Shift-S you will receive Prestored constant string

© 2006 Microchip Technology Incorporated. All Rights Reserved.

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Oscillators & Power Saving Modes

V3.2 August 10, 2007

PIC18F: Clock System Clock Sources Primary Fixed Selection LP, XT, HS, RC, EC, Int RC Osc

Secondary Timer1 Oscillator - fixed frequency Required for Real Time Clock time base

Internal RC Oscillator INTOSC (8 MHz) source 4, 2, 1 MHz, 500, 250, 125 and 31 kHz

INTRC (31 kHz) source © 2006 Microchip Technology Incorporated. All Rights Reserved.

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PIC18F: Clock System New Internal RC Oscillator 2 separate RC sources 8 MHz (INTOSC) 31 kHz (INTRC)

2 - 31 kHz sources INTOSC 8 & 4 MHz can be routed through PLL 16 or 32 MHz

Modifying IRCF bits immediately selects a different INTOSC postscaler tap

© 2006 Microchip Technology Incorporated. All Rights Reserved.

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PIC18F: Power Managed Modes

3 Categories RUN - 3 clock sources IDLE - 3 clock sources SLEEP - no clocks Total = 7 Modes © 2006 Microchip Technology Incorporated. All Rights Reserved.

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PIC18F: Power Managed Modes PRI_RUN Mode Config Word defines Primary Clock Source FOSC3:FOSC0 (_CONFIG1H) 10 modes Crystal Oscillator - LP, XT, HS, HSPLL External Clock - EC, ECIO External RC Oscillator - RC, RCIO Internal RC Oscillator - INTIO1, INTIO2

SEC_RUN Mode Clock switching mechanism in other PIC18 controllers Timer1 source, Primary oscillator is disabled

RC_RUN Mode

IRCF selects clock speed IOFS set after 1us (typ.) delay if Freq ≠ 31 kHz © 2006 Microchip Technology Incorporated. All Rights Reserved.

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PIC18F Special Features

V3.2 August 10, 2007

PIC18F Special Features Wide operating voltage range: 2.0V to 5.5V 100,000 erase/write cycle Enhanced Flash program memory (typical) 1,000,000 erase/write cycle Data EEPROM memory (typical) Flash/Data EEPROM Retention: 100 years typical

© 2006 Microchip Technology Incorporated. All Rights Reserved.

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PIC18F Special Features Extended Watchdog Timer (WDT): Programmable period from 4 ms to 131s In-Circuit Serial Programming™ (ICSP™) Programmable High/Low-Voltage Detection (HLVD) module Supports interrupt on High/Low-Voltage Detection Programmable Brown-out Reset Enable during Configuration Or Software enable option © 2006 Microchip Technology Incorporated. All Rights Reserved.

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PIC18F Special Features Programmable Low Voltage Detect

Provides “Early Warning” Programmable internal or external reference Up to 14 internal reference voltages (2 - 4.77V)

Operates during SLEEP Low Voltage condition wakes-up/interrupts MCU

Software Controlled enable/disable Useful for low power applications © 2006 Microchip Technology Incorporated. All Rights Reserved.

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PIC18F Special Features Programmable Brown-Out RESET

Monitors operating voltage range Resets MCU during predefined range Removes RESET after Vdd returns to normal (+ 72 ms)

Programmable internal reference Up to 4 references (2.0, 2.7, 4.2, 4.5)

Enabled via Configuration register © 2006 Microchip Technology Incorporated. All Rights Reserved.

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PIC18F Special Features Programmable Brown-Out RESET Vdd drops below

Vdd rises to normal

BOR setting

VDD BOR Reset removed MCLR asserted

MCLR 72mS delay

© 2006 Microchip Technology Incorporated. All Rights Reserved.

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PIC18F Special Features In-Circuit Serial ProgrammingTM In-System Programming Method Uses only two pins to send/receive data Non-intrusive to normal operation Advantages of ICSP™ MCLR/VPP Reduce cost of field upgrades Calibrate and Serialize Systems during manufacturing Reduce handling: Important for DIE and fine lead package © 2006 Microchip Technology Incorporated. All Rights Reserved.

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VPP

VDD

VDD

VSS

VSS

I/O 1

Clock

I/O 2

Data

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PIC18F Special Features Watchdog Timer (WDT)

Recovers from software malfunction Resets MCU if not attended on-time Software must clear it periodically (CLRWDT)

Programmable period 4 ms to 131.0 s typical

Configuration controlled postscaler Enabled via Configuration register or Software Wakes up CPU from Sleep/Idle mode © 2006 Microchip Technology Incorporated. All Rights Reserved.

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PIC18F Special Features Resets

PIC18 RESETS Power-on Reset (POR) MCLR Reset during normal operation Programmable Brown-out Reset (BOR) Watchdog Timer (WDT) Reset (during execution) RESET Instruction Stack Full Reset Stack Underflow Reset

For all the resets PC vectors to address 0 © 2006 Microchip Technology Incorporated. All Rights Reserved.

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PIC18F Special Features RESET Registers

After RESET PC will have the address 0x000000 Following bits will be affected after each RESETS POR = ‘0’: Power On RESET BOR = ‘0’ & POR = ‘1’: BOR RESET TO = ‘0’: WDT RESET RI = ‘0’: RESET Instruction STKFUL = ‘1’: Stack over flow RESET STKUNF = ‘1’: Stack under flow RESET POR, BOR, TO & RI = ‘1’ and STKFUL & STKUNF = ‘0’: MCLR RESET © 2006 Microchip Technology Incorporated. All Rights Reserved.

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Summary

V3.2 August 10, 2007

Summary We discussed PIC18 Architecture: Programmers’ Model Instruction set Overview Interrupt Handling and latency

Covered The Basic Peripherals: I/O Ports Development Tools Comparators, Voltage Reference ADC © 2006 Microchip Technology Incorporated. All Rights Reserved.

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Summary Timers CCP (Capture, Compare & PWM) MSSP (I2C & SPI / Microwire) USART

Discussed: Oscillator and power saving modes Special features of PIC18F controllers

© 2006 Microchip Technology Incorporated. All Rights Reserved.

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Summary Carried out hands-on labs on: Basic C18 Project Creation IO Port initialization and reading and writing to the Ports Initialization and ADC conversion Timer configuration Generating PWM Capturing the input signal I2C module configuration EUSART configuration © 2006 Microchip Technology Incorporated. All Rights Reserved.

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References PIC18F4520 Datasheets PIC18F Family Reference manual PICDEM2 Plus Users Guide MPLAB® C18 C Compiler User’s Guide MPLAB C18 C Compiler Getting Started Guide MPLAB C18 C Compiler Libraries Guide Other PIC18-based classes:

101_TLS: Introduction to MPLAB-IDE 102_ASP: Introduction to PIC18F Architecture 202_ASP: PIC18 Peripherals in MPASM 390_USB: USB From Scratch

© 2006 Microchip Technology Incorporated. All Rights Reserved.

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Please complete the review form © 2006 Microchip Technology Incorporated. All Rights Reserved.

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Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KeeLoq, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies.

© 2006 Microchip Technology Incorporated. All Rights Reserved.

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