AN174 C8051F06 X D E V E L O P M E N T K I T U S E R ’ S G U I D E 1. Kit Contents The C8051F06x Development Kit contains the following items: • • •

• • • • •

C8051F060 Target Board Serial Adapter (RS232 to Target Board Debug Interface Protocol Converter) Silicon Laboratories IDE and Product Information CD-ROM. CD content includes: • Silicon Laboratories Integrated Development Environment (IDE) • Keil 8051 Development Tools (macro assembler, linker, evaluation ‘C’ compiler) • Installation Utility (SETUP.EXE) • Source code examples and register definition files • Documentation AC to DC Power Adapter RS232 Serial Cable 7” Ribbon Cable Quick-start Guide C8051F06x Development Kit User’s Guide (this document)

2. Hardware Setup The target board is connected to a PC running the Silicon Laboratories IDE via the Serial Adapter as shown in Figure 1. 1. 2. 3. 4.

Connect one end of the RS232 serial cable to a Serial (COM) Port on the PC. Connect the other end of the RS232 serial cable to the DB-9 connector on the Serial Adapter. Connect the Serial Adapter to the JTAG connector on the target board with the10-pin ribbon cable. Connect the AC/DC power adapter to power jack P1 on the target board.

AC/DC Adapter

PC Serial Cable

Serial Adpater

Ribbon Cable Target Board

Serial Port

Figure 1. Hardware Setup

Note: The Reset switch on the target board is disabled when the serial adapter is connected to the target board. Use the Reset button in the Silicon Laboratories IDE toolbar to reset the target when connected to the Serial Adapter. Rev. 0.5 1/04

Copyright © 2004 by Silicon Laboratories

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AN174 3. Software Setup The included CD-ROM contains the Silicon Laboratories Integrated Development Environment (IDE), Keil software 8051 tools and additional documentation. Insert the CD-ROM into your PC’s CD-ROM drive. An installer will automatically launch, allowing you to install the IDE software or read documentation by clicking buttons on the Installation Panel. If the installer does not automatically start when you insert the CD-ROM, run autorun.exe found in the root directory of the CD-ROM. Refer to the readme.txt file on the CD-ROM for the latest information regarding known IDE problems and restrictions.

4. Silicon Laboratories Integrated Development Environment The Silicon Laboratories IDE integrates a source-code editor, source-level debugger and in-system Flash programmer. The use of third-party compilers and assemblers is also supported. This development kit includes the Keil Software A51 macro assembler, BL51 linker and evaluation version C51 ‘C’ compiler. These tools can be used from within the Silicon Laboratories IDE.

4.1. System Requirements The Silicon Laboratories IDE requirements: • • •

Pentium-class host PC running Microsoft Windows 95 or later, or Microsoft Windows NT or later. One available COM port. 64 MB RAM and 40 MB free HD space recommended.

4.2. Assembler and Linker A full-version Keil A51 macro assembler and BL51 banking linker are included with the development kit and are installed during IDE installation. The complete assembler and linker reference manual can be found on-line under the Help menu in the IDE or in the “SiLabs\MCU\hlp” directory (A51.pdf).

4.3. Evaluation C51 ‘C’ Compiler An evaluation version of the Keil C51 ‘C’ compiler is included with the development kit and is installed during IDE installation. The evaluation version of the C51 compiler is the same as the full professional version except code size is limited to 4 kB and the floating point library is not included. The C51 compiler reference manual can be found under the Help menu in the IDE or in the “SiLabs\MCU\hlp” directory (C51.pdf).

4.4. Using the Keil Software 8051 Tools with the Silicon Laboratories IDE To perform source-level debugging with the IDE, you must configure the Keil 8051 tools to generate an absolute object file in the OMF-51 format with object extensions and debug records enabled. You may build the OMF-51 absolute object file by calling the Keil 8051 tools at the command line (e.g. batch file or make file) or by using the project manager built into the IDE. The default configuration when using the Silicon Laboratories IDE project manager enables object extension and debug record generation. Refer to Applications Note AN104 - Integrating Keil 8051 Tools Into the Silicon Labs IDE in the “SiLabs\MCU\Documentation\Appnotes” directory on the CDROM for additional information on using the Keil 8051 tools with the Silicon Laboratories IDE. To build an absolute object file using the Silicon Laboratories IDE project manager, you must first create a project. A project consists of a set of files, IDE configuration, debug views, and a target build configuration (list of files and tool configurations used as input to the assembler, compiler, and linker when building an output object file). The following sections illustrate the steps necessary to manually create a project with one or more source files, build a program and download the program to the target in preparation for debugging. (The IDE will automatically create a single-file project using the currently open and active source file if you select Build/Make Project before a project is defined.)

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AN174 4.4.1. Creating a New Project 1. Select Project->New Project to open a new project and reset all configuration settings to default. 2. Select File->New File to open an editor window. Create your source file(s) and save the file(s) with a recognized extension, such as .c, .h, or .asm, to enable color syntax highlighting. 3. Right-click on “New Project” in the Project Window. Select Add files to project. Select files in the file browser and click Open. Continue adding files until all project files have been added. 4. For each of the files in the Project Window that you want assembled, compiled and linked into the target build, right-click on the file name and select Add file to build. Each file will be assembled or compiled as appropriate (based on file extension) and linked into the build of the absolute object file. Note: If a project contains a large number of files, the “Group” feature of the IDE can be used to organize. Right-click on “New Project” in the Project Window. Select Add Groups to project. Add pre-defined groups or add customized groups. Right-click on the group name and choose Add file to group. Select files to be added. Continue adding files until all project files have been added.

4.4.2. Building and Downloading the Program for Debugging 1. Once all source files have been added to the target build, build the project by clicking on the Build/Make Project button in the toolbar or selecting Project->Build/Make Project from the menu. Note: After the project has been built the first time, the Build/Make Project command will only build the files that have been changed since the previous build. To rebuild all files and project dependencies, click on the Rebuild All button in the toolbar or select Project->Rebuild All from the menu. 2. C8051F06x family devices use the JTAG debug interface. You must select JTAG in the Options->Debug Interface menu to enable connection to C8051F06x target devices. Click the Connect button in the toolbar or select Debug->Connect from the menu to connect to the device. 3. Download the project to the target by clicking the Download Code button in the toolbar. Note: To enable automatic downloading if the program build is successful select Enable automatic connect/download after build in the Project->Target Build Configuration dialog. If errors occur during the build process, the IDE will not attempt the download. 4. Save the project when finished with the debug session to preserve the current target build configuration, editor settings and the location of all open debug views. To save the project, select Project->Save Project As... from the menu. Create a new name for the project and click on Save.

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AN174 5. Example Source Code Example source code and register definition files are provided in the “SiLabs\MCU\Examples\C8051F06x” directory during IDE installation. These files may be used as a template for code development. Example applications include a blinking LED example which configures the green LED on the target board to blink at a fixed rate.

5.1. Register Definition Files Register definition files C8051F060.inc and C8051F060.h define all SFR registers and bit-addressable control/ status bits. They are installed into the “SiLabs\MCU\Examples\C8051F06x” directory during IDE installation. The register and bit names are identical to those used in the C8051F06x data sheet. Both register definition files are also installed in the default search path used by the Keil Software 8051 tools. Therefore, when using the Keil 8051 tools included with the development kit (A51, C51), it is not necessary to copy a register definition file to each project’s file directory.

5.2. Blinking LED Example The example source files blink.asm and blinky.c show examples of several basic C8051F06x functions. These include; disabling the watchdog timer (WDT), configuring the Port I/O crossbar, configuring a timer for an interrupt routine, initializing the system clock, and configuring a GPIO port. When compiled/assembled and linked this program flashes the green LED on the C8051F060 target board about five times a second using the interrupt handler with a C8051F060 timer.

5.3. Data Aquisition Example The Data Aquisition example can be found in the “SiLabs\MCU\Examples\C8051F06x\C” directory in source file SAR16data.c. This example illustrates the use of ADC1 and the DMA to acquire and store data. It is intended for use with the C8051F060TB target board in the development kit. The code measures a signal at the AIN0 input with the 16-bit SAR ADC0. The data is then sampled at a rate of 100kHz. ADC output data is transferred to XDATA memory space using the DMA.

5.3.1. Code Description With the EMIF configured for off-chip XRAM access (on the upper ports), the code moves the ADC data to the C8051F060TB target boards's SRAM device. Once data acquisition is complete, the code then prompts the user to press the P3.7 button on the target board when ready to receive the data via the UART0 serial port. The TB features an RS-232 transceiver and connector, so the data can be transferred to a PC via its serial port. The code is set to acquire up to 32768 samples (for 64kbytes of data). The SRAM device can accommodate up to 128kbytes, but this requires banking (A16 signal on the SRAM).

5.3.2. Target Board Configuration This example uses RS-232 communications, typically with a PC. A serial cable should be connected to the J5 RS232 DB9 connector on the target board and to a serial port on a PC. (A serial port will also be needed for PC communications with the EC-2 serial adapter for programming and debug). Data can be input from the PC's serial port using the commonly available program Hyperterminal. The following target board jumpers must be configured (see Section 8 on page 11 for schematic): J1 J6, J9 J11 J14[2:3] J17, J28 J20[1:2]

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Connect P3.7 to push-button SW2. Connect UART0 TX and RX to the J5 DB9 connector. Enable External Memory Interface SRAM device. Connect the SRAM A16 pin to GND. Set analog input VREF options. Enable ±5 V switching power supply by connecting Vin, +5 V, to /SHDN.

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AN174 6. Target Board The C8051F06x Development Kit includes a target board with a C8051F060 device pre-installed for evaluation and preliminary software development. Numerous input/output (I/O) connections are provided to facilitate prototyping using the target board. Refer to Figure 2 for the locations of the various I/O connectors. Power connector (accepts input from 7 to 15 VDC unregulated power adapter) Connects SW2 to P3.7 pin Connects LED D3 to P1.6 pin JTAG connector for Serial Adapter interface DB-9 connector for UART0 RS232 interface Jumper to connect UART0 TX (P0.0) to DB9 Jumper to connect UART0 RX (P0.1) to DB9 External Memory Interface connectors Port 0 - 1 connectors Port 2- 3 connectors Enable the -5 V supply for analog inputs Set analog input VREF options Set analog input external conversion start options VREF connector VDD Monitor Disable 96-pin Expansion I/O connector DB-9 connector for CAN interface Mini BNC conncectors for analog inputs

J3

P1.6 J24

P3.7 RESET

PWR P1

Pin 1 Port 1 J18 J10 J8 J6 J9 C8051 F06X

Pin 1 Port 3

J2 J21

J15

J14

Pin 2 Pin 1 J22

J4

J26 J27

XRAM

J7

Pin 1

J28 J17

J25

Pin 1 Port 0

Pin 1 J23

J16

CAN

Pin 1 Port 2

J5

J12

RS232

J1

J11

P1 J1 J3 J4 J5 J6 J9 J11, J14 J12, J15 J16, J18 J20 J17, J28 J26, J27 J22 J23 J24 J25 AIN_0,1

J20 Pin 1

JTAG

Pin 1

AIN_1 AIN_0

Figure 2. C8051F060 Target Board

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AN174 6.1. System Clock Sources The C8051F060 device installed on the target board features a calibrated programmable internal oscillator which is enabled as the system clock source on reset. After reset, the internal oscillator operates at a frequency of 3.0625MHz (±2%) by default but may be configured by software to operate at other frequencies. Therefore, in many applications an external oscillator is not required. However, an external 22.1184 MHz crystal is installed on the target board for additional applications. Refer to the C8051F06x data sheet for more information on configuring the system clock source.

6.2. Switches and LEDs Two switches are provided on the target board. Switch SW1 is connected to the RESET pin of the C8051F060. Pressing SW1 puts the device into its hardware-reset state. Switch SW2 is connected to the C8051F060’s general purpose I/O (GPIO) pin through jumpers. Pressing SW2 generates a logic low signal on the port pin. Remove the shorting block from the jumper to disconnect SW2 from the port pins. The port pin signal is also routed to a pin on the J24 I/O connector. See Table 1 for the port pins and jumpers corresponding to each switch. Two LEDs are also provided on the target board. The red LED labeled PWR is used to indicate a power connection to the target board. The green LED labeled with a port pin name is connected to the C8051F060’s GPIO pin through jumpers. Remove the shorting block from the jumper to disconnect the LED from the port pin. The port pin signal is also routed to a pin on the J24 I/O connector. See Table 1 for the port pins and jumpers corresponding to each LED.

Description

I/O

Jumper

SW1 SW2 Green LED Red LED

Reset P3.7 P1.6 PWR

none J1 J3 none

Table 1. Target Board I/O Descriptions 6.3. Target Board JTAG Interface (J4) The JTAG connector (J4) provides access to the JTAG pins of the C8051F060. It is used to connect the Serial Adapter to the target board for in-circuit debugging and Flash programming. Table 2 shows the JTAG pin definitions.

Pin #

Description

1 2, 3, 9 4 5 6 7 8, 10

+3 VD (+3.3 VDC) GND (Ground) TCK TMS TDO TDI Not Connected

Table 2. JTAG Connector Pin Descriptions

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AN174 6.4. Serial Interface (J5) A RS232 transceiver circuit and DB-9 (J5) connector are provided on the target board to facilitate serial connections to UART0 of the C8051F060. The TX, RX, RTS and CTS signals of UART0 may be connected to the DB-9 connector and transceiver by installing shorting blocks on jumpers J6, J8, J9 and J10. J6 J9 J8 J10

- Install shorting block to connect UART0 TX (P0.0) to transceiver. - Install shorting block to connect UART0 RX (P0.1) to transceiver. - Install shorting block to connect UART0 RTS (P4.0) to transceiver. - Install shorting block to connect UART0 CTS (P4.1) to transceiver.

6.5. Controller Area Network (CAN) Interface (J25) A DB-9 (J25) connector is provided to facilitate serial connections to the CAN interface on the C8051F060. In addition, when a shorting block is installed on jumper J7, writing a logic 'high' to port pin P4.2 will place the CAN transceiver in low-current standby mode. Also, resistor R12 may be replaced with a higher value to control the slew rate of the CAN_H and CAN_L signals. See the TI SN65HVD230 data sheet for further information. Table 3 listes the pin descriptions for J25.

Pin #

Description

2 7 3, 6 1, 4, 5, 8, 9

CAN_L CAN_H GND (Ground) Not Connected

Table 3. CAN Connector Pin Descriptions 6.6. External Memory Interface (J11) The C8051F060 target board provides an External Memory Interface by connecting a 128 kB SRAM to the device port pins. The device’s External Memory Interface can be enabled by installing a shorting block at jumper J11. This will connect port pin P4.5 to the Chip Select (/CS) signal on the SRAM, pulling this signal low. Placing a shorting block on jumper J14[2-3] enables the use of the lower address bank on the SRAM. Moving the shorting block to J14[1-2] will enable port pin P3.7 to select between the upper and lower address banks on the SRAM. Refer to Table 4 for the external memory interface signal descriptions.

SRAM Signal C8051F060 Signal /WE /CS /OE VDD GND I/O0...I/O7 A0...A7 A8...A15 A16 A16

P4.7 P4.5 (J11) P4.6 +3 VD2 GND P7.0...P7.7 P6.0...P6.7 P5.0...P5.7 P3.7 (J14[1-2]) GND (J14[2-3])

Description Write Enable Chip Select Output Enable Digital Power Digital Ground Data Bus Address Bus Low Byte Address Bus High Byte Bank Select Bank Select Always 0

Table 4. External Memory Interface Signal Descriptions

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AN174 6.7. Analog Inputs (AIN_0, AIN_1) Two mini BNC connectors are provided on the C8051F060 target board, AIN_0 and AIN_1. These analog inputs can be used to input an analog signal to the 16-bit ADCs located on the device, ADC0 and ADC1. Additionally, opamp circuitry is provided to filter the analog signals. To use this circuitry the following guidelines should be followed: • • • • •

Enable the -5 V voltage supply by placing a shorting block at jumper J20[1-2]. Provide an external VREF0 to ADC0 by placing a shorting block at jumper J28. Provide an external VREF1 to ADC1 by placing a shorting block at jumper J17. Provide an external Conversion Start signal to ADC0 by placing a shorting block at jumper J27. Provide an external Conversion Start signal to ADC1 by placing a shorting block at jumper J26.

6.8. PORT I/O Connectors (J12, J15, J16 & J18) In addition to all port I/O signals being routed to the 96-pin expansion connector, four of the eight parallel ports of the C8051F060 has its own 10-pin header connector. Each connector provides a pin for the corresponding port pins 0-7, +3.3 VDC and digital ground. Table 5 defines the pins for the port connectors. The same pin-out order is used for all of the port connectors.

Pin #

Description

1 2 3 4 5 6 7 8 9 10

Pn.0 Pn.1 Pn.2 Pn.3 Pn.4 Pn.5 Pn.6 Pn.7 +3 VD (+3.3 VDC) GND (Ground)

Table 5. J12- J19 Port Connector Pin Descriptions 6.9. VDD Monitor Disable Jumper (J23) The VDD Monitor of the C8051F060 may be disabled by moving the shorting block on J23 from pins 1-2 to pins 23, as shown in Figure 3. MONEN

1 2 3

Figure 3. VDD Monitor Hardware Setup

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AN174 6.10. Expansion I/O Connector (J24) The 96-pin expansion I/O connector J24 is used to connect daughter boards to the main target board. J24 provides access to many C8051F060 signal pins. Pins for analog and digital grounds and voltage supplies are also available. See Table 6 for a complete list of pins available at J24. The J24 socket connector is manufactured by Hirose Electronic Co. Ltd, part number PCN13-96S-2.54DS, DigiKey part number H7096-ND. The corresponding plug connector is also manufactured by Hirose Electronic Co. Ltd, part number PCN10-96P-2.54DS, Digi-Key part number H5096-ND.

Pin #

Description

A-1 +3 VD2 (+3.3 VDC) A-2 MONEN A-3 P1.5 A-4 P1.2 A-5 P2.7 A-6 P2.4 A-7 P2.1 A-8 P3.6 A-9 P3.3 A-10 P3.0 A-11 P0.5 A-12 P0.2 A-13 P7.7 A-14 P7.4 A-15 P7.1 A-16 P6.6 A-17 P6.3 A-18 P6.0 A-19 P5.5 A-20 P5.2 A-21 P4.7 A-22 A-23 A-24 TCK A-25 /RST A-26 AGND (Analog Gnd) A-27 CANRX A-28 A-29 A-30 A-31 A-32

Pin #

Description

B-1 DGND (Digital Gnd) B-2 P1.7 B-3 P1.4 B-4 P1.1 B-5 P2.6 B-6 P2.3 B-7 P2.0 B-8 P3.5 B-9 P3.2 B-10 P0.7 B-11 P0.4 B-12 P0.1 B-13 P7.6 B-14 P7.3 B-15 P7.0 B-16 P6.5 B-17 P6.2 B-18 P5.7 B-19 P5.4 B-20 P5.1 B-21 P4.6 B-22 B-23 B-24 TDI B-25 DGND (Digital Gnd) B-26 DAC1 B-27 CANTX B-28 B-29 VREF2 B-30 B-31 B-32 AGND (Analog Gnd)

Pin #

Description

C-1 XTAL1 C-2 P1.6 C-3 P1.3 C-4 P1.0 C-5 P2.5 C-6 P2.2 C-7 P3.7 C-8 P3.4 C-9 P3.1 C-10 P0.6 C-11 P0.3 C-12 P0.0 C-13 P7.5 C-14 P7.2 C-15 P6.7 C-16 P6.4 C-17 P6.1 C-18 P5.6 C-19 P5.3 C-20 P5.0 C-21 P4.5 C-22 C-23 TMS C-24 TDO C-25 C-26 DAC0 C-27 C-28 VREFD C-29 CNVSTR0_EX C-30 CNVSTR1_EX C-31 C-32 AV+ (+3.3 VDC Analog)

Table 6. J24 Pin Descriptions

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AN174 6.11. VREF Connector (J22) The VREF jumper block, J22, can be used to connect the VREF (Voltage Reference) output of the C8051F060 to any (or all) of its voltage reference inputs. Install shorting blocks on J22 in the following manner: 1-2 to connect VREF to VREFD 3-4 to connect VREF to VREF2

7. Serial Adapter The Serial Adapter provides the interface between the PC’s RS232 serial port and the C8051F06x’s in-system debug/programming circuitry. The Serial Adapter connects to the C8051F060 JTAG debug interface on the target board using the 10-pin connector on the Serial Adapter labeled “JTAG”, see Figure 4. (The Serial Adapter supports both Silicon Laboratories JTAG and C2 debug interfaces.). All Serial Adapters may be powered from the target board, but the EC1 and EC2 Serial Adapter units cannot provide power to the target board. Table 7 shows the pin definitions for the Serial Adapter’s JTAG connector. Notes: 1. When powering the Serial Adapter via the JTAG connector, the input voltage to the JTAG connector’s power pin must be 3.0 to 3.6 VDC. Otherwise, the Serial Adapter must be powered directly by connecting the AC/DC adapter to the Serial Adapter’s DC power jack. 2. The Serial Adapter requires a target system clock of 32 Khz or greater.

Pin #

Description

1 2 4 5 6 7 3,8,9,10

3.0 to 3.6 VDC Input GND (Ground) TCK (C2DAT) TMS TDO TDI (C2CLK) Not Connected

JTAG

Serial Adapter

RS232

Pwr

Run/ Stop

Table 7. JTAG/DEBUG Connector Pin Descriptions

Pin 1 Pin 2

Figure 4. Serial Adapter JTAG/DEBUG Connector

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Figure 5. C8051F060 Target Board Schematic (page 1)

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8. Schematic

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Figure 7. C8051F060 Target Board Schematic (page 2)

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Figure 8. C8051F060 Target Board Schematic (page 3)

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AN174 Contact Information Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: [email protected] Internet: www.silabs.com

The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.

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