1 Instruction Set

1.2 Load/Store Instructions. Instruction. Signification. Description. LDW a b ic. R.a = load word. LDB a b ic. R.a =
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1 1.1

Instruction Set Register Instructions

Instruction Signification Instruction Signification integer addition integer multiplication ADD a b c R.a = R.b + R.c MUL a b c R.a = R.b * R.c ADDI a b ic R.a = R.b + ic MULI a b ic R.a = R.b * ic ADDIU a b uc R.a = R.b + uc MULIU a b uc R.a = R.b * uc integer subtraction integer division SUB a b c R.a = R.b - R.c DIV a b c R.a = R.b / R.c SUBI a b ic R.a = R.b - ic DIVI a b ic R.a = R.b / ic SUBIU a b uc R.a = R.b - uc DIVIU a b uc R.a = R.b / uc integer comparison integer modulo CMP a b c R.a = cmp(R.b,R.c) MOD a b c R.a = R.b % R.c CMPI a b ic R.a = cmp(R.b, ic) MODI a b ic R.a = R.b % ic CMPIU a b uc R.a = cmp(R.b, uc) MODIU a b uc R.a = R.b % uc logical or logical xor OR a b c R.a = R.b | R.c XOR a b c R.a = R.b ^ R.c ORI a b ic R.a = R.b | ic XORI a b ic R.a = R.b ^ ic ORIU a b uc R.a = R.b | uc XORIU a b uc R.a = R.b ^ uc logical and logical bic AND a b c R.a = R.b & R.c BIC a b c R.a = R.b & ~R.c ANDI a b ic R.a = R.b & ic BICI a b ic R.a = R.b & ~ ic ANDIU a b uc R.a = R.b & uc BICIU a b uc R.a = R.b & ~ uc logical shift arithmetic shift LSH a b c R.a = lsh(R.b,R.c) ASH a b c R.a = ash(R.b,R.c) LSHI a b ic R.a = lsh(R.b, ic) ASHI a b ic R.a = ash(R.b, ic) bound check CHK a c raise an error if not 0 -c ash(b,c) = c > 0 ? b > -c

1.2

Load/Store Instructions

Instruction LDW a b ic LDB a b ic POP a b ic STW a b ic STB a b ic PSH a b ic

Signification R.a =

R.a (byte)R.a

Description load word load byte pop word store word store byte push word

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Control Instructions

Instruction BEQ a oc BNE a oc BLT a oc BGE a oc BLE a oc BGT a oc BSR oc JSR

lc

RET

c

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Signification PC += 4 * (R.a PC += 4 * (R.a PC += 4 * (R.a PC += 4 * (R.a PC += 4 * (R.a PC += 4 * (R.a R.31 = PC + 4 PC += 4 * oc R.31 = PC + 4 PC = 4 * lc PC = R.c

] 1 2 6 7 15 11 12 13 19

3

? ? ? ? ? ?

oc oc oc oc oc oc

: : : : : :

1) 1) 1) 1) 1) 1)

jump to subroutine jump to return address

Signification R.a = SYS_uc(R.a,R.b)

Description break execution invoke a system function

System Calls Instruction SYSCALL a 0 SYSCALL a 0 SYSCALL a 0 SYSCALL a 0 SYSCALL 0 0 SYSCALL a b SYSCALL a b SYSCALL a 0 SYSCALL a 0

Signification R.a = Unicode of read character or -1 if EOF R.a = value of read integer write character with Unicode R.a write signed value R.a in decimal format flush the output stream initialize the garbage collector R.a = address of a newly allocated block of R.b bytes R.a = total memory size in bytes terminates the emulation with status code R.a

SYS_IO_RD_CHR SYS_IO_RD_INT SYS_IO_WR_CHR SYS_IO_WR_INT SYS_IO_FLUSH SYS_GC_INIT SYS_GC_ALLOC SYS_GET_TOTAL_MEM_SIZE SYS_EXIT

Constants

Notation a, b, c ic uc oc lc

4

0 0 0 0 0 0

Miscellaneous Instructions

Instruction BREAK SYSCALL a b uc

2

== != < >=

Description branch if equal branch if not equal branch if less than branch if greater or equal branch if less or equal branch if greater than branch to subroutine

Size 5 bits 16 bits 16 bits 21 bits 26 bits

Signification Register number Signed integer Unsigned integer Signed displacement Absolute address

Registers

The DLX processor has 32 registers which are 32 bits large. The register R0 is always equal to 0 and is immutable. The register R31 is used to save the return address (BSR and JSR). By convention, R1 is used to store the result of a function call and R30 is the stack pointer.

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